iwl-prph.h 13 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of version 2 of the GNU General Public License as
  12. * published by the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but
  15. * WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17. * General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22. * USA
  23. *
  24. * The full GNU General Public License is included in this distribution
  25. * in the file called LICENSE.GPL.
  26. *
  27. * Contact Information:
  28. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  29. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30. *
  31. * BSD LICENSE
  32. *
  33. * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
  34. * All rights reserved.
  35. *
  36. * Redistribution and use in source and binary forms, with or without
  37. * modification, are permitted provided that the following conditions
  38. * are met:
  39. *
  40. * * Redistributions of source code must retain the above copyright
  41. * notice, this list of conditions and the following disclaimer.
  42. * * Redistributions in binary form must reproduce the above copyright
  43. * notice, this list of conditions and the following disclaimer in
  44. * the documentation and/or other materials provided with the
  45. * distribution.
  46. * * Neither the name Intel Corporation nor the names of its
  47. * contributors may be used to endorse or promote products derived
  48. * from this software without specific prior written permission.
  49. *
  50. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61. *****************************************************************************/
  62. #ifndef __iwl_prph_h__
  63. #define __iwl_prph_h__
  64. /*
  65. * Registers in this file are internal, not PCI bus memory mapped.
  66. * Driver accesses these via HBUS_TARG_PRPH_* registers.
  67. */
  68. #define PRPH_BASE (0x00000)
  69. #define PRPH_END (0xFFFFF)
  70. /* APMG (power management) constants */
  71. #define APMG_BASE (PRPH_BASE + 0x3000)
  72. #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
  73. #define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
  74. #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
  75. #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
  76. #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
  77. #define APMG_RFKILL_REG (APMG_BASE + 0x0014)
  78. #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
  79. #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)
  80. #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
  81. #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
  82. #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
  83. #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
  84. #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
  85. #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
  86. #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x01000000)
  87. /**
  88. * BSM (Bootstrap State Machine)
  89. *
  90. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  91. * in special SRAM that does not power down when the embedded control
  92. * processor is sleeping (e.g. for periodic power-saving shutdowns of radio).
  93. *
  94. * When powering back up after sleeps (or during initial uCode load), the BSM
  95. * internally loads the short bootstrap program from the special SRAM into the
  96. * embedded processor's instruction SRAM, and starts the processor so it runs
  97. * the bootstrap program.
  98. *
  99. * This bootstrap program loads (via PCI busmaster DMA) instructions and data
  100. * images for a uCode program from host DRAM locations. The host driver
  101. * indicates DRAM locations and sizes for instruction and data images via the
  102. * four BSM_DRAM_* registers. Once the bootstrap program loads the new program,
  103. * the new program starts automatically.
  104. *
  105. * The uCode used for open-source drivers includes two programs:
  106. *
  107. * 1) Initialization -- performs hardware calibration and sets up some
  108. * internal data, then notifies host via "initialize alive" notification
  109. * (struct iwl_init_alive_resp) that it has completed all of its work.
  110. * After signal from host, it then loads and starts the runtime program.
  111. * The initialization program must be used when initially setting up the
  112. * NIC after loading the driver.
  113. *
  114. * 2) Runtime/Protocol -- performs all normal runtime operations. This
  115. * notifies host via "alive" notification (struct iwl_alive_resp) that it
  116. * is ready to be used.
  117. *
  118. * When initializing the NIC, the host driver does the following procedure:
  119. *
  120. * 1) Load bootstrap program (instructions only, no data image for bootstrap)
  121. * into bootstrap memory. Use dword writes starting at BSM_SRAM_LOWER_BOUND
  122. *
  123. * 2) Point (via BSM_DRAM_*) to the "initialize" uCode data and instruction
  124. * images in host DRAM.
  125. *
  126. * 3) Set up BSM to copy from BSM SRAM into uCode instruction SRAM when asked:
  127. * BSM_WR_MEM_SRC_REG = 0
  128. * BSM_WR_MEM_DST_REG = RTC_INST_LOWER_BOUND
  129. * BSM_WR_MEM_DWCOUNT_REG = # dwords in bootstrap instruction image
  130. *
  131. * 4) Load bootstrap into instruction SRAM:
  132. * BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START
  133. *
  134. * 5) Wait for load completion:
  135. * Poll BSM_WR_CTRL_REG for BSM_WR_CTRL_REG_BIT_START = 0
  136. *
  137. * 6) Enable future boot loads whenever NIC's power management triggers it:
  138. * BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START_EN
  139. *
  140. * 7) Start the NIC by removing all reset bits:
  141. * CSR_RESET = 0
  142. *
  143. * The bootstrap uCode (already in instruction SRAM) loads initialization
  144. * uCode. Initialization uCode performs data initialization, sends
  145. * "initialize alive" notification to host, and waits for a signal from
  146. * host to load runtime code.
  147. *
  148. * 4) Point (via BSM_DRAM_*) to the "runtime" uCode data and instruction
  149. * images in host DRAM. The last register loaded must be the instruction
  150. * bytecount register ("1" in MSbit tells initialization uCode to load
  151. * the runtime uCode):
  152. * BSM_DRAM_INST_BYTECOUNT_REG = bytecount | BSM_DRAM_INST_LOAD
  153. *
  154. * 5) Wait for "alive" notification, then issue normal runtime commands.
  155. *
  156. * Data caching during power-downs:
  157. *
  158. * Just before the embedded controller powers down (e.g for automatic
  159. * power-saving modes, or for RFKILL), uCode stores (via PCI busmaster DMA)
  160. * a current snapshot of the embedded processor's data SRAM into host DRAM.
  161. * This caches the data while the embedded processor's memory is powered down.
  162. * Location and size are controlled by BSM_DRAM_DATA_* registers.
  163. *
  164. * NOTE: Instruction SRAM does not need to be saved, since that doesn't
  165. * change during operation; the original image (from uCode distribution
  166. * file) can be used for reload.
  167. *
  168. * When powering back up, the BSM loads the bootstrap program. Bootstrap looks
  169. * at the BSM_DRAM_* registers, which now point to the runtime instruction
  170. * image and the cached (modified) runtime data (*not* the initialization
  171. * uCode). Bootstrap reloads these runtime images into SRAM, and restarts the
  172. * uCode from where it left off before the power-down.
  173. *
  174. * NOTE: Initialization uCode does *not* run as part of the save/restore
  175. * procedure.
  176. *
  177. * This save/restore method is mostly for autonomous power management during
  178. * normal operation (result of POWER_TABLE_CMD). Platform suspend/resume and
  179. * RFKILL should use complete restarts (with total re-initialization) of uCode,
  180. * allowing total shutdown (including BSM memory).
  181. *
  182. * Note that, during normal operation, the host DRAM that held the initial
  183. * startup data for the runtime code is now being used as a backup data cache
  184. * for modified data! If you need to completely re-initialize the NIC, make
  185. * sure that you use the runtime data image from the uCode distribution file,
  186. * not the modified/saved runtime data. You may want to store a separate
  187. * "clean" runtime data image in DRAM to avoid disk reads of distribution file.
  188. */
  189. /* BSM bit fields */
  190. #define BSM_WR_CTRL_REG_BIT_START (0x80000000) /* start boot load now */
  191. #define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) /* enable boot after pwrup*/
  192. #define BSM_DRAM_INST_LOAD (0x80000000) /* start program load now */
  193. /* BSM addresses */
  194. #define BSM_BASE (PRPH_BASE + 0x3400)
  195. #define BSM_END (PRPH_BASE + 0x3800)
  196. #define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */
  197. #define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */
  198. #define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */
  199. #define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */
  200. #define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */
  201. /*
  202. * Pointers and size regs for bootstrap load and data SRAM save/restore.
  203. * NOTE: 3945 pointers use bits 31:0 of DRAM address.
  204. * 4965 pointers use bits 35:4 of DRAM address.
  205. */
  206. #define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090)
  207. #define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094)
  208. #define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098)
  209. #define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C)
  210. /*
  211. * BSM special memory, stays powered on during power-save sleeps.
  212. * Read/write, address range from LOWER_BOUND to (LOWER_BOUND + SIZE -1)
  213. */
  214. #define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800)
  215. #define BSM_SRAM_SIZE (1024) /* bytes */
  216. /* 3945 Tx scheduler registers */
  217. #define ALM_SCD_BASE (PRPH_BASE + 0x2E00)
  218. #define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000)
  219. #define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004)
  220. #define ALM_SCD_TXFACT_REG (ALM_SCD_BASE + 0x010)
  221. #define ALM_SCD_TXF4MF_REG (ALM_SCD_BASE + 0x014)
  222. #define ALM_SCD_TXF5MF_REG (ALM_SCD_BASE + 0x020)
  223. #define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C)
  224. #define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030)
  225. /*
  226. * 4965 Tx Scheduler registers.
  227. * Details are documented in iwl-4965-hw.h
  228. */
  229. #define IWL49_SCD_BASE (PRPH_BASE + 0xa02c00)
  230. #define IWL49_SCD_SRAM_BASE_ADDR (IWL49_SCD_BASE + 0x0)
  231. #define IWL49_SCD_EMPTY_BITS (IWL49_SCD_BASE + 0x4)
  232. #define IWL49_SCD_DRAM_BASE_ADDR (IWL49_SCD_BASE + 0x10)
  233. #define IWL49_SCD_AIT (IWL49_SCD_BASE + 0x18)
  234. #define IWL49_SCD_TXFACT (IWL49_SCD_BASE + 0x1c)
  235. #define IWL49_SCD_QUEUE_WRPTR(x) (IWL49_SCD_BASE + 0x24 + (x) * 4)
  236. #define IWL49_SCD_QUEUE_RDPTR(x) (IWL49_SCD_BASE + 0x64 + (x) * 4)
  237. #define IWL49_SCD_SETQUEUENUM (IWL49_SCD_BASE + 0xa4)
  238. #define IWL49_SCD_SET_TXSTAT_TXED (IWL49_SCD_BASE + 0xa8)
  239. #define IWL49_SCD_SET_TXSTAT_DONE (IWL49_SCD_BASE + 0xac)
  240. #define IWL49_SCD_SET_TXSTAT_NOT_SCHD (IWL49_SCD_BASE + 0xb0)
  241. #define IWL49_SCD_DECREASE_CREDIT (IWL49_SCD_BASE + 0xb4)
  242. #define IWL49_SCD_DECREASE_SCREDIT (IWL49_SCD_BASE + 0xb8)
  243. #define IWL49_SCD_LOAD_CREDIT (IWL49_SCD_BASE + 0xbc)
  244. #define IWL49_SCD_LOAD_SCREDIT (IWL49_SCD_BASE + 0xc0)
  245. #define IWL49_SCD_BAR (IWL49_SCD_BASE + 0xc4)
  246. #define IWL49_SCD_BAR_DW0 (IWL49_SCD_BASE + 0xc8)
  247. #define IWL49_SCD_BAR_DW1 (IWL49_SCD_BASE + 0xcc)
  248. #define IWL49_SCD_QUEUECHAIN_SEL (IWL49_SCD_BASE + 0xd0)
  249. #define IWL49_SCD_QUERY_REQ (IWL49_SCD_BASE + 0xd8)
  250. #define IWL49_SCD_QUERY_RES (IWL49_SCD_BASE + 0xdc)
  251. #define IWL49_SCD_PENDING_FRAMES (IWL49_SCD_BASE + 0xe0)
  252. #define IWL49_SCD_INTERRUPT_MASK (IWL49_SCD_BASE + 0xe4)
  253. #define IWL49_SCD_INTERRUPT_THRESHOLD (IWL49_SCD_BASE + 0xe8)
  254. #define IWL49_SCD_QUERY_MIN_FRAME_SIZE (IWL49_SCD_BASE + 0x100)
  255. #define IWL49_SCD_QUEUE_STATUS_BITS(x) (IWL49_SCD_BASE + 0x104 + (x) * 4)
  256. /* SP SCD */
  257. #define IWL50_SCD_BASE (PRPH_BASE + 0xa02c00)
  258. #define IWL50_SCD_SRAM_BASE_ADDR (IWL50_SCD_BASE + 0x0)
  259. #define IWL50_SCD_DRAM_BASE_ADDR (IWL50_SCD_BASE + 0x8)
  260. #define IWL50_SCD_AIT (IWL50_SCD_BASE + 0x0c)
  261. #define IWL50_SCD_TXFACT (IWL50_SCD_BASE + 0x10)
  262. #define IWL50_SCD_ACTIVE (IWL50_SCD_BASE + 0x14)
  263. #define IWL50_SCD_QUEUE_WRPTR(x) (IWL50_SCD_BASE + 0x18 + (x) * 4)
  264. #define IWL50_SCD_QUEUE_RDPTR(x) (IWL50_SCD_BASE + 0x68 + (x) * 4)
  265. #define IWL50_SCD_QUEUECHAIN_SEL (IWL50_SCD_BASE + 0xe8)
  266. #define IWL50_SCD_AGGR_SEL (IWL50_SCD_BASE + 0x248)
  267. #define IWL50_SCD_INTERRUPT_MASK (IWL50_SCD_BASE + 0x108)
  268. #define IWL50_SCD_QUEUE_STATUS_BITS(x) (IWL50_SCD_BASE + 0x10c + (x) * 4)
  269. #endif /* __iwl_prph_h__ */