mthca_main.c 37 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/module.h>
  37. #include <linux/init.h>
  38. #include <linux/errno.h>
  39. #include <linux/pci.h>
  40. #include <linux/interrupt.h>
  41. #include "mthca_dev.h"
  42. #include "mthca_config_reg.h"
  43. #include "mthca_cmd.h"
  44. #include "mthca_profile.h"
  45. #include "mthca_memfree.h"
  46. MODULE_AUTHOR("Roland Dreier");
  47. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  48. MODULE_LICENSE("Dual BSD/GPL");
  49. MODULE_VERSION(DRV_VERSION);
  50. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  51. int mthca_debug_level = 0;
  52. module_param_named(debug_level, mthca_debug_level, int, 0644);
  53. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  54. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  55. #ifdef CONFIG_PCI_MSI
  56. static int msi_x = 1;
  57. module_param(msi_x, int, 0444);
  58. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  59. #else /* CONFIG_PCI_MSI */
  60. #define msi_x (0)
  61. #endif /* CONFIG_PCI_MSI */
  62. static int tune_pci = 0;
  63. module_param(tune_pci, int, 0444);
  64. MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
  65. DEFINE_MUTEX(mthca_device_mutex);
  66. #define MTHCA_DEFAULT_NUM_QP (1 << 16)
  67. #define MTHCA_DEFAULT_RDB_PER_QP (1 << 2)
  68. #define MTHCA_DEFAULT_NUM_CQ (1 << 16)
  69. #define MTHCA_DEFAULT_NUM_MCG (1 << 13)
  70. #define MTHCA_DEFAULT_NUM_MPT (1 << 17)
  71. #define MTHCA_DEFAULT_NUM_MTT (1 << 20)
  72. #define MTHCA_DEFAULT_NUM_UDAV (1 << 15)
  73. #define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18)
  74. #define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18)
  75. static struct mthca_profile hca_profile = {
  76. .num_qp = MTHCA_DEFAULT_NUM_QP,
  77. .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP,
  78. .num_cq = MTHCA_DEFAULT_NUM_CQ,
  79. .num_mcg = MTHCA_DEFAULT_NUM_MCG,
  80. .num_mpt = MTHCA_DEFAULT_NUM_MPT,
  81. .num_mtt = MTHCA_DEFAULT_NUM_MTT,
  82. .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */
  83. .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */
  84. .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */
  85. };
  86. module_param_named(num_qp, hca_profile.num_qp, int, 0444);
  87. MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA");
  88. module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444);
  89. MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP");
  90. module_param_named(num_cq, hca_profile.num_cq, int, 0444);
  91. MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA");
  92. module_param_named(num_mcg, hca_profile.num_mcg, int, 0444);
  93. MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA");
  94. module_param_named(num_mpt, hca_profile.num_mpt, int, 0444);
  95. MODULE_PARM_DESC(num_mpt,
  96. "maximum number of memory protection table entries per HCA");
  97. module_param_named(num_mtt, hca_profile.num_mtt, int, 0444);
  98. MODULE_PARM_DESC(num_mtt,
  99. "maximum number of memory translation table segments per HCA");
  100. module_param_named(num_udav, hca_profile.num_udav, int, 0444);
  101. MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA");
  102. module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444);
  103. MODULE_PARM_DESC(fmr_reserved_mtts,
  104. "number of memory translation table segments reserved for FMR");
  105. static char mthca_version[] __devinitdata =
  106. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  107. DRV_VERSION " (" DRV_RELDATE ")\n";
  108. static int mthca_tune_pci(struct mthca_dev *mdev)
  109. {
  110. if (!tune_pci)
  111. return 0;
  112. /* First try to max out Read Byte Count */
  113. if (pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX)) {
  114. if (pcix_set_mmrbc(mdev->pdev, pcix_get_max_mmrbc(mdev->pdev))) {
  115. mthca_err(mdev, "Couldn't set PCI-X max read count, "
  116. "aborting.\n");
  117. return -ENODEV;
  118. }
  119. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  120. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  121. if (pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP)) {
  122. if (pcie_set_readrq(mdev->pdev, 4096)) {
  123. mthca_err(mdev, "Couldn't write PCI Express read request, "
  124. "aborting.\n");
  125. return -ENODEV;
  126. }
  127. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  128. mthca_info(mdev, "No PCI Express capability, "
  129. "not setting Max Read Request Size.\n");
  130. return 0;
  131. }
  132. static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  133. {
  134. int err;
  135. u8 status;
  136. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  137. if (err) {
  138. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  139. return err;
  140. }
  141. if (status) {
  142. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  143. "aborting.\n", status);
  144. return -EINVAL;
  145. }
  146. if (dev_lim->min_page_sz > PAGE_SIZE) {
  147. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  148. "kernel PAGE_SIZE of %ld, aborting.\n",
  149. dev_lim->min_page_sz, PAGE_SIZE);
  150. return -ENODEV;
  151. }
  152. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  153. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  154. "aborting.\n",
  155. dev_lim->num_ports, MTHCA_MAX_PORTS);
  156. return -ENODEV;
  157. }
  158. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  159. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  160. "PCI resource 2 size of 0x%llx, aborting.\n",
  161. dev_lim->uar_size,
  162. (unsigned long long)pci_resource_len(mdev->pdev, 2));
  163. return -ENODEV;
  164. }
  165. mdev->limits.num_ports = dev_lim->num_ports;
  166. mdev->limits.vl_cap = dev_lim->max_vl;
  167. mdev->limits.mtu_cap = dev_lim->max_mtu;
  168. mdev->limits.gid_table_len = dev_lim->max_gids;
  169. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  170. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  171. mdev->limits.max_sg = dev_lim->max_sg;
  172. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  173. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  174. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  175. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  176. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  177. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  178. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  179. mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
  180. /*
  181. * Subtract 1 from the limit because we need to allocate a
  182. * spare CQE so the HCA HW can tell the difference between an
  183. * empty CQ and a full CQ.
  184. */
  185. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  186. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  187. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  188. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  189. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  190. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  191. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  192. mdev->limits.port_width_cap = dev_lim->max_port_width;
  193. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  194. mdev->limits.flags = dev_lim->flags;
  195. /*
  196. * For old FW that doesn't return static rate support, use a
  197. * value of 0x3 (only static rate values of 0 or 1 are handled),
  198. * except on Sinai, where even old FW can handle static rate
  199. * values of 2 and 3.
  200. */
  201. if (dev_lim->stat_rate_support)
  202. mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
  203. else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  204. mdev->limits.stat_rate_support = 0xf;
  205. else
  206. mdev->limits.stat_rate_support = 0x3;
  207. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  208. May be doable since hardware supports it for SRQ.
  209. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  210. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  211. supported by driver. */
  212. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  213. IB_DEVICE_PORT_ACTIVE_EVENT |
  214. IB_DEVICE_SYS_IMAGE_GUID |
  215. IB_DEVICE_RC_RNR_NAK_GEN;
  216. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  217. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  218. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  219. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  220. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  221. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  222. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  223. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  224. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  225. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  226. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  227. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  228. if (mthca_is_memfree(mdev))
  229. if (dev_lim->flags & DEV_LIM_FLAG_IPOIB_CSUM)
  230. mdev->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  231. return 0;
  232. }
  233. static int mthca_init_tavor(struct mthca_dev *mdev)
  234. {
  235. s64 size;
  236. u8 status;
  237. int err;
  238. struct mthca_dev_lim dev_lim;
  239. struct mthca_profile profile;
  240. struct mthca_init_hca_param init_hca;
  241. err = mthca_SYS_EN(mdev, &status);
  242. if (err) {
  243. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  244. return err;
  245. }
  246. if (status) {
  247. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  248. "aborting.\n", status);
  249. return -EINVAL;
  250. }
  251. err = mthca_QUERY_FW(mdev, &status);
  252. if (err) {
  253. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  254. goto err_disable;
  255. }
  256. if (status) {
  257. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  258. "aborting.\n", status);
  259. err = -EINVAL;
  260. goto err_disable;
  261. }
  262. err = mthca_QUERY_DDR(mdev, &status);
  263. if (err) {
  264. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  265. goto err_disable;
  266. }
  267. if (status) {
  268. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  269. "aborting.\n", status);
  270. err = -EINVAL;
  271. goto err_disable;
  272. }
  273. err = mthca_dev_lim(mdev, &dev_lim);
  274. if (err) {
  275. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  276. goto err_disable;
  277. }
  278. profile = hca_profile;
  279. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  280. profile.uarc_size = 0;
  281. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  282. profile.num_srq = dev_lim.max_srqs;
  283. size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  284. if (size < 0) {
  285. err = size;
  286. goto err_disable;
  287. }
  288. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  289. if (err) {
  290. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  291. goto err_disable;
  292. }
  293. if (status) {
  294. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  295. "aborting.\n", status);
  296. err = -EINVAL;
  297. goto err_disable;
  298. }
  299. return 0;
  300. err_disable:
  301. mthca_SYS_DIS(mdev, &status);
  302. return err;
  303. }
  304. static int mthca_load_fw(struct mthca_dev *mdev)
  305. {
  306. u8 status;
  307. int err;
  308. /* FIXME: use HCA-attached memory for FW if present */
  309. mdev->fw.arbel.fw_icm =
  310. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  311. GFP_HIGHUSER | __GFP_NOWARN, 0);
  312. if (!mdev->fw.arbel.fw_icm) {
  313. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  314. return -ENOMEM;
  315. }
  316. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  317. if (err) {
  318. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  319. goto err_free;
  320. }
  321. if (status) {
  322. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  323. err = -EINVAL;
  324. goto err_free;
  325. }
  326. err = mthca_RUN_FW(mdev, &status);
  327. if (err) {
  328. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  329. goto err_unmap_fa;
  330. }
  331. if (status) {
  332. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  333. err = -EINVAL;
  334. goto err_unmap_fa;
  335. }
  336. return 0;
  337. err_unmap_fa:
  338. mthca_UNMAP_FA(mdev, &status);
  339. err_free:
  340. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  341. return err;
  342. }
  343. static int mthca_init_icm(struct mthca_dev *mdev,
  344. struct mthca_dev_lim *dev_lim,
  345. struct mthca_init_hca_param *init_hca,
  346. u64 icm_size)
  347. {
  348. u64 aux_pages;
  349. u8 status;
  350. int err;
  351. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  352. if (err) {
  353. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  354. return err;
  355. }
  356. if (status) {
  357. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  358. "aborting.\n", status);
  359. return -EINVAL;
  360. }
  361. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  362. (unsigned long long) icm_size >> 10,
  363. (unsigned long long) aux_pages << 2);
  364. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  365. GFP_HIGHUSER | __GFP_NOWARN, 0);
  366. if (!mdev->fw.arbel.aux_icm) {
  367. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  368. return -ENOMEM;
  369. }
  370. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  371. if (err) {
  372. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  373. goto err_free_aux;
  374. }
  375. if (status) {
  376. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  377. err = -EINVAL;
  378. goto err_free_aux;
  379. }
  380. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  381. if (err) {
  382. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  383. goto err_unmap_aux;
  384. }
  385. /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */
  386. mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * MTHCA_MTT_SEG_SIZE,
  387. dma_get_cache_alignment()) / MTHCA_MTT_SEG_SIZE;
  388. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  389. MTHCA_MTT_SEG_SIZE,
  390. mdev->limits.num_mtt_segs,
  391. mdev->limits.reserved_mtts,
  392. 1, 0);
  393. if (!mdev->mr_table.mtt_table) {
  394. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  395. err = -ENOMEM;
  396. goto err_unmap_eq;
  397. }
  398. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  399. dev_lim->mpt_entry_sz,
  400. mdev->limits.num_mpts,
  401. mdev->limits.reserved_mrws,
  402. 1, 1);
  403. if (!mdev->mr_table.mpt_table) {
  404. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  405. err = -ENOMEM;
  406. goto err_unmap_mtt;
  407. }
  408. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  409. dev_lim->qpc_entry_sz,
  410. mdev->limits.num_qps,
  411. mdev->limits.reserved_qps,
  412. 0, 0);
  413. if (!mdev->qp_table.qp_table) {
  414. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  415. err = -ENOMEM;
  416. goto err_unmap_mpt;
  417. }
  418. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  419. dev_lim->eqpc_entry_sz,
  420. mdev->limits.num_qps,
  421. mdev->limits.reserved_qps,
  422. 0, 0);
  423. if (!mdev->qp_table.eqp_table) {
  424. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  425. err = -ENOMEM;
  426. goto err_unmap_qp;
  427. }
  428. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  429. MTHCA_RDB_ENTRY_SIZE,
  430. mdev->limits.num_qps <<
  431. mdev->qp_table.rdb_shift, 0,
  432. 0, 0);
  433. if (!mdev->qp_table.rdb_table) {
  434. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  435. err = -ENOMEM;
  436. goto err_unmap_eqp;
  437. }
  438. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  439. dev_lim->cqc_entry_sz,
  440. mdev->limits.num_cqs,
  441. mdev->limits.reserved_cqs,
  442. 0, 0);
  443. if (!mdev->cq_table.table) {
  444. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  445. err = -ENOMEM;
  446. goto err_unmap_rdb;
  447. }
  448. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  449. mdev->srq_table.table =
  450. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  451. dev_lim->srq_entry_sz,
  452. mdev->limits.num_srqs,
  453. mdev->limits.reserved_srqs,
  454. 0, 0);
  455. if (!mdev->srq_table.table) {
  456. mthca_err(mdev, "Failed to map SRQ context memory, "
  457. "aborting.\n");
  458. err = -ENOMEM;
  459. goto err_unmap_cq;
  460. }
  461. }
  462. /*
  463. * It's not strictly required, but for simplicity just map the
  464. * whole multicast group table now. The table isn't very big
  465. * and it's a lot easier than trying to track ref counts.
  466. */
  467. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  468. MTHCA_MGM_ENTRY_SIZE,
  469. mdev->limits.num_mgms +
  470. mdev->limits.num_amgms,
  471. mdev->limits.num_mgms +
  472. mdev->limits.num_amgms,
  473. 0, 0);
  474. if (!mdev->mcg_table.table) {
  475. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  476. err = -ENOMEM;
  477. goto err_unmap_srq;
  478. }
  479. return 0;
  480. err_unmap_srq:
  481. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  482. mthca_free_icm_table(mdev, mdev->srq_table.table);
  483. err_unmap_cq:
  484. mthca_free_icm_table(mdev, mdev->cq_table.table);
  485. err_unmap_rdb:
  486. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  487. err_unmap_eqp:
  488. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  489. err_unmap_qp:
  490. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  491. err_unmap_mpt:
  492. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  493. err_unmap_mtt:
  494. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  495. err_unmap_eq:
  496. mthca_unmap_eq_icm(mdev);
  497. err_unmap_aux:
  498. mthca_UNMAP_ICM_AUX(mdev, &status);
  499. err_free_aux:
  500. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  501. return err;
  502. }
  503. static void mthca_free_icms(struct mthca_dev *mdev)
  504. {
  505. u8 status;
  506. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  507. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  508. mthca_free_icm_table(mdev, mdev->srq_table.table);
  509. mthca_free_icm_table(mdev, mdev->cq_table.table);
  510. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  511. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  512. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  513. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  514. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  515. mthca_unmap_eq_icm(mdev);
  516. mthca_UNMAP_ICM_AUX(mdev, &status);
  517. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  518. }
  519. static int mthca_init_arbel(struct mthca_dev *mdev)
  520. {
  521. struct mthca_dev_lim dev_lim;
  522. struct mthca_profile profile;
  523. struct mthca_init_hca_param init_hca;
  524. s64 icm_size;
  525. u8 status;
  526. int err;
  527. err = mthca_QUERY_FW(mdev, &status);
  528. if (err) {
  529. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  530. return err;
  531. }
  532. if (status) {
  533. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  534. "aborting.\n", status);
  535. return -EINVAL;
  536. }
  537. err = mthca_ENABLE_LAM(mdev, &status);
  538. if (err) {
  539. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  540. return err;
  541. }
  542. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  543. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  544. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  545. } else if (status) {
  546. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  547. "aborting.\n", status);
  548. return -EINVAL;
  549. }
  550. err = mthca_load_fw(mdev);
  551. if (err) {
  552. mthca_err(mdev, "Failed to start FW, aborting.\n");
  553. goto err_disable;
  554. }
  555. err = mthca_dev_lim(mdev, &dev_lim);
  556. if (err) {
  557. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  558. goto err_stop_fw;
  559. }
  560. profile = hca_profile;
  561. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  562. profile.num_udav = 0;
  563. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  564. profile.num_srq = dev_lim.max_srqs;
  565. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  566. if (icm_size < 0) {
  567. err = icm_size;
  568. goto err_stop_fw;
  569. }
  570. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  571. if (err)
  572. goto err_stop_fw;
  573. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  574. if (err) {
  575. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  576. goto err_free_icm;
  577. }
  578. if (status) {
  579. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  580. "aborting.\n", status);
  581. err = -EINVAL;
  582. goto err_free_icm;
  583. }
  584. return 0;
  585. err_free_icm:
  586. mthca_free_icms(mdev);
  587. err_stop_fw:
  588. mthca_UNMAP_FA(mdev, &status);
  589. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  590. err_disable:
  591. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  592. mthca_DISABLE_LAM(mdev, &status);
  593. return err;
  594. }
  595. static void mthca_close_hca(struct mthca_dev *mdev)
  596. {
  597. u8 status;
  598. mthca_CLOSE_HCA(mdev, 0, &status);
  599. if (mthca_is_memfree(mdev)) {
  600. mthca_free_icms(mdev);
  601. mthca_UNMAP_FA(mdev, &status);
  602. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  603. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  604. mthca_DISABLE_LAM(mdev, &status);
  605. } else
  606. mthca_SYS_DIS(mdev, &status);
  607. }
  608. static int mthca_init_hca(struct mthca_dev *mdev)
  609. {
  610. u8 status;
  611. int err;
  612. struct mthca_adapter adapter;
  613. if (mthca_is_memfree(mdev))
  614. err = mthca_init_arbel(mdev);
  615. else
  616. err = mthca_init_tavor(mdev);
  617. if (err)
  618. return err;
  619. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  620. if (err) {
  621. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  622. goto err_close;
  623. }
  624. if (status) {
  625. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  626. "aborting.\n", status);
  627. err = -EINVAL;
  628. goto err_close;
  629. }
  630. mdev->eq_table.inta_pin = adapter.inta_pin;
  631. if (!mthca_is_memfree(mdev))
  632. mdev->rev_id = adapter.revision_id;
  633. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  634. return 0;
  635. err_close:
  636. mthca_close_hca(mdev);
  637. return err;
  638. }
  639. static int mthca_setup_hca(struct mthca_dev *dev)
  640. {
  641. int err;
  642. u8 status;
  643. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  644. err = mthca_init_uar_table(dev);
  645. if (err) {
  646. mthca_err(dev, "Failed to initialize "
  647. "user access region table, aborting.\n");
  648. return err;
  649. }
  650. err = mthca_uar_alloc(dev, &dev->driver_uar);
  651. if (err) {
  652. mthca_err(dev, "Failed to allocate driver access region, "
  653. "aborting.\n");
  654. goto err_uar_table_free;
  655. }
  656. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  657. if (!dev->kar) {
  658. mthca_err(dev, "Couldn't map kernel access region, "
  659. "aborting.\n");
  660. err = -ENOMEM;
  661. goto err_uar_free;
  662. }
  663. err = mthca_init_pd_table(dev);
  664. if (err) {
  665. mthca_err(dev, "Failed to initialize "
  666. "protection domain table, aborting.\n");
  667. goto err_kar_unmap;
  668. }
  669. err = mthca_init_mr_table(dev);
  670. if (err) {
  671. mthca_err(dev, "Failed to initialize "
  672. "memory region table, aborting.\n");
  673. goto err_pd_table_free;
  674. }
  675. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  676. if (err) {
  677. mthca_err(dev, "Failed to create driver PD, "
  678. "aborting.\n");
  679. goto err_mr_table_free;
  680. }
  681. err = mthca_init_eq_table(dev);
  682. if (err) {
  683. mthca_err(dev, "Failed to initialize "
  684. "event queue table, aborting.\n");
  685. goto err_pd_free;
  686. }
  687. err = mthca_cmd_use_events(dev);
  688. if (err) {
  689. mthca_err(dev, "Failed to switch to event-driven "
  690. "firmware commands, aborting.\n");
  691. goto err_eq_table_free;
  692. }
  693. err = mthca_NOP(dev, &status);
  694. if (err || status) {
  695. if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
  696. mthca_warn(dev, "NOP command failed to generate interrupt "
  697. "(IRQ %d).\n",
  698. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector);
  699. mthca_warn(dev, "Trying again with MSI-X disabled.\n");
  700. } else {
  701. mthca_err(dev, "NOP command failed to generate interrupt "
  702. "(IRQ %d), aborting.\n",
  703. dev->pdev->irq);
  704. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  705. }
  706. goto err_cmd_poll;
  707. }
  708. mthca_dbg(dev, "NOP command IRQ test passed\n");
  709. err = mthca_init_cq_table(dev);
  710. if (err) {
  711. mthca_err(dev, "Failed to initialize "
  712. "completion queue table, aborting.\n");
  713. goto err_cmd_poll;
  714. }
  715. err = mthca_init_srq_table(dev);
  716. if (err) {
  717. mthca_err(dev, "Failed to initialize "
  718. "shared receive queue table, aborting.\n");
  719. goto err_cq_table_free;
  720. }
  721. err = mthca_init_qp_table(dev);
  722. if (err) {
  723. mthca_err(dev, "Failed to initialize "
  724. "queue pair table, aborting.\n");
  725. goto err_srq_table_free;
  726. }
  727. err = mthca_init_av_table(dev);
  728. if (err) {
  729. mthca_err(dev, "Failed to initialize "
  730. "address vector table, aborting.\n");
  731. goto err_qp_table_free;
  732. }
  733. err = mthca_init_mcg_table(dev);
  734. if (err) {
  735. mthca_err(dev, "Failed to initialize "
  736. "multicast group table, aborting.\n");
  737. goto err_av_table_free;
  738. }
  739. return 0;
  740. err_av_table_free:
  741. mthca_cleanup_av_table(dev);
  742. err_qp_table_free:
  743. mthca_cleanup_qp_table(dev);
  744. err_srq_table_free:
  745. mthca_cleanup_srq_table(dev);
  746. err_cq_table_free:
  747. mthca_cleanup_cq_table(dev);
  748. err_cmd_poll:
  749. mthca_cmd_use_polling(dev);
  750. err_eq_table_free:
  751. mthca_cleanup_eq_table(dev);
  752. err_pd_free:
  753. mthca_pd_free(dev, &dev->driver_pd);
  754. err_mr_table_free:
  755. mthca_cleanup_mr_table(dev);
  756. err_pd_table_free:
  757. mthca_cleanup_pd_table(dev);
  758. err_kar_unmap:
  759. iounmap(dev->kar);
  760. err_uar_free:
  761. mthca_uar_free(dev, &dev->driver_uar);
  762. err_uar_table_free:
  763. mthca_cleanup_uar_table(dev);
  764. return err;
  765. }
  766. static int mthca_request_regions(struct pci_dev *pdev, int ddr_hidden)
  767. {
  768. int err;
  769. /*
  770. * We can't just use pci_request_regions() because the MSI-X
  771. * table is right in the middle of the first BAR. If we did
  772. * pci_request_region and grab all of the first BAR, then
  773. * setting up MSI-X would fail, since the PCI core wants to do
  774. * request_mem_region on the MSI-X vector table.
  775. *
  776. * So just request what we need right now, and request any
  777. * other regions we need when setting up EQs.
  778. */
  779. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  780. MTHCA_HCR_SIZE, DRV_NAME))
  781. return -EBUSY;
  782. err = pci_request_region(pdev, 2, DRV_NAME);
  783. if (err)
  784. goto err_bar2_failed;
  785. if (!ddr_hidden) {
  786. err = pci_request_region(pdev, 4, DRV_NAME);
  787. if (err)
  788. goto err_bar4_failed;
  789. }
  790. return 0;
  791. err_bar4_failed:
  792. pci_release_region(pdev, 2);
  793. err_bar2_failed:
  794. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  795. MTHCA_HCR_SIZE);
  796. return err;
  797. }
  798. static void mthca_release_regions(struct pci_dev *pdev,
  799. int ddr_hidden)
  800. {
  801. if (!ddr_hidden)
  802. pci_release_region(pdev, 4);
  803. pci_release_region(pdev, 2);
  804. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  805. MTHCA_HCR_SIZE);
  806. }
  807. static int mthca_enable_msi_x(struct mthca_dev *mdev)
  808. {
  809. struct msix_entry entries[3];
  810. int err;
  811. entries[0].entry = 0;
  812. entries[1].entry = 1;
  813. entries[2].entry = 2;
  814. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  815. if (err) {
  816. if (err > 0)
  817. mthca_info(mdev, "Only %d MSI-X vectors available, "
  818. "not using MSI-X\n", err);
  819. return err;
  820. }
  821. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  822. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  823. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  824. return 0;
  825. }
  826. /* Types of supported HCA */
  827. enum {
  828. TAVOR, /* MT23108 */
  829. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  830. ARBEL_NATIVE, /* MT25208 with extended features */
  831. SINAI /* MT25204 */
  832. };
  833. #define MTHCA_FW_VER(major, minor, subminor) \
  834. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  835. static struct {
  836. u64 latest_fw;
  837. u32 flags;
  838. } mthca_hca_table[] = {
  839. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 5, 0),
  840. .flags = 0 },
  841. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 8, 200),
  842. .flags = MTHCA_FLAG_PCIE },
  843. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 3, 0),
  844. .flags = MTHCA_FLAG_MEMFREE |
  845. MTHCA_FLAG_PCIE },
  846. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 2, 0),
  847. .flags = MTHCA_FLAG_MEMFREE |
  848. MTHCA_FLAG_PCIE |
  849. MTHCA_FLAG_SINAI_OPT }
  850. };
  851. static int __mthca_init_one(struct pci_dev *pdev, int hca_type)
  852. {
  853. int ddr_hidden = 0;
  854. int err;
  855. struct mthca_dev *mdev;
  856. printk(KERN_INFO PFX "Initializing %s\n",
  857. pci_name(pdev));
  858. err = pci_enable_device(pdev);
  859. if (err) {
  860. dev_err(&pdev->dev, "Cannot enable PCI device, "
  861. "aborting.\n");
  862. return err;
  863. }
  864. /*
  865. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  866. * be present)
  867. */
  868. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  869. pci_resource_len(pdev, 0) != 1 << 20) {
  870. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  871. err = -ENODEV;
  872. goto err_disable_pdev;
  873. }
  874. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  875. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  876. err = -ENODEV;
  877. goto err_disable_pdev;
  878. }
  879. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  880. ddr_hidden = 1;
  881. err = mthca_request_regions(pdev, ddr_hidden);
  882. if (err) {
  883. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  884. "aborting.\n");
  885. goto err_disable_pdev;
  886. }
  887. pci_set_master(pdev);
  888. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  889. if (err) {
  890. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  891. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  892. if (err) {
  893. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  894. goto err_free_res;
  895. }
  896. }
  897. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  898. if (err) {
  899. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  900. "consistent PCI DMA mask.\n");
  901. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  902. if (err) {
  903. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  904. "aborting.\n");
  905. goto err_free_res;
  906. }
  907. }
  908. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  909. if (!mdev) {
  910. dev_err(&pdev->dev, "Device struct alloc failed, "
  911. "aborting.\n");
  912. err = -ENOMEM;
  913. goto err_free_res;
  914. }
  915. mdev->pdev = pdev;
  916. mdev->mthca_flags = mthca_hca_table[hca_type].flags;
  917. if (ddr_hidden)
  918. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  919. /*
  920. * Now reset the HCA before we touch the PCI capabilities or
  921. * attempt a firmware command, since a boot ROM may have left
  922. * the HCA in an undefined state.
  923. */
  924. err = mthca_reset(mdev);
  925. if (err) {
  926. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  927. goto err_free_dev;
  928. }
  929. if (mthca_cmd_init(mdev)) {
  930. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  931. goto err_free_dev;
  932. }
  933. err = mthca_tune_pci(mdev);
  934. if (err)
  935. goto err_cmd;
  936. err = mthca_init_hca(mdev);
  937. if (err)
  938. goto err_cmd;
  939. if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) {
  940. mthca_warn(mdev, "HCA FW version %d.%d.%03d is old (%d.%d.%03d is current).\n",
  941. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  942. (int) (mdev->fw_ver & 0xffff),
  943. (int) (mthca_hca_table[hca_type].latest_fw >> 32),
  944. (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff,
  945. (int) (mthca_hca_table[hca_type].latest_fw & 0xffff));
  946. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  947. }
  948. if (msi_x && !mthca_enable_msi_x(mdev))
  949. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  950. err = mthca_setup_hca(mdev);
  951. if (err == -EBUSY && (mdev->mthca_flags & MTHCA_FLAG_MSI_X)) {
  952. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  953. pci_disable_msix(pdev);
  954. mdev->mthca_flags &= ~MTHCA_FLAG_MSI_X;
  955. err = mthca_setup_hca(mdev);
  956. }
  957. if (err)
  958. goto err_close;
  959. err = mthca_register_device(mdev);
  960. if (err)
  961. goto err_cleanup;
  962. err = mthca_create_agents(mdev);
  963. if (err)
  964. goto err_unregister;
  965. pci_set_drvdata(pdev, mdev);
  966. mdev->hca_type = hca_type;
  967. return 0;
  968. err_unregister:
  969. mthca_unregister_device(mdev);
  970. err_cleanup:
  971. mthca_cleanup_mcg_table(mdev);
  972. mthca_cleanup_av_table(mdev);
  973. mthca_cleanup_qp_table(mdev);
  974. mthca_cleanup_srq_table(mdev);
  975. mthca_cleanup_cq_table(mdev);
  976. mthca_cmd_use_polling(mdev);
  977. mthca_cleanup_eq_table(mdev);
  978. mthca_pd_free(mdev, &mdev->driver_pd);
  979. mthca_cleanup_mr_table(mdev);
  980. mthca_cleanup_pd_table(mdev);
  981. mthca_cleanup_uar_table(mdev);
  982. err_close:
  983. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  984. pci_disable_msix(pdev);
  985. mthca_close_hca(mdev);
  986. err_cmd:
  987. mthca_cmd_cleanup(mdev);
  988. err_free_dev:
  989. ib_dealloc_device(&mdev->ib_dev);
  990. err_free_res:
  991. mthca_release_regions(pdev, ddr_hidden);
  992. err_disable_pdev:
  993. pci_disable_device(pdev);
  994. pci_set_drvdata(pdev, NULL);
  995. return err;
  996. }
  997. static void __mthca_remove_one(struct pci_dev *pdev)
  998. {
  999. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  1000. u8 status;
  1001. int p;
  1002. if (mdev) {
  1003. mthca_free_agents(mdev);
  1004. mthca_unregister_device(mdev);
  1005. for (p = 1; p <= mdev->limits.num_ports; ++p)
  1006. mthca_CLOSE_IB(mdev, p, &status);
  1007. mthca_cleanup_mcg_table(mdev);
  1008. mthca_cleanup_av_table(mdev);
  1009. mthca_cleanup_qp_table(mdev);
  1010. mthca_cleanup_srq_table(mdev);
  1011. mthca_cleanup_cq_table(mdev);
  1012. mthca_cmd_use_polling(mdev);
  1013. mthca_cleanup_eq_table(mdev);
  1014. mthca_pd_free(mdev, &mdev->driver_pd);
  1015. mthca_cleanup_mr_table(mdev);
  1016. mthca_cleanup_pd_table(mdev);
  1017. iounmap(mdev->kar);
  1018. mthca_uar_free(mdev, &mdev->driver_uar);
  1019. mthca_cleanup_uar_table(mdev);
  1020. mthca_close_hca(mdev);
  1021. mthca_cmd_cleanup(mdev);
  1022. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  1023. pci_disable_msix(pdev);
  1024. ib_dealloc_device(&mdev->ib_dev);
  1025. mthca_release_regions(pdev, mdev->mthca_flags &
  1026. MTHCA_FLAG_DDR_HIDDEN);
  1027. pci_disable_device(pdev);
  1028. pci_set_drvdata(pdev, NULL);
  1029. }
  1030. }
  1031. int __mthca_restart_one(struct pci_dev *pdev)
  1032. {
  1033. struct mthca_dev *mdev;
  1034. int hca_type;
  1035. mdev = pci_get_drvdata(pdev);
  1036. if (!mdev)
  1037. return -ENODEV;
  1038. hca_type = mdev->hca_type;
  1039. __mthca_remove_one(pdev);
  1040. return __mthca_init_one(pdev, hca_type);
  1041. }
  1042. static int __devinit mthca_init_one(struct pci_dev *pdev,
  1043. const struct pci_device_id *id)
  1044. {
  1045. static int mthca_version_printed = 0;
  1046. int ret;
  1047. mutex_lock(&mthca_device_mutex);
  1048. if (!mthca_version_printed) {
  1049. printk(KERN_INFO "%s", mthca_version);
  1050. ++mthca_version_printed;
  1051. }
  1052. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  1053. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  1054. pci_name(pdev), id->driver_data);
  1055. mutex_unlock(&mthca_device_mutex);
  1056. return -ENODEV;
  1057. }
  1058. ret = __mthca_init_one(pdev, id->driver_data);
  1059. mutex_unlock(&mthca_device_mutex);
  1060. return ret;
  1061. }
  1062. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  1063. {
  1064. mutex_lock(&mthca_device_mutex);
  1065. __mthca_remove_one(pdev);
  1066. mutex_unlock(&mthca_device_mutex);
  1067. }
  1068. static struct pci_device_id mthca_pci_table[] = {
  1069. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1070. .driver_data = TAVOR },
  1071. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1072. .driver_data = TAVOR },
  1073. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1074. .driver_data = ARBEL_COMPAT },
  1075. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1076. .driver_data = ARBEL_COMPAT },
  1077. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1078. .driver_data = ARBEL_NATIVE },
  1079. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1080. .driver_data = ARBEL_NATIVE },
  1081. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  1082. .driver_data = SINAI },
  1083. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1084. .driver_data = SINAI },
  1085. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1086. .driver_data = SINAI },
  1087. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1088. .driver_data = SINAI },
  1089. { 0, }
  1090. };
  1091. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1092. static struct pci_driver mthca_driver = {
  1093. .name = DRV_NAME,
  1094. .id_table = mthca_pci_table,
  1095. .probe = mthca_init_one,
  1096. .remove = __devexit_p(mthca_remove_one)
  1097. };
  1098. static void __init __mthca_check_profile_val(const char *name, int *pval,
  1099. int pval_default)
  1100. {
  1101. /* value must be positive and power of 2 */
  1102. int old_pval = *pval;
  1103. if (old_pval <= 0)
  1104. *pval = pval_default;
  1105. else
  1106. *pval = roundup_pow_of_two(old_pval);
  1107. if (old_pval != *pval) {
  1108. printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n",
  1109. old_pval, name);
  1110. printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval);
  1111. }
  1112. }
  1113. #define mthca_check_profile_val(name, default) \
  1114. __mthca_check_profile_val(#name, &hca_profile.name, default)
  1115. static void __init mthca_validate_profile(void)
  1116. {
  1117. mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP);
  1118. mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP);
  1119. mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ);
  1120. mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG);
  1121. mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT);
  1122. mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT);
  1123. mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV);
  1124. mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS);
  1125. if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) {
  1126. printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n",
  1127. hca_profile.fmr_reserved_mtts);
  1128. printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n",
  1129. hca_profile.num_mtt);
  1130. hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2;
  1131. printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n",
  1132. hca_profile.fmr_reserved_mtts);
  1133. }
  1134. }
  1135. static int __init mthca_init(void)
  1136. {
  1137. int ret;
  1138. mthca_validate_profile();
  1139. ret = mthca_catas_init();
  1140. if (ret)
  1141. return ret;
  1142. ret = pci_register_driver(&mthca_driver);
  1143. if (ret < 0) {
  1144. mthca_catas_cleanup();
  1145. return ret;
  1146. }
  1147. return 0;
  1148. }
  1149. static void __exit mthca_cleanup(void)
  1150. {
  1151. pci_unregister_driver(&mthca_driver);
  1152. mthca_catas_cleanup();
  1153. }
  1154. module_init(mthca_init);
  1155. module_exit(mthca_cleanup);