ide-cris.c 28 KB

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  1. /*
  2. * Etrax specific IDE functions, like init and PIO-mode setting etc.
  3. * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
  4. * Copyright (c) 2000-2005 Axis Communications AB
  5. *
  6. * Authors: Bjorn Wesen (initial version)
  7. * Mikael Starvik (crisv32 port)
  8. */
  9. /* Regarding DMA:
  10. *
  11. * There are two forms of DMA - "DMA handshaking" between the interface and the drive,
  12. * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
  13. * something built-in in the Etrax. However only some drives support the DMA-mode handshaking
  14. * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
  15. * device can't do DMA handshaking for some stupid reason. We don't need to do that.
  16. */
  17. #include <linux/types.h>
  18. #include <linux/kernel.h>
  19. #include <linux/timer.h>
  20. #include <linux/mm.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/delay.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/hdreg.h>
  25. #include <linux/ide.h>
  26. #include <linux/init.h>
  27. #include <asm/io.h>
  28. #include <asm/dma.h>
  29. /* number of DMA descriptors */
  30. #define MAX_DMA_DESCRS 64
  31. /* number of times to retry busy-flags when reading/writing IDE-registers
  32. * this can't be too high because a hung harddisk might cause the watchdog
  33. * to trigger (sometimes INB and OUTB are called with irq's disabled)
  34. */
  35. #define IDE_REGISTER_TIMEOUT 300
  36. #define LOWDB(x)
  37. #define D(x)
  38. enum /* Transfer types */
  39. {
  40. TYPE_PIO,
  41. TYPE_DMA,
  42. TYPE_UDMA
  43. };
  44. /* CRISv32 specifics */
  45. #ifdef CONFIG_ETRAX_ARCH_V32
  46. #include <asm/arch/hwregs/ata_defs.h>
  47. #include <asm/arch/hwregs/dma_defs.h>
  48. #include <asm/arch/hwregs/dma.h>
  49. #include <asm/arch/pinmux.h>
  50. #define ATA_UDMA2_CYC 2
  51. #define ATA_UDMA2_DVS 3
  52. #define ATA_UDMA1_CYC 2
  53. #define ATA_UDMA1_DVS 4
  54. #define ATA_UDMA0_CYC 4
  55. #define ATA_UDMA0_DVS 6
  56. #define ATA_DMA2_STROBE 7
  57. #define ATA_DMA2_HOLD 1
  58. #define ATA_DMA1_STROBE 8
  59. #define ATA_DMA1_HOLD 3
  60. #define ATA_DMA0_STROBE 25
  61. #define ATA_DMA0_HOLD 19
  62. #define ATA_PIO4_SETUP 3
  63. #define ATA_PIO4_STROBE 7
  64. #define ATA_PIO4_HOLD 1
  65. #define ATA_PIO3_SETUP 3
  66. #define ATA_PIO3_STROBE 9
  67. #define ATA_PIO3_HOLD 3
  68. #define ATA_PIO2_SETUP 3
  69. #define ATA_PIO2_STROBE 13
  70. #define ATA_PIO2_HOLD 5
  71. #define ATA_PIO1_SETUP 5
  72. #define ATA_PIO1_STROBE 23
  73. #define ATA_PIO1_HOLD 9
  74. #define ATA_PIO0_SETUP 9
  75. #define ATA_PIO0_STROBE 39
  76. #define ATA_PIO0_HOLD 9
  77. int
  78. cris_ide_ack_intr(ide_hwif_t* hwif)
  79. {
  80. reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2,
  81. int, hwif->io_ports[0]);
  82. REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel);
  83. return 1;
  84. }
  85. static inline int
  86. cris_ide_busy(void)
  87. {
  88. reg_ata_rs_stat_data stat_data;
  89. stat_data = REG_RD(ata, regi_ata, rs_stat_data);
  90. return stat_data.busy;
  91. }
  92. static inline int
  93. cris_ide_ready(void)
  94. {
  95. return !cris_ide_busy();
  96. }
  97. static inline int
  98. cris_ide_data_available(unsigned short* data)
  99. {
  100. reg_ata_rs_stat_data stat_data;
  101. stat_data = REG_RD(ata, regi_ata, rs_stat_data);
  102. *data = stat_data.data;
  103. return stat_data.dav;
  104. }
  105. static void
  106. cris_ide_write_command(unsigned long command)
  107. {
  108. REG_WR_INT(ata, regi_ata, rw_ctrl2, command); /* write data to the drive's register */
  109. }
  110. static void
  111. cris_ide_set_speed(int type, int setup, int strobe, int hold)
  112. {
  113. reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0);
  114. reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1);
  115. if (type == TYPE_PIO) {
  116. ctrl0.pio_setup = setup;
  117. ctrl0.pio_strb = strobe;
  118. ctrl0.pio_hold = hold;
  119. } else if (type == TYPE_DMA) {
  120. ctrl0.dma_strb = strobe;
  121. ctrl0.dma_hold = hold;
  122. } else if (type == TYPE_UDMA) {
  123. ctrl1.udma_tcyc = setup;
  124. ctrl1.udma_tdvs = strobe;
  125. }
  126. REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
  127. REG_WR(ata, regi_ata, rw_ctrl1, ctrl1);
  128. }
  129. static unsigned long
  130. cris_ide_base_address(int bus)
  131. {
  132. reg_ata_rw_ctrl2 ctrl2 = {0};
  133. ctrl2.sel = bus;
  134. return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
  135. }
  136. static unsigned long
  137. cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
  138. {
  139. reg_ata_rw_ctrl2 ctrl2 = {0};
  140. ctrl2.addr = addr;
  141. ctrl2.cs1 = cs1;
  142. ctrl2.cs0 = cs0;
  143. return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
  144. }
  145. static __init void
  146. cris_ide_reset(unsigned val)
  147. {
  148. reg_ata_rw_ctrl0 ctrl0 = {0};
  149. ctrl0.rst = val ? regk_ata_active : regk_ata_inactive;
  150. REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
  151. }
  152. static __init void
  153. cris_ide_init(void)
  154. {
  155. reg_ata_rw_ctrl0 ctrl0 = {0};
  156. reg_ata_rw_intr_mask intr_mask = {0};
  157. ctrl0.en = regk_ata_yes;
  158. REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
  159. intr_mask.bus0 = regk_ata_yes;
  160. intr_mask.bus1 = regk_ata_yes;
  161. intr_mask.bus2 = regk_ata_yes;
  162. intr_mask.bus3 = regk_ata_yes;
  163. REG_WR(ata, regi_ata, rw_intr_mask, intr_mask);
  164. crisv32_request_dma(2, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
  165. crisv32_request_dma(3, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
  166. crisv32_pinmux_alloc_fixed(pinmux_ata);
  167. crisv32_pinmux_alloc_fixed(pinmux_ata0);
  168. crisv32_pinmux_alloc_fixed(pinmux_ata1);
  169. crisv32_pinmux_alloc_fixed(pinmux_ata2);
  170. crisv32_pinmux_alloc_fixed(pinmux_ata3);
  171. DMA_RESET(regi_dma2);
  172. DMA_ENABLE(regi_dma2);
  173. DMA_RESET(regi_dma3);
  174. DMA_ENABLE(regi_dma3);
  175. DMA_WR_CMD (regi_dma2, regk_dma_set_w_size2);
  176. DMA_WR_CMD (regi_dma3, regk_dma_set_w_size2);
  177. }
  178. static dma_descr_context mycontext __attribute__ ((__aligned__(32)));
  179. #define cris_dma_descr_type dma_descr_data
  180. #define cris_pio_read regk_ata_rd
  181. #define cris_ultra_mask 0x7
  182. #define MAX_DESCR_SIZE 0xffffffffUL
  183. static unsigned long
  184. cris_ide_get_reg(unsigned long reg)
  185. {
  186. return (reg & 0x0e000000) >> 25;
  187. }
  188. static void
  189. cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
  190. {
  191. d->buf = (char*)virt_to_phys(buf);
  192. d->after = d->buf + len;
  193. d->eol = last;
  194. }
  195. static void
  196. cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir,int type,int len)
  197. {
  198. ide_hwif_t *hwif = drive->hwif;
  199. reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
  200. hwif->io_ports[IDE_DATA_OFFSET]);
  201. reg_ata_rw_trf_cnt trf_cnt = {0};
  202. mycontext.saved_data = (dma_descr_data*)virt_to_phys(d);
  203. mycontext.saved_data_buf = d->buf;
  204. /* start the dma channel */
  205. DMA_START_CONTEXT(dir ? regi_dma3 : regi_dma2, virt_to_phys(&mycontext));
  206. /* initiate a multi word dma read using PIO handshaking */
  207. trf_cnt.cnt = len >> 1;
  208. /* Due to a "feature" the transfer count has to be one extra word for UDMA. */
  209. if (type == TYPE_UDMA)
  210. trf_cnt.cnt++;
  211. REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt);
  212. ctrl2.rw = dir ? regk_ata_rd : regk_ata_wr;
  213. ctrl2.trf_mode = regk_ata_dma;
  214. ctrl2.hsh = type == TYPE_PIO ? regk_ata_pio :
  215. type == TYPE_DMA ? regk_ata_dma : regk_ata_udma;
  216. ctrl2.multi = regk_ata_yes;
  217. ctrl2.dma_size = regk_ata_word;
  218. REG_WR(ata, regi_ata, rw_ctrl2, ctrl2);
  219. }
  220. static void
  221. cris_ide_wait_dma(int dir)
  222. {
  223. reg_dma_rw_stat status;
  224. do
  225. {
  226. status = REG_RD(dma, dir ? regi_dma3 : regi_dma2, rw_stat);
  227. } while(status.list_state != regk_dma_data_at_eol);
  228. }
  229. static int cris_dma_test_irq(ide_drive_t *drive)
  230. {
  231. ide_hwif_t *hwif = drive->hwif;
  232. int intr = REG_RD_INT(ata, regi_ata, r_intr);
  233. reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
  234. hwif->io_ports[IDE_DATA_OFFSET]);
  235. return intr & (1 << ctrl2.sel) ? 1 : 0;
  236. }
  237. static void cris_ide_initialize_dma(int dir)
  238. {
  239. }
  240. #else
  241. /* CRISv10 specifics */
  242. #include <asm/arch/svinto.h>
  243. #include <asm/arch/io_interface_mux.h>
  244. /* PIO timing (in R_ATA_CONFIG)
  245. *
  246. * _____________________________
  247. * ADDRESS : ________/
  248. *
  249. * _______________
  250. * DIOR : ____________/ \__________
  251. *
  252. * _______________
  253. * DATA : XXXXXXXXXXXXXXXX_______________XXXXXXXX
  254. *
  255. *
  256. * DIOR is unbuffered while address and data is buffered.
  257. * This creates two problems:
  258. * 1. The DIOR pulse is to early (because it is unbuffered)
  259. * 2. The rise time of DIOR is long
  260. *
  261. * There are at least three different plausible solutions
  262. * 1. Use a pad capable of larger currents in Etrax
  263. * 2. Use an external buffer
  264. * 3. Make the strobe pulse longer
  265. *
  266. * Some of the strobe timings below are modified to compensate
  267. * for this. This implies a slight performance decrease.
  268. *
  269. * THIS SHOULD NEVER BE CHANGED!
  270. *
  271. * TODO: Is this true for the latest LX boards still ?
  272. */
  273. #define ATA_UDMA2_CYC 0 /* No UDMA supported, just to make it compile. */
  274. #define ATA_UDMA2_DVS 0
  275. #define ATA_UDMA1_CYC 0
  276. #define ATA_UDMA1_DVS 0
  277. #define ATA_UDMA0_CYC 0
  278. #define ATA_UDMA0_DVS 0
  279. #define ATA_DMA2_STROBE 4
  280. #define ATA_DMA2_HOLD 0
  281. #define ATA_DMA1_STROBE 4
  282. #define ATA_DMA1_HOLD 1
  283. #define ATA_DMA0_STROBE 12
  284. #define ATA_DMA0_HOLD 9
  285. #define ATA_PIO4_SETUP 1
  286. #define ATA_PIO4_STROBE 5
  287. #define ATA_PIO4_HOLD 0
  288. #define ATA_PIO3_SETUP 1
  289. #define ATA_PIO3_STROBE 5
  290. #define ATA_PIO3_HOLD 1
  291. #define ATA_PIO2_SETUP 1
  292. #define ATA_PIO2_STROBE 6
  293. #define ATA_PIO2_HOLD 2
  294. #define ATA_PIO1_SETUP 2
  295. #define ATA_PIO1_STROBE 11
  296. #define ATA_PIO1_HOLD 4
  297. #define ATA_PIO0_SETUP 4
  298. #define ATA_PIO0_STROBE 19
  299. #define ATA_PIO0_HOLD 4
  300. int
  301. cris_ide_ack_intr(ide_hwif_t* hwif)
  302. {
  303. return 1;
  304. }
  305. static inline int
  306. cris_ide_busy(void)
  307. {
  308. return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy) ;
  309. }
  310. static inline int
  311. cris_ide_ready(void)
  312. {
  313. return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy) ;
  314. }
  315. static inline int
  316. cris_ide_data_available(unsigned short* data)
  317. {
  318. unsigned long status = *R_ATA_STATUS_DATA;
  319. *data = (unsigned short)status;
  320. return status & IO_MASK(R_ATA_STATUS_DATA, dav);
  321. }
  322. static void
  323. cris_ide_write_command(unsigned long command)
  324. {
  325. *R_ATA_CTRL_DATA = command;
  326. }
  327. static void
  328. cris_ide_set_speed(int type, int setup, int strobe, int hold)
  329. {
  330. static int pio_setup = ATA_PIO4_SETUP;
  331. static int pio_strobe = ATA_PIO4_STROBE;
  332. static int pio_hold = ATA_PIO4_HOLD;
  333. static int dma_strobe = ATA_DMA2_STROBE;
  334. static int dma_hold = ATA_DMA2_HOLD;
  335. if (type == TYPE_PIO) {
  336. pio_setup = setup;
  337. pio_strobe = strobe;
  338. pio_hold = hold;
  339. } else if (type == TYPE_DMA) {
  340. dma_strobe = strobe;
  341. dma_hold = hold;
  342. }
  343. *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
  344. IO_FIELD( R_ATA_CONFIG, dma_strobe, dma_strobe ) |
  345. IO_FIELD( R_ATA_CONFIG, dma_hold, dma_hold ) |
  346. IO_FIELD( R_ATA_CONFIG, pio_setup, pio_setup ) |
  347. IO_FIELD( R_ATA_CONFIG, pio_strobe, pio_strobe ) |
  348. IO_FIELD( R_ATA_CONFIG, pio_hold, pio_hold ) );
  349. }
  350. static unsigned long
  351. cris_ide_base_address(int bus)
  352. {
  353. return IO_FIELD(R_ATA_CTRL_DATA, sel, bus);
  354. }
  355. static unsigned long
  356. cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
  357. {
  358. return IO_FIELD(R_ATA_CTRL_DATA, addr, addr) |
  359. IO_FIELD(R_ATA_CTRL_DATA, cs0, cs0) |
  360. IO_FIELD(R_ATA_CTRL_DATA, cs1, cs1);
  361. }
  362. static __init void
  363. cris_ide_reset(unsigned val)
  364. {
  365. #ifdef CONFIG_ETRAX_IDE_G27_RESET
  366. REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, val);
  367. #endif
  368. #ifdef CONFIG_ETRAX_IDE_PB7_RESET
  369. port_pb_dir_shadow = port_pb_dir_shadow |
  370. IO_STATE(R_PORT_PB_DIR, dir7, output);
  371. *R_PORT_PB_DIR = port_pb_dir_shadow;
  372. REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, val);
  373. #endif
  374. }
  375. static __init void
  376. cris_ide_init(void)
  377. {
  378. volatile unsigned int dummy;
  379. *R_ATA_CTRL_DATA = 0;
  380. *R_ATA_TRANSFER_CNT = 0;
  381. *R_ATA_CONFIG = 0;
  382. if (cris_request_io_interface(if_ata, "ETRAX100LX IDE")) {
  383. printk(KERN_CRIT "ide: Failed to get IO interface\n");
  384. return;
  385. } else if (cris_request_dma(ATA_TX_DMA_NBR,
  386. "ETRAX100LX IDE TX",
  387. DMA_VERBOSE_ON_ERROR,
  388. dma_ata)) {
  389. cris_free_io_interface(if_ata);
  390. printk(KERN_CRIT "ide: Failed to get Tx DMA channel\n");
  391. return;
  392. } else if (cris_request_dma(ATA_RX_DMA_NBR,
  393. "ETRAX100LX IDE RX",
  394. DMA_VERBOSE_ON_ERROR,
  395. dma_ata)) {
  396. cris_free_dma(ATA_TX_DMA_NBR, "ETRAX100LX IDE Tx");
  397. cris_free_io_interface(if_ata);
  398. printk(KERN_CRIT "ide: Failed to get Rx DMA channel\n");
  399. return;
  400. }
  401. /* make a dummy read to set the ata controller in a proper state */
  402. dummy = *R_ATA_STATUS_DATA;
  403. *R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ));
  404. *R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw, read) |
  405. IO_FIELD( R_ATA_CTRL_DATA, addr, 1 ) );
  406. while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/
  407. *R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) |
  408. IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) |
  409. IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
  410. IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );
  411. /* reset the dma channels we will use */
  412. RESET_DMA(ATA_TX_DMA_NBR);
  413. RESET_DMA(ATA_RX_DMA_NBR);
  414. WAIT_DMA(ATA_TX_DMA_NBR);
  415. WAIT_DMA(ATA_RX_DMA_NBR);
  416. }
  417. #define cris_dma_descr_type etrax_dma_descr
  418. #define cris_pio_read IO_STATE(R_ATA_CTRL_DATA, rw, read)
  419. #define cris_ultra_mask 0x0
  420. #define MAX_DESCR_SIZE 0x10000UL
  421. static unsigned long
  422. cris_ide_get_reg(unsigned long reg)
  423. {
  424. return (reg & 0x0e000000) >> 25;
  425. }
  426. static void
  427. cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
  428. {
  429. d->buf = virt_to_phys(buf);
  430. d->sw_len = len == MAX_DESCR_SIZE ? 0 : len;
  431. if (last)
  432. d->ctrl |= d_eol;
  433. }
  434. static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir, int type, int len)
  435. {
  436. unsigned long cmd;
  437. if (dir) {
  438. /* need to do this before RX DMA due to a chip bug
  439. * it is enough to just flush the part of the cache that
  440. * corresponds to the buffers we start, but since HD transfers
  441. * usually are more than 8 kB, it is easier to optimize for the
  442. * normal case and just flush the entire cache. its the only
  443. * way to be sure! (OB movie quote)
  444. */
  445. flush_etrax_cache();
  446. *R_DMA_CH3_FIRST = virt_to_phys(d);
  447. *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, start);
  448. } else {
  449. *R_DMA_CH2_FIRST = virt_to_phys(d);
  450. *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, start);
  451. }
  452. /* initiate a multi word dma read using DMA handshaking */
  453. *R_ATA_TRANSFER_CNT =
  454. IO_FIELD(R_ATA_TRANSFER_CNT, count, len >> 1);
  455. cmd = dir ? IO_STATE(R_ATA_CTRL_DATA, rw, read) : IO_STATE(R_ATA_CTRL_DATA, rw, write);
  456. cmd |= type == TYPE_PIO ? IO_STATE(R_ATA_CTRL_DATA, handsh, pio) :
  457. IO_STATE(R_ATA_CTRL_DATA, handsh, dma);
  458. *R_ATA_CTRL_DATA =
  459. cmd |
  460. IO_FIELD(R_ATA_CTRL_DATA, data,
  461. drive->hwif->io_ports[IDE_DATA_OFFSET]) |
  462. IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
  463. IO_STATE(R_ATA_CTRL_DATA, multi, on) |
  464. IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
  465. }
  466. static void
  467. cris_ide_wait_dma(int dir)
  468. {
  469. if (dir)
  470. WAIT_DMA(ATA_RX_DMA_NBR);
  471. else
  472. WAIT_DMA(ATA_TX_DMA_NBR);
  473. }
  474. static int cris_dma_test_irq(ide_drive_t *drive)
  475. {
  476. int intr = *R_IRQ_MASK0_RD;
  477. int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel,
  478. drive->hwif->io_ports[IDE_DATA_OFFSET]);
  479. return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0;
  480. }
  481. static void cris_ide_initialize_dma(int dir)
  482. {
  483. if (dir)
  484. {
  485. RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
  486. WAIT_DMA(ATA_RX_DMA_NBR);
  487. }
  488. else
  489. {
  490. RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
  491. WAIT_DMA(ATA_TX_DMA_NBR);
  492. }
  493. }
  494. #endif
  495. void
  496. cris_ide_outw(unsigned short data, unsigned long reg) {
  497. int timeleft;
  498. LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg));
  499. /* note the lack of handling any timeouts. we stop waiting, but we don't
  500. * really notify anybody.
  501. */
  502. timeleft = IDE_REGISTER_TIMEOUT;
  503. /* wait for busy flag */
  504. do {
  505. timeleft--;
  506. } while(timeleft && cris_ide_busy());
  507. /*
  508. * Fall through at a timeout, so the ongoing command will be
  509. * aborted by the write below, which is expected to be a dummy
  510. * command to the command register. This happens when a faulty
  511. * drive times out on a command. See comment on timeout in
  512. * INB.
  513. */
  514. if(!timeleft)
  515. printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data);
  516. cris_ide_write_command(reg|data); /* write data to the drive's register */
  517. timeleft = IDE_REGISTER_TIMEOUT;
  518. /* wait for transmitter ready */
  519. do {
  520. timeleft--;
  521. } while(timeleft && !cris_ide_ready());
  522. }
  523. void
  524. cris_ide_outb(unsigned char data, unsigned long reg)
  525. {
  526. cris_ide_outw(data, reg);
  527. }
  528. void
  529. cris_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
  530. {
  531. cris_ide_outw(addr, port);
  532. }
  533. unsigned short
  534. cris_ide_inw(unsigned long reg) {
  535. int timeleft;
  536. unsigned short val;
  537. timeleft = IDE_REGISTER_TIMEOUT;
  538. /* wait for busy flag */
  539. do {
  540. timeleft--;
  541. } while(timeleft && cris_ide_busy());
  542. if(!timeleft) {
  543. /*
  544. * If we're asked to read the status register, like for
  545. * example when a command does not complete for an
  546. * extended time, but the ATA interface is stuck in a
  547. * busy state at the *ETRAX* ATA interface level (as has
  548. * happened repeatedly with at least one bad disk), then
  549. * the best thing to do is to pretend that we read
  550. * "busy" in the status register, so the IDE driver will
  551. * time-out, abort the ongoing command and perform a
  552. * reset sequence. Note that the subsequent OUT_BYTE
  553. * call will also timeout on busy, but as long as the
  554. * write is still performed, everything will be fine.
  555. */
  556. if (cris_ide_get_reg(reg) == IDE_STATUS_OFFSET)
  557. return BUSY_STAT;
  558. else
  559. /* For other rare cases we assume 0 is good enough. */
  560. return 0;
  561. }
  562. cris_ide_write_command(reg | cris_pio_read);
  563. timeleft = IDE_REGISTER_TIMEOUT;
  564. /* wait for available */
  565. do {
  566. timeleft--;
  567. } while(timeleft && !cris_ide_data_available(&val));
  568. if(!timeleft)
  569. return 0;
  570. LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg));
  571. return val;
  572. }
  573. unsigned char
  574. cris_ide_inb(unsigned long reg)
  575. {
  576. return (unsigned char)cris_ide_inw(reg);
  577. }
  578. static int cris_dma_end (ide_drive_t *drive);
  579. static int cris_dma_setup (ide_drive_t *drive);
  580. static void cris_dma_exec_cmd (ide_drive_t *drive, u8 command);
  581. static int cris_dma_test_irq(ide_drive_t *drive);
  582. static void cris_dma_start(ide_drive_t *drive);
  583. static void cris_ide_input_data (ide_drive_t *drive, void *, unsigned int);
  584. static void cris_ide_output_data (ide_drive_t *drive, void *, unsigned int);
  585. static void cris_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int);
  586. static void cris_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int);
  587. static void cris_dma_host_set(ide_drive_t *drive, int on)
  588. {
  589. }
  590. static void cris_set_pio_mode(ide_drive_t *drive, const u8 pio)
  591. {
  592. int setup, strobe, hold;
  593. switch(pio)
  594. {
  595. case 0:
  596. setup = ATA_PIO0_SETUP;
  597. strobe = ATA_PIO0_STROBE;
  598. hold = ATA_PIO0_HOLD;
  599. break;
  600. case 1:
  601. setup = ATA_PIO1_SETUP;
  602. strobe = ATA_PIO1_STROBE;
  603. hold = ATA_PIO1_HOLD;
  604. break;
  605. case 2:
  606. setup = ATA_PIO2_SETUP;
  607. strobe = ATA_PIO2_STROBE;
  608. hold = ATA_PIO2_HOLD;
  609. break;
  610. case 3:
  611. setup = ATA_PIO3_SETUP;
  612. strobe = ATA_PIO3_STROBE;
  613. hold = ATA_PIO3_HOLD;
  614. break;
  615. case 4:
  616. setup = ATA_PIO4_SETUP;
  617. strobe = ATA_PIO4_STROBE;
  618. hold = ATA_PIO4_HOLD;
  619. break;
  620. default:
  621. return;
  622. }
  623. cris_ide_set_speed(TYPE_PIO, setup, strobe, hold);
  624. }
  625. static void cris_set_dma_mode(ide_drive_t *drive, const u8 speed)
  626. {
  627. int cyc = 0, dvs = 0, strobe = 0, hold = 0;
  628. switch(speed)
  629. {
  630. case XFER_UDMA_0:
  631. cyc = ATA_UDMA0_CYC;
  632. dvs = ATA_UDMA0_DVS;
  633. break;
  634. case XFER_UDMA_1:
  635. cyc = ATA_UDMA1_CYC;
  636. dvs = ATA_UDMA1_DVS;
  637. break;
  638. case XFER_UDMA_2:
  639. cyc = ATA_UDMA2_CYC;
  640. dvs = ATA_UDMA2_DVS;
  641. break;
  642. case XFER_MW_DMA_0:
  643. strobe = ATA_DMA0_STROBE;
  644. hold = ATA_DMA0_HOLD;
  645. break;
  646. case XFER_MW_DMA_1:
  647. strobe = ATA_DMA1_STROBE;
  648. hold = ATA_DMA1_HOLD;
  649. break;
  650. case XFER_MW_DMA_2:
  651. strobe = ATA_DMA2_STROBE;
  652. hold = ATA_DMA2_HOLD;
  653. break;
  654. }
  655. if (speed >= XFER_UDMA_0)
  656. cris_ide_set_speed(TYPE_UDMA, cyc, dvs, 0);
  657. else
  658. cris_ide_set_speed(TYPE_DMA, 0, strobe, hold);
  659. }
  660. static void __init cris_setup_ports(hw_regs_t *hw, unsigned long base)
  661. {
  662. int i;
  663. memset(hw, 0, sizeof(*hw));
  664. for (i = 0; i <= 7; i++)
  665. hw->io_ports[i] = base + cris_ide_reg_addr(i, 0, 1);
  666. /*
  667. * the IDE control register is at ATA address 6,
  668. * with CS1 active instead of CS0
  669. */
  670. hw->io_ports[IDE_CONTROL_OFFSET] = base + cris_ide_reg_addr(6, 1, 0);
  671. hw->irq = ide_default_irq(0);
  672. hw->ack_intr = cris_ide_ack_intr;
  673. }
  674. static const struct ide_port_info cris_port_info __initdata = {
  675. .chipset = ide_etrax100,
  676. .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
  677. IDE_HFLAG_NO_DMA, /* no SFF-style DMA */
  678. .pio_mask = ATA_PIO4,
  679. .udma_mask = cris_ultra_mask,
  680. .mwdma_mask = ATA_MWDMA2,
  681. };
  682. static int __init init_e100_ide(void)
  683. {
  684. hw_regs_t hw;
  685. int h;
  686. u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
  687. printk("ide: ETRAX FS built-in ATA DMA controller\n");
  688. for (h = 0; h < 4; h++) {
  689. ide_hwif_t *hwif = NULL;
  690. cris_setup_ports(&hw, cris_ide_base_address(h));
  691. hwif = ide_find_port();
  692. if (hwif == NULL)
  693. continue;
  694. ide_init_port_data(hwif, hwif->index);
  695. ide_init_port_hw(hwif, &hw);
  696. hwif->mmio = 1;
  697. hwif->set_pio_mode = &cris_set_pio_mode;
  698. hwif->set_dma_mode = &cris_set_dma_mode;
  699. hwif->ata_input_data = &cris_ide_input_data;
  700. hwif->ata_output_data = &cris_ide_output_data;
  701. hwif->atapi_input_bytes = &cris_atapi_input_bytes;
  702. hwif->atapi_output_bytes = &cris_atapi_output_bytes;
  703. hwif->dma_host_set = &cris_dma_host_set;
  704. hwif->ide_dma_end = &cris_dma_end;
  705. hwif->dma_setup = &cris_dma_setup;
  706. hwif->dma_exec_cmd = &cris_dma_exec_cmd;
  707. hwif->ide_dma_test_irq = &cris_dma_test_irq;
  708. hwif->dma_start = &cris_dma_start;
  709. hwif->OUTB = &cris_ide_outb;
  710. hwif->OUTW = &cris_ide_outw;
  711. hwif->OUTBSYNC = &cris_ide_outbsync;
  712. hwif->INB = &cris_ide_inb;
  713. hwif->INW = &cris_ide_inw;
  714. hwif->cbl = ATA_CBL_PATA40;
  715. idx[h] = hwif->index;
  716. }
  717. /* Reset pulse */
  718. cris_ide_reset(0);
  719. udelay(25);
  720. cris_ide_reset(1);
  721. cris_ide_init();
  722. cris_ide_set_speed(TYPE_PIO, ATA_PIO4_SETUP, ATA_PIO4_STROBE, ATA_PIO4_HOLD);
  723. cris_ide_set_speed(TYPE_DMA, 0, ATA_DMA2_STROBE, ATA_DMA2_HOLD);
  724. cris_ide_set_speed(TYPE_UDMA, ATA_UDMA2_CYC, ATA_UDMA2_DVS, 0);
  725. ide_device_add(idx, &cris_port_info);
  726. return 0;
  727. }
  728. static cris_dma_descr_type mydescr __attribute__ ((__aligned__(16)));
  729. /*
  730. * The following routines are mainly used by the ATAPI drivers.
  731. *
  732. * These routines will round up any request for an odd number of bytes,
  733. * so if an odd bytecount is specified, be sure that there's at least one
  734. * extra byte allocated for the buffer.
  735. */
  736. static void
  737. cris_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
  738. {
  739. D(printk("atapi_input_bytes, buffer 0x%x, count %d\n",
  740. buffer, bytecount));
  741. if(bytecount & 1) {
  742. printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
  743. bytecount++; /* to round off */
  744. }
  745. /* setup DMA and start transfer */
  746. cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
  747. cris_ide_start_dma(drive, &mydescr, 1, TYPE_PIO, bytecount);
  748. /* wait for completion */
  749. LED_DISK_READ(1);
  750. cris_ide_wait_dma(1);
  751. LED_DISK_READ(0);
  752. }
  753. static void
  754. cris_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
  755. {
  756. D(printk("atapi_output_bytes, buffer 0x%x, count %d\n",
  757. buffer, bytecount));
  758. if(bytecount & 1) {
  759. printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
  760. bytecount++;
  761. }
  762. cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
  763. cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount);
  764. /* wait for completion */
  765. LED_DISK_WRITE(1);
  766. LED_DISK_READ(1);
  767. cris_ide_wait_dma(0);
  768. LED_DISK_WRITE(0);
  769. }
  770. /*
  771. * This is used for most PIO data transfers *from* the IDE interface
  772. */
  773. static void
  774. cris_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
  775. {
  776. cris_atapi_input_bytes(drive, buffer, wcount << 2);
  777. }
  778. /*
  779. * This is used for most PIO data transfers *to* the IDE interface
  780. */
  781. static void
  782. cris_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
  783. {
  784. cris_atapi_output_bytes(drive, buffer, wcount << 2);
  785. }
  786. /* we only have one DMA channel on the chip for ATA, so we can keep these statically */
  787. static cris_dma_descr_type ata_descrs[MAX_DMA_DESCRS] __attribute__ ((__aligned__(16)));
  788. static unsigned int ata_tot_size;
  789. /*
  790. * cris_ide_build_dmatable() prepares a dma request.
  791. * Returns 0 if all went okay, returns 1 otherwise.
  792. */
  793. static int cris_ide_build_dmatable (ide_drive_t *drive)
  794. {
  795. ide_hwif_t *hwif = drive->hwif;
  796. struct scatterlist* sg;
  797. struct request *rq = drive->hwif->hwgroup->rq;
  798. unsigned long size, addr;
  799. unsigned int count = 0;
  800. int i = 0;
  801. sg = hwif->sg_table;
  802. ata_tot_size = 0;
  803. ide_map_sg(drive, rq);
  804. i = hwif->sg_nents;
  805. while(i) {
  806. /*
  807. * Determine addr and size of next buffer area. We assume that
  808. * individual virtual buffers are always composed linearly in
  809. * physical memory. For example, we assume that any 8kB buffer
  810. * is always composed of two adjacent physical 4kB pages rather
  811. * than two possibly non-adjacent physical 4kB pages.
  812. */
  813. /* group sequential buffers into one large buffer */
  814. addr = sg_phys(sg);
  815. size = sg_dma_len(sg);
  816. while (--i) {
  817. sg = sg_next(sg);
  818. if ((addr + size) != sg_phys(sg))
  819. break;
  820. size += sg_dma_len(sg);
  821. }
  822. /* did we run out of descriptors? */
  823. if(count >= MAX_DMA_DESCRS) {
  824. printk("%s: too few DMA descriptors\n", drive->name);
  825. return 1;
  826. }
  827. /* however, this case is more difficult - rw_trf_cnt cannot be more
  828. than 65536 words per transfer, so in that case we need to either
  829. 1) use a DMA interrupt to re-trigger rw_trf_cnt and continue with
  830. the descriptors, or
  831. 2) simply do the request here, and get dma_intr to only ide_end_request on
  832. those blocks that were actually set-up for transfer.
  833. */
  834. if(ata_tot_size + size > 131072) {
  835. printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size);
  836. return 1;
  837. }
  838. /* If size > MAX_DESCR_SIZE it has to be splitted into new descriptors. Since we
  839. don't handle size > 131072 only one split is necessary */
  840. if(size > MAX_DESCR_SIZE) {
  841. cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, MAX_DESCR_SIZE, 0);
  842. count++;
  843. ata_tot_size += MAX_DESCR_SIZE;
  844. size -= MAX_DESCR_SIZE;
  845. addr += MAX_DESCR_SIZE;
  846. }
  847. cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, size,i ? 0 : 1);
  848. count++;
  849. ata_tot_size += size;
  850. }
  851. if (count) {
  852. /* return and say all is ok */
  853. return 0;
  854. }
  855. printk("%s: empty DMA table?\n", drive->name);
  856. return 1; /* let the PIO routines handle this weirdness */
  857. }
  858. /*
  859. * cris_dma_intr() is the handler for disk read/write DMA interrupts
  860. */
  861. static ide_startstop_t cris_dma_intr (ide_drive_t *drive)
  862. {
  863. LED_DISK_READ(0);
  864. LED_DISK_WRITE(0);
  865. return ide_dma_intr(drive);
  866. }
  867. /*
  868. * Functions below initiates/aborts DMA read/write operations on a drive.
  869. *
  870. * The caller is assumed to have selected the drive and programmed the drive's
  871. * sector address using CHS or LBA. All that remains is to prepare for DMA
  872. * and then issue the actual read/write DMA/PIO command to the drive.
  873. *
  874. * For ATAPI devices, we just prepare for DMA and return. The caller should
  875. * then issue the packet command to the drive and call us again with
  876. * cris_dma_start afterwards.
  877. *
  878. * Returns 0 if all went well.
  879. * Returns 1 if DMA read/write could not be started, in which case
  880. * the caller should revert to PIO for the current request.
  881. */
  882. static int cris_dma_end(ide_drive_t *drive)
  883. {
  884. drive->waiting_for_dma = 0;
  885. return 0;
  886. }
  887. static int cris_dma_setup(ide_drive_t *drive)
  888. {
  889. struct request *rq = drive->hwif->hwgroup->rq;
  890. cris_ide_initialize_dma(!rq_data_dir(rq));
  891. if (cris_ide_build_dmatable (drive)) {
  892. ide_map_sg(drive, rq);
  893. return 1;
  894. }
  895. drive->waiting_for_dma = 1;
  896. return 0;
  897. }
  898. static void cris_dma_exec_cmd(ide_drive_t *drive, u8 command)
  899. {
  900. ide_execute_command(drive, command, &cris_dma_intr, WAIT_CMD, NULL);
  901. }
  902. static void cris_dma_start(ide_drive_t *drive)
  903. {
  904. struct request *rq = drive->hwif->hwgroup->rq;
  905. int writing = rq_data_dir(rq);
  906. int type = TYPE_DMA;
  907. if (drive->current_speed >= XFER_UDMA_0)
  908. type = TYPE_UDMA;
  909. cris_ide_start_dma(drive, &ata_descrs[0], writing ? 0 : 1, type, ata_tot_size);
  910. if (writing) {
  911. LED_DISK_WRITE(1);
  912. } else {
  913. LED_DISK_READ(1);
  914. }
  915. }
  916. module_init(init_e100_ide);
  917. MODULE_LICENSE("GPL");