time.c 34 KB

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  1. /*
  2. * arch/s390/kernel/time.c
  3. * Time of day based timer functions.
  4. *
  5. * S390 version
  6. * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
  7. * Author(s): Hartmut Penner (hp@de.ibm.com),
  8. * Martin Schwidefsky (schwidefsky@de.ibm.com),
  9. * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
  10. *
  11. * Derived from "arch/i386/kernel/time.c"
  12. * Copyright (C) 1991, 1992, 1995 Linus Torvalds
  13. */
  14. #include <linux/errno.h>
  15. #include <linux/module.h>
  16. #include <linux/sched.h>
  17. #include <linux/kernel.h>
  18. #include <linux/param.h>
  19. #include <linux/string.h>
  20. #include <linux/mm.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/time.h>
  23. #include <linux/sysdev.h>
  24. #include <linux/delay.h>
  25. #include <linux/init.h>
  26. #include <linux/smp.h>
  27. #include <linux/types.h>
  28. #include <linux/profile.h>
  29. #include <linux/timex.h>
  30. #include <linux/notifier.h>
  31. #include <linux/clocksource.h>
  32. #include <linux/clockchips.h>
  33. #include <asm/uaccess.h>
  34. #include <asm/delay.h>
  35. #include <asm/s390_ext.h>
  36. #include <asm/div64.h>
  37. #include <asm/irq.h>
  38. #include <asm/irq_regs.h>
  39. #include <asm/timer.h>
  40. #include <asm/etr.h>
  41. #include <asm/cio.h>
  42. /* change this if you have some constant time drift */
  43. #define USECS_PER_JIFFY ((unsigned long) 1000000/HZ)
  44. #define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12)
  45. /* The value of the TOD clock for 1.1.1970. */
  46. #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
  47. /*
  48. * Create a small time difference between the timer interrupts
  49. * on the different cpus to avoid lock contention.
  50. */
  51. #define CPU_DEVIATION (smp_processor_id() << 12)
  52. #define TICK_SIZE tick
  53. static ext_int_info_t ext_int_info_cc;
  54. static ext_int_info_t ext_int_etr_cc;
  55. static u64 jiffies_timer_cc;
  56. static DEFINE_PER_CPU(struct clock_event_device, comparators);
  57. /*
  58. * Scheduler clock - returns current time in nanosec units.
  59. */
  60. unsigned long long sched_clock(void)
  61. {
  62. return ((get_clock_xt() - jiffies_timer_cc) * 125) >> 9;
  63. }
  64. /*
  65. * Monotonic_clock - returns # of nanoseconds passed since time_init()
  66. */
  67. unsigned long long monotonic_clock(void)
  68. {
  69. return sched_clock();
  70. }
  71. EXPORT_SYMBOL(monotonic_clock);
  72. void tod_to_timeval(__u64 todval, struct timespec *xtime)
  73. {
  74. unsigned long long sec;
  75. sec = todval >> 12;
  76. do_div(sec, 1000000);
  77. xtime->tv_sec = sec;
  78. todval -= (sec * 1000000) << 12;
  79. xtime->tv_nsec = ((todval * 1000) >> 12);
  80. }
  81. #ifdef CONFIG_PROFILING
  82. #define s390_do_profile() profile_tick(CPU_PROFILING)
  83. #else
  84. #define s390_do_profile() do { ; } while(0)
  85. #endif /* CONFIG_PROFILING */
  86. void clock_comparator_work(void)
  87. {
  88. struct clock_event_device *cd;
  89. S390_lowcore.clock_comparator = -1ULL;
  90. set_clock_comparator(S390_lowcore.clock_comparator);
  91. cd = &__get_cpu_var(comparators);
  92. cd->event_handler(cd);
  93. s390_do_profile();
  94. }
  95. /*
  96. * Fixup the clock comparator.
  97. */
  98. static void fixup_clock_comparator(unsigned long long delta)
  99. {
  100. /* If nobody is waiting there's nothing to fix. */
  101. if (S390_lowcore.clock_comparator == -1ULL)
  102. return;
  103. S390_lowcore.clock_comparator += delta;
  104. set_clock_comparator(S390_lowcore.clock_comparator);
  105. }
  106. static int s390_next_event(unsigned long delta,
  107. struct clock_event_device *evt)
  108. {
  109. S390_lowcore.clock_comparator = get_clock() + delta;
  110. set_clock_comparator(S390_lowcore.clock_comparator);
  111. return 0;
  112. }
  113. static void s390_set_mode(enum clock_event_mode mode,
  114. struct clock_event_device *evt)
  115. {
  116. }
  117. /*
  118. * Set up lowcore and control register of the current cpu to
  119. * enable TOD clock and clock comparator interrupts.
  120. */
  121. void init_cpu_timer(void)
  122. {
  123. struct clock_event_device *cd;
  124. int cpu;
  125. S390_lowcore.clock_comparator = -1ULL;
  126. set_clock_comparator(S390_lowcore.clock_comparator);
  127. cpu = smp_processor_id();
  128. cd = &per_cpu(comparators, cpu);
  129. cd->name = "comparator";
  130. cd->features = CLOCK_EVT_FEAT_ONESHOT;
  131. cd->mult = 16777;
  132. cd->shift = 12;
  133. cd->min_delta_ns = 1;
  134. cd->max_delta_ns = LONG_MAX;
  135. cd->rating = 400;
  136. cd->cpumask = cpumask_of_cpu(cpu);
  137. cd->set_next_event = s390_next_event;
  138. cd->set_mode = s390_set_mode;
  139. clockevents_register_device(cd);
  140. /* Enable clock comparator timer interrupt. */
  141. __ctl_set_bit(0,11);
  142. /* Always allow ETR external interrupts, even without an ETR. */
  143. __ctl_set_bit(0, 4);
  144. }
  145. static void clock_comparator_interrupt(__u16 code)
  146. {
  147. }
  148. static void etr_reset(void);
  149. static void etr_ext_handler(__u16);
  150. /*
  151. * Get the TOD clock running.
  152. */
  153. static u64 __init reset_tod_clock(void)
  154. {
  155. u64 time;
  156. etr_reset();
  157. if (store_clock(&time) == 0)
  158. return time;
  159. /* TOD clock not running. Set the clock to Unix Epoch. */
  160. if (set_clock(TOD_UNIX_EPOCH) != 0 || store_clock(&time) != 0)
  161. panic("TOD clock not operational.");
  162. return TOD_UNIX_EPOCH;
  163. }
  164. static cycle_t read_tod_clock(void)
  165. {
  166. return get_clock();
  167. }
  168. static struct clocksource clocksource_tod = {
  169. .name = "tod",
  170. .rating = 400,
  171. .read = read_tod_clock,
  172. .mask = -1ULL,
  173. .mult = 1000,
  174. .shift = 12,
  175. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  176. };
  177. /*
  178. * Initialize the TOD clock and the CPU timer of
  179. * the boot cpu.
  180. */
  181. void __init time_init(void)
  182. {
  183. u64 init_timer_cc;
  184. init_timer_cc = reset_tod_clock();
  185. jiffies_timer_cc = init_timer_cc - jiffies_64 * CLK_TICKS_PER_JIFFY;
  186. /* set xtime */
  187. tod_to_timeval(init_timer_cc - TOD_UNIX_EPOCH, &xtime);
  188. set_normalized_timespec(&wall_to_monotonic,
  189. -xtime.tv_sec, -xtime.tv_nsec);
  190. /* request the clock comparator external interrupt */
  191. if (register_early_external_interrupt(0x1004,
  192. clock_comparator_interrupt,
  193. &ext_int_info_cc) != 0)
  194. panic("Couldn't request external interrupt 0x1004");
  195. if (clocksource_register(&clocksource_tod) != 0)
  196. panic("Could not register TOD clock source");
  197. /* request the etr external interrupt */
  198. if (register_early_external_interrupt(0x1406, etr_ext_handler,
  199. &ext_int_etr_cc) != 0)
  200. panic("Couldn't request external interrupt 0x1406");
  201. /* Enable TOD clock interrupts on the boot cpu. */
  202. init_cpu_timer();
  203. #ifdef CONFIG_VIRT_TIMER
  204. vtime_init();
  205. #endif
  206. }
  207. /*
  208. * External Time Reference (ETR) code.
  209. */
  210. static int etr_port0_online;
  211. static int etr_port1_online;
  212. static int __init early_parse_etr(char *p)
  213. {
  214. if (strncmp(p, "off", 3) == 0)
  215. etr_port0_online = etr_port1_online = 0;
  216. else if (strncmp(p, "port0", 5) == 0)
  217. etr_port0_online = 1;
  218. else if (strncmp(p, "port1", 5) == 0)
  219. etr_port1_online = 1;
  220. else if (strncmp(p, "on", 2) == 0)
  221. etr_port0_online = etr_port1_online = 1;
  222. return 0;
  223. }
  224. early_param("etr", early_parse_etr);
  225. enum etr_event {
  226. ETR_EVENT_PORT0_CHANGE,
  227. ETR_EVENT_PORT1_CHANGE,
  228. ETR_EVENT_PORT_ALERT,
  229. ETR_EVENT_SYNC_CHECK,
  230. ETR_EVENT_SWITCH_LOCAL,
  231. ETR_EVENT_UPDATE,
  232. };
  233. enum etr_flags {
  234. ETR_FLAG_ENOSYS,
  235. ETR_FLAG_EACCES,
  236. ETR_FLAG_STEAI,
  237. };
  238. /*
  239. * Valid bit combinations of the eacr register are (x = don't care):
  240. * e0 e1 dp p0 p1 ea es sl
  241. * 0 0 x 0 0 0 0 0 initial, disabled state
  242. * 0 0 x 0 1 1 0 0 port 1 online
  243. * 0 0 x 1 0 1 0 0 port 0 online
  244. * 0 0 x 1 1 1 0 0 both ports online
  245. * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode
  246. * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode
  247. * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync
  248. * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync
  249. * 0 1 x 1 1 1 0 0 both ports online, port 1 usable
  250. * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync
  251. * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync
  252. * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode
  253. * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode
  254. * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync
  255. * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync
  256. * 1 0 x 1 1 1 0 0 both ports online, port 0 usable
  257. * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync
  258. * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync
  259. * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync
  260. * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync
  261. */
  262. static struct etr_eacr etr_eacr;
  263. static u64 etr_tolec; /* time of last eacr update */
  264. static unsigned long etr_flags;
  265. static struct etr_aib etr_port0;
  266. static int etr_port0_uptodate;
  267. static struct etr_aib etr_port1;
  268. static int etr_port1_uptodate;
  269. static unsigned long etr_events;
  270. static struct timer_list etr_timer;
  271. static DEFINE_PER_CPU(atomic_t, etr_sync_word);
  272. static void etr_timeout(unsigned long dummy);
  273. static void etr_work_fn(struct work_struct *work);
  274. static DECLARE_WORK(etr_work, etr_work_fn);
  275. /*
  276. * The etr get_clock function. It will write the current clock value
  277. * to the clock pointer and return 0 if the clock is in sync with the
  278. * external time source. If the clock mode is local it will return
  279. * -ENOSYS and -EAGAIN if the clock is not in sync with the external
  280. * reference. This function is what ETR is all about..
  281. */
  282. int get_sync_clock(unsigned long long *clock)
  283. {
  284. atomic_t *sw_ptr;
  285. unsigned int sw0, sw1;
  286. sw_ptr = &get_cpu_var(etr_sync_word);
  287. sw0 = atomic_read(sw_ptr);
  288. *clock = get_clock();
  289. sw1 = atomic_read(sw_ptr);
  290. put_cpu_var(etr_sync_sync);
  291. if (sw0 == sw1 && (sw0 & 0x80000000U))
  292. /* Success: time is in sync. */
  293. return 0;
  294. if (test_bit(ETR_FLAG_ENOSYS, &etr_flags))
  295. return -ENOSYS;
  296. if (test_bit(ETR_FLAG_EACCES, &etr_flags))
  297. return -EACCES;
  298. return -EAGAIN;
  299. }
  300. EXPORT_SYMBOL(get_sync_clock);
  301. /*
  302. * Make get_sync_clock return -EAGAIN.
  303. */
  304. static void etr_disable_sync_clock(void *dummy)
  305. {
  306. atomic_t *sw_ptr = &__get_cpu_var(etr_sync_word);
  307. /*
  308. * Clear the in-sync bit 2^31. All get_sync_clock calls will
  309. * fail until the sync bit is turned back on. In addition
  310. * increase the "sequence" counter to avoid the race of an
  311. * etr event and the complete recovery against get_sync_clock.
  312. */
  313. atomic_clear_mask(0x80000000, sw_ptr);
  314. atomic_inc(sw_ptr);
  315. }
  316. /*
  317. * Make get_sync_clock return 0 again.
  318. * Needs to be called from a context disabled for preemption.
  319. */
  320. static void etr_enable_sync_clock(void)
  321. {
  322. atomic_t *sw_ptr = &__get_cpu_var(etr_sync_word);
  323. atomic_set_mask(0x80000000, sw_ptr);
  324. }
  325. /*
  326. * Reset ETR attachment.
  327. */
  328. static void etr_reset(void)
  329. {
  330. etr_eacr = (struct etr_eacr) {
  331. .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0,
  332. .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0,
  333. .es = 0, .sl = 0 };
  334. if (etr_setr(&etr_eacr) == 0)
  335. etr_tolec = get_clock();
  336. else {
  337. set_bit(ETR_FLAG_ENOSYS, &etr_flags);
  338. if (etr_port0_online || etr_port1_online) {
  339. printk(KERN_WARNING "Running on non ETR capable "
  340. "machine, only local mode available.\n");
  341. etr_port0_online = etr_port1_online = 0;
  342. }
  343. }
  344. }
  345. static int __init etr_init(void)
  346. {
  347. struct etr_aib aib;
  348. if (test_bit(ETR_FLAG_ENOSYS, &etr_flags))
  349. return 0;
  350. /* Check if this machine has the steai instruction. */
  351. if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0)
  352. set_bit(ETR_FLAG_STEAI, &etr_flags);
  353. setup_timer(&etr_timer, etr_timeout, 0UL);
  354. if (!etr_port0_online && !etr_port1_online)
  355. set_bit(ETR_FLAG_EACCES, &etr_flags);
  356. if (etr_port0_online) {
  357. set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
  358. schedule_work(&etr_work);
  359. }
  360. if (etr_port1_online) {
  361. set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
  362. schedule_work(&etr_work);
  363. }
  364. return 0;
  365. }
  366. arch_initcall(etr_init);
  367. /*
  368. * Two sorts of ETR machine checks. The architecture reads:
  369. * "When a machine-check niterruption occurs and if a switch-to-local or
  370. * ETR-sync-check interrupt request is pending but disabled, this pending
  371. * disabled interruption request is indicated and is cleared".
  372. * Which means that we can get etr_switch_to_local events from the machine
  373. * check handler although the interruption condition is disabled. Lovely..
  374. */
  375. /*
  376. * Switch to local machine check. This is called when the last usable
  377. * ETR port goes inactive. After switch to local the clock is not in sync.
  378. */
  379. void etr_switch_to_local(void)
  380. {
  381. if (!etr_eacr.sl)
  382. return;
  383. etr_disable_sync_clock(NULL);
  384. set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events);
  385. schedule_work(&etr_work);
  386. }
  387. /*
  388. * ETR sync check machine check. This is called when the ETR OTE and the
  389. * local clock OTE are farther apart than the ETR sync check tolerance.
  390. * After a ETR sync check the clock is not in sync. The machine check
  391. * is broadcasted to all cpus at the same time.
  392. */
  393. void etr_sync_check(void)
  394. {
  395. if (!etr_eacr.es)
  396. return;
  397. etr_disable_sync_clock(NULL);
  398. set_bit(ETR_EVENT_SYNC_CHECK, &etr_events);
  399. schedule_work(&etr_work);
  400. }
  401. /*
  402. * ETR external interrupt. There are two causes:
  403. * 1) port state change, check the usability of the port
  404. * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the
  405. * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3)
  406. * or ETR-data word 4 (edf4) has changed.
  407. */
  408. static void etr_ext_handler(__u16 code)
  409. {
  410. struct etr_interruption_parameter *intparm =
  411. (struct etr_interruption_parameter *) &S390_lowcore.ext_params;
  412. if (intparm->pc0)
  413. /* ETR port 0 state change. */
  414. set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
  415. if (intparm->pc1)
  416. /* ETR port 1 state change. */
  417. set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
  418. if (intparm->eai)
  419. /*
  420. * ETR port alert on either port 0, 1 or both.
  421. * Both ports are not up-to-date now.
  422. */
  423. set_bit(ETR_EVENT_PORT_ALERT, &etr_events);
  424. schedule_work(&etr_work);
  425. }
  426. static void etr_timeout(unsigned long dummy)
  427. {
  428. set_bit(ETR_EVENT_UPDATE, &etr_events);
  429. schedule_work(&etr_work);
  430. }
  431. /*
  432. * Check if the etr mode is pss.
  433. */
  434. static inline int etr_mode_is_pps(struct etr_eacr eacr)
  435. {
  436. return eacr.es && !eacr.sl;
  437. }
  438. /*
  439. * Check if the etr mode is etr.
  440. */
  441. static inline int etr_mode_is_etr(struct etr_eacr eacr)
  442. {
  443. return eacr.es && eacr.sl;
  444. }
  445. /*
  446. * Check if the port can be used for TOD synchronization.
  447. * For PPS mode the port has to receive OTEs. For ETR mode
  448. * the port has to receive OTEs, the ETR stepping bit has to
  449. * be zero and the validity bits for data frame 1, 2, and 3
  450. * have to be 1.
  451. */
  452. static int etr_port_valid(struct etr_aib *aib, int port)
  453. {
  454. unsigned int psc;
  455. /* Check that this port is receiving OTEs. */
  456. if (aib->tsp == 0)
  457. return 0;
  458. psc = port ? aib->esw.psc1 : aib->esw.psc0;
  459. if (psc == etr_lpsc_pps_mode)
  460. return 1;
  461. if (psc == etr_lpsc_operational_step)
  462. return !aib->esw.y && aib->slsw.v1 &&
  463. aib->slsw.v2 && aib->slsw.v3;
  464. return 0;
  465. }
  466. /*
  467. * Check if two ports are on the same network.
  468. */
  469. static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2)
  470. {
  471. // FIXME: any other fields we have to compare?
  472. return aib1->edf1.net_id == aib2->edf1.net_id;
  473. }
  474. /*
  475. * Wrapper for etr_stei that converts physical port states
  476. * to logical port states to be consistent with the output
  477. * of stetr (see etr_psc vs. etr_lpsc).
  478. */
  479. static void etr_steai_cv(struct etr_aib *aib, unsigned int func)
  480. {
  481. BUG_ON(etr_steai(aib, func) != 0);
  482. /* Convert port state to logical port state. */
  483. if (aib->esw.psc0 == 1)
  484. aib->esw.psc0 = 2;
  485. else if (aib->esw.psc0 == 0 && aib->esw.p == 0)
  486. aib->esw.psc0 = 1;
  487. if (aib->esw.psc1 == 1)
  488. aib->esw.psc1 = 2;
  489. else if (aib->esw.psc1 == 0 && aib->esw.p == 1)
  490. aib->esw.psc1 = 1;
  491. }
  492. /*
  493. * Check if the aib a2 is still connected to the same attachment as
  494. * aib a1, the etv values differ by one and a2 is valid.
  495. */
  496. static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p)
  497. {
  498. int state_a1, state_a2;
  499. /* Paranoia check: e0/e1 should better be the same. */
  500. if (a1->esw.eacr.e0 != a2->esw.eacr.e0 ||
  501. a1->esw.eacr.e1 != a2->esw.eacr.e1)
  502. return 0;
  503. /* Still connected to the same etr ? */
  504. state_a1 = p ? a1->esw.psc1 : a1->esw.psc0;
  505. state_a2 = p ? a2->esw.psc1 : a2->esw.psc0;
  506. if (state_a1 == etr_lpsc_operational_step) {
  507. if (state_a2 != etr_lpsc_operational_step ||
  508. a1->edf1.net_id != a2->edf1.net_id ||
  509. a1->edf1.etr_id != a2->edf1.etr_id ||
  510. a1->edf1.etr_pn != a2->edf1.etr_pn)
  511. return 0;
  512. } else if (state_a2 != etr_lpsc_pps_mode)
  513. return 0;
  514. /* The ETV value of a2 needs to be ETV of a1 + 1. */
  515. if (a1->edf2.etv + 1 != a2->edf2.etv)
  516. return 0;
  517. if (!etr_port_valid(a2, p))
  518. return 0;
  519. return 1;
  520. }
  521. /*
  522. * The time is "clock". old is what we think the time is.
  523. * Adjust the value by a multiple of jiffies and add the delta to ntp.
  524. * "delay" is an approximation how long the synchronization took. If
  525. * the time correction is positive, then "delay" is subtracted from
  526. * the time difference and only the remaining part is passed to ntp.
  527. */
  528. static unsigned long long etr_adjust_time(unsigned long long old,
  529. unsigned long long clock,
  530. unsigned long long delay)
  531. {
  532. unsigned long long delta, ticks;
  533. struct timex adjust;
  534. if (clock > old) {
  535. /* It is later than we thought. */
  536. delta = ticks = clock - old;
  537. delta = ticks = (delta < delay) ? 0 : delta - delay;
  538. delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
  539. adjust.offset = ticks * (1000000 / HZ);
  540. } else {
  541. /* It is earlier than we thought. */
  542. delta = ticks = old - clock;
  543. delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
  544. delta = -delta;
  545. adjust.offset = -ticks * (1000000 / HZ);
  546. }
  547. jiffies_timer_cc += delta;
  548. if (adjust.offset != 0) {
  549. printk(KERN_NOTICE "etr: time adjusted by %li micro-seconds\n",
  550. adjust.offset);
  551. adjust.modes = ADJ_OFFSET_SINGLESHOT;
  552. do_adjtimex(&adjust);
  553. }
  554. return delta;
  555. }
  556. static struct {
  557. int in_sync;
  558. unsigned long long fixup_cc;
  559. } etr_sync;
  560. static void etr_sync_cpu_start(void *dummy)
  561. {
  562. etr_enable_sync_clock();
  563. /*
  564. * This looks like a busy wait loop but it isn't. etr_sync_cpus
  565. * is called on all other cpus while the TOD clocks is stopped.
  566. * __udelay will stop the cpu on an enabled wait psw until the
  567. * TOD is running again.
  568. */
  569. while (etr_sync.in_sync == 0) {
  570. __udelay(1);
  571. /*
  572. * A different cpu changes *in_sync. Therefore use
  573. * barrier() to force memory access.
  574. */
  575. barrier();
  576. }
  577. if (etr_sync.in_sync != 1)
  578. /* Didn't work. Clear per-cpu in sync bit again. */
  579. etr_disable_sync_clock(NULL);
  580. /*
  581. * This round of TOD syncing is done. Set the clock comparator
  582. * to the next tick and let the processor continue.
  583. */
  584. fixup_clock_comparator(etr_sync.fixup_cc);
  585. }
  586. static void etr_sync_cpu_end(void *dummy)
  587. {
  588. }
  589. /*
  590. * Sync the TOD clock using the port refered to by aibp. This port
  591. * has to be enabled and the other port has to be disabled. The
  592. * last eacr update has to be more than 1.6 seconds in the past.
  593. */
  594. static int etr_sync_clock(struct etr_aib *aib, int port)
  595. {
  596. struct etr_aib *sync_port;
  597. unsigned long long clock, old_clock, delay, delta;
  598. int follows;
  599. int rc;
  600. /* Check if the current aib is adjacent to the sync port aib. */
  601. sync_port = (port == 0) ? &etr_port0 : &etr_port1;
  602. follows = etr_aib_follows(sync_port, aib, port);
  603. memcpy(sync_port, aib, sizeof(*aib));
  604. if (!follows)
  605. return -EAGAIN;
  606. /*
  607. * Catch all other cpus and make them wait until we have
  608. * successfully synced the clock. smp_call_function will
  609. * return after all other cpus are in etr_sync_cpu_start.
  610. */
  611. memset(&etr_sync, 0, sizeof(etr_sync));
  612. preempt_disable();
  613. smp_call_function(etr_sync_cpu_start, NULL, 0, 0);
  614. local_irq_disable();
  615. etr_enable_sync_clock();
  616. /* Set clock to next OTE. */
  617. __ctl_set_bit(14, 21);
  618. __ctl_set_bit(0, 29);
  619. clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32;
  620. old_clock = get_clock();
  621. if (set_clock(clock) == 0) {
  622. __udelay(1); /* Wait for the clock to start. */
  623. __ctl_clear_bit(0, 29);
  624. __ctl_clear_bit(14, 21);
  625. etr_stetr(aib);
  626. /* Adjust Linux timing variables. */
  627. delay = (unsigned long long)
  628. (aib->edf2.etv - sync_port->edf2.etv) << 32;
  629. delta = etr_adjust_time(old_clock, clock, delay);
  630. etr_sync.fixup_cc = delta;
  631. fixup_clock_comparator(delta);
  632. /* Verify that the clock is properly set. */
  633. if (!etr_aib_follows(sync_port, aib, port)) {
  634. /* Didn't work. */
  635. etr_disable_sync_clock(NULL);
  636. etr_sync.in_sync = -EAGAIN;
  637. rc = -EAGAIN;
  638. } else {
  639. etr_sync.in_sync = 1;
  640. rc = 0;
  641. }
  642. } else {
  643. /* Could not set the clock ?!? */
  644. __ctl_clear_bit(0, 29);
  645. __ctl_clear_bit(14, 21);
  646. etr_disable_sync_clock(NULL);
  647. etr_sync.in_sync = -EAGAIN;
  648. rc = -EAGAIN;
  649. }
  650. local_irq_enable();
  651. smp_call_function(etr_sync_cpu_end,NULL,0,0);
  652. preempt_enable();
  653. return rc;
  654. }
  655. /*
  656. * Handle the immediate effects of the different events.
  657. * The port change event is used for online/offline changes.
  658. */
  659. static struct etr_eacr etr_handle_events(struct etr_eacr eacr)
  660. {
  661. if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events))
  662. eacr.es = 0;
  663. if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events))
  664. eacr.es = eacr.sl = 0;
  665. if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events))
  666. etr_port0_uptodate = etr_port1_uptodate = 0;
  667. if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) {
  668. if (eacr.e0)
  669. /*
  670. * Port change of an enabled port. We have to
  671. * assume that this can have caused an stepping
  672. * port switch.
  673. */
  674. etr_tolec = get_clock();
  675. eacr.p0 = etr_port0_online;
  676. if (!eacr.p0)
  677. eacr.e0 = 0;
  678. etr_port0_uptodate = 0;
  679. }
  680. if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) {
  681. if (eacr.e1)
  682. /*
  683. * Port change of an enabled port. We have to
  684. * assume that this can have caused an stepping
  685. * port switch.
  686. */
  687. etr_tolec = get_clock();
  688. eacr.p1 = etr_port1_online;
  689. if (!eacr.p1)
  690. eacr.e1 = 0;
  691. etr_port1_uptodate = 0;
  692. }
  693. clear_bit(ETR_EVENT_UPDATE, &etr_events);
  694. return eacr;
  695. }
  696. /*
  697. * Set up a timer that expires after the etr_tolec + 1.6 seconds if
  698. * one of the ports needs an update.
  699. */
  700. static void etr_set_tolec_timeout(unsigned long long now)
  701. {
  702. unsigned long micros;
  703. if ((!etr_eacr.p0 || etr_port0_uptodate) &&
  704. (!etr_eacr.p1 || etr_port1_uptodate))
  705. return;
  706. micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0;
  707. micros = (micros > 1600000) ? 0 : 1600000 - micros;
  708. mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1);
  709. }
  710. /*
  711. * Set up a time that expires after 1/2 second.
  712. */
  713. static void etr_set_sync_timeout(void)
  714. {
  715. mod_timer(&etr_timer, jiffies + HZ/2);
  716. }
  717. /*
  718. * Update the aib information for one or both ports.
  719. */
  720. static struct etr_eacr etr_handle_update(struct etr_aib *aib,
  721. struct etr_eacr eacr)
  722. {
  723. /* With both ports disabled the aib information is useless. */
  724. if (!eacr.e0 && !eacr.e1)
  725. return eacr;
  726. /* Update port0 or port1 with aib stored in etr_work_fn. */
  727. if (aib->esw.q == 0) {
  728. /* Information for port 0 stored. */
  729. if (eacr.p0 && !etr_port0_uptodate) {
  730. etr_port0 = *aib;
  731. if (etr_port0_online)
  732. etr_port0_uptodate = 1;
  733. }
  734. } else {
  735. /* Information for port 1 stored. */
  736. if (eacr.p1 && !etr_port1_uptodate) {
  737. etr_port1 = *aib;
  738. if (etr_port0_online)
  739. etr_port1_uptodate = 1;
  740. }
  741. }
  742. /*
  743. * Do not try to get the alternate port aib if the clock
  744. * is not in sync yet.
  745. */
  746. if (!eacr.es)
  747. return eacr;
  748. /*
  749. * If steai is available we can get the information about
  750. * the other port immediately. If only stetr is available the
  751. * data-port bit toggle has to be used.
  752. */
  753. if (test_bit(ETR_FLAG_STEAI, &etr_flags)) {
  754. if (eacr.p0 && !etr_port0_uptodate) {
  755. etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0);
  756. etr_port0_uptodate = 1;
  757. }
  758. if (eacr.p1 && !etr_port1_uptodate) {
  759. etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1);
  760. etr_port1_uptodate = 1;
  761. }
  762. } else {
  763. /*
  764. * One port was updated above, if the other
  765. * port is not uptodate toggle dp bit.
  766. */
  767. if ((eacr.p0 && !etr_port0_uptodate) ||
  768. (eacr.p1 && !etr_port1_uptodate))
  769. eacr.dp ^= 1;
  770. else
  771. eacr.dp = 0;
  772. }
  773. return eacr;
  774. }
  775. /*
  776. * Write new etr control register if it differs from the current one.
  777. * Return 1 if etr_tolec has been updated as well.
  778. */
  779. static void etr_update_eacr(struct etr_eacr eacr)
  780. {
  781. int dp_changed;
  782. if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0)
  783. /* No change, return. */
  784. return;
  785. /*
  786. * The disable of an active port of the change of the data port
  787. * bit can/will cause a change in the data port.
  788. */
  789. dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 ||
  790. (etr_eacr.dp ^ eacr.dp) != 0;
  791. etr_eacr = eacr;
  792. etr_setr(&etr_eacr);
  793. if (dp_changed)
  794. etr_tolec = get_clock();
  795. }
  796. /*
  797. * ETR tasklet. In this function you'll find the main logic. In
  798. * particular this is the only function that calls etr_update_eacr(),
  799. * it "controls" the etr control register.
  800. */
  801. static void etr_work_fn(struct work_struct *work)
  802. {
  803. unsigned long long now;
  804. struct etr_eacr eacr;
  805. struct etr_aib aib;
  806. int sync_port;
  807. /* Create working copy of etr_eacr. */
  808. eacr = etr_eacr;
  809. /* Check for the different events and their immediate effects. */
  810. eacr = etr_handle_events(eacr);
  811. /* Check if ETR is supposed to be active. */
  812. eacr.ea = eacr.p0 || eacr.p1;
  813. if (!eacr.ea) {
  814. /* Both ports offline. Reset everything. */
  815. eacr.dp = eacr.es = eacr.sl = 0;
  816. on_each_cpu(etr_disable_sync_clock, NULL, 0, 1);
  817. del_timer_sync(&etr_timer);
  818. etr_update_eacr(eacr);
  819. set_bit(ETR_FLAG_EACCES, &etr_flags);
  820. return;
  821. }
  822. /* Store aib to get the current ETR status word. */
  823. BUG_ON(etr_stetr(&aib) != 0);
  824. etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */
  825. now = get_clock();
  826. /*
  827. * Update the port information if the last stepping port change
  828. * or data port change is older than 1.6 seconds.
  829. */
  830. if (now >= etr_tolec + (1600000 << 12))
  831. eacr = etr_handle_update(&aib, eacr);
  832. /*
  833. * Select ports to enable. The prefered synchronization mode is PPS.
  834. * If a port can be enabled depends on a number of things:
  835. * 1) The port needs to be online and uptodate. A port is not
  836. * disabled just because it is not uptodate, but it is only
  837. * enabled if it is uptodate.
  838. * 2) The port needs to have the same mode (pps / etr).
  839. * 3) The port needs to be usable -> etr_port_valid() == 1
  840. * 4) To enable the second port the clock needs to be in sync.
  841. * 5) If both ports are useable and are ETR ports, the network id
  842. * has to be the same.
  843. * The eacr.sl bit is used to indicate etr mode vs. pps mode.
  844. */
  845. if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) {
  846. eacr.sl = 0;
  847. eacr.e0 = 1;
  848. if (!etr_mode_is_pps(etr_eacr))
  849. eacr.es = 0;
  850. if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode)
  851. eacr.e1 = 0;
  852. // FIXME: uptodate checks ?
  853. else if (etr_port0_uptodate && etr_port1_uptodate)
  854. eacr.e1 = 1;
  855. sync_port = (etr_port0_uptodate &&
  856. etr_port_valid(&etr_port0, 0)) ? 0 : -1;
  857. clear_bit(ETR_FLAG_EACCES, &etr_flags);
  858. } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) {
  859. eacr.sl = 0;
  860. eacr.e0 = 0;
  861. eacr.e1 = 1;
  862. if (!etr_mode_is_pps(etr_eacr))
  863. eacr.es = 0;
  864. sync_port = (etr_port1_uptodate &&
  865. etr_port_valid(&etr_port1, 1)) ? 1 : -1;
  866. clear_bit(ETR_FLAG_EACCES, &etr_flags);
  867. } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) {
  868. eacr.sl = 1;
  869. eacr.e0 = 1;
  870. if (!etr_mode_is_etr(etr_eacr))
  871. eacr.es = 0;
  872. if (!eacr.es || !eacr.p1 ||
  873. aib.esw.psc1 != etr_lpsc_operational_alt)
  874. eacr.e1 = 0;
  875. else if (etr_port0_uptodate && etr_port1_uptodate &&
  876. etr_compare_network(&etr_port0, &etr_port1))
  877. eacr.e1 = 1;
  878. sync_port = (etr_port0_uptodate &&
  879. etr_port_valid(&etr_port0, 0)) ? 0 : -1;
  880. clear_bit(ETR_FLAG_EACCES, &etr_flags);
  881. } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) {
  882. eacr.sl = 1;
  883. eacr.e0 = 0;
  884. eacr.e1 = 1;
  885. if (!etr_mode_is_etr(etr_eacr))
  886. eacr.es = 0;
  887. sync_port = (etr_port1_uptodate &&
  888. etr_port_valid(&etr_port1, 1)) ? 1 : -1;
  889. clear_bit(ETR_FLAG_EACCES, &etr_flags);
  890. } else {
  891. /* Both ports not usable. */
  892. eacr.es = eacr.sl = 0;
  893. sync_port = -1;
  894. set_bit(ETR_FLAG_EACCES, &etr_flags);
  895. }
  896. /*
  897. * If the clock is in sync just update the eacr and return.
  898. * If there is no valid sync port wait for a port update.
  899. */
  900. if (eacr.es || sync_port < 0) {
  901. etr_update_eacr(eacr);
  902. etr_set_tolec_timeout(now);
  903. return;
  904. }
  905. /*
  906. * Prepare control register for clock syncing
  907. * (reset data port bit, set sync check control.
  908. */
  909. eacr.dp = 0;
  910. eacr.es = 1;
  911. /*
  912. * Update eacr and try to synchronize the clock. If the update
  913. * of eacr caused a stepping port switch (or if we have to
  914. * assume that a stepping port switch has occured) or the
  915. * clock syncing failed, reset the sync check control bit
  916. * and set up a timer to try again after 0.5 seconds
  917. */
  918. etr_update_eacr(eacr);
  919. if (now < etr_tolec + (1600000 << 12) ||
  920. etr_sync_clock(&aib, sync_port) != 0) {
  921. /* Sync failed. Try again in 1/2 second. */
  922. eacr.es = 0;
  923. etr_update_eacr(eacr);
  924. etr_set_sync_timeout();
  925. } else
  926. etr_set_tolec_timeout(now);
  927. }
  928. /*
  929. * Sysfs interface functions
  930. */
  931. static struct sysdev_class etr_sysclass = {
  932. .name = "etr",
  933. };
  934. static struct sys_device etr_port0_dev = {
  935. .id = 0,
  936. .cls = &etr_sysclass,
  937. };
  938. static struct sys_device etr_port1_dev = {
  939. .id = 1,
  940. .cls = &etr_sysclass,
  941. };
  942. /*
  943. * ETR class attributes
  944. */
  945. static ssize_t etr_stepping_port_show(struct sysdev_class *class, char *buf)
  946. {
  947. return sprintf(buf, "%i\n", etr_port0.esw.p);
  948. }
  949. static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL);
  950. static ssize_t etr_stepping_mode_show(struct sysdev_class *class, char *buf)
  951. {
  952. char *mode_str;
  953. if (etr_mode_is_pps(etr_eacr))
  954. mode_str = "pps";
  955. else if (etr_mode_is_etr(etr_eacr))
  956. mode_str = "etr";
  957. else
  958. mode_str = "local";
  959. return sprintf(buf, "%s\n", mode_str);
  960. }
  961. static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL);
  962. /*
  963. * ETR port attributes
  964. */
  965. static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev)
  966. {
  967. if (dev == &etr_port0_dev)
  968. return etr_port0_online ? &etr_port0 : NULL;
  969. else
  970. return etr_port1_online ? &etr_port1 : NULL;
  971. }
  972. static ssize_t etr_online_show(struct sys_device *dev, char *buf)
  973. {
  974. unsigned int online;
  975. online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online;
  976. return sprintf(buf, "%i\n", online);
  977. }
  978. static ssize_t etr_online_store(struct sys_device *dev,
  979. const char *buf, size_t count)
  980. {
  981. unsigned int value;
  982. value = simple_strtoul(buf, NULL, 0);
  983. if (value != 0 && value != 1)
  984. return -EINVAL;
  985. if (test_bit(ETR_FLAG_ENOSYS, &etr_flags))
  986. return -ENOSYS;
  987. if (dev == &etr_port0_dev) {
  988. if (etr_port0_online == value)
  989. return count; /* Nothing to do. */
  990. etr_port0_online = value;
  991. set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
  992. schedule_work(&etr_work);
  993. } else {
  994. if (etr_port1_online == value)
  995. return count; /* Nothing to do. */
  996. etr_port1_online = value;
  997. set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
  998. schedule_work(&etr_work);
  999. }
  1000. return count;
  1001. }
  1002. static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store);
  1003. static ssize_t etr_stepping_control_show(struct sys_device *dev, char *buf)
  1004. {
  1005. return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
  1006. etr_eacr.e0 : etr_eacr.e1);
  1007. }
  1008. static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL);
  1009. static ssize_t etr_mode_code_show(struct sys_device *dev, char *buf)
  1010. {
  1011. if (!etr_port0_online && !etr_port1_online)
  1012. /* Status word is not uptodate if both ports are offline. */
  1013. return -ENODATA;
  1014. return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
  1015. etr_port0.esw.psc0 : etr_port0.esw.psc1);
  1016. }
  1017. static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL);
  1018. static ssize_t etr_untuned_show(struct sys_device *dev, char *buf)
  1019. {
  1020. struct etr_aib *aib = etr_aib_from_dev(dev);
  1021. if (!aib || !aib->slsw.v1)
  1022. return -ENODATA;
  1023. return sprintf(buf, "%i\n", aib->edf1.u);
  1024. }
  1025. static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL);
  1026. static ssize_t etr_network_id_show(struct sys_device *dev, char *buf)
  1027. {
  1028. struct etr_aib *aib = etr_aib_from_dev(dev);
  1029. if (!aib || !aib->slsw.v1)
  1030. return -ENODATA;
  1031. return sprintf(buf, "%i\n", aib->edf1.net_id);
  1032. }
  1033. static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL);
  1034. static ssize_t etr_id_show(struct sys_device *dev, char *buf)
  1035. {
  1036. struct etr_aib *aib = etr_aib_from_dev(dev);
  1037. if (!aib || !aib->slsw.v1)
  1038. return -ENODATA;
  1039. return sprintf(buf, "%i\n", aib->edf1.etr_id);
  1040. }
  1041. static SYSDEV_ATTR(id, 0400, etr_id_show, NULL);
  1042. static ssize_t etr_port_number_show(struct sys_device *dev, char *buf)
  1043. {
  1044. struct etr_aib *aib = etr_aib_from_dev(dev);
  1045. if (!aib || !aib->slsw.v1)
  1046. return -ENODATA;
  1047. return sprintf(buf, "%i\n", aib->edf1.etr_pn);
  1048. }
  1049. static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL);
  1050. static ssize_t etr_coupled_show(struct sys_device *dev, char *buf)
  1051. {
  1052. struct etr_aib *aib = etr_aib_from_dev(dev);
  1053. if (!aib || !aib->slsw.v3)
  1054. return -ENODATA;
  1055. return sprintf(buf, "%i\n", aib->edf3.c);
  1056. }
  1057. static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL);
  1058. static ssize_t etr_local_time_show(struct sys_device *dev, char *buf)
  1059. {
  1060. struct etr_aib *aib = etr_aib_from_dev(dev);
  1061. if (!aib || !aib->slsw.v3)
  1062. return -ENODATA;
  1063. return sprintf(buf, "%i\n", aib->edf3.blto);
  1064. }
  1065. static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL);
  1066. static ssize_t etr_utc_offset_show(struct sys_device *dev, char *buf)
  1067. {
  1068. struct etr_aib *aib = etr_aib_from_dev(dev);
  1069. if (!aib || !aib->slsw.v3)
  1070. return -ENODATA;
  1071. return sprintf(buf, "%i\n", aib->edf3.buo);
  1072. }
  1073. static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL);
  1074. static struct sysdev_attribute *etr_port_attributes[] = {
  1075. &attr_online,
  1076. &attr_stepping_control,
  1077. &attr_state_code,
  1078. &attr_untuned,
  1079. &attr_network,
  1080. &attr_id,
  1081. &attr_port,
  1082. &attr_coupled,
  1083. &attr_local_time,
  1084. &attr_utc_offset,
  1085. NULL
  1086. };
  1087. static int __init etr_register_port(struct sys_device *dev)
  1088. {
  1089. struct sysdev_attribute **attr;
  1090. int rc;
  1091. rc = sysdev_register(dev);
  1092. if (rc)
  1093. goto out;
  1094. for (attr = etr_port_attributes; *attr; attr++) {
  1095. rc = sysdev_create_file(dev, *attr);
  1096. if (rc)
  1097. goto out_unreg;
  1098. }
  1099. return 0;
  1100. out_unreg:
  1101. for (; attr >= etr_port_attributes; attr--)
  1102. sysdev_remove_file(dev, *attr);
  1103. sysdev_unregister(dev);
  1104. out:
  1105. return rc;
  1106. }
  1107. static void __init etr_unregister_port(struct sys_device *dev)
  1108. {
  1109. struct sysdev_attribute **attr;
  1110. for (attr = etr_port_attributes; *attr; attr++)
  1111. sysdev_remove_file(dev, *attr);
  1112. sysdev_unregister(dev);
  1113. }
  1114. static int __init etr_init_sysfs(void)
  1115. {
  1116. int rc;
  1117. rc = sysdev_class_register(&etr_sysclass);
  1118. if (rc)
  1119. goto out;
  1120. rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port);
  1121. if (rc)
  1122. goto out_unreg_class;
  1123. rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode);
  1124. if (rc)
  1125. goto out_remove_stepping_port;
  1126. rc = etr_register_port(&etr_port0_dev);
  1127. if (rc)
  1128. goto out_remove_stepping_mode;
  1129. rc = etr_register_port(&etr_port1_dev);
  1130. if (rc)
  1131. goto out_remove_port0;
  1132. return 0;
  1133. out_remove_port0:
  1134. etr_unregister_port(&etr_port0_dev);
  1135. out_remove_stepping_mode:
  1136. sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode);
  1137. out_remove_stepping_port:
  1138. sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port);
  1139. out_unreg_class:
  1140. sysdev_class_unregister(&etr_sysclass);
  1141. out:
  1142. return rc;
  1143. }
  1144. device_initcall(etr_init_sysfs);