Kconfig 2.9 KB

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  1. config PPC_CELL
  2. bool
  3. default n
  4. config PPC_CELL_NATIVE
  5. bool
  6. select PPC_CELL
  7. select PPC_DCR_MMIO
  8. select PPC_OF_PLATFORM_PCI
  9. select PPC_INDIRECT_IO
  10. select PPC_NATIVE
  11. select MPIC
  12. select IBM_NEW_EMAC_EMAC4
  13. select IBM_NEW_EMAC_RGMII
  14. select IBM_NEW_EMAC_ZMII #test only
  15. select IBM_NEW_EMAC_TAH #test only
  16. default n
  17. config PPC_IBM_CELL_BLADE
  18. bool "IBM Cell Blade"
  19. depends on PPC_MULTIPLATFORM && PPC64
  20. select PPC_CELL_NATIVE
  21. select PPC_RTAS
  22. select MMIO_NVRAM
  23. select PPC_UDBG_16550
  24. select UDBG_RTAS_CONSOLE
  25. config PPC_CELLEB
  26. bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
  27. depends on PPC_MULTIPLATFORM && PPC64
  28. select PPC_CELL
  29. select PPC_CELL_NATIVE
  30. select PPC_RTAS
  31. select PPC_INDIRECT_IO
  32. select PPC_OF_PLATFORM_PCI
  33. select HAS_TXX9_SERIAL
  34. select PPC_UDBG_BEAT
  35. select USB_OHCI_BIG_ENDIAN_MMIO
  36. select USB_EHCI_BIG_ENDIAN_MMIO
  37. menu "Cell Broadband Engine options"
  38. depends on PPC_CELL
  39. config SPU_FS
  40. tristate "SPU file system"
  41. default m
  42. depends on PPC_CELL
  43. select SPU_BASE
  44. select MEMORY_HOTPLUG
  45. help
  46. The SPU file system is used to access Synergistic Processing
  47. Units on machines implementing the Broadband Processor
  48. Architecture.
  49. config SPU_FS_64K_LS
  50. bool "Use 64K pages to map SPE local store"
  51. # we depend on PPC_MM_SLICES for now rather than selecting
  52. # it because we depend on hugetlbfs hooks being present. We
  53. # will fix that when the generic code has been improved to
  54. # not require hijacking hugetlbfs hooks.
  55. depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES
  56. default y
  57. select PPC_HAS_HASH_64K
  58. help
  59. This option causes SPE local stores to be mapped in process
  60. address spaces using 64K pages while the rest of the kernel
  61. uses 4K pages. This can improve performances of applications
  62. using multiple SPEs by lowering the TLB pressure on them.
  63. config SPU_TRACE
  64. tristate "SPU event tracing support"
  65. depends on SPU_FS && MARKERS
  66. help
  67. This option allows reading a trace of spu-related events through
  68. the sputrace file in procfs.
  69. config SPU_BASE
  70. bool
  71. default n
  72. config CBE_RAS
  73. bool "RAS features for bare metal Cell BE"
  74. depends on PPC_CELL_NATIVE
  75. default y
  76. config CBE_THERM
  77. tristate "CBE thermal support"
  78. default m
  79. depends on CBE_RAS
  80. config CBE_CPUFREQ
  81. tristate "CBE frequency scaling"
  82. depends on CBE_RAS && CPU_FREQ
  83. default m
  84. help
  85. This adds the cpufreq driver for Cell BE processors.
  86. For details, take a look at <file:Documentation/cpu-freq/>.
  87. If you don't have such processor, say N
  88. config CBE_CPUFREQ_PMI
  89. tristate "CBE frequency scaling using PMI interface"
  90. depends on CBE_CPUFREQ && PPC_PMI && EXPERIMENTAL
  91. default n
  92. help
  93. Select this, if you want to use the PMI interface
  94. to switch frequencies. Using PMI, the
  95. processor will not only be able to run at lower speed,
  96. but also at lower core voltage.
  97. endmenu
  98. config OPROFILE_CELL
  99. def_bool y
  100. depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y)