platsmp.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256
  1. /*
  2. * linux/arch/arm/mach-realview/platsmp.c
  3. *
  4. * Copyright (C) 2002 ARM Ltd.
  5. * All Rights Reserved
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/errno.h>
  13. #include <linux/delay.h>
  14. #include <linux/device.h>
  15. #include <linux/smp.h>
  16. #include <asm/cacheflush.h>
  17. #include <asm/hardware.h>
  18. #include <asm/io.h>
  19. #include <asm/mach-types.h>
  20. #include <asm/arch/board-eb.h>
  21. #include <asm/arch/board-pb11mp.h>
  22. #include <asm/arch/scu.h>
  23. extern void realview_secondary_startup(void);
  24. /*
  25. * control for which core is the next to come out of the secondary
  26. * boot "holding pen"
  27. */
  28. volatile int __cpuinitdata pen_release = -1;
  29. static unsigned int __init get_core_count(void)
  30. {
  31. unsigned int ncores;
  32. void __iomem *scu_base = 0;
  33. if (machine_is_realview_eb() && core_tile_eb11mp())
  34. scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
  35. else if (machine_is_realview_pb11mp())
  36. scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
  37. if (scu_base) {
  38. ncores = __raw_readl(scu_base + SCU_CONFIG);
  39. ncores = (ncores & 0x03) + 1;
  40. } else
  41. ncores = 1;
  42. return ncores;
  43. }
  44. /*
  45. * Setup the SCU
  46. */
  47. static void scu_enable(void)
  48. {
  49. u32 scu_ctrl;
  50. void __iomem *scu_base;
  51. if (machine_is_realview_eb() && core_tile_eb11mp())
  52. scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
  53. else if (machine_is_realview_pb11mp())
  54. scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
  55. else
  56. BUG();
  57. scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
  58. scu_ctrl |= 1;
  59. __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
  60. }
  61. static DEFINE_SPINLOCK(boot_lock);
  62. void __cpuinit platform_secondary_init(unsigned int cpu)
  63. {
  64. /*
  65. * the primary core may have used a "cross call" soft interrupt
  66. * to get this processor out of WFI in the BootMonitor - make
  67. * sure that we are no longer being sent this soft interrupt
  68. */
  69. smp_cross_call_done(cpumask_of_cpu(cpu));
  70. /*
  71. * if any interrupts are already enabled for the primary
  72. * core (e.g. timer irq), then they will not have been enabled
  73. * for us: do so
  74. */
  75. if (machine_is_realview_eb() && core_tile_eb11mp())
  76. gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
  77. else if (machine_is_realview_pb11mp())
  78. gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
  79. /*
  80. * let the primary processor know we're out of the
  81. * pen, then head off into the C entry point
  82. */
  83. pen_release = -1;
  84. smp_wmb();
  85. /*
  86. * Synchronise with the boot thread.
  87. */
  88. spin_lock(&boot_lock);
  89. spin_unlock(&boot_lock);
  90. }
  91. int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  92. {
  93. unsigned long timeout;
  94. /*
  95. * set synchronisation state between this boot processor
  96. * and the secondary one
  97. */
  98. spin_lock(&boot_lock);
  99. /*
  100. * The secondary processor is waiting to be released from
  101. * the holding pen - release it, then wait for it to flag
  102. * that it has been released by resetting pen_release.
  103. *
  104. * Note that "pen_release" is the hardware CPU ID, whereas
  105. * "cpu" is Linux's internal ID.
  106. */
  107. pen_release = cpu;
  108. flush_cache_all();
  109. /*
  110. * XXX
  111. *
  112. * This is a later addition to the booting protocol: the
  113. * bootMonitor now puts secondary cores into WFI, so
  114. * poke_milo() no longer gets the cores moving; we need
  115. * to send a soft interrupt to wake the secondary core.
  116. * Use smp_cross_call() for this, since there's little
  117. * point duplicating the code here
  118. */
  119. smp_cross_call(cpumask_of_cpu(cpu));
  120. timeout = jiffies + (1 * HZ);
  121. while (time_before(jiffies, timeout)) {
  122. smp_rmb();
  123. if (pen_release == -1)
  124. break;
  125. udelay(10);
  126. }
  127. /*
  128. * now the secondary core is starting up let it run its
  129. * calibrations, then wait for it to finish
  130. */
  131. spin_unlock(&boot_lock);
  132. return pen_release != -1 ? -ENOSYS : 0;
  133. }
  134. static void __init poke_milo(void)
  135. {
  136. extern void secondary_startup(void);
  137. /* nobody is to be released from the pen yet */
  138. pen_release = -1;
  139. /*
  140. * write the address of secondary startup into the system-wide
  141. * flags register, then clear the bottom two bits, which is what
  142. * BootMonitor is waiting for
  143. */
  144. #if 1
  145. #define REALVIEW_SYS_FLAGSS_OFFSET 0x30
  146. __raw_writel(virt_to_phys(realview_secondary_startup),
  147. __io_address(REALVIEW_SYS_BASE) +
  148. REALVIEW_SYS_FLAGSS_OFFSET);
  149. #define REALVIEW_SYS_FLAGSC_OFFSET 0x34
  150. __raw_writel(3,
  151. __io_address(REALVIEW_SYS_BASE) +
  152. REALVIEW_SYS_FLAGSC_OFFSET);
  153. #endif
  154. mb();
  155. }
  156. /*
  157. * Initialise the CPU possible map early - this describes the CPUs
  158. * which may be present or become present in the system.
  159. */
  160. void __init smp_init_cpus(void)
  161. {
  162. unsigned int i, ncores = get_core_count();
  163. for (i = 0; i < ncores; i++)
  164. cpu_set(i, cpu_possible_map);
  165. }
  166. void __init smp_prepare_cpus(unsigned int max_cpus)
  167. {
  168. unsigned int ncores = get_core_count();
  169. unsigned int cpu = smp_processor_id();
  170. int i;
  171. /* sanity check */
  172. if (ncores == 0) {
  173. printk(KERN_ERR
  174. "Realview: strange CM count of 0? Default to 1\n");
  175. ncores = 1;
  176. }
  177. if (ncores > NR_CPUS) {
  178. printk(KERN_WARNING
  179. "Realview: no. of cores (%d) greater than configured "
  180. "maximum of %d - clipping\n",
  181. ncores, NR_CPUS);
  182. ncores = NR_CPUS;
  183. }
  184. smp_store_cpu_info(cpu);
  185. /*
  186. * are we trying to boot more cores than exist?
  187. */
  188. if (max_cpus > ncores)
  189. max_cpus = ncores;
  190. #ifdef CONFIG_LOCAL_TIMERS
  191. /*
  192. * Enable the local timer for primary CPU. If the device is
  193. * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
  194. * realview_timer_init
  195. */
  196. if ((machine_is_realview_eb() && core_tile_eb11mp()) ||
  197. machine_is_realview_pb11mp())
  198. local_timer_setup(cpu);
  199. #endif
  200. /*
  201. * Initialise the present map, which describes the set of CPUs
  202. * actually populated at the present time.
  203. */
  204. for (i = 0; i < max_cpus; i++)
  205. cpu_set(i, cpu_present_map);
  206. /*
  207. * Initialise the SCU if there are more than one CPU and let
  208. * them know where to start. Note that, on modern versions of
  209. * MILO, the "poke" doesn't actually do anything until each
  210. * individual core is sent a soft interrupt to get it out of
  211. * WFI
  212. */
  213. if (max_cpus > 1) {
  214. scu_enable();
  215. poke_milo();
  216. }
  217. }