x2apic_phys.c 5.1 KB

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  1. #include <linux/threads.h>
  2. #include <linux/cpumask.h>
  3. #include <linux/string.h>
  4. #include <linux/kernel.h>
  5. #include <linux/ctype.h>
  6. #include <linux/init.h>
  7. #include <linux/dmar.h>
  8. #include <asm/smp.h>
  9. #include <asm/apic.h>
  10. #include <asm/ipi.h>
  11. int x2apic_phys;
  12. static int set_x2apic_phys_mode(char *arg)
  13. {
  14. x2apic_phys = 1;
  15. return 0;
  16. }
  17. early_param("x2apic_phys", set_x2apic_phys_mode);
  18. static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  19. {
  20. if (x2apic_phys)
  21. return x2apic_enabled();
  22. else
  23. return 0;
  24. }
  25. /*
  26. * need to use more than cpu 0, because we need more vectors when
  27. * MSI-X are used.
  28. */
  29. static const struct cpumask *x2apic_target_cpus(void)
  30. {
  31. return cpu_online_mask;
  32. }
  33. static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
  34. {
  35. cpumask_clear(retmask);
  36. cpumask_set_cpu(cpu, retmask);
  37. }
  38. static void __x2apic_send_IPI_dest(unsigned int apicid, int vector,
  39. unsigned int dest)
  40. {
  41. unsigned long cfg;
  42. cfg = __prepare_ICR(0, vector, dest);
  43. /*
  44. * send the IPI.
  45. */
  46. native_x2apic_icr_write(cfg, apicid);
  47. }
  48. static void
  49. __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
  50. {
  51. unsigned long query_cpu;
  52. unsigned long this_cpu;
  53. unsigned long flags;
  54. x2apic_wrmsr_fence();
  55. local_irq_save(flags);
  56. this_cpu = smp_processor_id();
  57. for_each_cpu(query_cpu, mask) {
  58. if (apic_dest == APIC_DEST_ALLBUT && this_cpu == query_cpu)
  59. continue;
  60. __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
  61. vector, APIC_DEST_PHYSICAL);
  62. }
  63. local_irq_restore(flags);
  64. }
  65. static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
  66. {
  67. __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
  68. }
  69. static void
  70. x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
  71. {
  72. __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
  73. }
  74. static void x2apic_send_IPI_allbutself(int vector)
  75. {
  76. __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT);
  77. }
  78. static void x2apic_send_IPI_all(int vector)
  79. {
  80. __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
  81. }
  82. static int x2apic_apic_id_registered(void)
  83. {
  84. return 1;
  85. }
  86. static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
  87. {
  88. /*
  89. * We're using fixed IRQ delivery, can only return one phys APIC ID.
  90. * May as well be the first.
  91. */
  92. int cpu = cpumask_first(cpumask);
  93. if ((unsigned)cpu < nr_cpu_ids)
  94. return per_cpu(x86_cpu_to_apicid, cpu);
  95. else
  96. return BAD_APICID;
  97. }
  98. static unsigned int
  99. x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
  100. const struct cpumask *andmask)
  101. {
  102. int cpu;
  103. /*
  104. * We're using fixed IRQ delivery, can only return one phys APIC ID.
  105. * May as well be the first.
  106. */
  107. for_each_cpu_and(cpu, cpumask, andmask) {
  108. if (cpumask_test_cpu(cpu, cpu_online_mask))
  109. break;
  110. }
  111. return per_cpu(x86_cpu_to_apicid, cpu);
  112. }
  113. static unsigned int x2apic_phys_get_apic_id(unsigned long x)
  114. {
  115. return x;
  116. }
  117. static unsigned long set_apic_id(unsigned int id)
  118. {
  119. return id;
  120. }
  121. static int x2apic_phys_pkg_id(int initial_apicid, int index_msb)
  122. {
  123. return initial_apicid >> index_msb;
  124. }
  125. static void x2apic_send_IPI_self(int vector)
  126. {
  127. apic_write(APIC_SELF_IPI, vector);
  128. }
  129. static void init_x2apic_ldr(void)
  130. {
  131. }
  132. static int x2apic_phys_probe(void)
  133. {
  134. if (x2apic_mode && x2apic_phys)
  135. return 1;
  136. return apic == &apic_x2apic_phys;
  137. }
  138. struct apic apic_x2apic_phys = {
  139. .name = "physical x2apic",
  140. .probe = x2apic_phys_probe,
  141. .acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
  142. .apic_id_registered = x2apic_apic_id_registered,
  143. .irq_delivery_mode = dest_Fixed,
  144. .irq_dest_mode = 0, /* physical */
  145. .target_cpus = x2apic_target_cpus,
  146. .disable_esr = 0,
  147. .dest_logical = 0,
  148. .check_apicid_used = NULL,
  149. .check_apicid_present = NULL,
  150. .vector_allocation_domain = x2apic_vector_allocation_domain,
  151. .init_apic_ldr = init_x2apic_ldr,
  152. .ioapic_phys_id_map = NULL,
  153. .setup_apic_routing = NULL,
  154. .multi_timer_check = NULL,
  155. .cpu_present_to_apicid = default_cpu_present_to_apicid,
  156. .apicid_to_cpu_present = NULL,
  157. .setup_portio_remap = NULL,
  158. .check_phys_apicid_present = default_check_phys_apicid_present,
  159. .enable_apic_mode = NULL,
  160. .phys_pkg_id = x2apic_phys_pkg_id,
  161. .mps_oem_check = NULL,
  162. .get_apic_id = x2apic_phys_get_apic_id,
  163. .set_apic_id = set_apic_id,
  164. .apic_id_mask = 0xFFFFFFFFu,
  165. .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
  166. .cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and,
  167. .send_IPI_mask = x2apic_send_IPI_mask,
  168. .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself,
  169. .send_IPI_allbutself = x2apic_send_IPI_allbutself,
  170. .send_IPI_all = x2apic_send_IPI_all,
  171. .send_IPI_self = x2apic_send_IPI_self,
  172. .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
  173. .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
  174. .wait_for_init_deassert = NULL,
  175. .smp_callin_clear_local_apic = NULL,
  176. .inquire_remote_apic = NULL,
  177. .read = native_apic_msr_read,
  178. .write = native_apic_msr_write,
  179. .icr_read = native_x2apic_icr_read,
  180. .icr_write = native_x2apic_icr_write,
  181. .wait_icr_idle = native_x2apic_wait_icr_idle,
  182. .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
  183. };