r600.c 115 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/slab.h>
  29. #include <linux/seq_file.h>
  30. #include <linux/firmware.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/module.h>
  33. #include "drmP.h"
  34. #include "radeon_drm.h"
  35. #include "radeon.h"
  36. #include "radeon_asic.h"
  37. #include "radeon_mode.h"
  38. #include "r600d.h"
  39. #include "atom.h"
  40. #include "avivod.h"
  41. #define PFP_UCODE_SIZE 576
  42. #define PM4_UCODE_SIZE 1792
  43. #define RLC_UCODE_SIZE 768
  44. #define R700_PFP_UCODE_SIZE 848
  45. #define R700_PM4_UCODE_SIZE 1360
  46. #define R700_RLC_UCODE_SIZE 1024
  47. #define EVERGREEN_PFP_UCODE_SIZE 1120
  48. #define EVERGREEN_PM4_UCODE_SIZE 1376
  49. #define EVERGREEN_RLC_UCODE_SIZE 768
  50. #define CAYMAN_RLC_UCODE_SIZE 1024
  51. #define ARUBA_RLC_UCODE_SIZE 1536
  52. /* Firmware Names */
  53. MODULE_FIRMWARE("radeon/R600_pfp.bin");
  54. MODULE_FIRMWARE("radeon/R600_me.bin");
  55. MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  56. MODULE_FIRMWARE("radeon/RV610_me.bin");
  57. MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  58. MODULE_FIRMWARE("radeon/RV630_me.bin");
  59. MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  60. MODULE_FIRMWARE("radeon/RV620_me.bin");
  61. MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  62. MODULE_FIRMWARE("radeon/RV635_me.bin");
  63. MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  64. MODULE_FIRMWARE("radeon/RV670_me.bin");
  65. MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  66. MODULE_FIRMWARE("radeon/RS780_me.bin");
  67. MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  68. MODULE_FIRMWARE("radeon/RV770_me.bin");
  69. MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  70. MODULE_FIRMWARE("radeon/RV730_me.bin");
  71. MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  72. MODULE_FIRMWARE("radeon/RV710_me.bin");
  73. MODULE_FIRMWARE("radeon/R600_rlc.bin");
  74. MODULE_FIRMWARE("radeon/R700_rlc.bin");
  75. MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  76. MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  77. MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  78. MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  79. MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  80. MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  81. MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  82. MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  83. MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  84. MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  85. MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  86. MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  87. MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  88. MODULE_FIRMWARE("radeon/PALM_me.bin");
  89. MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  90. MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
  91. MODULE_FIRMWARE("radeon/SUMO_me.bin");
  92. MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
  93. MODULE_FIRMWARE("radeon/SUMO2_me.bin");
  94. int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  95. /* r600,rv610,rv630,rv620,rv635,rv670 */
  96. int r600_mc_wait_for_idle(struct radeon_device *rdev);
  97. void r600_gpu_init(struct radeon_device *rdev);
  98. void r600_fini(struct radeon_device *rdev);
  99. void r600_irq_disable(struct radeon_device *rdev);
  100. static void r600_pcie_gen2_enable(struct radeon_device *rdev);
  101. /* get temperature in millidegrees */
  102. int rv6xx_get_temp(struct radeon_device *rdev)
  103. {
  104. u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
  105. ASIC_T_SHIFT;
  106. int actual_temp = temp & 0xff;
  107. if (temp & 0x100)
  108. actual_temp -= 256;
  109. return actual_temp * 1000;
  110. }
  111. void r600_pm_get_dynpm_state(struct radeon_device *rdev)
  112. {
  113. int i;
  114. rdev->pm.dynpm_can_upclock = true;
  115. rdev->pm.dynpm_can_downclock = true;
  116. /* power state array is low to high, default is first */
  117. if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
  118. int min_power_state_index = 0;
  119. if (rdev->pm.num_power_states > 2)
  120. min_power_state_index = 1;
  121. switch (rdev->pm.dynpm_planned_action) {
  122. case DYNPM_ACTION_MINIMUM:
  123. rdev->pm.requested_power_state_index = min_power_state_index;
  124. rdev->pm.requested_clock_mode_index = 0;
  125. rdev->pm.dynpm_can_downclock = false;
  126. break;
  127. case DYNPM_ACTION_DOWNCLOCK:
  128. if (rdev->pm.current_power_state_index == min_power_state_index) {
  129. rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  130. rdev->pm.dynpm_can_downclock = false;
  131. } else {
  132. if (rdev->pm.active_crtc_count > 1) {
  133. for (i = 0; i < rdev->pm.num_power_states; i++) {
  134. if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
  135. continue;
  136. else if (i >= rdev->pm.current_power_state_index) {
  137. rdev->pm.requested_power_state_index =
  138. rdev->pm.current_power_state_index;
  139. break;
  140. } else {
  141. rdev->pm.requested_power_state_index = i;
  142. break;
  143. }
  144. }
  145. } else {
  146. if (rdev->pm.current_power_state_index == 0)
  147. rdev->pm.requested_power_state_index =
  148. rdev->pm.num_power_states - 1;
  149. else
  150. rdev->pm.requested_power_state_index =
  151. rdev->pm.current_power_state_index - 1;
  152. }
  153. }
  154. rdev->pm.requested_clock_mode_index = 0;
  155. /* don't use the power state if crtcs are active and no display flag is set */
  156. if ((rdev->pm.active_crtc_count > 0) &&
  157. (rdev->pm.power_state[rdev->pm.requested_power_state_index].
  158. clock_info[rdev->pm.requested_clock_mode_index].flags &
  159. RADEON_PM_MODE_NO_DISPLAY)) {
  160. rdev->pm.requested_power_state_index++;
  161. }
  162. break;
  163. case DYNPM_ACTION_UPCLOCK:
  164. if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
  165. rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  166. rdev->pm.dynpm_can_upclock = false;
  167. } else {
  168. if (rdev->pm.active_crtc_count > 1) {
  169. for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
  170. if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
  171. continue;
  172. else if (i <= rdev->pm.current_power_state_index) {
  173. rdev->pm.requested_power_state_index =
  174. rdev->pm.current_power_state_index;
  175. break;
  176. } else {
  177. rdev->pm.requested_power_state_index = i;
  178. break;
  179. }
  180. }
  181. } else
  182. rdev->pm.requested_power_state_index =
  183. rdev->pm.current_power_state_index + 1;
  184. }
  185. rdev->pm.requested_clock_mode_index = 0;
  186. break;
  187. case DYNPM_ACTION_DEFAULT:
  188. rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
  189. rdev->pm.requested_clock_mode_index = 0;
  190. rdev->pm.dynpm_can_upclock = false;
  191. break;
  192. case DYNPM_ACTION_NONE:
  193. default:
  194. DRM_ERROR("Requested mode for not defined action\n");
  195. return;
  196. }
  197. } else {
  198. /* XXX select a power state based on AC/DC, single/dualhead, etc. */
  199. /* for now just select the first power state and switch between clock modes */
  200. /* power state array is low to high, default is first (0) */
  201. if (rdev->pm.active_crtc_count > 1) {
  202. rdev->pm.requested_power_state_index = -1;
  203. /* start at 1 as we don't want the default mode */
  204. for (i = 1; i < rdev->pm.num_power_states; i++) {
  205. if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
  206. continue;
  207. else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
  208. (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
  209. rdev->pm.requested_power_state_index = i;
  210. break;
  211. }
  212. }
  213. /* if nothing selected, grab the default state. */
  214. if (rdev->pm.requested_power_state_index == -1)
  215. rdev->pm.requested_power_state_index = 0;
  216. } else
  217. rdev->pm.requested_power_state_index = 1;
  218. switch (rdev->pm.dynpm_planned_action) {
  219. case DYNPM_ACTION_MINIMUM:
  220. rdev->pm.requested_clock_mode_index = 0;
  221. rdev->pm.dynpm_can_downclock = false;
  222. break;
  223. case DYNPM_ACTION_DOWNCLOCK:
  224. if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
  225. if (rdev->pm.current_clock_mode_index == 0) {
  226. rdev->pm.requested_clock_mode_index = 0;
  227. rdev->pm.dynpm_can_downclock = false;
  228. } else
  229. rdev->pm.requested_clock_mode_index =
  230. rdev->pm.current_clock_mode_index - 1;
  231. } else {
  232. rdev->pm.requested_clock_mode_index = 0;
  233. rdev->pm.dynpm_can_downclock = false;
  234. }
  235. /* don't use the power state if crtcs are active and no display flag is set */
  236. if ((rdev->pm.active_crtc_count > 0) &&
  237. (rdev->pm.power_state[rdev->pm.requested_power_state_index].
  238. clock_info[rdev->pm.requested_clock_mode_index].flags &
  239. RADEON_PM_MODE_NO_DISPLAY)) {
  240. rdev->pm.requested_clock_mode_index++;
  241. }
  242. break;
  243. case DYNPM_ACTION_UPCLOCK:
  244. if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
  245. if (rdev->pm.current_clock_mode_index ==
  246. (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
  247. rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
  248. rdev->pm.dynpm_can_upclock = false;
  249. } else
  250. rdev->pm.requested_clock_mode_index =
  251. rdev->pm.current_clock_mode_index + 1;
  252. } else {
  253. rdev->pm.requested_clock_mode_index =
  254. rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
  255. rdev->pm.dynpm_can_upclock = false;
  256. }
  257. break;
  258. case DYNPM_ACTION_DEFAULT:
  259. rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
  260. rdev->pm.requested_clock_mode_index = 0;
  261. rdev->pm.dynpm_can_upclock = false;
  262. break;
  263. case DYNPM_ACTION_NONE:
  264. default:
  265. DRM_ERROR("Requested mode for not defined action\n");
  266. return;
  267. }
  268. }
  269. DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
  270. rdev->pm.power_state[rdev->pm.requested_power_state_index].
  271. clock_info[rdev->pm.requested_clock_mode_index].sclk,
  272. rdev->pm.power_state[rdev->pm.requested_power_state_index].
  273. clock_info[rdev->pm.requested_clock_mode_index].mclk,
  274. rdev->pm.power_state[rdev->pm.requested_power_state_index].
  275. pcie_lanes);
  276. }
  277. void rs780_pm_init_profile(struct radeon_device *rdev)
  278. {
  279. if (rdev->pm.num_power_states == 2) {
  280. /* default */
  281. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  282. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  283. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
  284. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
  285. /* low sh */
  286. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
  287. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
  288. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
  289. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
  290. /* mid sh */
  291. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
  292. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
  293. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
  294. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
  295. /* high sh */
  296. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
  297. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
  298. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
  299. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
  300. /* low mh */
  301. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
  302. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
  303. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
  304. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
  305. /* mid mh */
  306. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
  307. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
  308. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
  309. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
  310. /* high mh */
  311. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
  312. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
  313. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
  314. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
  315. } else if (rdev->pm.num_power_states == 3) {
  316. /* default */
  317. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  318. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  319. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
  320. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
  321. /* low sh */
  322. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
  323. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
  324. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
  325. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
  326. /* mid sh */
  327. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
  328. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
  329. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
  330. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
  331. /* high sh */
  332. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
  333. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
  334. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
  335. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
  336. /* low mh */
  337. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
  338. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
  339. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
  340. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
  341. /* mid mh */
  342. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
  343. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
  344. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
  345. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
  346. /* high mh */
  347. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
  348. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
  349. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
  350. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
  351. } else {
  352. /* default */
  353. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  354. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  355. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
  356. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
  357. /* low sh */
  358. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
  359. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
  360. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
  361. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
  362. /* mid sh */
  363. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
  364. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
  365. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
  366. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
  367. /* high sh */
  368. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
  369. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
  370. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
  371. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
  372. /* low mh */
  373. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
  374. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
  375. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
  376. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
  377. /* mid mh */
  378. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
  379. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
  380. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
  381. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
  382. /* high mh */
  383. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
  384. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
  385. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
  386. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
  387. }
  388. }
  389. void r600_pm_init_profile(struct radeon_device *rdev)
  390. {
  391. int idx;
  392. if (rdev->family == CHIP_R600) {
  393. /* XXX */
  394. /* default */
  395. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  396. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  397. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
  398. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
  399. /* low sh */
  400. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  401. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  402. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
  403. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
  404. /* mid sh */
  405. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  406. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  407. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
  408. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
  409. /* high sh */
  410. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  411. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  412. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
  413. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
  414. /* low mh */
  415. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  416. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  417. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
  418. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
  419. /* mid mh */
  420. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  421. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  422. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
  423. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
  424. /* high mh */
  425. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  426. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  427. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
  428. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
  429. } else {
  430. if (rdev->pm.num_power_states < 4) {
  431. /* default */
  432. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  433. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  434. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
  435. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
  436. /* low sh */
  437. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
  438. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
  439. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
  440. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
  441. /* mid sh */
  442. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
  443. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
  444. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
  445. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
  446. /* high sh */
  447. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
  448. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
  449. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
  450. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
  451. /* low mh */
  452. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
  453. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
  454. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
  455. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
  456. /* low mh */
  457. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
  458. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
  459. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
  460. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
  461. /* high mh */
  462. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
  463. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
  464. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
  465. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
  466. } else {
  467. /* default */
  468. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  469. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  470. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
  471. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
  472. /* low sh */
  473. if (rdev->flags & RADEON_IS_MOBILITY)
  474. idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
  475. else
  476. idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
  477. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
  478. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
  479. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
  480. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
  481. /* mid sh */
  482. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
  483. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
  484. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
  485. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
  486. /* high sh */
  487. idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
  488. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
  489. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
  490. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
  491. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
  492. /* low mh */
  493. if (rdev->flags & RADEON_IS_MOBILITY)
  494. idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
  495. else
  496. idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
  497. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
  498. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
  499. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
  500. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
  501. /* mid mh */
  502. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
  503. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
  504. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
  505. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
  506. /* high mh */
  507. idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
  508. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
  509. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
  510. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
  511. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
  512. }
  513. }
  514. }
  515. void r600_pm_misc(struct radeon_device *rdev)
  516. {
  517. int req_ps_idx = rdev->pm.requested_power_state_index;
  518. int req_cm_idx = rdev->pm.requested_clock_mode_index;
  519. struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
  520. struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
  521. if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
  522. /* 0xff01 is a flag rather then an actual voltage */
  523. if (voltage->voltage == 0xff01)
  524. return;
  525. if (voltage->voltage != rdev->pm.current_vddc) {
  526. radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
  527. rdev->pm.current_vddc = voltage->voltage;
  528. DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
  529. }
  530. }
  531. }
  532. bool r600_gui_idle(struct radeon_device *rdev)
  533. {
  534. if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
  535. return false;
  536. else
  537. return true;
  538. }
  539. /* hpd for digital panel detect/disconnect */
  540. bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  541. {
  542. bool connected = false;
  543. if (ASIC_IS_DCE3(rdev)) {
  544. switch (hpd) {
  545. case RADEON_HPD_1:
  546. if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
  547. connected = true;
  548. break;
  549. case RADEON_HPD_2:
  550. if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
  551. connected = true;
  552. break;
  553. case RADEON_HPD_3:
  554. if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
  555. connected = true;
  556. break;
  557. case RADEON_HPD_4:
  558. if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
  559. connected = true;
  560. break;
  561. /* DCE 3.2 */
  562. case RADEON_HPD_5:
  563. if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
  564. connected = true;
  565. break;
  566. case RADEON_HPD_6:
  567. if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
  568. connected = true;
  569. break;
  570. default:
  571. break;
  572. }
  573. } else {
  574. switch (hpd) {
  575. case RADEON_HPD_1:
  576. if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
  577. connected = true;
  578. break;
  579. case RADEON_HPD_2:
  580. if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
  581. connected = true;
  582. break;
  583. case RADEON_HPD_3:
  584. if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
  585. connected = true;
  586. break;
  587. default:
  588. break;
  589. }
  590. }
  591. return connected;
  592. }
  593. void r600_hpd_set_polarity(struct radeon_device *rdev,
  594. enum radeon_hpd_id hpd)
  595. {
  596. u32 tmp;
  597. bool connected = r600_hpd_sense(rdev, hpd);
  598. if (ASIC_IS_DCE3(rdev)) {
  599. switch (hpd) {
  600. case RADEON_HPD_1:
  601. tmp = RREG32(DC_HPD1_INT_CONTROL);
  602. if (connected)
  603. tmp &= ~DC_HPDx_INT_POLARITY;
  604. else
  605. tmp |= DC_HPDx_INT_POLARITY;
  606. WREG32(DC_HPD1_INT_CONTROL, tmp);
  607. break;
  608. case RADEON_HPD_2:
  609. tmp = RREG32(DC_HPD2_INT_CONTROL);
  610. if (connected)
  611. tmp &= ~DC_HPDx_INT_POLARITY;
  612. else
  613. tmp |= DC_HPDx_INT_POLARITY;
  614. WREG32(DC_HPD2_INT_CONTROL, tmp);
  615. break;
  616. case RADEON_HPD_3:
  617. tmp = RREG32(DC_HPD3_INT_CONTROL);
  618. if (connected)
  619. tmp &= ~DC_HPDx_INT_POLARITY;
  620. else
  621. tmp |= DC_HPDx_INT_POLARITY;
  622. WREG32(DC_HPD3_INT_CONTROL, tmp);
  623. break;
  624. case RADEON_HPD_4:
  625. tmp = RREG32(DC_HPD4_INT_CONTROL);
  626. if (connected)
  627. tmp &= ~DC_HPDx_INT_POLARITY;
  628. else
  629. tmp |= DC_HPDx_INT_POLARITY;
  630. WREG32(DC_HPD4_INT_CONTROL, tmp);
  631. break;
  632. case RADEON_HPD_5:
  633. tmp = RREG32(DC_HPD5_INT_CONTROL);
  634. if (connected)
  635. tmp &= ~DC_HPDx_INT_POLARITY;
  636. else
  637. tmp |= DC_HPDx_INT_POLARITY;
  638. WREG32(DC_HPD5_INT_CONTROL, tmp);
  639. break;
  640. /* DCE 3.2 */
  641. case RADEON_HPD_6:
  642. tmp = RREG32(DC_HPD6_INT_CONTROL);
  643. if (connected)
  644. tmp &= ~DC_HPDx_INT_POLARITY;
  645. else
  646. tmp |= DC_HPDx_INT_POLARITY;
  647. WREG32(DC_HPD6_INT_CONTROL, tmp);
  648. break;
  649. default:
  650. break;
  651. }
  652. } else {
  653. switch (hpd) {
  654. case RADEON_HPD_1:
  655. tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
  656. if (connected)
  657. tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
  658. else
  659. tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
  660. WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
  661. break;
  662. case RADEON_HPD_2:
  663. tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
  664. if (connected)
  665. tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
  666. else
  667. tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
  668. WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
  669. break;
  670. case RADEON_HPD_3:
  671. tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
  672. if (connected)
  673. tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
  674. else
  675. tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
  676. WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
  677. break;
  678. default:
  679. break;
  680. }
  681. }
  682. }
  683. void r600_hpd_init(struct radeon_device *rdev)
  684. {
  685. struct drm_device *dev = rdev->ddev;
  686. struct drm_connector *connector;
  687. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  688. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  689. if (ASIC_IS_DCE3(rdev)) {
  690. u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
  691. if (ASIC_IS_DCE32(rdev))
  692. tmp |= DC_HPDx_EN;
  693. switch (radeon_connector->hpd.hpd) {
  694. case RADEON_HPD_1:
  695. WREG32(DC_HPD1_CONTROL, tmp);
  696. rdev->irq.hpd[0] = true;
  697. break;
  698. case RADEON_HPD_2:
  699. WREG32(DC_HPD2_CONTROL, tmp);
  700. rdev->irq.hpd[1] = true;
  701. break;
  702. case RADEON_HPD_3:
  703. WREG32(DC_HPD3_CONTROL, tmp);
  704. rdev->irq.hpd[2] = true;
  705. break;
  706. case RADEON_HPD_4:
  707. WREG32(DC_HPD4_CONTROL, tmp);
  708. rdev->irq.hpd[3] = true;
  709. break;
  710. /* DCE 3.2 */
  711. case RADEON_HPD_5:
  712. WREG32(DC_HPD5_CONTROL, tmp);
  713. rdev->irq.hpd[4] = true;
  714. break;
  715. case RADEON_HPD_6:
  716. WREG32(DC_HPD6_CONTROL, tmp);
  717. rdev->irq.hpd[5] = true;
  718. break;
  719. default:
  720. break;
  721. }
  722. } else {
  723. switch (radeon_connector->hpd.hpd) {
  724. case RADEON_HPD_1:
  725. WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
  726. rdev->irq.hpd[0] = true;
  727. break;
  728. case RADEON_HPD_2:
  729. WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
  730. rdev->irq.hpd[1] = true;
  731. break;
  732. case RADEON_HPD_3:
  733. WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
  734. rdev->irq.hpd[2] = true;
  735. break;
  736. default:
  737. break;
  738. }
  739. }
  740. radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
  741. }
  742. if (rdev->irq.installed)
  743. r600_irq_set(rdev);
  744. }
  745. void r600_hpd_fini(struct radeon_device *rdev)
  746. {
  747. struct drm_device *dev = rdev->ddev;
  748. struct drm_connector *connector;
  749. if (ASIC_IS_DCE3(rdev)) {
  750. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  751. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  752. switch (radeon_connector->hpd.hpd) {
  753. case RADEON_HPD_1:
  754. WREG32(DC_HPD1_CONTROL, 0);
  755. rdev->irq.hpd[0] = false;
  756. break;
  757. case RADEON_HPD_2:
  758. WREG32(DC_HPD2_CONTROL, 0);
  759. rdev->irq.hpd[1] = false;
  760. break;
  761. case RADEON_HPD_3:
  762. WREG32(DC_HPD3_CONTROL, 0);
  763. rdev->irq.hpd[2] = false;
  764. break;
  765. case RADEON_HPD_4:
  766. WREG32(DC_HPD4_CONTROL, 0);
  767. rdev->irq.hpd[3] = false;
  768. break;
  769. /* DCE 3.2 */
  770. case RADEON_HPD_5:
  771. WREG32(DC_HPD5_CONTROL, 0);
  772. rdev->irq.hpd[4] = false;
  773. break;
  774. case RADEON_HPD_6:
  775. WREG32(DC_HPD6_CONTROL, 0);
  776. rdev->irq.hpd[5] = false;
  777. break;
  778. default:
  779. break;
  780. }
  781. }
  782. } else {
  783. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  784. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  785. switch (radeon_connector->hpd.hpd) {
  786. case RADEON_HPD_1:
  787. WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
  788. rdev->irq.hpd[0] = false;
  789. break;
  790. case RADEON_HPD_2:
  791. WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
  792. rdev->irq.hpd[1] = false;
  793. break;
  794. case RADEON_HPD_3:
  795. WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
  796. rdev->irq.hpd[2] = false;
  797. break;
  798. default:
  799. break;
  800. }
  801. }
  802. }
  803. }
  804. /*
  805. * R600 PCIE GART
  806. */
  807. void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
  808. {
  809. unsigned i;
  810. u32 tmp;
  811. /* flush hdp cache so updates hit vram */
  812. if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
  813. !(rdev->flags & RADEON_IS_AGP)) {
  814. void __iomem *ptr = (void *)rdev->gart.ptr;
  815. u32 tmp;
  816. /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
  817. * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
  818. * This seems to cause problems on some AGP cards. Just use the old
  819. * method for them.
  820. */
  821. WREG32(HDP_DEBUG1, 0);
  822. tmp = readl((void __iomem *)ptr);
  823. } else
  824. WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
  825. WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
  826. WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
  827. WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
  828. for (i = 0; i < rdev->usec_timeout; i++) {
  829. /* read MC_STATUS */
  830. tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
  831. tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
  832. if (tmp == 2) {
  833. printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
  834. return;
  835. }
  836. if (tmp) {
  837. return;
  838. }
  839. udelay(1);
  840. }
  841. }
  842. int r600_pcie_gart_init(struct radeon_device *rdev)
  843. {
  844. int r;
  845. if (rdev->gart.robj) {
  846. WARN(1, "R600 PCIE GART already initialized\n");
  847. return 0;
  848. }
  849. /* Initialize common gart structure */
  850. r = radeon_gart_init(rdev);
  851. if (r)
  852. return r;
  853. rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
  854. return radeon_gart_table_vram_alloc(rdev);
  855. }
  856. int r600_pcie_gart_enable(struct radeon_device *rdev)
  857. {
  858. u32 tmp;
  859. int r, i;
  860. if (rdev->gart.robj == NULL) {
  861. dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  862. return -EINVAL;
  863. }
  864. r = radeon_gart_table_vram_pin(rdev);
  865. if (r)
  866. return r;
  867. radeon_gart_restore(rdev);
  868. /* Setup L2 cache */
  869. WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
  870. ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  871. EFFECTIVE_L2_QUEUE_SIZE(7));
  872. WREG32(VM_L2_CNTL2, 0);
  873. WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
  874. /* Setup TLB control */
  875. tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
  876. SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  877. EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
  878. ENABLE_WAIT_L2_QUERY;
  879. WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
  880. WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
  881. WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
  882. WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
  883. WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
  884. WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
  885. WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
  886. WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
  887. WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
  888. WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
  889. WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
  890. WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
  891. WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
  892. WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
  893. WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
  894. WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
  895. WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
  896. WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
  897. RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
  898. WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
  899. (u32)(rdev->dummy_page.addr >> 12));
  900. for (i = 1; i < 7; i++)
  901. WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  902. r600_pcie_gart_tlb_flush(rdev);
  903. DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
  904. (unsigned)(rdev->mc.gtt_size >> 20),
  905. (unsigned long long)rdev->gart.table_addr);
  906. rdev->gart.ready = true;
  907. return 0;
  908. }
  909. void r600_pcie_gart_disable(struct radeon_device *rdev)
  910. {
  911. u32 tmp;
  912. int i;
  913. /* Disable all tables */
  914. for (i = 0; i < 7; i++)
  915. WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  916. /* Disable L2 cache */
  917. WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
  918. EFFECTIVE_L2_QUEUE_SIZE(7));
  919. WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
  920. /* Setup L1 TLB control */
  921. tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
  922. ENABLE_WAIT_L2_QUERY;
  923. WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
  924. WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
  925. WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
  926. WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
  927. WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
  928. WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
  929. WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
  930. WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
  931. WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
  932. WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
  933. WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
  934. WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
  935. WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
  936. WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
  937. radeon_gart_table_vram_unpin(rdev);
  938. }
  939. void r600_pcie_gart_fini(struct radeon_device *rdev)
  940. {
  941. radeon_gart_fini(rdev);
  942. r600_pcie_gart_disable(rdev);
  943. radeon_gart_table_vram_free(rdev);
  944. }
  945. void r600_agp_enable(struct radeon_device *rdev)
  946. {
  947. u32 tmp;
  948. int i;
  949. /* Setup L2 cache */
  950. WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
  951. ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  952. EFFECTIVE_L2_QUEUE_SIZE(7));
  953. WREG32(VM_L2_CNTL2, 0);
  954. WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
  955. /* Setup TLB control */
  956. tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
  957. SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  958. EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
  959. ENABLE_WAIT_L2_QUERY;
  960. WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
  961. WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
  962. WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
  963. WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
  964. WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
  965. WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
  966. WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
  967. WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
  968. WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
  969. WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
  970. WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
  971. WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
  972. WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
  973. WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
  974. for (i = 0; i < 7; i++)
  975. WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  976. }
  977. int r600_mc_wait_for_idle(struct radeon_device *rdev)
  978. {
  979. unsigned i;
  980. u32 tmp;
  981. for (i = 0; i < rdev->usec_timeout; i++) {
  982. /* read MC_STATUS */
  983. tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
  984. if (!tmp)
  985. return 0;
  986. udelay(1);
  987. }
  988. return -1;
  989. }
  990. static void r600_mc_program(struct radeon_device *rdev)
  991. {
  992. struct rv515_mc_save save;
  993. u32 tmp;
  994. int i, j;
  995. /* Initialize HDP */
  996. for (i = 0, j = 0; i < 32; i++, j += 0x18) {
  997. WREG32((0x2c14 + j), 0x00000000);
  998. WREG32((0x2c18 + j), 0x00000000);
  999. WREG32((0x2c1c + j), 0x00000000);
  1000. WREG32((0x2c20 + j), 0x00000000);
  1001. WREG32((0x2c24 + j), 0x00000000);
  1002. }
  1003. WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
  1004. rv515_mc_stop(rdev, &save);
  1005. if (r600_mc_wait_for_idle(rdev)) {
  1006. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  1007. }
  1008. /* Lockout access through VGA aperture (doesn't exist before R600) */
  1009. WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
  1010. /* Update configuration */
  1011. if (rdev->flags & RADEON_IS_AGP) {
  1012. if (rdev->mc.vram_start < rdev->mc.gtt_start) {
  1013. /* VRAM before AGP */
  1014. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  1015. rdev->mc.vram_start >> 12);
  1016. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  1017. rdev->mc.gtt_end >> 12);
  1018. } else {
  1019. /* VRAM after AGP */
  1020. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  1021. rdev->mc.gtt_start >> 12);
  1022. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  1023. rdev->mc.vram_end >> 12);
  1024. }
  1025. } else {
  1026. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
  1027. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
  1028. }
  1029. WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
  1030. tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
  1031. tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
  1032. WREG32(MC_VM_FB_LOCATION, tmp);
  1033. WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
  1034. WREG32(HDP_NONSURFACE_INFO, (2 << 7));
  1035. WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
  1036. if (rdev->flags & RADEON_IS_AGP) {
  1037. WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
  1038. WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
  1039. WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
  1040. } else {
  1041. WREG32(MC_VM_AGP_BASE, 0);
  1042. WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
  1043. WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
  1044. }
  1045. if (r600_mc_wait_for_idle(rdev)) {
  1046. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  1047. }
  1048. rv515_mc_resume(rdev, &save);
  1049. /* we need to own VRAM, so turn off the VGA renderer here
  1050. * to stop it overwriting our objects */
  1051. rv515_vga_render_disable(rdev);
  1052. }
  1053. /**
  1054. * r600_vram_gtt_location - try to find VRAM & GTT location
  1055. * @rdev: radeon device structure holding all necessary informations
  1056. * @mc: memory controller structure holding memory informations
  1057. *
  1058. * Function will place try to place VRAM at same place as in CPU (PCI)
  1059. * address space as some GPU seems to have issue when we reprogram at
  1060. * different address space.
  1061. *
  1062. * If there is not enough space to fit the unvisible VRAM after the
  1063. * aperture then we limit the VRAM size to the aperture.
  1064. *
  1065. * If we are using AGP then place VRAM adjacent to AGP aperture are we need
  1066. * them to be in one from GPU point of view so that we can program GPU to
  1067. * catch access outside them (weird GPU policy see ??).
  1068. *
  1069. * This function will never fails, worst case are limiting VRAM or GTT.
  1070. *
  1071. * Note: GTT start, end, size should be initialized before calling this
  1072. * function on AGP platform.
  1073. */
  1074. static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
  1075. {
  1076. u64 size_bf, size_af;
  1077. if (mc->mc_vram_size > 0xE0000000) {
  1078. /* leave room for at least 512M GTT */
  1079. dev_warn(rdev->dev, "limiting VRAM\n");
  1080. mc->real_vram_size = 0xE0000000;
  1081. mc->mc_vram_size = 0xE0000000;
  1082. }
  1083. if (rdev->flags & RADEON_IS_AGP) {
  1084. size_bf = mc->gtt_start;
  1085. size_af = 0xFFFFFFFF - mc->gtt_end;
  1086. if (size_bf > size_af) {
  1087. if (mc->mc_vram_size > size_bf) {
  1088. dev_warn(rdev->dev, "limiting VRAM\n");
  1089. mc->real_vram_size = size_bf;
  1090. mc->mc_vram_size = size_bf;
  1091. }
  1092. mc->vram_start = mc->gtt_start - mc->mc_vram_size;
  1093. } else {
  1094. if (mc->mc_vram_size > size_af) {
  1095. dev_warn(rdev->dev, "limiting VRAM\n");
  1096. mc->real_vram_size = size_af;
  1097. mc->mc_vram_size = size_af;
  1098. }
  1099. mc->vram_start = mc->gtt_end + 1;
  1100. }
  1101. mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
  1102. dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
  1103. mc->mc_vram_size >> 20, mc->vram_start,
  1104. mc->vram_end, mc->real_vram_size >> 20);
  1105. } else {
  1106. u64 base = 0;
  1107. if (rdev->flags & RADEON_IS_IGP) {
  1108. base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
  1109. base <<= 24;
  1110. }
  1111. radeon_vram_location(rdev, &rdev->mc, base);
  1112. rdev->mc.gtt_base_align = 0;
  1113. radeon_gtt_location(rdev, mc);
  1114. }
  1115. }
  1116. int r600_mc_init(struct radeon_device *rdev)
  1117. {
  1118. u32 tmp;
  1119. int chansize, numchan;
  1120. /* Get VRAM informations */
  1121. rdev->mc.vram_is_ddr = true;
  1122. tmp = RREG32(RAMCFG);
  1123. if (tmp & CHANSIZE_OVERRIDE) {
  1124. chansize = 16;
  1125. } else if (tmp & CHANSIZE_MASK) {
  1126. chansize = 64;
  1127. } else {
  1128. chansize = 32;
  1129. }
  1130. tmp = RREG32(CHMAP);
  1131. switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
  1132. case 0:
  1133. default:
  1134. numchan = 1;
  1135. break;
  1136. case 1:
  1137. numchan = 2;
  1138. break;
  1139. case 2:
  1140. numchan = 4;
  1141. break;
  1142. case 3:
  1143. numchan = 8;
  1144. break;
  1145. }
  1146. rdev->mc.vram_width = numchan * chansize;
  1147. /* Could aper size report 0 ? */
  1148. rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
  1149. rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
  1150. /* Setup GPU memory space */
  1151. rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
  1152. rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
  1153. rdev->mc.visible_vram_size = rdev->mc.aper_size;
  1154. r600_vram_gtt_location(rdev, &rdev->mc);
  1155. if (rdev->flags & RADEON_IS_IGP) {
  1156. rs690_pm_info(rdev);
  1157. rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
  1158. }
  1159. radeon_update_bandwidth_info(rdev);
  1160. return 0;
  1161. }
  1162. int r600_vram_scratch_init(struct radeon_device *rdev)
  1163. {
  1164. int r;
  1165. if (rdev->vram_scratch.robj == NULL) {
  1166. r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
  1167. PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
  1168. &rdev->vram_scratch.robj);
  1169. if (r) {
  1170. return r;
  1171. }
  1172. }
  1173. r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
  1174. if (unlikely(r != 0))
  1175. return r;
  1176. r = radeon_bo_pin(rdev->vram_scratch.robj,
  1177. RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
  1178. if (r) {
  1179. radeon_bo_unreserve(rdev->vram_scratch.robj);
  1180. return r;
  1181. }
  1182. r = radeon_bo_kmap(rdev->vram_scratch.robj,
  1183. (void **)&rdev->vram_scratch.ptr);
  1184. if (r)
  1185. radeon_bo_unpin(rdev->vram_scratch.robj);
  1186. radeon_bo_unreserve(rdev->vram_scratch.robj);
  1187. return r;
  1188. }
  1189. void r600_vram_scratch_fini(struct radeon_device *rdev)
  1190. {
  1191. int r;
  1192. if (rdev->vram_scratch.robj == NULL) {
  1193. return;
  1194. }
  1195. r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
  1196. if (likely(r == 0)) {
  1197. radeon_bo_kunmap(rdev->vram_scratch.robj);
  1198. radeon_bo_unpin(rdev->vram_scratch.robj);
  1199. radeon_bo_unreserve(rdev->vram_scratch.robj);
  1200. }
  1201. radeon_bo_unref(&rdev->vram_scratch.robj);
  1202. }
  1203. /* We doesn't check that the GPU really needs a reset we simply do the
  1204. * reset, it's up to the caller to determine if the GPU needs one. We
  1205. * might add an helper function to check that.
  1206. */
  1207. int r600_gpu_soft_reset(struct radeon_device *rdev)
  1208. {
  1209. struct rv515_mc_save save;
  1210. u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
  1211. S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
  1212. S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
  1213. S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
  1214. S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
  1215. S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
  1216. S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
  1217. S_008010_GUI_ACTIVE(1);
  1218. u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
  1219. S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
  1220. S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
  1221. S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
  1222. S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
  1223. S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
  1224. S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
  1225. S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
  1226. u32 tmp;
  1227. if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
  1228. return 0;
  1229. dev_info(rdev->dev, "GPU softreset \n");
  1230. dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
  1231. RREG32(R_008010_GRBM_STATUS));
  1232. dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
  1233. RREG32(R_008014_GRBM_STATUS2));
  1234. dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
  1235. RREG32(R_000E50_SRBM_STATUS));
  1236. rv515_mc_stop(rdev, &save);
  1237. if (r600_mc_wait_for_idle(rdev)) {
  1238. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  1239. }
  1240. /* Disable CP parsing/prefetching */
  1241. WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
  1242. /* Check if any of the rendering block is busy and reset it */
  1243. if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
  1244. (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
  1245. tmp = S_008020_SOFT_RESET_CR(1) |
  1246. S_008020_SOFT_RESET_DB(1) |
  1247. S_008020_SOFT_RESET_CB(1) |
  1248. S_008020_SOFT_RESET_PA(1) |
  1249. S_008020_SOFT_RESET_SC(1) |
  1250. S_008020_SOFT_RESET_SMX(1) |
  1251. S_008020_SOFT_RESET_SPI(1) |
  1252. S_008020_SOFT_RESET_SX(1) |
  1253. S_008020_SOFT_RESET_SH(1) |
  1254. S_008020_SOFT_RESET_TC(1) |
  1255. S_008020_SOFT_RESET_TA(1) |
  1256. S_008020_SOFT_RESET_VC(1) |
  1257. S_008020_SOFT_RESET_VGT(1);
  1258. dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
  1259. WREG32(R_008020_GRBM_SOFT_RESET, tmp);
  1260. RREG32(R_008020_GRBM_SOFT_RESET);
  1261. mdelay(15);
  1262. WREG32(R_008020_GRBM_SOFT_RESET, 0);
  1263. }
  1264. /* Reset CP (we always reset CP) */
  1265. tmp = S_008020_SOFT_RESET_CP(1);
  1266. dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
  1267. WREG32(R_008020_GRBM_SOFT_RESET, tmp);
  1268. RREG32(R_008020_GRBM_SOFT_RESET);
  1269. mdelay(15);
  1270. WREG32(R_008020_GRBM_SOFT_RESET, 0);
  1271. /* Wait a little for things to settle down */
  1272. mdelay(1);
  1273. dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
  1274. RREG32(R_008010_GRBM_STATUS));
  1275. dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
  1276. RREG32(R_008014_GRBM_STATUS2));
  1277. dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
  1278. RREG32(R_000E50_SRBM_STATUS));
  1279. rv515_mc_resume(rdev, &save);
  1280. return 0;
  1281. }
  1282. bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
  1283. {
  1284. u32 srbm_status;
  1285. u32 grbm_status;
  1286. u32 grbm_status2;
  1287. srbm_status = RREG32(R_000E50_SRBM_STATUS);
  1288. grbm_status = RREG32(R_008010_GRBM_STATUS);
  1289. grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
  1290. if (!G_008010_GUI_ACTIVE(grbm_status)) {
  1291. radeon_ring_lockup_update(ring);
  1292. return false;
  1293. }
  1294. /* force CP activities */
  1295. radeon_ring_force_activity(rdev, ring);
  1296. return radeon_ring_test_lockup(rdev, ring);
  1297. }
  1298. int r600_asic_reset(struct radeon_device *rdev)
  1299. {
  1300. return r600_gpu_soft_reset(rdev);
  1301. }
  1302. static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
  1303. u32 num_backends,
  1304. u32 backend_disable_mask)
  1305. {
  1306. u32 backend_map = 0;
  1307. u32 enabled_backends_mask;
  1308. u32 enabled_backends_count;
  1309. u32 cur_pipe;
  1310. u32 swizzle_pipe[R6XX_MAX_PIPES];
  1311. u32 cur_backend;
  1312. u32 i;
  1313. if (num_tile_pipes > R6XX_MAX_PIPES)
  1314. num_tile_pipes = R6XX_MAX_PIPES;
  1315. if (num_tile_pipes < 1)
  1316. num_tile_pipes = 1;
  1317. if (num_backends > R6XX_MAX_BACKENDS)
  1318. num_backends = R6XX_MAX_BACKENDS;
  1319. if (num_backends < 1)
  1320. num_backends = 1;
  1321. enabled_backends_mask = 0;
  1322. enabled_backends_count = 0;
  1323. for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
  1324. if (((backend_disable_mask >> i) & 1) == 0) {
  1325. enabled_backends_mask |= (1 << i);
  1326. ++enabled_backends_count;
  1327. }
  1328. if (enabled_backends_count == num_backends)
  1329. break;
  1330. }
  1331. if (enabled_backends_count == 0) {
  1332. enabled_backends_mask = 1;
  1333. enabled_backends_count = 1;
  1334. }
  1335. if (enabled_backends_count != num_backends)
  1336. num_backends = enabled_backends_count;
  1337. memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
  1338. switch (num_tile_pipes) {
  1339. case 1:
  1340. swizzle_pipe[0] = 0;
  1341. break;
  1342. case 2:
  1343. swizzle_pipe[0] = 0;
  1344. swizzle_pipe[1] = 1;
  1345. break;
  1346. case 3:
  1347. swizzle_pipe[0] = 0;
  1348. swizzle_pipe[1] = 1;
  1349. swizzle_pipe[2] = 2;
  1350. break;
  1351. case 4:
  1352. swizzle_pipe[0] = 0;
  1353. swizzle_pipe[1] = 1;
  1354. swizzle_pipe[2] = 2;
  1355. swizzle_pipe[3] = 3;
  1356. break;
  1357. case 5:
  1358. swizzle_pipe[0] = 0;
  1359. swizzle_pipe[1] = 1;
  1360. swizzle_pipe[2] = 2;
  1361. swizzle_pipe[3] = 3;
  1362. swizzle_pipe[4] = 4;
  1363. break;
  1364. case 6:
  1365. swizzle_pipe[0] = 0;
  1366. swizzle_pipe[1] = 2;
  1367. swizzle_pipe[2] = 4;
  1368. swizzle_pipe[3] = 5;
  1369. swizzle_pipe[4] = 1;
  1370. swizzle_pipe[5] = 3;
  1371. break;
  1372. case 7:
  1373. swizzle_pipe[0] = 0;
  1374. swizzle_pipe[1] = 2;
  1375. swizzle_pipe[2] = 4;
  1376. swizzle_pipe[3] = 6;
  1377. swizzle_pipe[4] = 1;
  1378. swizzle_pipe[5] = 3;
  1379. swizzle_pipe[6] = 5;
  1380. break;
  1381. case 8:
  1382. swizzle_pipe[0] = 0;
  1383. swizzle_pipe[1] = 2;
  1384. swizzle_pipe[2] = 4;
  1385. swizzle_pipe[3] = 6;
  1386. swizzle_pipe[4] = 1;
  1387. swizzle_pipe[5] = 3;
  1388. swizzle_pipe[6] = 5;
  1389. swizzle_pipe[7] = 7;
  1390. break;
  1391. }
  1392. cur_backend = 0;
  1393. for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
  1394. while (((1 << cur_backend) & enabled_backends_mask) == 0)
  1395. cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
  1396. backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
  1397. cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
  1398. }
  1399. return backend_map;
  1400. }
  1401. int r600_count_pipe_bits(uint32_t val)
  1402. {
  1403. int i, ret = 0;
  1404. for (i = 0; i < 32; i++) {
  1405. ret += val & 1;
  1406. val >>= 1;
  1407. }
  1408. return ret;
  1409. }
  1410. void r600_gpu_init(struct radeon_device *rdev)
  1411. {
  1412. u32 tiling_config;
  1413. u32 ramcfg;
  1414. u32 backend_map;
  1415. u32 cc_rb_backend_disable;
  1416. u32 cc_gc_shader_pipe_config;
  1417. u32 tmp;
  1418. int i, j;
  1419. u32 sq_config;
  1420. u32 sq_gpr_resource_mgmt_1 = 0;
  1421. u32 sq_gpr_resource_mgmt_2 = 0;
  1422. u32 sq_thread_resource_mgmt = 0;
  1423. u32 sq_stack_resource_mgmt_1 = 0;
  1424. u32 sq_stack_resource_mgmt_2 = 0;
  1425. /* FIXME: implement */
  1426. switch (rdev->family) {
  1427. case CHIP_R600:
  1428. rdev->config.r600.max_pipes = 4;
  1429. rdev->config.r600.max_tile_pipes = 8;
  1430. rdev->config.r600.max_simds = 4;
  1431. rdev->config.r600.max_backends = 4;
  1432. rdev->config.r600.max_gprs = 256;
  1433. rdev->config.r600.max_threads = 192;
  1434. rdev->config.r600.max_stack_entries = 256;
  1435. rdev->config.r600.max_hw_contexts = 8;
  1436. rdev->config.r600.max_gs_threads = 16;
  1437. rdev->config.r600.sx_max_export_size = 128;
  1438. rdev->config.r600.sx_max_export_pos_size = 16;
  1439. rdev->config.r600.sx_max_export_smx_size = 128;
  1440. rdev->config.r600.sq_num_cf_insts = 2;
  1441. break;
  1442. case CHIP_RV630:
  1443. case CHIP_RV635:
  1444. rdev->config.r600.max_pipes = 2;
  1445. rdev->config.r600.max_tile_pipes = 2;
  1446. rdev->config.r600.max_simds = 3;
  1447. rdev->config.r600.max_backends = 1;
  1448. rdev->config.r600.max_gprs = 128;
  1449. rdev->config.r600.max_threads = 192;
  1450. rdev->config.r600.max_stack_entries = 128;
  1451. rdev->config.r600.max_hw_contexts = 8;
  1452. rdev->config.r600.max_gs_threads = 4;
  1453. rdev->config.r600.sx_max_export_size = 128;
  1454. rdev->config.r600.sx_max_export_pos_size = 16;
  1455. rdev->config.r600.sx_max_export_smx_size = 128;
  1456. rdev->config.r600.sq_num_cf_insts = 2;
  1457. break;
  1458. case CHIP_RV610:
  1459. case CHIP_RV620:
  1460. case CHIP_RS780:
  1461. case CHIP_RS880:
  1462. rdev->config.r600.max_pipes = 1;
  1463. rdev->config.r600.max_tile_pipes = 1;
  1464. rdev->config.r600.max_simds = 2;
  1465. rdev->config.r600.max_backends = 1;
  1466. rdev->config.r600.max_gprs = 128;
  1467. rdev->config.r600.max_threads = 192;
  1468. rdev->config.r600.max_stack_entries = 128;
  1469. rdev->config.r600.max_hw_contexts = 4;
  1470. rdev->config.r600.max_gs_threads = 4;
  1471. rdev->config.r600.sx_max_export_size = 128;
  1472. rdev->config.r600.sx_max_export_pos_size = 16;
  1473. rdev->config.r600.sx_max_export_smx_size = 128;
  1474. rdev->config.r600.sq_num_cf_insts = 1;
  1475. break;
  1476. case CHIP_RV670:
  1477. rdev->config.r600.max_pipes = 4;
  1478. rdev->config.r600.max_tile_pipes = 4;
  1479. rdev->config.r600.max_simds = 4;
  1480. rdev->config.r600.max_backends = 4;
  1481. rdev->config.r600.max_gprs = 192;
  1482. rdev->config.r600.max_threads = 192;
  1483. rdev->config.r600.max_stack_entries = 256;
  1484. rdev->config.r600.max_hw_contexts = 8;
  1485. rdev->config.r600.max_gs_threads = 16;
  1486. rdev->config.r600.sx_max_export_size = 128;
  1487. rdev->config.r600.sx_max_export_pos_size = 16;
  1488. rdev->config.r600.sx_max_export_smx_size = 128;
  1489. rdev->config.r600.sq_num_cf_insts = 2;
  1490. break;
  1491. default:
  1492. break;
  1493. }
  1494. /* Initialize HDP */
  1495. for (i = 0, j = 0; i < 32; i++, j += 0x18) {
  1496. WREG32((0x2c14 + j), 0x00000000);
  1497. WREG32((0x2c18 + j), 0x00000000);
  1498. WREG32((0x2c1c + j), 0x00000000);
  1499. WREG32((0x2c20 + j), 0x00000000);
  1500. WREG32((0x2c24 + j), 0x00000000);
  1501. }
  1502. WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
  1503. /* Setup tiling */
  1504. tiling_config = 0;
  1505. ramcfg = RREG32(RAMCFG);
  1506. switch (rdev->config.r600.max_tile_pipes) {
  1507. case 1:
  1508. tiling_config |= PIPE_TILING(0);
  1509. break;
  1510. case 2:
  1511. tiling_config |= PIPE_TILING(1);
  1512. break;
  1513. case 4:
  1514. tiling_config |= PIPE_TILING(2);
  1515. break;
  1516. case 8:
  1517. tiling_config |= PIPE_TILING(3);
  1518. break;
  1519. default:
  1520. break;
  1521. }
  1522. rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
  1523. rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
  1524. tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
  1525. tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
  1526. if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
  1527. rdev->config.r600.tiling_group_size = 512;
  1528. else
  1529. rdev->config.r600.tiling_group_size = 256;
  1530. tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
  1531. if (tmp > 3) {
  1532. tiling_config |= ROW_TILING(3);
  1533. tiling_config |= SAMPLE_SPLIT(3);
  1534. } else {
  1535. tiling_config |= ROW_TILING(tmp);
  1536. tiling_config |= SAMPLE_SPLIT(tmp);
  1537. }
  1538. tiling_config |= BANK_SWAPS(1);
  1539. cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
  1540. cc_rb_backend_disable |=
  1541. BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
  1542. cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
  1543. cc_gc_shader_pipe_config |=
  1544. INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
  1545. cc_gc_shader_pipe_config |=
  1546. INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
  1547. backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
  1548. (R6XX_MAX_BACKENDS -
  1549. r600_count_pipe_bits((cc_rb_backend_disable &
  1550. R6XX_MAX_BACKENDS_MASK) >> 16)),
  1551. (cc_rb_backend_disable >> 16));
  1552. rdev->config.r600.tile_config = tiling_config;
  1553. rdev->config.r600.backend_map = backend_map;
  1554. tiling_config |= BACKEND_MAP(backend_map);
  1555. WREG32(GB_TILING_CONFIG, tiling_config);
  1556. WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
  1557. WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
  1558. /* Setup pipes */
  1559. WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
  1560. WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
  1561. WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
  1562. tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
  1563. WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
  1564. WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
  1565. /* Setup some CP states */
  1566. WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
  1567. WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
  1568. WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
  1569. SYNC_WALKER | SYNC_ALIGNER));
  1570. /* Setup various GPU states */
  1571. if (rdev->family == CHIP_RV670)
  1572. WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
  1573. tmp = RREG32(SX_DEBUG_1);
  1574. tmp |= SMX_EVENT_RELEASE;
  1575. if ((rdev->family > CHIP_R600))
  1576. tmp |= ENABLE_NEW_SMX_ADDRESS;
  1577. WREG32(SX_DEBUG_1, tmp);
  1578. if (((rdev->family) == CHIP_R600) ||
  1579. ((rdev->family) == CHIP_RV630) ||
  1580. ((rdev->family) == CHIP_RV610) ||
  1581. ((rdev->family) == CHIP_RV620) ||
  1582. ((rdev->family) == CHIP_RS780) ||
  1583. ((rdev->family) == CHIP_RS880)) {
  1584. WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
  1585. } else {
  1586. WREG32(DB_DEBUG, 0);
  1587. }
  1588. WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
  1589. DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
  1590. WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
  1591. WREG32(VGT_NUM_INSTANCES, 0);
  1592. WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
  1593. WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
  1594. tmp = RREG32(SQ_MS_FIFO_SIZES);
  1595. if (((rdev->family) == CHIP_RV610) ||
  1596. ((rdev->family) == CHIP_RV620) ||
  1597. ((rdev->family) == CHIP_RS780) ||
  1598. ((rdev->family) == CHIP_RS880)) {
  1599. tmp = (CACHE_FIFO_SIZE(0xa) |
  1600. FETCH_FIFO_HIWATER(0xa) |
  1601. DONE_FIFO_HIWATER(0xe0) |
  1602. ALU_UPDATE_FIFO_HIWATER(0x8));
  1603. } else if (((rdev->family) == CHIP_R600) ||
  1604. ((rdev->family) == CHIP_RV630)) {
  1605. tmp &= ~DONE_FIFO_HIWATER(0xff);
  1606. tmp |= DONE_FIFO_HIWATER(0x4);
  1607. }
  1608. WREG32(SQ_MS_FIFO_SIZES, tmp);
  1609. /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
  1610. * should be adjusted as needed by the 2D/3D drivers. This just sets default values
  1611. */
  1612. sq_config = RREG32(SQ_CONFIG);
  1613. sq_config &= ~(PS_PRIO(3) |
  1614. VS_PRIO(3) |
  1615. GS_PRIO(3) |
  1616. ES_PRIO(3));
  1617. sq_config |= (DX9_CONSTS |
  1618. VC_ENABLE |
  1619. PS_PRIO(0) |
  1620. VS_PRIO(1) |
  1621. GS_PRIO(2) |
  1622. ES_PRIO(3));
  1623. if ((rdev->family) == CHIP_R600) {
  1624. sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
  1625. NUM_VS_GPRS(124) |
  1626. NUM_CLAUSE_TEMP_GPRS(4));
  1627. sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
  1628. NUM_ES_GPRS(0));
  1629. sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
  1630. NUM_VS_THREADS(48) |
  1631. NUM_GS_THREADS(4) |
  1632. NUM_ES_THREADS(4));
  1633. sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
  1634. NUM_VS_STACK_ENTRIES(128));
  1635. sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
  1636. NUM_ES_STACK_ENTRIES(0));
  1637. } else if (((rdev->family) == CHIP_RV610) ||
  1638. ((rdev->family) == CHIP_RV620) ||
  1639. ((rdev->family) == CHIP_RS780) ||
  1640. ((rdev->family) == CHIP_RS880)) {
  1641. /* no vertex cache */
  1642. sq_config &= ~VC_ENABLE;
  1643. sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
  1644. NUM_VS_GPRS(44) |
  1645. NUM_CLAUSE_TEMP_GPRS(2));
  1646. sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
  1647. NUM_ES_GPRS(17));
  1648. sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
  1649. NUM_VS_THREADS(78) |
  1650. NUM_GS_THREADS(4) |
  1651. NUM_ES_THREADS(31));
  1652. sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
  1653. NUM_VS_STACK_ENTRIES(40));
  1654. sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
  1655. NUM_ES_STACK_ENTRIES(16));
  1656. } else if (((rdev->family) == CHIP_RV630) ||
  1657. ((rdev->family) == CHIP_RV635)) {
  1658. sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
  1659. NUM_VS_GPRS(44) |
  1660. NUM_CLAUSE_TEMP_GPRS(2));
  1661. sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
  1662. NUM_ES_GPRS(18));
  1663. sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
  1664. NUM_VS_THREADS(78) |
  1665. NUM_GS_THREADS(4) |
  1666. NUM_ES_THREADS(31));
  1667. sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
  1668. NUM_VS_STACK_ENTRIES(40));
  1669. sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
  1670. NUM_ES_STACK_ENTRIES(16));
  1671. } else if ((rdev->family) == CHIP_RV670) {
  1672. sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
  1673. NUM_VS_GPRS(44) |
  1674. NUM_CLAUSE_TEMP_GPRS(2));
  1675. sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
  1676. NUM_ES_GPRS(17));
  1677. sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
  1678. NUM_VS_THREADS(78) |
  1679. NUM_GS_THREADS(4) |
  1680. NUM_ES_THREADS(31));
  1681. sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
  1682. NUM_VS_STACK_ENTRIES(64));
  1683. sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
  1684. NUM_ES_STACK_ENTRIES(64));
  1685. }
  1686. WREG32(SQ_CONFIG, sq_config);
  1687. WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
  1688. WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
  1689. WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
  1690. WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
  1691. WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
  1692. if (((rdev->family) == CHIP_RV610) ||
  1693. ((rdev->family) == CHIP_RV620) ||
  1694. ((rdev->family) == CHIP_RS780) ||
  1695. ((rdev->family) == CHIP_RS880)) {
  1696. WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
  1697. } else {
  1698. WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
  1699. }
  1700. /* More default values. 2D/3D driver should adjust as needed */
  1701. WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
  1702. S1_X(0x4) | S1_Y(0xc)));
  1703. WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
  1704. S1_X(0x2) | S1_Y(0x2) |
  1705. S2_X(0xa) | S2_Y(0x6) |
  1706. S3_X(0x6) | S3_Y(0xa)));
  1707. WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
  1708. S1_X(0x4) | S1_Y(0xc) |
  1709. S2_X(0x1) | S2_Y(0x6) |
  1710. S3_X(0xa) | S3_Y(0xe)));
  1711. WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
  1712. S5_X(0x0) | S5_Y(0x0) |
  1713. S6_X(0xb) | S6_Y(0x4) |
  1714. S7_X(0x7) | S7_Y(0x8)));
  1715. WREG32(VGT_STRMOUT_EN, 0);
  1716. tmp = rdev->config.r600.max_pipes * 16;
  1717. switch (rdev->family) {
  1718. case CHIP_RV610:
  1719. case CHIP_RV620:
  1720. case CHIP_RS780:
  1721. case CHIP_RS880:
  1722. tmp += 32;
  1723. break;
  1724. case CHIP_RV670:
  1725. tmp += 128;
  1726. break;
  1727. default:
  1728. break;
  1729. }
  1730. if (tmp > 256) {
  1731. tmp = 256;
  1732. }
  1733. WREG32(VGT_ES_PER_GS, 128);
  1734. WREG32(VGT_GS_PER_ES, tmp);
  1735. WREG32(VGT_GS_PER_VS, 2);
  1736. WREG32(VGT_GS_VERTEX_REUSE, 16);
  1737. /* more default values. 2D/3D driver should adjust as needed */
  1738. WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
  1739. WREG32(VGT_STRMOUT_EN, 0);
  1740. WREG32(SX_MISC, 0);
  1741. WREG32(PA_SC_MODE_CNTL, 0);
  1742. WREG32(PA_SC_AA_CONFIG, 0);
  1743. WREG32(PA_SC_LINE_STIPPLE, 0);
  1744. WREG32(SPI_INPUT_Z, 0);
  1745. WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
  1746. WREG32(CB_COLOR7_FRAG, 0);
  1747. /* Clear render buffer base addresses */
  1748. WREG32(CB_COLOR0_BASE, 0);
  1749. WREG32(CB_COLOR1_BASE, 0);
  1750. WREG32(CB_COLOR2_BASE, 0);
  1751. WREG32(CB_COLOR3_BASE, 0);
  1752. WREG32(CB_COLOR4_BASE, 0);
  1753. WREG32(CB_COLOR5_BASE, 0);
  1754. WREG32(CB_COLOR6_BASE, 0);
  1755. WREG32(CB_COLOR7_BASE, 0);
  1756. WREG32(CB_COLOR7_FRAG, 0);
  1757. switch (rdev->family) {
  1758. case CHIP_RV610:
  1759. case CHIP_RV620:
  1760. case CHIP_RS780:
  1761. case CHIP_RS880:
  1762. tmp = TC_L2_SIZE(8);
  1763. break;
  1764. case CHIP_RV630:
  1765. case CHIP_RV635:
  1766. tmp = TC_L2_SIZE(4);
  1767. break;
  1768. case CHIP_R600:
  1769. tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
  1770. break;
  1771. default:
  1772. tmp = TC_L2_SIZE(0);
  1773. break;
  1774. }
  1775. WREG32(TC_CNTL, tmp);
  1776. tmp = RREG32(HDP_HOST_PATH_CNTL);
  1777. WREG32(HDP_HOST_PATH_CNTL, tmp);
  1778. tmp = RREG32(ARB_POP);
  1779. tmp |= ENABLE_TC128;
  1780. WREG32(ARB_POP, tmp);
  1781. WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
  1782. WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
  1783. NUM_CLIP_SEQ(3)));
  1784. WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
  1785. }
  1786. /*
  1787. * Indirect registers accessor
  1788. */
  1789. u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
  1790. {
  1791. u32 r;
  1792. WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
  1793. (void)RREG32(PCIE_PORT_INDEX);
  1794. r = RREG32(PCIE_PORT_DATA);
  1795. return r;
  1796. }
  1797. void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  1798. {
  1799. WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
  1800. (void)RREG32(PCIE_PORT_INDEX);
  1801. WREG32(PCIE_PORT_DATA, (v));
  1802. (void)RREG32(PCIE_PORT_DATA);
  1803. }
  1804. /*
  1805. * CP & Ring
  1806. */
  1807. void r600_cp_stop(struct radeon_device *rdev)
  1808. {
  1809. radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
  1810. WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
  1811. WREG32(SCRATCH_UMSK, 0);
  1812. }
  1813. int r600_init_microcode(struct radeon_device *rdev)
  1814. {
  1815. struct platform_device *pdev;
  1816. const char *chip_name;
  1817. const char *rlc_chip_name;
  1818. size_t pfp_req_size, me_req_size, rlc_req_size;
  1819. char fw_name[30];
  1820. int err;
  1821. DRM_DEBUG("\n");
  1822. pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
  1823. err = IS_ERR(pdev);
  1824. if (err) {
  1825. printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
  1826. return -EINVAL;
  1827. }
  1828. switch (rdev->family) {
  1829. case CHIP_R600:
  1830. chip_name = "R600";
  1831. rlc_chip_name = "R600";
  1832. break;
  1833. case CHIP_RV610:
  1834. chip_name = "RV610";
  1835. rlc_chip_name = "R600";
  1836. break;
  1837. case CHIP_RV630:
  1838. chip_name = "RV630";
  1839. rlc_chip_name = "R600";
  1840. break;
  1841. case CHIP_RV620:
  1842. chip_name = "RV620";
  1843. rlc_chip_name = "R600";
  1844. break;
  1845. case CHIP_RV635:
  1846. chip_name = "RV635";
  1847. rlc_chip_name = "R600";
  1848. break;
  1849. case CHIP_RV670:
  1850. chip_name = "RV670";
  1851. rlc_chip_name = "R600";
  1852. break;
  1853. case CHIP_RS780:
  1854. case CHIP_RS880:
  1855. chip_name = "RS780";
  1856. rlc_chip_name = "R600";
  1857. break;
  1858. case CHIP_RV770:
  1859. chip_name = "RV770";
  1860. rlc_chip_name = "R700";
  1861. break;
  1862. case CHIP_RV730:
  1863. case CHIP_RV740:
  1864. chip_name = "RV730";
  1865. rlc_chip_name = "R700";
  1866. break;
  1867. case CHIP_RV710:
  1868. chip_name = "RV710";
  1869. rlc_chip_name = "R700";
  1870. break;
  1871. case CHIP_CEDAR:
  1872. chip_name = "CEDAR";
  1873. rlc_chip_name = "CEDAR";
  1874. break;
  1875. case CHIP_REDWOOD:
  1876. chip_name = "REDWOOD";
  1877. rlc_chip_name = "REDWOOD";
  1878. break;
  1879. case CHIP_JUNIPER:
  1880. chip_name = "JUNIPER";
  1881. rlc_chip_name = "JUNIPER";
  1882. break;
  1883. case CHIP_CYPRESS:
  1884. case CHIP_HEMLOCK:
  1885. chip_name = "CYPRESS";
  1886. rlc_chip_name = "CYPRESS";
  1887. break;
  1888. case CHIP_PALM:
  1889. chip_name = "PALM";
  1890. rlc_chip_name = "SUMO";
  1891. break;
  1892. case CHIP_SUMO:
  1893. chip_name = "SUMO";
  1894. rlc_chip_name = "SUMO";
  1895. break;
  1896. case CHIP_SUMO2:
  1897. chip_name = "SUMO2";
  1898. rlc_chip_name = "SUMO";
  1899. break;
  1900. default: BUG();
  1901. }
  1902. if (rdev->family >= CHIP_CEDAR) {
  1903. pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
  1904. me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
  1905. rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
  1906. } else if (rdev->family >= CHIP_RV770) {
  1907. pfp_req_size = R700_PFP_UCODE_SIZE * 4;
  1908. me_req_size = R700_PM4_UCODE_SIZE * 4;
  1909. rlc_req_size = R700_RLC_UCODE_SIZE * 4;
  1910. } else {
  1911. pfp_req_size = PFP_UCODE_SIZE * 4;
  1912. me_req_size = PM4_UCODE_SIZE * 12;
  1913. rlc_req_size = RLC_UCODE_SIZE * 4;
  1914. }
  1915. DRM_INFO("Loading %s Microcode\n", chip_name);
  1916. snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
  1917. err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
  1918. if (err)
  1919. goto out;
  1920. if (rdev->pfp_fw->size != pfp_req_size) {
  1921. printk(KERN_ERR
  1922. "r600_cp: Bogus length %zu in firmware \"%s\"\n",
  1923. rdev->pfp_fw->size, fw_name);
  1924. err = -EINVAL;
  1925. goto out;
  1926. }
  1927. snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
  1928. err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
  1929. if (err)
  1930. goto out;
  1931. if (rdev->me_fw->size != me_req_size) {
  1932. printk(KERN_ERR
  1933. "r600_cp: Bogus length %zu in firmware \"%s\"\n",
  1934. rdev->me_fw->size, fw_name);
  1935. err = -EINVAL;
  1936. }
  1937. snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
  1938. err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
  1939. if (err)
  1940. goto out;
  1941. if (rdev->rlc_fw->size != rlc_req_size) {
  1942. printk(KERN_ERR
  1943. "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
  1944. rdev->rlc_fw->size, fw_name);
  1945. err = -EINVAL;
  1946. }
  1947. out:
  1948. platform_device_unregister(pdev);
  1949. if (err) {
  1950. if (err != -EINVAL)
  1951. printk(KERN_ERR
  1952. "r600_cp: Failed to load firmware \"%s\"\n",
  1953. fw_name);
  1954. release_firmware(rdev->pfp_fw);
  1955. rdev->pfp_fw = NULL;
  1956. release_firmware(rdev->me_fw);
  1957. rdev->me_fw = NULL;
  1958. release_firmware(rdev->rlc_fw);
  1959. rdev->rlc_fw = NULL;
  1960. }
  1961. return err;
  1962. }
  1963. static int r600_cp_load_microcode(struct radeon_device *rdev)
  1964. {
  1965. const __be32 *fw_data;
  1966. int i;
  1967. if (!rdev->me_fw || !rdev->pfp_fw)
  1968. return -EINVAL;
  1969. r600_cp_stop(rdev);
  1970. WREG32(CP_RB_CNTL,
  1971. #ifdef __BIG_ENDIAN
  1972. BUF_SWAP_32BIT |
  1973. #endif
  1974. RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
  1975. /* Reset cp */
  1976. WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
  1977. RREG32(GRBM_SOFT_RESET);
  1978. mdelay(15);
  1979. WREG32(GRBM_SOFT_RESET, 0);
  1980. WREG32(CP_ME_RAM_WADDR, 0);
  1981. fw_data = (const __be32 *)rdev->me_fw->data;
  1982. WREG32(CP_ME_RAM_WADDR, 0);
  1983. for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
  1984. WREG32(CP_ME_RAM_DATA,
  1985. be32_to_cpup(fw_data++));
  1986. fw_data = (const __be32 *)rdev->pfp_fw->data;
  1987. WREG32(CP_PFP_UCODE_ADDR, 0);
  1988. for (i = 0; i < PFP_UCODE_SIZE; i++)
  1989. WREG32(CP_PFP_UCODE_DATA,
  1990. be32_to_cpup(fw_data++));
  1991. WREG32(CP_PFP_UCODE_ADDR, 0);
  1992. WREG32(CP_ME_RAM_WADDR, 0);
  1993. WREG32(CP_ME_RAM_RADDR, 0);
  1994. return 0;
  1995. }
  1996. int r600_cp_start(struct radeon_device *rdev)
  1997. {
  1998. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  1999. int r;
  2000. uint32_t cp_me;
  2001. r = radeon_ring_lock(rdev, ring, 7);
  2002. if (r) {
  2003. DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
  2004. return r;
  2005. }
  2006. radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
  2007. radeon_ring_write(ring, 0x1);
  2008. if (rdev->family >= CHIP_RV770) {
  2009. radeon_ring_write(ring, 0x0);
  2010. radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
  2011. } else {
  2012. radeon_ring_write(ring, 0x3);
  2013. radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
  2014. }
  2015. radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
  2016. radeon_ring_write(ring, 0);
  2017. radeon_ring_write(ring, 0);
  2018. radeon_ring_unlock_commit(rdev, ring);
  2019. cp_me = 0xff;
  2020. WREG32(R_0086D8_CP_ME_CNTL, cp_me);
  2021. return 0;
  2022. }
  2023. int r600_cp_resume(struct radeon_device *rdev)
  2024. {
  2025. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  2026. u32 tmp;
  2027. u32 rb_bufsz;
  2028. int r;
  2029. /* Reset cp */
  2030. WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
  2031. RREG32(GRBM_SOFT_RESET);
  2032. mdelay(15);
  2033. WREG32(GRBM_SOFT_RESET, 0);
  2034. /* Set ring buffer size */
  2035. rb_bufsz = drm_order(ring->ring_size / 8);
  2036. tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
  2037. #ifdef __BIG_ENDIAN
  2038. tmp |= BUF_SWAP_32BIT;
  2039. #endif
  2040. WREG32(CP_RB_CNTL, tmp);
  2041. WREG32(CP_SEM_WAIT_TIMER, 0x0);
  2042. /* Set the write pointer delay */
  2043. WREG32(CP_RB_WPTR_DELAY, 0);
  2044. /* Initialize the ring buffer's read and write pointers */
  2045. WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
  2046. WREG32(CP_RB_RPTR_WR, 0);
  2047. ring->wptr = 0;
  2048. WREG32(CP_RB_WPTR, ring->wptr);
  2049. /* set the wb address whether it's enabled or not */
  2050. WREG32(CP_RB_RPTR_ADDR,
  2051. ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
  2052. WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
  2053. WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
  2054. if (rdev->wb.enabled)
  2055. WREG32(SCRATCH_UMSK, 0xff);
  2056. else {
  2057. tmp |= RB_NO_UPDATE;
  2058. WREG32(SCRATCH_UMSK, 0);
  2059. }
  2060. mdelay(1);
  2061. WREG32(CP_RB_CNTL, tmp);
  2062. WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
  2063. WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
  2064. ring->rptr = RREG32(CP_RB_RPTR);
  2065. r600_cp_start(rdev);
  2066. ring->ready = true;
  2067. r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
  2068. if (r) {
  2069. ring->ready = false;
  2070. return r;
  2071. }
  2072. return 0;
  2073. }
  2074. void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
  2075. {
  2076. u32 rb_bufsz;
  2077. /* Align ring size */
  2078. rb_bufsz = drm_order(ring_size / 8);
  2079. ring_size = (1 << (rb_bufsz + 1)) * 4;
  2080. ring->ring_size = ring_size;
  2081. ring->align_mask = 16 - 1;
  2082. }
  2083. void r600_cp_fini(struct radeon_device *rdev)
  2084. {
  2085. r600_cp_stop(rdev);
  2086. radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
  2087. }
  2088. /*
  2089. * GPU scratch registers helpers function.
  2090. */
  2091. void r600_scratch_init(struct radeon_device *rdev)
  2092. {
  2093. int i;
  2094. rdev->scratch.num_reg = 7;
  2095. rdev->scratch.reg_base = SCRATCH_REG0;
  2096. for (i = 0; i < rdev->scratch.num_reg; i++) {
  2097. rdev->scratch.free[i] = true;
  2098. rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
  2099. }
  2100. }
  2101. int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
  2102. {
  2103. uint32_t scratch;
  2104. uint32_t tmp = 0;
  2105. unsigned i, ridx = radeon_ring_index(rdev, ring);
  2106. int r;
  2107. r = radeon_scratch_get(rdev, &scratch);
  2108. if (r) {
  2109. DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
  2110. return r;
  2111. }
  2112. WREG32(scratch, 0xCAFEDEAD);
  2113. r = radeon_ring_lock(rdev, ring, 3);
  2114. if (r) {
  2115. DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ridx, r);
  2116. radeon_scratch_free(rdev, scratch);
  2117. return r;
  2118. }
  2119. radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
  2120. radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
  2121. radeon_ring_write(ring, 0xDEADBEEF);
  2122. radeon_ring_unlock_commit(rdev, ring);
  2123. for (i = 0; i < rdev->usec_timeout; i++) {
  2124. tmp = RREG32(scratch);
  2125. if (tmp == 0xDEADBEEF)
  2126. break;
  2127. DRM_UDELAY(1);
  2128. }
  2129. if (i < rdev->usec_timeout) {
  2130. DRM_INFO("ring test on %d succeeded in %d usecs\n", ridx, i);
  2131. } else {
  2132. DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
  2133. ridx, scratch, tmp);
  2134. r = -EINVAL;
  2135. }
  2136. radeon_scratch_free(rdev, scratch);
  2137. return r;
  2138. }
  2139. void r600_fence_ring_emit(struct radeon_device *rdev,
  2140. struct radeon_fence *fence)
  2141. {
  2142. struct radeon_ring *ring = &rdev->ring[fence->ring];
  2143. if (rdev->wb.use_event) {
  2144. u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
  2145. /* flush read cache over gart */
  2146. radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
  2147. radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
  2148. PACKET3_VC_ACTION_ENA |
  2149. PACKET3_SH_ACTION_ENA);
  2150. radeon_ring_write(ring, 0xFFFFFFFF);
  2151. radeon_ring_write(ring, 0);
  2152. radeon_ring_write(ring, 10); /* poll interval */
  2153. /* EVENT_WRITE_EOP - flush caches, send int */
  2154. radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
  2155. radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
  2156. radeon_ring_write(ring, addr & 0xffffffff);
  2157. radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
  2158. radeon_ring_write(ring, fence->seq);
  2159. radeon_ring_write(ring, 0);
  2160. } else {
  2161. /* flush read cache over gart */
  2162. radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
  2163. radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
  2164. PACKET3_VC_ACTION_ENA |
  2165. PACKET3_SH_ACTION_ENA);
  2166. radeon_ring_write(ring, 0xFFFFFFFF);
  2167. radeon_ring_write(ring, 0);
  2168. radeon_ring_write(ring, 10); /* poll interval */
  2169. radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
  2170. radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
  2171. /* wait for 3D idle clean */
  2172. radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
  2173. radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
  2174. radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
  2175. /* Emit fence sequence & fire IRQ */
  2176. radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
  2177. radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
  2178. radeon_ring_write(ring, fence->seq);
  2179. /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
  2180. radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
  2181. radeon_ring_write(ring, RB_INT_STAT);
  2182. }
  2183. }
  2184. void r600_semaphore_ring_emit(struct radeon_device *rdev,
  2185. struct radeon_ring *ring,
  2186. struct radeon_semaphore *semaphore,
  2187. bool emit_wait)
  2188. {
  2189. uint64_t addr = semaphore->gpu_addr;
  2190. unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
  2191. if (rdev->family < CHIP_CAYMAN)
  2192. sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
  2193. radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
  2194. radeon_ring_write(ring, addr & 0xffffffff);
  2195. radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
  2196. }
  2197. int r600_copy_blit(struct radeon_device *rdev,
  2198. uint64_t src_offset,
  2199. uint64_t dst_offset,
  2200. unsigned num_gpu_pages,
  2201. struct radeon_fence *fence)
  2202. {
  2203. struct radeon_sa_bo *vb = NULL;
  2204. int r;
  2205. r = r600_blit_prepare_copy(rdev, num_gpu_pages, &vb);
  2206. if (r) {
  2207. return r;
  2208. }
  2209. r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
  2210. r600_blit_done_copy(rdev, fence, vb);
  2211. return 0;
  2212. }
  2213. void r600_blit_suspend(struct radeon_device *rdev)
  2214. {
  2215. int r;
  2216. /* unpin shaders bo */
  2217. if (rdev->r600_blit.shader_obj) {
  2218. r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
  2219. if (!r) {
  2220. radeon_bo_unpin(rdev->r600_blit.shader_obj);
  2221. radeon_bo_unreserve(rdev->r600_blit.shader_obj);
  2222. }
  2223. }
  2224. }
  2225. int r600_set_surface_reg(struct radeon_device *rdev, int reg,
  2226. uint32_t tiling_flags, uint32_t pitch,
  2227. uint32_t offset, uint32_t obj_size)
  2228. {
  2229. /* FIXME: implement */
  2230. return 0;
  2231. }
  2232. void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
  2233. {
  2234. /* FIXME: implement */
  2235. }
  2236. int r600_startup(struct radeon_device *rdev)
  2237. {
  2238. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  2239. int r;
  2240. /* enable pcie gen2 link */
  2241. r600_pcie_gen2_enable(rdev);
  2242. if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
  2243. r = r600_init_microcode(rdev);
  2244. if (r) {
  2245. DRM_ERROR("Failed to load firmware!\n");
  2246. return r;
  2247. }
  2248. }
  2249. r = r600_vram_scratch_init(rdev);
  2250. if (r)
  2251. return r;
  2252. r600_mc_program(rdev);
  2253. if (rdev->flags & RADEON_IS_AGP) {
  2254. r600_agp_enable(rdev);
  2255. } else {
  2256. r = r600_pcie_gart_enable(rdev);
  2257. if (r)
  2258. return r;
  2259. }
  2260. r600_gpu_init(rdev);
  2261. r = r600_blit_init(rdev);
  2262. if (r) {
  2263. r600_blit_fini(rdev);
  2264. rdev->asic->copy.copy = NULL;
  2265. dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
  2266. }
  2267. /* allocate wb buffer */
  2268. r = radeon_wb_init(rdev);
  2269. if (r)
  2270. return r;
  2271. r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
  2272. if (r) {
  2273. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  2274. return r;
  2275. }
  2276. /* Enable IRQ */
  2277. r = r600_irq_init(rdev);
  2278. if (r) {
  2279. DRM_ERROR("radeon: IH init failed (%d).\n", r);
  2280. radeon_irq_kms_fini(rdev);
  2281. return r;
  2282. }
  2283. r600_irq_set(rdev);
  2284. r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
  2285. R600_CP_RB_RPTR, R600_CP_RB_WPTR,
  2286. 0, 0xfffff, RADEON_CP_PACKET2);
  2287. if (r)
  2288. return r;
  2289. r = r600_cp_load_microcode(rdev);
  2290. if (r)
  2291. return r;
  2292. r = r600_cp_resume(rdev);
  2293. if (r)
  2294. return r;
  2295. r = radeon_ib_pool_start(rdev);
  2296. if (r)
  2297. return r;
  2298. r = radeon_ib_ring_tests(rdev);
  2299. if (r)
  2300. return r;
  2301. return 0;
  2302. }
  2303. void r600_vga_set_state(struct radeon_device *rdev, bool state)
  2304. {
  2305. uint32_t temp;
  2306. temp = RREG32(CONFIG_CNTL);
  2307. if (state == false) {
  2308. temp &= ~(1<<0);
  2309. temp |= (1<<1);
  2310. } else {
  2311. temp &= ~(1<<1);
  2312. }
  2313. WREG32(CONFIG_CNTL, temp);
  2314. }
  2315. int r600_resume(struct radeon_device *rdev)
  2316. {
  2317. int r;
  2318. /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
  2319. * posting will perform necessary task to bring back GPU into good
  2320. * shape.
  2321. */
  2322. /* post card */
  2323. atom_asic_init(rdev->mode_info.atom_context);
  2324. rdev->accel_working = true;
  2325. r = r600_startup(rdev);
  2326. if (r) {
  2327. DRM_ERROR("r600 startup failed on resume\n");
  2328. rdev->accel_working = false;
  2329. return r;
  2330. }
  2331. r = r600_audio_init(rdev);
  2332. if (r) {
  2333. DRM_ERROR("radeon: audio resume failed\n");
  2334. return r;
  2335. }
  2336. return r;
  2337. }
  2338. int r600_suspend(struct radeon_device *rdev)
  2339. {
  2340. r600_audio_fini(rdev);
  2341. radeon_ib_pool_suspend(rdev);
  2342. r600_blit_suspend(rdev);
  2343. /* FIXME: we should wait for ring to be empty */
  2344. r600_cp_stop(rdev);
  2345. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
  2346. r600_irq_suspend(rdev);
  2347. radeon_wb_disable(rdev);
  2348. r600_pcie_gart_disable(rdev);
  2349. return 0;
  2350. }
  2351. /* Plan is to move initialization in that function and use
  2352. * helper function so that radeon_device_init pretty much
  2353. * do nothing more than calling asic specific function. This
  2354. * should also allow to remove a bunch of callback function
  2355. * like vram_info.
  2356. */
  2357. int r600_init(struct radeon_device *rdev)
  2358. {
  2359. int r;
  2360. if (r600_debugfs_mc_info_init(rdev)) {
  2361. DRM_ERROR("Failed to register debugfs file for mc !\n");
  2362. }
  2363. /* This don't do much */
  2364. r = radeon_gem_init(rdev);
  2365. if (r)
  2366. return r;
  2367. /* Read BIOS */
  2368. if (!radeon_get_bios(rdev)) {
  2369. if (ASIC_IS_AVIVO(rdev))
  2370. return -EINVAL;
  2371. }
  2372. /* Must be an ATOMBIOS */
  2373. if (!rdev->is_atom_bios) {
  2374. dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
  2375. return -EINVAL;
  2376. }
  2377. r = radeon_atombios_init(rdev);
  2378. if (r)
  2379. return r;
  2380. /* Post card if necessary */
  2381. if (!radeon_card_posted(rdev)) {
  2382. if (!rdev->bios) {
  2383. dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
  2384. return -EINVAL;
  2385. }
  2386. DRM_INFO("GPU not posted. posting now...\n");
  2387. atom_asic_init(rdev->mode_info.atom_context);
  2388. }
  2389. /* Initialize scratch registers */
  2390. r600_scratch_init(rdev);
  2391. /* Initialize surface registers */
  2392. radeon_surface_init(rdev);
  2393. /* Initialize clocks */
  2394. radeon_get_clock_info(rdev->ddev);
  2395. /* Fence driver */
  2396. r = radeon_fence_driver_init(rdev);
  2397. if (r)
  2398. return r;
  2399. if (rdev->flags & RADEON_IS_AGP) {
  2400. r = radeon_agp_init(rdev);
  2401. if (r)
  2402. radeon_agp_disable(rdev);
  2403. }
  2404. r = r600_mc_init(rdev);
  2405. if (r)
  2406. return r;
  2407. /* Memory manager */
  2408. r = radeon_bo_init(rdev);
  2409. if (r)
  2410. return r;
  2411. r = radeon_irq_kms_init(rdev);
  2412. if (r)
  2413. return r;
  2414. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
  2415. r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
  2416. rdev->ih.ring_obj = NULL;
  2417. r600_ih_ring_init(rdev, 64 * 1024);
  2418. r = r600_pcie_gart_init(rdev);
  2419. if (r)
  2420. return r;
  2421. r = radeon_ib_pool_init(rdev);
  2422. rdev->accel_working = true;
  2423. if (r) {
  2424. dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
  2425. rdev->accel_working = false;
  2426. }
  2427. r = r600_startup(rdev);
  2428. if (r) {
  2429. dev_err(rdev->dev, "disabling GPU acceleration\n");
  2430. r600_cp_fini(rdev);
  2431. r600_irq_fini(rdev);
  2432. radeon_wb_fini(rdev);
  2433. r100_ib_fini(rdev);
  2434. radeon_irq_kms_fini(rdev);
  2435. r600_pcie_gart_fini(rdev);
  2436. rdev->accel_working = false;
  2437. }
  2438. r = r600_audio_init(rdev);
  2439. if (r)
  2440. return r; /* TODO error handling */
  2441. return 0;
  2442. }
  2443. void r600_fini(struct radeon_device *rdev)
  2444. {
  2445. r600_audio_fini(rdev);
  2446. r600_blit_fini(rdev);
  2447. r600_cp_fini(rdev);
  2448. r600_irq_fini(rdev);
  2449. radeon_wb_fini(rdev);
  2450. r100_ib_fini(rdev);
  2451. radeon_irq_kms_fini(rdev);
  2452. r600_pcie_gart_fini(rdev);
  2453. r600_vram_scratch_fini(rdev);
  2454. radeon_agp_fini(rdev);
  2455. radeon_gem_fini(rdev);
  2456. radeon_fence_driver_fini(rdev);
  2457. radeon_bo_fini(rdev);
  2458. radeon_atombios_fini(rdev);
  2459. kfree(rdev->bios);
  2460. rdev->bios = NULL;
  2461. }
  2462. /*
  2463. * CS stuff
  2464. */
  2465. void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
  2466. {
  2467. struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
  2468. /* FIXME: implement */
  2469. radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
  2470. radeon_ring_write(ring,
  2471. #ifdef __BIG_ENDIAN
  2472. (2 << 0) |
  2473. #endif
  2474. (ib->gpu_addr & 0xFFFFFFFC));
  2475. radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
  2476. radeon_ring_write(ring, ib->length_dw);
  2477. }
  2478. int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
  2479. {
  2480. struct radeon_ib ib;
  2481. uint32_t scratch;
  2482. uint32_t tmp = 0;
  2483. unsigned i;
  2484. int r;
  2485. int ring_index = radeon_ring_index(rdev, ring);
  2486. r = radeon_scratch_get(rdev, &scratch);
  2487. if (r) {
  2488. DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
  2489. return r;
  2490. }
  2491. WREG32(scratch, 0xCAFEDEAD);
  2492. r = radeon_ib_get(rdev, ring_index, &ib, 256);
  2493. if (r) {
  2494. DRM_ERROR("radeon: failed to get ib (%d).\n", r);
  2495. return r;
  2496. }
  2497. ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
  2498. ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
  2499. ib.ptr[2] = 0xDEADBEEF;
  2500. ib.length_dw = 3;
  2501. r = radeon_ib_schedule(rdev, &ib);
  2502. if (r) {
  2503. radeon_scratch_free(rdev, scratch);
  2504. radeon_ib_free(rdev, &ib);
  2505. DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
  2506. return r;
  2507. }
  2508. r = radeon_fence_wait(ib.fence, false);
  2509. if (r) {
  2510. DRM_ERROR("radeon: fence wait failed (%d).\n", r);
  2511. return r;
  2512. }
  2513. for (i = 0; i < rdev->usec_timeout; i++) {
  2514. tmp = RREG32(scratch);
  2515. if (tmp == 0xDEADBEEF)
  2516. break;
  2517. DRM_UDELAY(1);
  2518. }
  2519. if (i < rdev->usec_timeout) {
  2520. DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
  2521. } else {
  2522. DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
  2523. scratch, tmp);
  2524. r = -EINVAL;
  2525. }
  2526. radeon_scratch_free(rdev, scratch);
  2527. radeon_ib_free(rdev, &ib);
  2528. return r;
  2529. }
  2530. /*
  2531. * Interrupts
  2532. *
  2533. * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
  2534. * the same as the CP ring buffer, but in reverse. Rather than the CPU
  2535. * writing to the ring and the GPU consuming, the GPU writes to the ring
  2536. * and host consumes. As the host irq handler processes interrupts, it
  2537. * increments the rptr. When the rptr catches up with the wptr, all the
  2538. * current interrupts have been processed.
  2539. */
  2540. void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
  2541. {
  2542. u32 rb_bufsz;
  2543. /* Align ring size */
  2544. rb_bufsz = drm_order(ring_size / 4);
  2545. ring_size = (1 << rb_bufsz) * 4;
  2546. rdev->ih.ring_size = ring_size;
  2547. rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
  2548. rdev->ih.rptr = 0;
  2549. }
  2550. int r600_ih_ring_alloc(struct radeon_device *rdev)
  2551. {
  2552. int r;
  2553. /* Allocate ring buffer */
  2554. if (rdev->ih.ring_obj == NULL) {
  2555. r = radeon_bo_create(rdev, rdev->ih.ring_size,
  2556. PAGE_SIZE, true,
  2557. RADEON_GEM_DOMAIN_GTT,
  2558. &rdev->ih.ring_obj);
  2559. if (r) {
  2560. DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
  2561. return r;
  2562. }
  2563. r = radeon_bo_reserve(rdev->ih.ring_obj, false);
  2564. if (unlikely(r != 0))
  2565. return r;
  2566. r = radeon_bo_pin(rdev->ih.ring_obj,
  2567. RADEON_GEM_DOMAIN_GTT,
  2568. &rdev->ih.gpu_addr);
  2569. if (r) {
  2570. radeon_bo_unreserve(rdev->ih.ring_obj);
  2571. DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
  2572. return r;
  2573. }
  2574. r = radeon_bo_kmap(rdev->ih.ring_obj,
  2575. (void **)&rdev->ih.ring);
  2576. radeon_bo_unreserve(rdev->ih.ring_obj);
  2577. if (r) {
  2578. DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
  2579. return r;
  2580. }
  2581. }
  2582. return 0;
  2583. }
  2584. void r600_ih_ring_fini(struct radeon_device *rdev)
  2585. {
  2586. int r;
  2587. if (rdev->ih.ring_obj) {
  2588. r = radeon_bo_reserve(rdev->ih.ring_obj, false);
  2589. if (likely(r == 0)) {
  2590. radeon_bo_kunmap(rdev->ih.ring_obj);
  2591. radeon_bo_unpin(rdev->ih.ring_obj);
  2592. radeon_bo_unreserve(rdev->ih.ring_obj);
  2593. }
  2594. radeon_bo_unref(&rdev->ih.ring_obj);
  2595. rdev->ih.ring = NULL;
  2596. rdev->ih.ring_obj = NULL;
  2597. }
  2598. }
  2599. void r600_rlc_stop(struct radeon_device *rdev)
  2600. {
  2601. if ((rdev->family >= CHIP_RV770) &&
  2602. (rdev->family <= CHIP_RV740)) {
  2603. /* r7xx asics need to soft reset RLC before halting */
  2604. WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
  2605. RREG32(SRBM_SOFT_RESET);
  2606. mdelay(15);
  2607. WREG32(SRBM_SOFT_RESET, 0);
  2608. RREG32(SRBM_SOFT_RESET);
  2609. }
  2610. WREG32(RLC_CNTL, 0);
  2611. }
  2612. static void r600_rlc_start(struct radeon_device *rdev)
  2613. {
  2614. WREG32(RLC_CNTL, RLC_ENABLE);
  2615. }
  2616. static int r600_rlc_init(struct radeon_device *rdev)
  2617. {
  2618. u32 i;
  2619. const __be32 *fw_data;
  2620. if (!rdev->rlc_fw)
  2621. return -EINVAL;
  2622. r600_rlc_stop(rdev);
  2623. WREG32(RLC_HB_CNTL, 0);
  2624. if (rdev->family == CHIP_ARUBA) {
  2625. WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
  2626. WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
  2627. }
  2628. if (rdev->family <= CHIP_CAYMAN) {
  2629. WREG32(RLC_HB_BASE, 0);
  2630. WREG32(RLC_HB_RPTR, 0);
  2631. WREG32(RLC_HB_WPTR, 0);
  2632. }
  2633. if (rdev->family <= CHIP_CAICOS) {
  2634. WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
  2635. WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
  2636. }
  2637. WREG32(RLC_MC_CNTL, 0);
  2638. WREG32(RLC_UCODE_CNTL, 0);
  2639. fw_data = (const __be32 *)rdev->rlc_fw->data;
  2640. if (rdev->family >= CHIP_ARUBA) {
  2641. for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
  2642. WREG32(RLC_UCODE_ADDR, i);
  2643. WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
  2644. }
  2645. } else if (rdev->family >= CHIP_CAYMAN) {
  2646. for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
  2647. WREG32(RLC_UCODE_ADDR, i);
  2648. WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
  2649. }
  2650. } else if (rdev->family >= CHIP_CEDAR) {
  2651. for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
  2652. WREG32(RLC_UCODE_ADDR, i);
  2653. WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
  2654. }
  2655. } else if (rdev->family >= CHIP_RV770) {
  2656. for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
  2657. WREG32(RLC_UCODE_ADDR, i);
  2658. WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
  2659. }
  2660. } else {
  2661. for (i = 0; i < RLC_UCODE_SIZE; i++) {
  2662. WREG32(RLC_UCODE_ADDR, i);
  2663. WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
  2664. }
  2665. }
  2666. WREG32(RLC_UCODE_ADDR, 0);
  2667. r600_rlc_start(rdev);
  2668. return 0;
  2669. }
  2670. static void r600_enable_interrupts(struct radeon_device *rdev)
  2671. {
  2672. u32 ih_cntl = RREG32(IH_CNTL);
  2673. u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
  2674. ih_cntl |= ENABLE_INTR;
  2675. ih_rb_cntl |= IH_RB_ENABLE;
  2676. WREG32(IH_CNTL, ih_cntl);
  2677. WREG32(IH_RB_CNTL, ih_rb_cntl);
  2678. rdev->ih.enabled = true;
  2679. }
  2680. void r600_disable_interrupts(struct radeon_device *rdev)
  2681. {
  2682. u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
  2683. u32 ih_cntl = RREG32(IH_CNTL);
  2684. ih_rb_cntl &= ~IH_RB_ENABLE;
  2685. ih_cntl &= ~ENABLE_INTR;
  2686. WREG32(IH_RB_CNTL, ih_rb_cntl);
  2687. WREG32(IH_CNTL, ih_cntl);
  2688. /* set rptr, wptr to 0 */
  2689. WREG32(IH_RB_RPTR, 0);
  2690. WREG32(IH_RB_WPTR, 0);
  2691. rdev->ih.enabled = false;
  2692. rdev->ih.wptr = 0;
  2693. rdev->ih.rptr = 0;
  2694. }
  2695. static void r600_disable_interrupt_state(struct radeon_device *rdev)
  2696. {
  2697. u32 tmp;
  2698. WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
  2699. WREG32(GRBM_INT_CNTL, 0);
  2700. WREG32(DxMODE_INT_MASK, 0);
  2701. WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
  2702. WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
  2703. if (ASIC_IS_DCE3(rdev)) {
  2704. WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
  2705. WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
  2706. tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  2707. WREG32(DC_HPD1_INT_CONTROL, tmp);
  2708. tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  2709. WREG32(DC_HPD2_INT_CONTROL, tmp);
  2710. tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  2711. WREG32(DC_HPD3_INT_CONTROL, tmp);
  2712. tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  2713. WREG32(DC_HPD4_INT_CONTROL, tmp);
  2714. if (ASIC_IS_DCE32(rdev)) {
  2715. tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  2716. WREG32(DC_HPD5_INT_CONTROL, tmp);
  2717. tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
  2718. WREG32(DC_HPD6_INT_CONTROL, tmp);
  2719. tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
  2720. WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
  2721. tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
  2722. WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
  2723. } else {
  2724. tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
  2725. WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
  2726. tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
  2727. WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
  2728. }
  2729. } else {
  2730. WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
  2731. WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
  2732. tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
  2733. WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
  2734. tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
  2735. WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
  2736. tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
  2737. WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
  2738. tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
  2739. WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
  2740. tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
  2741. WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
  2742. }
  2743. }
  2744. int r600_irq_init(struct radeon_device *rdev)
  2745. {
  2746. int ret = 0;
  2747. int rb_bufsz;
  2748. u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
  2749. /* allocate ring */
  2750. ret = r600_ih_ring_alloc(rdev);
  2751. if (ret)
  2752. return ret;
  2753. /* disable irqs */
  2754. r600_disable_interrupts(rdev);
  2755. /* init rlc */
  2756. ret = r600_rlc_init(rdev);
  2757. if (ret) {
  2758. r600_ih_ring_fini(rdev);
  2759. return ret;
  2760. }
  2761. /* setup interrupt control */
  2762. /* set dummy read address to ring address */
  2763. WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
  2764. interrupt_cntl = RREG32(INTERRUPT_CNTL);
  2765. /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
  2766. * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
  2767. */
  2768. interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
  2769. /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
  2770. interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
  2771. WREG32(INTERRUPT_CNTL, interrupt_cntl);
  2772. WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
  2773. rb_bufsz = drm_order(rdev->ih.ring_size / 4);
  2774. ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
  2775. IH_WPTR_OVERFLOW_CLEAR |
  2776. (rb_bufsz << 1));
  2777. if (rdev->wb.enabled)
  2778. ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
  2779. /* set the writeback address whether it's enabled or not */
  2780. WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
  2781. WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
  2782. WREG32(IH_RB_CNTL, ih_rb_cntl);
  2783. /* set rptr, wptr to 0 */
  2784. WREG32(IH_RB_RPTR, 0);
  2785. WREG32(IH_RB_WPTR, 0);
  2786. /* Default settings for IH_CNTL (disabled at first) */
  2787. ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
  2788. /* RPTR_REARM only works if msi's are enabled */
  2789. if (rdev->msi_enabled)
  2790. ih_cntl |= RPTR_REARM;
  2791. WREG32(IH_CNTL, ih_cntl);
  2792. /* force the active interrupt state to all disabled */
  2793. if (rdev->family >= CHIP_CEDAR)
  2794. evergreen_disable_interrupt_state(rdev);
  2795. else
  2796. r600_disable_interrupt_state(rdev);
  2797. /* at this point everything should be setup correctly to enable master */
  2798. pci_set_master(rdev->pdev);
  2799. /* enable irqs */
  2800. r600_enable_interrupts(rdev);
  2801. return ret;
  2802. }
  2803. void r600_irq_suspend(struct radeon_device *rdev)
  2804. {
  2805. r600_irq_disable(rdev);
  2806. r600_rlc_stop(rdev);
  2807. }
  2808. void r600_irq_fini(struct radeon_device *rdev)
  2809. {
  2810. r600_irq_suspend(rdev);
  2811. r600_ih_ring_fini(rdev);
  2812. }
  2813. int r600_irq_set(struct radeon_device *rdev)
  2814. {
  2815. u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
  2816. u32 mode_int = 0;
  2817. u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
  2818. u32 grbm_int_cntl = 0;
  2819. u32 hdmi0, hdmi1;
  2820. u32 d1grph = 0, d2grph = 0;
  2821. if (!rdev->irq.installed) {
  2822. WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
  2823. return -EINVAL;
  2824. }
  2825. /* don't enable anything if the ih is disabled */
  2826. if (!rdev->ih.enabled) {
  2827. r600_disable_interrupts(rdev);
  2828. /* force the active interrupt state to all disabled */
  2829. r600_disable_interrupt_state(rdev);
  2830. return 0;
  2831. }
  2832. if (ASIC_IS_DCE3(rdev)) {
  2833. hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2834. hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2835. hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2836. hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2837. if (ASIC_IS_DCE32(rdev)) {
  2838. hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2839. hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2840. hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
  2841. hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
  2842. } else {
  2843. hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
  2844. hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
  2845. }
  2846. } else {
  2847. hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2848. hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2849. hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
  2850. hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
  2851. hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
  2852. }
  2853. if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
  2854. DRM_DEBUG("r600_irq_set: sw int\n");
  2855. cp_int_cntl |= RB_INT_ENABLE;
  2856. cp_int_cntl |= TIME_STAMP_INT_ENABLE;
  2857. }
  2858. if (rdev->irq.crtc_vblank_int[0] ||
  2859. rdev->irq.pflip[0]) {
  2860. DRM_DEBUG("r600_irq_set: vblank 0\n");
  2861. mode_int |= D1MODE_VBLANK_INT_MASK;
  2862. }
  2863. if (rdev->irq.crtc_vblank_int[1] ||
  2864. rdev->irq.pflip[1]) {
  2865. DRM_DEBUG("r600_irq_set: vblank 1\n");
  2866. mode_int |= D2MODE_VBLANK_INT_MASK;
  2867. }
  2868. if (rdev->irq.hpd[0]) {
  2869. DRM_DEBUG("r600_irq_set: hpd 1\n");
  2870. hpd1 |= DC_HPDx_INT_EN;
  2871. }
  2872. if (rdev->irq.hpd[1]) {
  2873. DRM_DEBUG("r600_irq_set: hpd 2\n");
  2874. hpd2 |= DC_HPDx_INT_EN;
  2875. }
  2876. if (rdev->irq.hpd[2]) {
  2877. DRM_DEBUG("r600_irq_set: hpd 3\n");
  2878. hpd3 |= DC_HPDx_INT_EN;
  2879. }
  2880. if (rdev->irq.hpd[3]) {
  2881. DRM_DEBUG("r600_irq_set: hpd 4\n");
  2882. hpd4 |= DC_HPDx_INT_EN;
  2883. }
  2884. if (rdev->irq.hpd[4]) {
  2885. DRM_DEBUG("r600_irq_set: hpd 5\n");
  2886. hpd5 |= DC_HPDx_INT_EN;
  2887. }
  2888. if (rdev->irq.hpd[5]) {
  2889. DRM_DEBUG("r600_irq_set: hpd 6\n");
  2890. hpd6 |= DC_HPDx_INT_EN;
  2891. }
  2892. if (rdev->irq.afmt[0]) {
  2893. DRM_DEBUG("r600_irq_set: hdmi 0\n");
  2894. hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
  2895. }
  2896. if (rdev->irq.afmt[1]) {
  2897. DRM_DEBUG("r600_irq_set: hdmi 0\n");
  2898. hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
  2899. }
  2900. if (rdev->irq.gui_idle) {
  2901. DRM_DEBUG("gui idle\n");
  2902. grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
  2903. }
  2904. WREG32(CP_INT_CNTL, cp_int_cntl);
  2905. WREG32(DxMODE_INT_MASK, mode_int);
  2906. WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
  2907. WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
  2908. WREG32(GRBM_INT_CNTL, grbm_int_cntl);
  2909. if (ASIC_IS_DCE3(rdev)) {
  2910. WREG32(DC_HPD1_INT_CONTROL, hpd1);
  2911. WREG32(DC_HPD2_INT_CONTROL, hpd2);
  2912. WREG32(DC_HPD3_INT_CONTROL, hpd3);
  2913. WREG32(DC_HPD4_INT_CONTROL, hpd4);
  2914. if (ASIC_IS_DCE32(rdev)) {
  2915. WREG32(DC_HPD5_INT_CONTROL, hpd5);
  2916. WREG32(DC_HPD6_INT_CONTROL, hpd6);
  2917. WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
  2918. WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
  2919. } else {
  2920. WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
  2921. WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
  2922. }
  2923. } else {
  2924. WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
  2925. WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
  2926. WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
  2927. WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
  2928. WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
  2929. }
  2930. return 0;
  2931. }
  2932. static void r600_irq_ack(struct radeon_device *rdev)
  2933. {
  2934. u32 tmp;
  2935. if (ASIC_IS_DCE3(rdev)) {
  2936. rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
  2937. rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
  2938. rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
  2939. if (ASIC_IS_DCE32(rdev)) {
  2940. rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
  2941. rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
  2942. } else {
  2943. rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
  2944. rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
  2945. }
  2946. } else {
  2947. rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
  2948. rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
  2949. rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
  2950. rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
  2951. rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
  2952. }
  2953. rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
  2954. rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
  2955. if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
  2956. WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
  2957. if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
  2958. WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
  2959. if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
  2960. WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
  2961. if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
  2962. WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
  2963. if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
  2964. WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
  2965. if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
  2966. WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
  2967. if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
  2968. if (ASIC_IS_DCE3(rdev)) {
  2969. tmp = RREG32(DC_HPD1_INT_CONTROL);
  2970. tmp |= DC_HPDx_INT_ACK;
  2971. WREG32(DC_HPD1_INT_CONTROL, tmp);
  2972. } else {
  2973. tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
  2974. tmp |= DC_HPDx_INT_ACK;
  2975. WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
  2976. }
  2977. }
  2978. if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
  2979. if (ASIC_IS_DCE3(rdev)) {
  2980. tmp = RREG32(DC_HPD2_INT_CONTROL);
  2981. tmp |= DC_HPDx_INT_ACK;
  2982. WREG32(DC_HPD2_INT_CONTROL, tmp);
  2983. } else {
  2984. tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
  2985. tmp |= DC_HPDx_INT_ACK;
  2986. WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
  2987. }
  2988. }
  2989. if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
  2990. if (ASIC_IS_DCE3(rdev)) {
  2991. tmp = RREG32(DC_HPD3_INT_CONTROL);
  2992. tmp |= DC_HPDx_INT_ACK;
  2993. WREG32(DC_HPD3_INT_CONTROL, tmp);
  2994. } else {
  2995. tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
  2996. tmp |= DC_HPDx_INT_ACK;
  2997. WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
  2998. }
  2999. }
  3000. if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
  3001. tmp = RREG32(DC_HPD4_INT_CONTROL);
  3002. tmp |= DC_HPDx_INT_ACK;
  3003. WREG32(DC_HPD4_INT_CONTROL, tmp);
  3004. }
  3005. if (ASIC_IS_DCE32(rdev)) {
  3006. if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
  3007. tmp = RREG32(DC_HPD5_INT_CONTROL);
  3008. tmp |= DC_HPDx_INT_ACK;
  3009. WREG32(DC_HPD5_INT_CONTROL, tmp);
  3010. }
  3011. if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
  3012. tmp = RREG32(DC_HPD5_INT_CONTROL);
  3013. tmp |= DC_HPDx_INT_ACK;
  3014. WREG32(DC_HPD6_INT_CONTROL, tmp);
  3015. }
  3016. if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
  3017. tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
  3018. tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
  3019. WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
  3020. }
  3021. if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
  3022. tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
  3023. tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
  3024. WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
  3025. }
  3026. } else {
  3027. if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
  3028. tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
  3029. tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
  3030. WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
  3031. }
  3032. if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
  3033. if (ASIC_IS_DCE3(rdev)) {
  3034. tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
  3035. tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
  3036. WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
  3037. } else {
  3038. tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
  3039. tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
  3040. WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
  3041. }
  3042. }
  3043. }
  3044. }
  3045. void r600_irq_disable(struct radeon_device *rdev)
  3046. {
  3047. r600_disable_interrupts(rdev);
  3048. /* Wait and acknowledge irq */
  3049. mdelay(1);
  3050. r600_irq_ack(rdev);
  3051. r600_disable_interrupt_state(rdev);
  3052. }
  3053. static u32 r600_get_ih_wptr(struct radeon_device *rdev)
  3054. {
  3055. u32 wptr, tmp;
  3056. if (rdev->wb.enabled)
  3057. wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
  3058. else
  3059. wptr = RREG32(IH_RB_WPTR);
  3060. if (wptr & RB_OVERFLOW) {
  3061. /* When a ring buffer overflow happen start parsing interrupt
  3062. * from the last not overwritten vector (wptr + 16). Hopefully
  3063. * this should allow us to catchup.
  3064. */
  3065. dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
  3066. wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
  3067. rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
  3068. tmp = RREG32(IH_RB_CNTL);
  3069. tmp |= IH_WPTR_OVERFLOW_CLEAR;
  3070. WREG32(IH_RB_CNTL, tmp);
  3071. }
  3072. return (wptr & rdev->ih.ptr_mask);
  3073. }
  3074. /* r600 IV Ring
  3075. * Each IV ring entry is 128 bits:
  3076. * [7:0] - interrupt source id
  3077. * [31:8] - reserved
  3078. * [59:32] - interrupt source data
  3079. * [127:60] - reserved
  3080. *
  3081. * The basic interrupt vector entries
  3082. * are decoded as follows:
  3083. * src_id src_data description
  3084. * 1 0 D1 Vblank
  3085. * 1 1 D1 Vline
  3086. * 5 0 D2 Vblank
  3087. * 5 1 D2 Vline
  3088. * 19 0 FP Hot plug detection A
  3089. * 19 1 FP Hot plug detection B
  3090. * 19 2 DAC A auto-detection
  3091. * 19 3 DAC B auto-detection
  3092. * 21 4 HDMI block A
  3093. * 21 5 HDMI block B
  3094. * 176 - CP_INT RB
  3095. * 177 - CP_INT IB1
  3096. * 178 - CP_INT IB2
  3097. * 181 - EOP Interrupt
  3098. * 233 - GUI Idle
  3099. *
  3100. * Note, these are based on r600 and may need to be
  3101. * adjusted or added to on newer asics
  3102. */
  3103. int r600_irq_process(struct radeon_device *rdev)
  3104. {
  3105. u32 wptr;
  3106. u32 rptr;
  3107. u32 src_id, src_data;
  3108. u32 ring_index;
  3109. unsigned long flags;
  3110. bool queue_hotplug = false;
  3111. bool queue_hdmi = false;
  3112. if (!rdev->ih.enabled || rdev->shutdown)
  3113. return IRQ_NONE;
  3114. /* No MSIs, need a dummy read to flush PCI DMAs */
  3115. if (!rdev->msi_enabled)
  3116. RREG32(IH_RB_WPTR);
  3117. wptr = r600_get_ih_wptr(rdev);
  3118. rptr = rdev->ih.rptr;
  3119. DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
  3120. spin_lock_irqsave(&rdev->ih.lock, flags);
  3121. if (rptr == wptr) {
  3122. spin_unlock_irqrestore(&rdev->ih.lock, flags);
  3123. return IRQ_NONE;
  3124. }
  3125. restart_ih:
  3126. /* Order reading of wptr vs. reading of IH ring data */
  3127. rmb();
  3128. /* display interrupts */
  3129. r600_irq_ack(rdev);
  3130. rdev->ih.wptr = wptr;
  3131. while (rptr != wptr) {
  3132. /* wptr/rptr are in bytes! */
  3133. ring_index = rptr / 4;
  3134. src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
  3135. src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
  3136. switch (src_id) {
  3137. case 1: /* D1 vblank/vline */
  3138. switch (src_data) {
  3139. case 0: /* D1 vblank */
  3140. if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
  3141. if (rdev->irq.crtc_vblank_int[0]) {
  3142. drm_handle_vblank(rdev->ddev, 0);
  3143. rdev->pm.vblank_sync = true;
  3144. wake_up(&rdev->irq.vblank_queue);
  3145. }
  3146. if (rdev->irq.pflip[0])
  3147. radeon_crtc_handle_flip(rdev, 0);
  3148. rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
  3149. DRM_DEBUG("IH: D1 vblank\n");
  3150. }
  3151. break;
  3152. case 1: /* D1 vline */
  3153. if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
  3154. rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
  3155. DRM_DEBUG("IH: D1 vline\n");
  3156. }
  3157. break;
  3158. default:
  3159. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  3160. break;
  3161. }
  3162. break;
  3163. case 5: /* D2 vblank/vline */
  3164. switch (src_data) {
  3165. case 0: /* D2 vblank */
  3166. if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
  3167. if (rdev->irq.crtc_vblank_int[1]) {
  3168. drm_handle_vblank(rdev->ddev, 1);
  3169. rdev->pm.vblank_sync = true;
  3170. wake_up(&rdev->irq.vblank_queue);
  3171. }
  3172. if (rdev->irq.pflip[1])
  3173. radeon_crtc_handle_flip(rdev, 1);
  3174. rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
  3175. DRM_DEBUG("IH: D2 vblank\n");
  3176. }
  3177. break;
  3178. case 1: /* D1 vline */
  3179. if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
  3180. rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
  3181. DRM_DEBUG("IH: D2 vline\n");
  3182. }
  3183. break;
  3184. default:
  3185. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  3186. break;
  3187. }
  3188. break;
  3189. case 19: /* HPD/DAC hotplug */
  3190. switch (src_data) {
  3191. case 0:
  3192. if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
  3193. rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
  3194. queue_hotplug = true;
  3195. DRM_DEBUG("IH: HPD1\n");
  3196. }
  3197. break;
  3198. case 1:
  3199. if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
  3200. rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
  3201. queue_hotplug = true;
  3202. DRM_DEBUG("IH: HPD2\n");
  3203. }
  3204. break;
  3205. case 4:
  3206. if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
  3207. rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
  3208. queue_hotplug = true;
  3209. DRM_DEBUG("IH: HPD3\n");
  3210. }
  3211. break;
  3212. case 5:
  3213. if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
  3214. rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
  3215. queue_hotplug = true;
  3216. DRM_DEBUG("IH: HPD4\n");
  3217. }
  3218. break;
  3219. case 10:
  3220. if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
  3221. rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
  3222. queue_hotplug = true;
  3223. DRM_DEBUG("IH: HPD5\n");
  3224. }
  3225. break;
  3226. case 12:
  3227. if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
  3228. rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
  3229. queue_hotplug = true;
  3230. DRM_DEBUG("IH: HPD6\n");
  3231. }
  3232. break;
  3233. default:
  3234. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  3235. break;
  3236. }
  3237. break;
  3238. case 21: /* hdmi */
  3239. switch (src_data) {
  3240. case 4:
  3241. if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
  3242. rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
  3243. queue_hdmi = true;
  3244. DRM_DEBUG("IH: HDMI0\n");
  3245. }
  3246. break;
  3247. case 5:
  3248. if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
  3249. rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
  3250. queue_hdmi = true;
  3251. DRM_DEBUG("IH: HDMI1\n");
  3252. }
  3253. break;
  3254. default:
  3255. DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
  3256. break;
  3257. }
  3258. break;
  3259. case 176: /* CP_INT in ring buffer */
  3260. case 177: /* CP_INT in IB1 */
  3261. case 178: /* CP_INT in IB2 */
  3262. DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
  3263. radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
  3264. break;
  3265. case 181: /* CP EOP event */
  3266. DRM_DEBUG("IH: CP EOP\n");
  3267. radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
  3268. break;
  3269. case 233: /* GUI IDLE */
  3270. DRM_DEBUG("IH: GUI idle\n");
  3271. rdev->pm.gui_idle = true;
  3272. wake_up(&rdev->irq.idle_queue);
  3273. break;
  3274. default:
  3275. DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
  3276. break;
  3277. }
  3278. /* wptr/rptr are in bytes! */
  3279. rptr += 16;
  3280. rptr &= rdev->ih.ptr_mask;
  3281. }
  3282. /* make sure wptr hasn't changed while processing */
  3283. wptr = r600_get_ih_wptr(rdev);
  3284. if (wptr != rdev->ih.wptr)
  3285. goto restart_ih;
  3286. if (queue_hotplug)
  3287. schedule_work(&rdev->hotplug_work);
  3288. if (queue_hdmi)
  3289. schedule_work(&rdev->audio_work);
  3290. rdev->ih.rptr = rptr;
  3291. WREG32(IH_RB_RPTR, rdev->ih.rptr);
  3292. spin_unlock_irqrestore(&rdev->ih.lock, flags);
  3293. return IRQ_HANDLED;
  3294. }
  3295. /*
  3296. * Debugfs info
  3297. */
  3298. #if defined(CONFIG_DEBUG_FS)
  3299. static int r600_debugfs_mc_info(struct seq_file *m, void *data)
  3300. {
  3301. struct drm_info_node *node = (struct drm_info_node *) m->private;
  3302. struct drm_device *dev = node->minor->dev;
  3303. struct radeon_device *rdev = dev->dev_private;
  3304. DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
  3305. DREG32_SYS(m, rdev, VM_L2_STATUS);
  3306. return 0;
  3307. }
  3308. static struct drm_info_list r600_mc_info_list[] = {
  3309. {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
  3310. };
  3311. #endif
  3312. int r600_debugfs_mc_info_init(struct radeon_device *rdev)
  3313. {
  3314. #if defined(CONFIG_DEBUG_FS)
  3315. return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
  3316. #else
  3317. return 0;
  3318. #endif
  3319. }
  3320. /**
  3321. * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
  3322. * rdev: radeon device structure
  3323. * bo: buffer object struct which userspace is waiting for idle
  3324. *
  3325. * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
  3326. * through ring buffer, this leads to corruption in rendering, see
  3327. * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
  3328. * directly perform HDP flush by writing register through MMIO.
  3329. */
  3330. void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
  3331. {
  3332. /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
  3333. * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
  3334. * This seems to cause problems on some AGP cards. Just use the old
  3335. * method for them.
  3336. */
  3337. if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
  3338. rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
  3339. void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
  3340. u32 tmp;
  3341. WREG32(HDP_DEBUG1, 0);
  3342. tmp = readl((void __iomem *)ptr);
  3343. } else
  3344. WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
  3345. }
  3346. void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
  3347. {
  3348. u32 link_width_cntl, mask, target_reg;
  3349. if (rdev->flags & RADEON_IS_IGP)
  3350. return;
  3351. if (!(rdev->flags & RADEON_IS_PCIE))
  3352. return;
  3353. /* x2 cards have a special sequence */
  3354. if (ASIC_IS_X2(rdev))
  3355. return;
  3356. /* FIXME wait for idle */
  3357. switch (lanes) {
  3358. case 0:
  3359. mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
  3360. break;
  3361. case 1:
  3362. mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
  3363. break;
  3364. case 2:
  3365. mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
  3366. break;
  3367. case 4:
  3368. mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
  3369. break;
  3370. case 8:
  3371. mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
  3372. break;
  3373. case 12:
  3374. mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
  3375. break;
  3376. case 16:
  3377. default:
  3378. mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
  3379. break;
  3380. }
  3381. link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
  3382. if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
  3383. (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
  3384. return;
  3385. if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
  3386. return;
  3387. link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
  3388. RADEON_PCIE_LC_RECONFIG_NOW |
  3389. R600_PCIE_LC_RENEGOTIATE_EN |
  3390. R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
  3391. link_width_cntl |= mask;
  3392. WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  3393. /* some northbridges can renegotiate the link rather than requiring
  3394. * a complete re-config.
  3395. * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
  3396. */
  3397. if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
  3398. link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
  3399. else
  3400. link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
  3401. WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
  3402. RADEON_PCIE_LC_RECONFIG_NOW));
  3403. if (rdev->family >= CHIP_RV770)
  3404. target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
  3405. else
  3406. target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
  3407. /* wait for lane set to complete */
  3408. link_width_cntl = RREG32(target_reg);
  3409. while (link_width_cntl == 0xffffffff)
  3410. link_width_cntl = RREG32(target_reg);
  3411. }
  3412. int r600_get_pcie_lanes(struct radeon_device *rdev)
  3413. {
  3414. u32 link_width_cntl;
  3415. if (rdev->flags & RADEON_IS_IGP)
  3416. return 0;
  3417. if (!(rdev->flags & RADEON_IS_PCIE))
  3418. return 0;
  3419. /* x2 cards have a special sequence */
  3420. if (ASIC_IS_X2(rdev))
  3421. return 0;
  3422. /* FIXME wait for idle */
  3423. link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
  3424. switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
  3425. case RADEON_PCIE_LC_LINK_WIDTH_X0:
  3426. return 0;
  3427. case RADEON_PCIE_LC_LINK_WIDTH_X1:
  3428. return 1;
  3429. case RADEON_PCIE_LC_LINK_WIDTH_X2:
  3430. return 2;
  3431. case RADEON_PCIE_LC_LINK_WIDTH_X4:
  3432. return 4;
  3433. case RADEON_PCIE_LC_LINK_WIDTH_X8:
  3434. return 8;
  3435. case RADEON_PCIE_LC_LINK_WIDTH_X16:
  3436. default:
  3437. return 16;
  3438. }
  3439. }
  3440. static void r600_pcie_gen2_enable(struct radeon_device *rdev)
  3441. {
  3442. u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
  3443. u16 link_cntl2;
  3444. if (radeon_pcie_gen2 == 0)
  3445. return;
  3446. if (rdev->flags & RADEON_IS_IGP)
  3447. return;
  3448. if (!(rdev->flags & RADEON_IS_PCIE))
  3449. return;
  3450. /* x2 cards have a special sequence */
  3451. if (ASIC_IS_X2(rdev))
  3452. return;
  3453. /* only RV6xx+ chips are supported */
  3454. if (rdev->family <= CHIP_R600)
  3455. return;
  3456. /* 55 nm r6xx asics */
  3457. if ((rdev->family == CHIP_RV670) ||
  3458. (rdev->family == CHIP_RV620) ||
  3459. (rdev->family == CHIP_RV635)) {
  3460. /* advertise upconfig capability */
  3461. link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
  3462. link_width_cntl &= ~LC_UPCONFIGURE_DIS;
  3463. WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  3464. link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
  3465. if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
  3466. lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
  3467. link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
  3468. LC_RECONFIG_ARC_MISSING_ESCAPE);
  3469. link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
  3470. WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  3471. } else {
  3472. link_width_cntl |= LC_UPCONFIGURE_DIS;
  3473. WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  3474. }
  3475. }
  3476. speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
  3477. if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
  3478. (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
  3479. /* 55 nm r6xx asics */
  3480. if ((rdev->family == CHIP_RV670) ||
  3481. (rdev->family == CHIP_RV620) ||
  3482. (rdev->family == CHIP_RV635)) {
  3483. WREG32(MM_CFGREGS_CNTL, 0x8);
  3484. link_cntl2 = RREG32(0x4088);
  3485. WREG32(MM_CFGREGS_CNTL, 0);
  3486. /* not supported yet */
  3487. if (link_cntl2 & SELECTABLE_DEEMPHASIS)
  3488. return;
  3489. }
  3490. speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
  3491. speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
  3492. speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
  3493. speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
  3494. speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
  3495. WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
  3496. tmp = RREG32(0x541c);
  3497. WREG32(0x541c, tmp | 0x8);
  3498. WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
  3499. link_cntl2 = RREG16(0x4088);
  3500. link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
  3501. link_cntl2 |= 0x2;
  3502. WREG16(0x4088, link_cntl2);
  3503. WREG32(MM_CFGREGS_CNTL, 0);
  3504. if ((rdev->family == CHIP_RV670) ||
  3505. (rdev->family == CHIP_RV620) ||
  3506. (rdev->family == CHIP_RV635)) {
  3507. training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
  3508. training_cntl &= ~LC_POINT_7_PLUS_EN;
  3509. WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
  3510. } else {
  3511. speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
  3512. speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
  3513. WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
  3514. }
  3515. speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
  3516. speed_cntl |= LC_GEN2_EN_STRAP;
  3517. WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
  3518. } else {
  3519. link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
  3520. /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
  3521. if (1)
  3522. link_width_cntl |= LC_UPCONFIGURE_DIS;
  3523. else
  3524. link_width_cntl &= ~LC_UPCONFIGURE_DIS;
  3525. WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  3526. }
  3527. }