netxen_nic_init.c 45 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901
  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * Copyright (C) 2009 - QLogic Corporation.
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  19. * MA 02111-1307, USA.
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called "COPYING".
  23. *
  24. */
  25. #include <linux/netdevice.h>
  26. #include <linux/delay.h>
  27. #include <linux/slab.h>
  28. #include "netxen_nic.h"
  29. #include "netxen_nic_hw.h"
  30. struct crb_addr_pair {
  31. u32 addr;
  32. u32 data;
  33. };
  34. #define NETXEN_MAX_CRB_XFORM 60
  35. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  36. #define NETXEN_ADDR_ERROR (0xffffffff)
  37. #define crb_addr_transform(name) \
  38. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  39. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  40. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  41. static void
  42. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  43. struct nx_host_rds_ring *rds_ring);
  44. static int netxen_p3_has_mn(struct netxen_adapter *adapter);
  45. static void crb_addr_transform_setup(void)
  46. {
  47. crb_addr_transform(XDMA);
  48. crb_addr_transform(TIMR);
  49. crb_addr_transform(SRE);
  50. crb_addr_transform(SQN3);
  51. crb_addr_transform(SQN2);
  52. crb_addr_transform(SQN1);
  53. crb_addr_transform(SQN0);
  54. crb_addr_transform(SQS3);
  55. crb_addr_transform(SQS2);
  56. crb_addr_transform(SQS1);
  57. crb_addr_transform(SQS0);
  58. crb_addr_transform(RPMX7);
  59. crb_addr_transform(RPMX6);
  60. crb_addr_transform(RPMX5);
  61. crb_addr_transform(RPMX4);
  62. crb_addr_transform(RPMX3);
  63. crb_addr_transform(RPMX2);
  64. crb_addr_transform(RPMX1);
  65. crb_addr_transform(RPMX0);
  66. crb_addr_transform(ROMUSB);
  67. crb_addr_transform(SN);
  68. crb_addr_transform(QMN);
  69. crb_addr_transform(QMS);
  70. crb_addr_transform(PGNI);
  71. crb_addr_transform(PGND);
  72. crb_addr_transform(PGN3);
  73. crb_addr_transform(PGN2);
  74. crb_addr_transform(PGN1);
  75. crb_addr_transform(PGN0);
  76. crb_addr_transform(PGSI);
  77. crb_addr_transform(PGSD);
  78. crb_addr_transform(PGS3);
  79. crb_addr_transform(PGS2);
  80. crb_addr_transform(PGS1);
  81. crb_addr_transform(PGS0);
  82. crb_addr_transform(PS);
  83. crb_addr_transform(PH);
  84. crb_addr_transform(NIU);
  85. crb_addr_transform(I2Q);
  86. crb_addr_transform(EG);
  87. crb_addr_transform(MN);
  88. crb_addr_transform(MS);
  89. crb_addr_transform(CAS2);
  90. crb_addr_transform(CAS1);
  91. crb_addr_transform(CAS0);
  92. crb_addr_transform(CAM);
  93. crb_addr_transform(C2C1);
  94. crb_addr_transform(C2C0);
  95. crb_addr_transform(SMB);
  96. crb_addr_transform(OCM0);
  97. crb_addr_transform(I2C0);
  98. }
  99. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  100. {
  101. struct netxen_recv_context *recv_ctx;
  102. struct nx_host_rds_ring *rds_ring;
  103. struct netxen_rx_buffer *rx_buf;
  104. int i, ring;
  105. recv_ctx = &adapter->recv_ctx;
  106. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  107. rds_ring = &recv_ctx->rds_rings[ring];
  108. for (i = 0; i < rds_ring->num_desc; ++i) {
  109. rx_buf = &(rds_ring->rx_buf_arr[i]);
  110. if (rx_buf->state == NETXEN_BUFFER_FREE)
  111. continue;
  112. pci_unmap_single(adapter->pdev,
  113. rx_buf->dma,
  114. rds_ring->dma_size,
  115. PCI_DMA_FROMDEVICE);
  116. if (rx_buf->skb != NULL)
  117. dev_kfree_skb_any(rx_buf->skb);
  118. }
  119. }
  120. }
  121. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  122. {
  123. struct netxen_cmd_buffer *cmd_buf;
  124. struct netxen_skb_frag *buffrag;
  125. int i, j;
  126. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  127. cmd_buf = tx_ring->cmd_buf_arr;
  128. for (i = 0; i < tx_ring->num_desc; i++) {
  129. buffrag = cmd_buf->frag_array;
  130. if (buffrag->dma) {
  131. pci_unmap_single(adapter->pdev, buffrag->dma,
  132. buffrag->length, PCI_DMA_TODEVICE);
  133. buffrag->dma = 0ULL;
  134. }
  135. for (j = 0; j < cmd_buf->frag_count; j++) {
  136. buffrag++;
  137. if (buffrag->dma) {
  138. pci_unmap_page(adapter->pdev, buffrag->dma,
  139. buffrag->length,
  140. PCI_DMA_TODEVICE);
  141. buffrag->dma = 0ULL;
  142. }
  143. }
  144. if (cmd_buf->skb) {
  145. dev_kfree_skb_any(cmd_buf->skb);
  146. cmd_buf->skb = NULL;
  147. }
  148. cmd_buf++;
  149. }
  150. }
  151. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  152. {
  153. struct netxen_recv_context *recv_ctx;
  154. struct nx_host_rds_ring *rds_ring;
  155. struct nx_host_tx_ring *tx_ring;
  156. int ring;
  157. recv_ctx = &adapter->recv_ctx;
  158. if (recv_ctx->rds_rings == NULL)
  159. goto skip_rds;
  160. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  161. rds_ring = &recv_ctx->rds_rings[ring];
  162. vfree(rds_ring->rx_buf_arr);
  163. rds_ring->rx_buf_arr = NULL;
  164. }
  165. kfree(recv_ctx->rds_rings);
  166. skip_rds:
  167. if (adapter->tx_ring == NULL)
  168. return;
  169. tx_ring = adapter->tx_ring;
  170. vfree(tx_ring->cmd_buf_arr);
  171. kfree(tx_ring);
  172. adapter->tx_ring = NULL;
  173. }
  174. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  175. {
  176. struct netxen_recv_context *recv_ctx;
  177. struct nx_host_rds_ring *rds_ring;
  178. struct nx_host_sds_ring *sds_ring;
  179. struct nx_host_tx_ring *tx_ring;
  180. struct netxen_rx_buffer *rx_buf;
  181. int ring, i, size;
  182. struct netxen_cmd_buffer *cmd_buf_arr;
  183. struct net_device *netdev = adapter->netdev;
  184. struct pci_dev *pdev = adapter->pdev;
  185. size = sizeof(struct nx_host_tx_ring);
  186. tx_ring = kzalloc(size, GFP_KERNEL);
  187. if (tx_ring == NULL) {
  188. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  189. netdev->name);
  190. return -ENOMEM;
  191. }
  192. adapter->tx_ring = tx_ring;
  193. tx_ring->num_desc = adapter->num_txd;
  194. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  195. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  196. if (cmd_buf_arr == NULL) {
  197. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  198. netdev->name);
  199. goto err_out;
  200. }
  201. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  202. tx_ring->cmd_buf_arr = cmd_buf_arr;
  203. recv_ctx = &adapter->recv_ctx;
  204. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  205. rds_ring = kzalloc(size, GFP_KERNEL);
  206. if (rds_ring == NULL) {
  207. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  208. netdev->name);
  209. goto err_out;
  210. }
  211. recv_ctx->rds_rings = rds_ring;
  212. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  213. rds_ring = &recv_ctx->rds_rings[ring];
  214. switch (ring) {
  215. case RCV_RING_NORMAL:
  216. rds_ring->num_desc = adapter->num_rxd;
  217. if (adapter->ahw.cut_through) {
  218. rds_ring->dma_size =
  219. NX_CT_DEFAULT_RX_BUF_LEN;
  220. rds_ring->skb_size =
  221. NX_CT_DEFAULT_RX_BUF_LEN;
  222. } else {
  223. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  224. rds_ring->dma_size =
  225. NX_P3_RX_BUF_MAX_LEN;
  226. else
  227. rds_ring->dma_size =
  228. NX_P2_RX_BUF_MAX_LEN;
  229. rds_ring->skb_size =
  230. rds_ring->dma_size + NET_IP_ALIGN;
  231. }
  232. break;
  233. case RCV_RING_JUMBO:
  234. rds_ring->num_desc = adapter->num_jumbo_rxd;
  235. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  236. rds_ring->dma_size =
  237. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  238. else
  239. rds_ring->dma_size =
  240. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  241. if (adapter->capabilities & NX_CAP0_HW_LRO)
  242. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  243. rds_ring->skb_size =
  244. rds_ring->dma_size + NET_IP_ALIGN;
  245. break;
  246. case RCV_RING_LRO:
  247. rds_ring->num_desc = adapter->num_lro_rxd;
  248. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  249. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  250. break;
  251. }
  252. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  253. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  254. if (rds_ring->rx_buf_arr == NULL) {
  255. printk(KERN_ERR "%s: Failed to allocate "
  256. "rx buffer ring %d\n",
  257. netdev->name, ring);
  258. /* free whatever was already allocated */
  259. goto err_out;
  260. }
  261. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  262. INIT_LIST_HEAD(&rds_ring->free_list);
  263. /*
  264. * Now go through all of them, set reference handles
  265. * and put them in the queues.
  266. */
  267. rx_buf = rds_ring->rx_buf_arr;
  268. for (i = 0; i < rds_ring->num_desc; i++) {
  269. list_add_tail(&rx_buf->list,
  270. &rds_ring->free_list);
  271. rx_buf->ref_handle = i;
  272. rx_buf->state = NETXEN_BUFFER_FREE;
  273. rx_buf++;
  274. }
  275. spin_lock_init(&rds_ring->lock);
  276. }
  277. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  278. sds_ring = &recv_ctx->sds_rings[ring];
  279. sds_ring->irq = adapter->msix_entries[ring].vector;
  280. sds_ring->adapter = adapter;
  281. sds_ring->num_desc = adapter->num_rxd;
  282. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  283. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  284. }
  285. return 0;
  286. err_out:
  287. netxen_free_sw_resources(adapter);
  288. return -ENOMEM;
  289. }
  290. /*
  291. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  292. * address to external PCI CRB address.
  293. */
  294. static u32 netxen_decode_crb_addr(u32 addr)
  295. {
  296. int i;
  297. u32 base_addr, offset, pci_base;
  298. crb_addr_transform_setup();
  299. pci_base = NETXEN_ADDR_ERROR;
  300. base_addr = addr & 0xfff00000;
  301. offset = addr & 0x000fffff;
  302. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  303. if (crb_addr_xform[i] == base_addr) {
  304. pci_base = i << 20;
  305. break;
  306. }
  307. }
  308. if (pci_base == NETXEN_ADDR_ERROR)
  309. return pci_base;
  310. else
  311. return (pci_base + offset);
  312. }
  313. #define NETXEN_MAX_ROM_WAIT_USEC 100
  314. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  315. {
  316. long timeout = 0;
  317. long done = 0;
  318. cond_resched();
  319. while (done == 0) {
  320. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  321. done &= 2;
  322. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  323. dev_err(&adapter->pdev->dev,
  324. "Timeout reached waiting for rom done");
  325. return -EIO;
  326. }
  327. udelay(1);
  328. }
  329. return 0;
  330. }
  331. static int do_rom_fast_read(struct netxen_adapter *adapter,
  332. int addr, int *valp)
  333. {
  334. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  335. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  336. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  337. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  338. if (netxen_wait_rom_done(adapter)) {
  339. printk("Error waiting for rom done\n");
  340. return -EIO;
  341. }
  342. /* reset abyte_cnt and dummy_byte_cnt */
  343. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  344. udelay(10);
  345. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  346. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  347. return 0;
  348. }
  349. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  350. u8 *bytes, size_t size)
  351. {
  352. int addridx;
  353. int ret = 0;
  354. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  355. int v;
  356. ret = do_rom_fast_read(adapter, addridx, &v);
  357. if (ret != 0)
  358. break;
  359. *(__le32 *)bytes = cpu_to_le32(v);
  360. bytes += 4;
  361. }
  362. return ret;
  363. }
  364. int
  365. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  366. u8 *bytes, size_t size)
  367. {
  368. int ret;
  369. ret = netxen_rom_lock(adapter);
  370. if (ret < 0)
  371. return ret;
  372. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  373. netxen_rom_unlock(adapter);
  374. return ret;
  375. }
  376. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  377. {
  378. int ret;
  379. if (netxen_rom_lock(adapter) != 0)
  380. return -EIO;
  381. ret = do_rom_fast_read(adapter, addr, valp);
  382. netxen_rom_unlock(adapter);
  383. return ret;
  384. }
  385. #define NETXEN_BOARDTYPE 0x4008
  386. #define NETXEN_BOARDNUM 0x400c
  387. #define NETXEN_CHIPNUM 0x4010
  388. int netxen_pinit_from_rom(struct netxen_adapter *adapter)
  389. {
  390. int addr, val;
  391. int i, n, init_delay = 0;
  392. struct crb_addr_pair *buf;
  393. unsigned offset;
  394. u32 off;
  395. /* resetall */
  396. netxen_rom_lock(adapter);
  397. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  398. netxen_rom_unlock(adapter);
  399. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  400. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  401. (n != 0xcafecafe) ||
  402. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  403. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  404. "n: %08x\n", netxen_nic_driver_name, n);
  405. return -EIO;
  406. }
  407. offset = n & 0xffffU;
  408. n = (n >> 16) & 0xffffU;
  409. } else {
  410. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  411. !(n & 0x80000000)) {
  412. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  413. "n: %08x\n", netxen_nic_driver_name, n);
  414. return -EIO;
  415. }
  416. offset = 1;
  417. n &= ~0x80000000;
  418. }
  419. if (n >= 1024) {
  420. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  421. " initialized.\n", __func__, n);
  422. return -EIO;
  423. }
  424. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  425. if (buf == NULL) {
  426. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  427. netxen_nic_driver_name);
  428. return -ENOMEM;
  429. }
  430. for (i = 0; i < n; i++) {
  431. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  432. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  433. kfree(buf);
  434. return -EIO;
  435. }
  436. buf[i].addr = addr;
  437. buf[i].data = val;
  438. }
  439. for (i = 0; i < n; i++) {
  440. off = netxen_decode_crb_addr(buf[i].addr);
  441. if (off == NETXEN_ADDR_ERROR) {
  442. printk(KERN_ERR"CRB init value out of range %x\n",
  443. buf[i].addr);
  444. continue;
  445. }
  446. off += NETXEN_PCI_CRBSPACE;
  447. if (off & 1)
  448. continue;
  449. /* skipping cold reboot MAGIC */
  450. if (off == NETXEN_CAM_RAM(0x1fc))
  451. continue;
  452. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  453. if (off == (NETXEN_CRB_I2C0 + 0x1c))
  454. continue;
  455. /* do not reset PCI */
  456. if (off == (ROMUSB_GLB + 0xbc))
  457. continue;
  458. if (off == (ROMUSB_GLB + 0xa8))
  459. continue;
  460. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  461. continue;
  462. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  463. continue;
  464. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  465. continue;
  466. if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
  467. continue;
  468. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
  469. !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  470. buf[i].data = 0x1020;
  471. /* skip the function enable register */
  472. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  473. continue;
  474. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  475. continue;
  476. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  477. continue;
  478. }
  479. init_delay = 1;
  480. /* After writing this register, HW needs time for CRB */
  481. /* to quiet down (else crb_window returns 0xffffffff) */
  482. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  483. init_delay = 1000;
  484. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  485. /* hold xdma in reset also */
  486. buf[i].data = NETXEN_NIC_XDMA_RESET;
  487. buf[i].data = 0x8000ff;
  488. }
  489. }
  490. NXWR32(adapter, off, buf[i].data);
  491. msleep(init_delay);
  492. }
  493. kfree(buf);
  494. /* disable_peg_cache_all */
  495. /* unreset_net_cache */
  496. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  497. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  498. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  499. }
  500. /* p2dn replyCount */
  501. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  502. /* disable_peg_cache 0 */
  503. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  504. /* disable_peg_cache 1 */
  505. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  506. /* peg_clr_all */
  507. /* peg_clr 0 */
  508. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  509. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  510. /* peg_clr 1 */
  511. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  512. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  513. /* peg_clr 2 */
  514. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  515. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  516. /* peg_clr 3 */
  517. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  518. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  519. return 0;
  520. }
  521. static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
  522. {
  523. uint32_t i;
  524. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  525. __le32 entries = cpu_to_le32(directory->num_entries);
  526. for (i = 0; i < entries; i++) {
  527. __le32 offs = cpu_to_le32(directory->findex) +
  528. (i * cpu_to_le32(directory->entry_size));
  529. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  530. if (tab_type == section)
  531. return (struct uni_table_desc *) &unirom[offs];
  532. }
  533. return NULL;
  534. }
  535. #define QLCNIC_FILEHEADER_SIZE (14 * 4)
  536. static int
  537. netxen_nic_validate_header(struct netxen_adapter *adapter)
  538. {
  539. const u8 *unirom = adapter->fw->data;
  540. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  541. u32 fw_file_size = adapter->fw->size;
  542. u32 tab_size;
  543. __le32 entries;
  544. __le32 entry_size;
  545. if (fw_file_size < QLCNIC_FILEHEADER_SIZE)
  546. return -EINVAL;
  547. entries = cpu_to_le32(directory->num_entries);
  548. entry_size = cpu_to_le32(directory->entry_size);
  549. tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
  550. if (fw_file_size < tab_size)
  551. return -EINVAL;
  552. return 0;
  553. }
  554. static int
  555. netxen_nic_validate_bootld(struct netxen_adapter *adapter)
  556. {
  557. struct uni_table_desc *tab_desc;
  558. struct uni_data_desc *descr;
  559. const u8 *unirom = adapter->fw->data;
  560. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  561. NX_UNI_BOOTLD_IDX_OFF));
  562. u32 offs;
  563. u32 tab_size;
  564. u32 data_size;
  565. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_BOOTLD);
  566. if (!tab_desc)
  567. return -EINVAL;
  568. tab_size = cpu_to_le32(tab_desc->findex) +
  569. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  570. if (adapter->fw->size < tab_size)
  571. return -EINVAL;
  572. offs = cpu_to_le32(tab_desc->findex) +
  573. (cpu_to_le32(tab_desc->entry_size) * (idx));
  574. descr = (struct uni_data_desc *)&unirom[offs];
  575. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  576. if (adapter->fw->size < data_size)
  577. return -EINVAL;
  578. return 0;
  579. }
  580. static int
  581. netxen_nic_validate_fw(struct netxen_adapter *adapter)
  582. {
  583. struct uni_table_desc *tab_desc;
  584. struct uni_data_desc *descr;
  585. const u8 *unirom = adapter->fw->data;
  586. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  587. NX_UNI_FIRMWARE_IDX_OFF));
  588. u32 offs;
  589. u32 tab_size;
  590. u32 data_size;
  591. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_FW);
  592. if (!tab_desc)
  593. return -EINVAL;
  594. tab_size = cpu_to_le32(tab_desc->findex) +
  595. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  596. if (adapter->fw->size < tab_size)
  597. return -EINVAL;
  598. offs = cpu_to_le32(tab_desc->findex) +
  599. (cpu_to_le32(tab_desc->entry_size) * (idx));
  600. descr = (struct uni_data_desc *)&unirom[offs];
  601. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  602. if (adapter->fw->size < data_size)
  603. return -EINVAL;
  604. return 0;
  605. }
  606. static int
  607. netxen_nic_validate_product_offs(struct netxen_adapter *adapter)
  608. {
  609. struct uni_table_desc *ptab_descr;
  610. const u8 *unirom = adapter->fw->data;
  611. int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
  612. 1 : netxen_p3_has_mn(adapter);
  613. __le32 entries;
  614. __le32 entry_size;
  615. u32 tab_size;
  616. u32 i;
  617. ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
  618. if (ptab_descr == NULL)
  619. return -EINVAL;
  620. entries = cpu_to_le32(ptab_descr->num_entries);
  621. entry_size = cpu_to_le32(ptab_descr->entry_size);
  622. tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
  623. if (adapter->fw->size < tab_size)
  624. return -EINVAL;
  625. nomn:
  626. for (i = 0; i < entries; i++) {
  627. __le32 flags, file_chiprev, offs;
  628. u8 chiprev = adapter->ahw.revision_id;
  629. uint32_t flagbit;
  630. offs = cpu_to_le32(ptab_descr->findex) +
  631. (i * cpu_to_le32(ptab_descr->entry_size));
  632. flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
  633. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  634. NX_UNI_CHIP_REV_OFF));
  635. flagbit = mn_present ? 1 : 2;
  636. if ((chiprev == file_chiprev) &&
  637. ((1ULL << flagbit) & flags)) {
  638. adapter->file_prd_off = offs;
  639. return 0;
  640. }
  641. }
  642. if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  643. mn_present = 0;
  644. goto nomn;
  645. }
  646. return -EINVAL;
  647. }
  648. static int
  649. netxen_nic_validate_unified_romimage(struct netxen_adapter *adapter)
  650. {
  651. if (netxen_nic_validate_header(adapter)) {
  652. dev_err(&adapter->pdev->dev,
  653. "unified image: header validation failed\n");
  654. return -EINVAL;
  655. }
  656. if (netxen_nic_validate_product_offs(adapter)) {
  657. dev_err(&adapter->pdev->dev,
  658. "unified image: product validation failed\n");
  659. return -EINVAL;
  660. }
  661. if (netxen_nic_validate_bootld(adapter)) {
  662. dev_err(&adapter->pdev->dev,
  663. "unified image: bootld validation failed\n");
  664. return -EINVAL;
  665. }
  666. if (netxen_nic_validate_fw(adapter)) {
  667. dev_err(&adapter->pdev->dev,
  668. "unified image: firmware validation failed\n");
  669. return -EINVAL;
  670. }
  671. return 0;
  672. }
  673. static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
  674. u32 section, u32 idx_offset)
  675. {
  676. const u8 *unirom = adapter->fw->data;
  677. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  678. idx_offset));
  679. struct uni_table_desc *tab_desc;
  680. __le32 offs;
  681. tab_desc = nx_get_table_desc(unirom, section);
  682. if (tab_desc == NULL)
  683. return NULL;
  684. offs = cpu_to_le32(tab_desc->findex) +
  685. (cpu_to_le32(tab_desc->entry_size) * idx);
  686. return (struct uni_data_desc *)&unirom[offs];
  687. }
  688. static u8 *
  689. nx_get_bootld_offs(struct netxen_adapter *adapter)
  690. {
  691. u32 offs = NETXEN_BOOTLD_START;
  692. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  693. offs = cpu_to_le32((nx_get_data_desc(adapter,
  694. NX_UNI_DIR_SECT_BOOTLD,
  695. NX_UNI_BOOTLD_IDX_OFF))->findex);
  696. return (u8 *)&adapter->fw->data[offs];
  697. }
  698. static u8 *
  699. nx_get_fw_offs(struct netxen_adapter *adapter)
  700. {
  701. u32 offs = NETXEN_IMAGE_START;
  702. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  703. offs = cpu_to_le32((nx_get_data_desc(adapter,
  704. NX_UNI_DIR_SECT_FW,
  705. NX_UNI_FIRMWARE_IDX_OFF))->findex);
  706. return (u8 *)&adapter->fw->data[offs];
  707. }
  708. static __le32
  709. nx_get_fw_size(struct netxen_adapter *adapter)
  710. {
  711. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  712. return cpu_to_le32((nx_get_data_desc(adapter,
  713. NX_UNI_DIR_SECT_FW,
  714. NX_UNI_FIRMWARE_IDX_OFF))->size);
  715. else
  716. return cpu_to_le32(
  717. *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
  718. }
  719. static __le32
  720. nx_get_fw_version(struct netxen_adapter *adapter)
  721. {
  722. struct uni_data_desc *fw_data_desc;
  723. const struct firmware *fw = adapter->fw;
  724. __le32 major, minor, sub;
  725. const u8 *ver_str;
  726. int i, ret = 0;
  727. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  728. fw_data_desc = nx_get_data_desc(adapter,
  729. NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
  730. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  731. cpu_to_le32(fw_data_desc->size) - 17;
  732. for (i = 0; i < 12; i++) {
  733. if (!strncmp(&ver_str[i], "REV=", 4)) {
  734. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  735. &major, &minor, &sub);
  736. break;
  737. }
  738. }
  739. if (ret != 3)
  740. return 0;
  741. return major + (minor << 8) + (sub << 16);
  742. } else
  743. return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  744. }
  745. static __le32
  746. nx_get_bios_version(struct netxen_adapter *adapter)
  747. {
  748. const struct firmware *fw = adapter->fw;
  749. __le32 bios_ver, prd_off = adapter->file_prd_off;
  750. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  751. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  752. + NX_UNI_BIOS_VERSION_OFF));
  753. return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) +
  754. (bios_ver >> 24);
  755. } else
  756. return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  757. }
  758. int
  759. netxen_need_fw_reset(struct netxen_adapter *adapter)
  760. {
  761. u32 count, old_count;
  762. u32 val, version, major, minor, build;
  763. int i, timeout;
  764. u8 fw_type;
  765. /* NX2031 firmware doesn't support heartbit */
  766. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  767. return 1;
  768. if (adapter->need_fw_reset)
  769. return 1;
  770. /* last attempt had failed */
  771. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  772. return 1;
  773. old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  774. for (i = 0; i < 10; i++) {
  775. timeout = msleep_interruptible(200);
  776. if (timeout) {
  777. NXWR32(adapter, CRB_CMDPEG_STATE,
  778. PHAN_INITIALIZE_FAILED);
  779. return -EINTR;
  780. }
  781. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  782. if (count != old_count)
  783. break;
  784. }
  785. /* firmware is dead */
  786. if (count == old_count)
  787. return 1;
  788. /* check if we have got newer or different file firmware */
  789. if (adapter->fw) {
  790. val = nx_get_fw_version(adapter);
  791. version = NETXEN_DECODE_VERSION(val);
  792. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  793. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  794. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  795. if (version > NETXEN_VERSION_CODE(major, minor, build))
  796. return 1;
  797. if (version == NETXEN_VERSION_CODE(major, minor, build) &&
  798. adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
  799. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  800. fw_type = (val & 0x4) ?
  801. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  802. if (adapter->fw_type != fw_type)
  803. return 1;
  804. }
  805. }
  806. return 0;
  807. }
  808. static char *fw_name[] = {
  809. NX_P2_MN_ROMIMAGE_NAME,
  810. NX_P3_CT_ROMIMAGE_NAME,
  811. NX_P3_MN_ROMIMAGE_NAME,
  812. NX_UNIFIED_ROMIMAGE_NAME,
  813. NX_FLASH_ROMIMAGE_NAME,
  814. };
  815. int
  816. netxen_load_firmware(struct netxen_adapter *adapter)
  817. {
  818. u64 *ptr64;
  819. u32 i, flashaddr, size;
  820. const struct firmware *fw = adapter->fw;
  821. struct pci_dev *pdev = adapter->pdev;
  822. dev_info(&pdev->dev, "loading firmware from %s\n",
  823. fw_name[adapter->fw_type]);
  824. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  825. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  826. if (fw) {
  827. __le64 data;
  828. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  829. ptr64 = (u64 *)nx_get_bootld_offs(adapter);
  830. flashaddr = NETXEN_BOOTLD_START;
  831. for (i = 0; i < size; i++) {
  832. data = cpu_to_le64(ptr64[i]);
  833. if (adapter->pci_mem_write(adapter, flashaddr, data))
  834. return -EIO;
  835. flashaddr += 8;
  836. }
  837. size = (__force u32)nx_get_fw_size(adapter) / 8;
  838. ptr64 = (u64 *)nx_get_fw_offs(adapter);
  839. flashaddr = NETXEN_IMAGE_START;
  840. for (i = 0; i < size; i++) {
  841. data = cpu_to_le64(ptr64[i]);
  842. if (adapter->pci_mem_write(adapter,
  843. flashaddr, data))
  844. return -EIO;
  845. flashaddr += 8;
  846. }
  847. size = (__force u32)nx_get_fw_size(adapter) % 8;
  848. if (size) {
  849. data = cpu_to_le64(ptr64[i]);
  850. if (adapter->pci_mem_write(adapter,
  851. flashaddr, data))
  852. return -EIO;
  853. }
  854. } else {
  855. u64 data;
  856. u32 hi, lo;
  857. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  858. flashaddr = NETXEN_BOOTLD_START;
  859. for (i = 0; i < size; i++) {
  860. if (netxen_rom_fast_read(adapter,
  861. flashaddr, (int *)&lo) != 0)
  862. return -EIO;
  863. if (netxen_rom_fast_read(adapter,
  864. flashaddr + 4, (int *)&hi) != 0)
  865. return -EIO;
  866. /* hi, lo are already in host endian byteorder */
  867. data = (((u64)hi << 32) | lo);
  868. if (adapter->pci_mem_write(adapter,
  869. flashaddr, data))
  870. return -EIO;
  871. flashaddr += 8;
  872. }
  873. }
  874. msleep(1);
  875. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
  876. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
  877. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
  878. } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  879. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  880. else {
  881. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  882. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  883. }
  884. return 0;
  885. }
  886. static int
  887. netxen_validate_firmware(struct netxen_adapter *adapter)
  888. {
  889. __le32 val;
  890. u32 ver, min_ver, bios;
  891. struct pci_dev *pdev = adapter->pdev;
  892. const struct firmware *fw = adapter->fw;
  893. u8 fw_type = adapter->fw_type;
  894. if (fw_type == NX_UNIFIED_ROMIMAGE) {
  895. if (netxen_nic_validate_unified_romimage(adapter))
  896. return -EINVAL;
  897. } else {
  898. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  899. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  900. return -EINVAL;
  901. if (fw->size < NX_FW_MIN_SIZE)
  902. return -EINVAL;
  903. }
  904. val = nx_get_fw_version(adapter);
  905. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  906. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  907. else
  908. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  909. ver = NETXEN_DECODE_VERSION(val);
  910. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  911. dev_err(&pdev->dev,
  912. "%s: firmware version %d.%d.%d unsupported\n",
  913. fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
  914. return -EINVAL;
  915. }
  916. val = nx_get_bios_version(adapter);
  917. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  918. if ((__force u32)val != bios) {
  919. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  920. fw_name[fw_type]);
  921. return -EINVAL;
  922. }
  923. /* check if flashed firmware is newer */
  924. if (netxen_rom_fast_read(adapter,
  925. NX_FW_VERSION_OFFSET, (int *)&val))
  926. return -EIO;
  927. val = NETXEN_DECODE_VERSION(val);
  928. if (val > ver) {
  929. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  930. fw_name[fw_type]);
  931. return -EINVAL;
  932. }
  933. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  934. return 0;
  935. }
  936. static void
  937. nx_get_next_fwtype(struct netxen_adapter *adapter)
  938. {
  939. u8 fw_type;
  940. switch (adapter->fw_type) {
  941. case NX_UNKNOWN_ROMIMAGE:
  942. fw_type = NX_UNIFIED_ROMIMAGE;
  943. break;
  944. case NX_UNIFIED_ROMIMAGE:
  945. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  946. fw_type = NX_FLASH_ROMIMAGE;
  947. else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  948. fw_type = NX_P2_MN_ROMIMAGE;
  949. else if (netxen_p3_has_mn(adapter))
  950. fw_type = NX_P3_MN_ROMIMAGE;
  951. else
  952. fw_type = NX_P3_CT_ROMIMAGE;
  953. break;
  954. case NX_P3_MN_ROMIMAGE:
  955. fw_type = NX_P3_CT_ROMIMAGE;
  956. break;
  957. case NX_P2_MN_ROMIMAGE:
  958. case NX_P3_CT_ROMIMAGE:
  959. default:
  960. fw_type = NX_FLASH_ROMIMAGE;
  961. break;
  962. }
  963. adapter->fw_type = fw_type;
  964. }
  965. static int
  966. netxen_p3_has_mn(struct netxen_adapter *adapter)
  967. {
  968. u32 capability, flashed_ver;
  969. capability = 0;
  970. /* NX2031 always had MN */
  971. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  972. return 1;
  973. netxen_rom_fast_read(adapter,
  974. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  975. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  976. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  977. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  978. if (capability & NX_PEG_TUNE_MN_PRESENT)
  979. return 1;
  980. }
  981. return 0;
  982. }
  983. void netxen_request_firmware(struct netxen_adapter *adapter)
  984. {
  985. struct pci_dev *pdev = adapter->pdev;
  986. int rc = 0;
  987. adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
  988. next:
  989. nx_get_next_fwtype(adapter);
  990. if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
  991. adapter->fw = NULL;
  992. } else {
  993. rc = request_firmware(&adapter->fw,
  994. fw_name[adapter->fw_type], &pdev->dev);
  995. if (rc != 0)
  996. goto next;
  997. rc = netxen_validate_firmware(adapter);
  998. if (rc != 0) {
  999. release_firmware(adapter->fw);
  1000. msleep(1);
  1001. goto next;
  1002. }
  1003. }
  1004. }
  1005. void
  1006. netxen_release_firmware(struct netxen_adapter *adapter)
  1007. {
  1008. if (adapter->fw)
  1009. release_firmware(adapter->fw);
  1010. adapter->fw = NULL;
  1011. }
  1012. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  1013. {
  1014. u64 addr;
  1015. u32 hi, lo;
  1016. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1017. return 0;
  1018. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  1019. NETXEN_HOST_DUMMY_DMA_SIZE,
  1020. &adapter->dummy_dma.phys_addr);
  1021. if (adapter->dummy_dma.addr == NULL) {
  1022. dev_err(&adapter->pdev->dev,
  1023. "ERROR: Could not allocate dummy DMA memory\n");
  1024. return -ENOMEM;
  1025. }
  1026. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  1027. hi = (addr >> 32) & 0xffffffff;
  1028. lo = addr & 0xffffffff;
  1029. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  1030. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  1031. return 0;
  1032. }
  1033. /*
  1034. * NetXen DMA watchdog control:
  1035. *
  1036. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  1037. * Bit 1 : disable_request => 1 req disable dma watchdog
  1038. * Bit 2 : enable_request => 1 req enable dma watchdog
  1039. * Bit 3-31 : unused
  1040. */
  1041. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  1042. {
  1043. int i = 100;
  1044. u32 ctrl;
  1045. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1046. return;
  1047. if (!adapter->dummy_dma.addr)
  1048. return;
  1049. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1050. if ((ctrl & 0x1) != 0) {
  1051. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  1052. while ((ctrl & 0x1) != 0) {
  1053. msleep(50);
  1054. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1055. if (--i == 0)
  1056. break;
  1057. };
  1058. }
  1059. if (i) {
  1060. pci_free_consistent(adapter->pdev,
  1061. NETXEN_HOST_DUMMY_DMA_SIZE,
  1062. adapter->dummy_dma.addr,
  1063. adapter->dummy_dma.phys_addr);
  1064. adapter->dummy_dma.addr = NULL;
  1065. } else
  1066. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  1067. }
  1068. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  1069. {
  1070. u32 val = 0;
  1071. int retries = 60;
  1072. if (pegtune_val)
  1073. return 0;
  1074. do {
  1075. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  1076. switch (val) {
  1077. case PHAN_INITIALIZE_COMPLETE:
  1078. case PHAN_INITIALIZE_ACK:
  1079. return 0;
  1080. case PHAN_INITIALIZE_FAILED:
  1081. goto out_err;
  1082. default:
  1083. break;
  1084. }
  1085. msleep(500);
  1086. } while (--retries);
  1087. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  1088. out_err:
  1089. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  1090. return -EIO;
  1091. }
  1092. static int
  1093. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  1094. {
  1095. u32 val = 0;
  1096. int retries = 2000;
  1097. do {
  1098. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  1099. if (val == PHAN_PEG_RCV_INITIALIZED)
  1100. return 0;
  1101. msleep(10);
  1102. } while (--retries);
  1103. if (!retries) {
  1104. printk(KERN_ERR "Receive Peg initialization not "
  1105. "complete, state: 0x%x.\n", val);
  1106. return -EIO;
  1107. }
  1108. return 0;
  1109. }
  1110. int netxen_init_firmware(struct netxen_adapter *adapter)
  1111. {
  1112. int err;
  1113. err = netxen_receive_peg_ready(adapter);
  1114. if (err)
  1115. return err;
  1116. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  1117. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  1118. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  1119. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1120. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  1121. return err;
  1122. }
  1123. static void
  1124. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  1125. {
  1126. u32 cable_OUI;
  1127. u16 cable_len;
  1128. u16 link_speed;
  1129. u8 link_status, module, duplex, autoneg;
  1130. struct net_device *netdev = adapter->netdev;
  1131. adapter->has_link_events = 1;
  1132. cable_OUI = msg->body[1] & 0xffffffff;
  1133. cable_len = (msg->body[1] >> 32) & 0xffff;
  1134. link_speed = (msg->body[1] >> 48) & 0xffff;
  1135. link_status = msg->body[2] & 0xff;
  1136. duplex = (msg->body[2] >> 16) & 0xff;
  1137. autoneg = (msg->body[2] >> 24) & 0xff;
  1138. module = (msg->body[2] >> 8) & 0xff;
  1139. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  1140. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  1141. netdev->name, cable_OUI, cable_len);
  1142. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  1143. printk(KERN_INFO "%s: unsupported cable length %d\n",
  1144. netdev->name, cable_len);
  1145. }
  1146. netxen_advert_link_change(adapter, link_status);
  1147. /* update link parameters */
  1148. if (duplex == LINKEVENT_FULL_DUPLEX)
  1149. adapter->link_duplex = DUPLEX_FULL;
  1150. else
  1151. adapter->link_duplex = DUPLEX_HALF;
  1152. adapter->module_type = module;
  1153. adapter->link_autoneg = autoneg;
  1154. adapter->link_speed = link_speed;
  1155. }
  1156. static void
  1157. netxen_handle_fw_message(int desc_cnt, int index,
  1158. struct nx_host_sds_ring *sds_ring)
  1159. {
  1160. nx_fw_msg_t msg;
  1161. struct status_desc *desc;
  1162. int i = 0, opcode;
  1163. while (desc_cnt > 0 && i < 8) {
  1164. desc = &sds_ring->desc_head[index];
  1165. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1166. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1167. index = get_next_index(index, sds_ring->num_desc);
  1168. desc_cnt--;
  1169. }
  1170. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  1171. switch (opcode) {
  1172. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1173. netxen_handle_linkevent(sds_ring->adapter, &msg);
  1174. break;
  1175. default:
  1176. break;
  1177. }
  1178. }
  1179. static int
  1180. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  1181. struct nx_host_rds_ring *rds_ring,
  1182. struct netxen_rx_buffer *buffer)
  1183. {
  1184. struct sk_buff *skb;
  1185. dma_addr_t dma;
  1186. struct pci_dev *pdev = adapter->pdev;
  1187. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  1188. if (!buffer->skb)
  1189. return 1;
  1190. skb = buffer->skb;
  1191. if (!adapter->ahw.cut_through)
  1192. skb_reserve(skb, 2);
  1193. dma = pci_map_single(pdev, skb->data,
  1194. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1195. if (pci_dma_mapping_error(pdev, dma)) {
  1196. dev_kfree_skb_any(skb);
  1197. buffer->skb = NULL;
  1198. return 1;
  1199. }
  1200. buffer->skb = skb;
  1201. buffer->dma = dma;
  1202. buffer->state = NETXEN_BUFFER_BUSY;
  1203. return 0;
  1204. }
  1205. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1206. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1207. {
  1208. struct netxen_rx_buffer *buffer;
  1209. struct sk_buff *skb;
  1210. buffer = &rds_ring->rx_buf_arr[index];
  1211. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1212. PCI_DMA_FROMDEVICE);
  1213. skb = buffer->skb;
  1214. if (!skb)
  1215. goto no_skb;
  1216. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1217. adapter->stats.csummed++;
  1218. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1219. } else
  1220. skb->ip_summed = CHECKSUM_NONE;
  1221. skb->dev = adapter->netdev;
  1222. buffer->skb = NULL;
  1223. no_skb:
  1224. buffer->state = NETXEN_BUFFER_FREE;
  1225. return skb;
  1226. }
  1227. static struct netxen_rx_buffer *
  1228. netxen_process_rcv(struct netxen_adapter *adapter,
  1229. struct nx_host_sds_ring *sds_ring,
  1230. int ring, u64 sts_data0)
  1231. {
  1232. struct net_device *netdev = adapter->netdev;
  1233. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1234. struct netxen_rx_buffer *buffer;
  1235. struct sk_buff *skb;
  1236. struct nx_host_rds_ring *rds_ring;
  1237. int index, length, cksum, pkt_offset;
  1238. if (unlikely(ring >= adapter->max_rds_rings))
  1239. return NULL;
  1240. rds_ring = &recv_ctx->rds_rings[ring];
  1241. index = netxen_get_sts_refhandle(sts_data0);
  1242. if (unlikely(index >= rds_ring->num_desc))
  1243. return NULL;
  1244. buffer = &rds_ring->rx_buf_arr[index];
  1245. length = netxen_get_sts_totallength(sts_data0);
  1246. cksum = netxen_get_sts_status(sts_data0);
  1247. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1248. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1249. if (!skb)
  1250. return buffer;
  1251. if (length > rds_ring->skb_size)
  1252. skb_put(skb, rds_ring->skb_size);
  1253. else
  1254. skb_put(skb, length);
  1255. if (pkt_offset)
  1256. skb_pull(skb, pkt_offset);
  1257. skb->protocol = eth_type_trans(skb, netdev);
  1258. napi_gro_receive(&sds_ring->napi, skb);
  1259. adapter->stats.rx_pkts++;
  1260. adapter->stats.rxbytes += length;
  1261. return buffer;
  1262. }
  1263. #define TCP_HDR_SIZE 20
  1264. #define TCP_TS_OPTION_SIZE 12
  1265. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1266. static struct netxen_rx_buffer *
  1267. netxen_process_lro(struct netxen_adapter *adapter,
  1268. struct nx_host_sds_ring *sds_ring,
  1269. int ring, u64 sts_data0, u64 sts_data1)
  1270. {
  1271. struct net_device *netdev = adapter->netdev;
  1272. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1273. struct netxen_rx_buffer *buffer;
  1274. struct sk_buff *skb;
  1275. struct nx_host_rds_ring *rds_ring;
  1276. struct iphdr *iph;
  1277. struct tcphdr *th;
  1278. bool push, timestamp;
  1279. int l2_hdr_offset, l4_hdr_offset;
  1280. int index;
  1281. u16 lro_length, length, data_offset;
  1282. u32 seq_number;
  1283. if (unlikely(ring > adapter->max_rds_rings))
  1284. return NULL;
  1285. rds_ring = &recv_ctx->rds_rings[ring];
  1286. index = netxen_get_lro_sts_refhandle(sts_data0);
  1287. if (unlikely(index > rds_ring->num_desc))
  1288. return NULL;
  1289. buffer = &rds_ring->rx_buf_arr[index];
  1290. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1291. lro_length = netxen_get_lro_sts_length(sts_data0);
  1292. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1293. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1294. push = netxen_get_lro_sts_push_flag(sts_data0);
  1295. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1296. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1297. if (!skb)
  1298. return buffer;
  1299. if (timestamp)
  1300. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1301. else
  1302. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1303. skb_put(skb, lro_length + data_offset);
  1304. skb_pull(skb, l2_hdr_offset);
  1305. skb->protocol = eth_type_trans(skb, netdev);
  1306. iph = (struct iphdr *)skb->data;
  1307. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1308. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1309. iph->tot_len = htons(length);
  1310. iph->check = 0;
  1311. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1312. th->psh = push;
  1313. th->seq = htonl(seq_number);
  1314. length = skb->len;
  1315. netif_receive_skb(skb);
  1316. adapter->stats.lro_pkts++;
  1317. adapter->stats.rxbytes += length;
  1318. return buffer;
  1319. }
  1320. #define netxen_merge_rx_buffers(list, head) \
  1321. do { list_splice_tail_init(list, head); } while (0);
  1322. int
  1323. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1324. {
  1325. struct netxen_adapter *adapter = sds_ring->adapter;
  1326. struct list_head *cur;
  1327. struct status_desc *desc;
  1328. struct netxen_rx_buffer *rxbuf;
  1329. u32 consumer = sds_ring->consumer;
  1330. int count = 0;
  1331. u64 sts_data0, sts_data1;
  1332. int opcode, ring = 0, desc_cnt;
  1333. while (count < max) {
  1334. desc = &sds_ring->desc_head[consumer];
  1335. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1336. if (!(sts_data0 & STATUS_OWNER_HOST))
  1337. break;
  1338. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1339. opcode = netxen_get_sts_opcode(sts_data0);
  1340. switch (opcode) {
  1341. case NETXEN_NIC_RXPKT_DESC:
  1342. case NETXEN_OLD_RXPKT_DESC:
  1343. case NETXEN_NIC_SYN_OFFLOAD:
  1344. ring = netxen_get_sts_type(sts_data0);
  1345. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1346. ring, sts_data0);
  1347. break;
  1348. case NETXEN_NIC_LRO_DESC:
  1349. ring = netxen_get_lro_sts_type(sts_data0);
  1350. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1351. rxbuf = netxen_process_lro(adapter, sds_ring,
  1352. ring, sts_data0, sts_data1);
  1353. break;
  1354. case NETXEN_NIC_RESPONSE_DESC:
  1355. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1356. default:
  1357. goto skip;
  1358. }
  1359. WARN_ON(desc_cnt > 1);
  1360. if (rxbuf)
  1361. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1362. skip:
  1363. for (; desc_cnt > 0; desc_cnt--) {
  1364. desc = &sds_ring->desc_head[consumer];
  1365. desc->status_desc_data[0] =
  1366. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1367. consumer = get_next_index(consumer, sds_ring->num_desc);
  1368. }
  1369. count++;
  1370. }
  1371. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1372. struct nx_host_rds_ring *rds_ring =
  1373. &adapter->recv_ctx.rds_rings[ring];
  1374. if (!list_empty(&sds_ring->free_list[ring])) {
  1375. list_for_each(cur, &sds_ring->free_list[ring]) {
  1376. rxbuf = list_entry(cur,
  1377. struct netxen_rx_buffer, list);
  1378. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1379. }
  1380. spin_lock(&rds_ring->lock);
  1381. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1382. &rds_ring->free_list);
  1383. spin_unlock(&rds_ring->lock);
  1384. }
  1385. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1386. }
  1387. if (count) {
  1388. sds_ring->consumer = consumer;
  1389. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1390. }
  1391. return count;
  1392. }
  1393. /* Process Command status ring */
  1394. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1395. {
  1396. u32 sw_consumer, hw_consumer;
  1397. int count = 0, i;
  1398. struct netxen_cmd_buffer *buffer;
  1399. struct pci_dev *pdev = adapter->pdev;
  1400. struct net_device *netdev = adapter->netdev;
  1401. struct netxen_skb_frag *frag;
  1402. int done = 0;
  1403. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1404. if (!spin_trylock(&adapter->tx_clean_lock))
  1405. return 1;
  1406. sw_consumer = tx_ring->sw_consumer;
  1407. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1408. while (sw_consumer != hw_consumer) {
  1409. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1410. if (buffer->skb) {
  1411. frag = &buffer->frag_array[0];
  1412. pci_unmap_single(pdev, frag->dma, frag->length,
  1413. PCI_DMA_TODEVICE);
  1414. frag->dma = 0ULL;
  1415. for (i = 1; i < buffer->frag_count; i++) {
  1416. frag++; /* Get the next frag */
  1417. pci_unmap_page(pdev, frag->dma, frag->length,
  1418. PCI_DMA_TODEVICE);
  1419. frag->dma = 0ULL;
  1420. }
  1421. adapter->stats.xmitfinished++;
  1422. dev_kfree_skb_any(buffer->skb);
  1423. buffer->skb = NULL;
  1424. }
  1425. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1426. if (++count >= MAX_STATUS_HANDLE)
  1427. break;
  1428. }
  1429. if (count && netif_running(netdev)) {
  1430. tx_ring->sw_consumer = sw_consumer;
  1431. smp_mb();
  1432. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1433. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1434. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) {
  1435. netif_wake_queue(netdev);
  1436. adapter->tx_timeo_cnt = 0;
  1437. }
  1438. __netif_tx_unlock(tx_ring->txq);
  1439. }
  1440. }
  1441. /*
  1442. * If everything is freed up to consumer then check if the ring is full
  1443. * If the ring is full then check if more needs to be freed and
  1444. * schedule the call back again.
  1445. *
  1446. * This happens when there are 2 CPUs. One could be freeing and the
  1447. * other filling it. If the ring is full when we get out of here and
  1448. * the card has already interrupted the host then the host can miss the
  1449. * interrupt.
  1450. *
  1451. * There is still a possible race condition and the host could miss an
  1452. * interrupt. The card has to take care of this.
  1453. */
  1454. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1455. done = (sw_consumer == hw_consumer);
  1456. spin_unlock(&adapter->tx_clean_lock);
  1457. return (done);
  1458. }
  1459. void
  1460. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1461. struct nx_host_rds_ring *rds_ring)
  1462. {
  1463. struct rcv_desc *pdesc;
  1464. struct netxen_rx_buffer *buffer;
  1465. int producer, count = 0;
  1466. netxen_ctx_msg msg = 0;
  1467. struct list_head *head;
  1468. producer = rds_ring->producer;
  1469. head = &rds_ring->free_list;
  1470. while (!list_empty(head)) {
  1471. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1472. if (!buffer->skb) {
  1473. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1474. break;
  1475. }
  1476. count++;
  1477. list_del(&buffer->list);
  1478. /* make a rcv descriptor */
  1479. pdesc = &rds_ring->desc_head[producer];
  1480. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1481. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1482. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1483. producer = get_next_index(producer, rds_ring->num_desc);
  1484. }
  1485. if (count) {
  1486. rds_ring->producer = producer;
  1487. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1488. (producer-1) & (rds_ring->num_desc-1));
  1489. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1490. /*
  1491. * Write a doorbell msg to tell phanmon of change in
  1492. * receive ring producer
  1493. * Only for firmware version < 4.0.0
  1494. */
  1495. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1496. netxen_set_msg_privid(msg);
  1497. netxen_set_msg_count(msg,
  1498. ((producer - 1) &
  1499. (rds_ring->num_desc - 1)));
  1500. netxen_set_msg_ctxid(msg, adapter->portnum);
  1501. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1502. NXWRIO(adapter, DB_NORMALIZE(adapter,
  1503. NETXEN_RCV_PRODUCER_OFFSET), msg);
  1504. }
  1505. }
  1506. }
  1507. static void
  1508. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1509. struct nx_host_rds_ring *rds_ring)
  1510. {
  1511. struct rcv_desc *pdesc;
  1512. struct netxen_rx_buffer *buffer;
  1513. int producer, count = 0;
  1514. struct list_head *head;
  1515. if (!spin_trylock(&rds_ring->lock))
  1516. return;
  1517. producer = rds_ring->producer;
  1518. head = &rds_ring->free_list;
  1519. while (!list_empty(head)) {
  1520. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1521. if (!buffer->skb) {
  1522. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1523. break;
  1524. }
  1525. count++;
  1526. list_del(&buffer->list);
  1527. /* make a rcv descriptor */
  1528. pdesc = &rds_ring->desc_head[producer];
  1529. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1530. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1531. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1532. producer = get_next_index(producer, rds_ring->num_desc);
  1533. }
  1534. if (count) {
  1535. rds_ring->producer = producer;
  1536. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1537. (producer - 1) & (rds_ring->num_desc - 1));
  1538. }
  1539. spin_unlock(&rds_ring->lock);
  1540. }
  1541. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1542. {
  1543. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1544. }