clock3xxx_data.c 110 KB

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  1. /*
  2. * OMAP3 clock data
  3. *
  4. * Copyright (C) 2007-2010 Texas Instruments, Inc.
  5. * Copyright (C) 2007-2011 Nokia Corporation
  6. *
  7. * Written by Paul Walmsley
  8. * With many device clock fixes by Kevin Hilman and Jouni Högander
  9. * DPLL bypass clock support added by Roman Tereshonkov
  10. *
  11. */
  12. /*
  13. * Virtual clocks are introduced as convenient tools.
  14. * They are sources for other clocks and not supposed
  15. * to be requested from drivers directly.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/clk.h>
  19. #include <linux/list.h>
  20. #include <plat/hardware.h>
  21. #include <plat/clkdev_omap.h>
  22. #include "iomap.h"
  23. #include "clock.h"
  24. #include "clock3xxx.h"
  25. #include "clock34xx.h"
  26. #include "clock36xx.h"
  27. #include "clock3517.h"
  28. #include "cm2xxx_3xxx.h"
  29. #include "cm-regbits-34xx.h"
  30. #include "prm2xxx_3xxx.h"
  31. #include "prm-regbits-34xx.h"
  32. #include "control.h"
  33. /*
  34. * clocks
  35. */
  36. #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
  37. /* Maximum DPLL multiplier, divider values for OMAP3 */
  38. #define OMAP3_MAX_DPLL_MULT 2047
  39. #define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
  40. #define OMAP3_MAX_DPLL_DIV 128
  41. /*
  42. * DPLL1 supplies clock to the MPU.
  43. * DPLL2 supplies clock to the IVA2.
  44. * DPLL3 supplies CORE domain clocks.
  45. * DPLL4 supplies peripheral clocks.
  46. * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  47. */
  48. /* Forward declarations for DPLL bypass clocks */
  49. static struct clk dpll1_fck;
  50. static struct clk dpll2_fck;
  51. /* PRM CLOCKS */
  52. /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  53. static struct clk omap_32k_fck = {
  54. .name = "omap_32k_fck",
  55. .ops = &clkops_null,
  56. .rate = 32768,
  57. };
  58. static struct clk secure_32k_fck = {
  59. .name = "secure_32k_fck",
  60. .ops = &clkops_null,
  61. .rate = 32768,
  62. };
  63. /* Virtual source clocks for osc_sys_ck */
  64. static struct clk virt_12m_ck = {
  65. .name = "virt_12m_ck",
  66. .ops = &clkops_null,
  67. .rate = 12000000,
  68. };
  69. static struct clk virt_13m_ck = {
  70. .name = "virt_13m_ck",
  71. .ops = &clkops_null,
  72. .rate = 13000000,
  73. };
  74. static struct clk virt_16_8m_ck = {
  75. .name = "virt_16_8m_ck",
  76. .ops = &clkops_null,
  77. .rate = 16800000,
  78. };
  79. static struct clk virt_19_2m_ck = {
  80. .name = "virt_19_2m_ck",
  81. .ops = &clkops_null,
  82. .rate = 19200000,
  83. };
  84. static struct clk virt_26m_ck = {
  85. .name = "virt_26m_ck",
  86. .ops = &clkops_null,
  87. .rate = 26000000,
  88. };
  89. static struct clk virt_38_4m_ck = {
  90. .name = "virt_38_4m_ck",
  91. .ops = &clkops_null,
  92. .rate = 38400000,
  93. };
  94. static const struct clksel_rate osc_sys_12m_rates[] = {
  95. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  96. { .div = 0 }
  97. };
  98. static const struct clksel_rate osc_sys_13m_rates[] = {
  99. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  100. { .div = 0 }
  101. };
  102. static const struct clksel_rate osc_sys_16_8m_rates[] = {
  103. { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
  104. { .div = 0 }
  105. };
  106. static const struct clksel_rate osc_sys_19_2m_rates[] = {
  107. { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
  108. { .div = 0 }
  109. };
  110. static const struct clksel_rate osc_sys_26m_rates[] = {
  111. { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
  112. { .div = 0 }
  113. };
  114. static const struct clksel_rate osc_sys_38_4m_rates[] = {
  115. { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
  116. { .div = 0 }
  117. };
  118. static const struct clksel osc_sys_clksel[] = {
  119. { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
  120. { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
  121. { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
  122. { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
  123. { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
  124. { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
  125. { .parent = NULL },
  126. };
  127. /* Oscillator clock */
  128. /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
  129. static struct clk osc_sys_ck = {
  130. .name = "osc_sys_ck",
  131. .ops = &clkops_null,
  132. .init = &omap2_init_clksel_parent,
  133. .clksel_reg = OMAP3430_PRM_CLKSEL,
  134. .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
  135. .clksel = osc_sys_clksel,
  136. /* REVISIT: deal with autoextclkmode? */
  137. .recalc = &omap2_clksel_recalc,
  138. };
  139. static const struct clksel_rate div2_rates[] = {
  140. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  141. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  142. { .div = 0 }
  143. };
  144. static const struct clksel sys_clksel[] = {
  145. { .parent = &osc_sys_ck, .rates = div2_rates },
  146. { .parent = NULL }
  147. };
  148. /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
  149. /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
  150. static struct clk sys_ck = {
  151. .name = "sys_ck",
  152. .ops = &clkops_null,
  153. .parent = &osc_sys_ck,
  154. .init = &omap2_init_clksel_parent,
  155. .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
  156. .clksel_mask = OMAP_SYSCLKDIV_MASK,
  157. .clksel = sys_clksel,
  158. .recalc = &omap2_clksel_recalc,
  159. };
  160. static struct clk sys_altclk = {
  161. .name = "sys_altclk",
  162. .ops = &clkops_null,
  163. };
  164. /* Optional external clock input for some McBSPs */
  165. static struct clk mcbsp_clks = {
  166. .name = "mcbsp_clks",
  167. .ops = &clkops_null,
  168. };
  169. /* PRM EXTERNAL CLOCK OUTPUT */
  170. static struct clk sys_clkout1 = {
  171. .name = "sys_clkout1",
  172. .ops = &clkops_omap2_dflt,
  173. .parent = &osc_sys_ck,
  174. .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
  175. .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
  176. .recalc = &followparent_recalc,
  177. };
  178. /* DPLLS */
  179. /* CM CLOCKS */
  180. static const struct clksel_rate div16_dpll_rates[] = {
  181. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  182. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  183. { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
  184. { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
  185. { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
  186. { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
  187. { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
  188. { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
  189. { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
  190. { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
  191. { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
  192. { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
  193. { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
  194. { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
  195. { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
  196. { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
  197. { .div = 0 }
  198. };
  199. static const struct clksel_rate dpll4_rates[] = {
  200. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  201. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  202. { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
  203. { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
  204. { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
  205. { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
  206. { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
  207. { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
  208. { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
  209. { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
  210. { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
  211. { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
  212. { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
  213. { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
  214. { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
  215. { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
  216. { .div = 17, .val = 17, .flags = RATE_IN_36XX },
  217. { .div = 18, .val = 18, .flags = RATE_IN_36XX },
  218. { .div = 19, .val = 19, .flags = RATE_IN_36XX },
  219. { .div = 20, .val = 20, .flags = RATE_IN_36XX },
  220. { .div = 21, .val = 21, .flags = RATE_IN_36XX },
  221. { .div = 22, .val = 22, .flags = RATE_IN_36XX },
  222. { .div = 23, .val = 23, .flags = RATE_IN_36XX },
  223. { .div = 24, .val = 24, .flags = RATE_IN_36XX },
  224. { .div = 25, .val = 25, .flags = RATE_IN_36XX },
  225. { .div = 26, .val = 26, .flags = RATE_IN_36XX },
  226. { .div = 27, .val = 27, .flags = RATE_IN_36XX },
  227. { .div = 28, .val = 28, .flags = RATE_IN_36XX },
  228. { .div = 29, .val = 29, .flags = RATE_IN_36XX },
  229. { .div = 30, .val = 30, .flags = RATE_IN_36XX },
  230. { .div = 31, .val = 31, .flags = RATE_IN_36XX },
  231. { .div = 32, .val = 32, .flags = RATE_IN_36XX },
  232. { .div = 0 }
  233. };
  234. /* DPLL1 */
  235. /* MPU clock source */
  236. /* Type: DPLL */
  237. static struct dpll_data dpll1_dd = {
  238. .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
  239. .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
  240. .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
  241. .clk_bypass = &dpll1_fck,
  242. .clk_ref = &sys_ck,
  243. .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
  244. .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
  245. .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
  246. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  247. .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
  248. .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
  249. .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
  250. .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
  251. .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
  252. .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
  253. .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
  254. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  255. .min_divider = 1,
  256. .max_divider = OMAP3_MAX_DPLL_DIV,
  257. };
  258. static struct clk dpll1_ck = {
  259. .name = "dpll1_ck",
  260. .ops = &clkops_omap3_noncore_dpll_ops,
  261. .parent = &sys_ck,
  262. .dpll_data = &dpll1_dd,
  263. .round_rate = &omap2_dpll_round_rate,
  264. .set_rate = &omap3_noncore_dpll_set_rate,
  265. .clkdm_name = "dpll1_clkdm",
  266. .recalc = &omap3_dpll_recalc,
  267. };
  268. /*
  269. * This virtual clock provides the CLKOUTX2 output from the DPLL if the
  270. * DPLL isn't bypassed.
  271. */
  272. static struct clk dpll1_x2_ck = {
  273. .name = "dpll1_x2_ck",
  274. .ops = &clkops_null,
  275. .parent = &dpll1_ck,
  276. .clkdm_name = "dpll1_clkdm",
  277. .recalc = &omap3_clkoutx2_recalc,
  278. };
  279. /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
  280. static const struct clksel div16_dpll1_x2m2_clksel[] = {
  281. { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
  282. { .parent = NULL }
  283. };
  284. /*
  285. * Does not exist in the TRM - needed to separate the M2 divider from
  286. * bypass selection in mpu_ck
  287. */
  288. static struct clk dpll1_x2m2_ck = {
  289. .name = "dpll1_x2m2_ck",
  290. .ops = &clkops_null,
  291. .parent = &dpll1_x2_ck,
  292. .init = &omap2_init_clksel_parent,
  293. .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
  294. .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
  295. .clksel = div16_dpll1_x2m2_clksel,
  296. .clkdm_name = "dpll1_clkdm",
  297. .recalc = &omap2_clksel_recalc,
  298. };
  299. /* DPLL2 */
  300. /* IVA2 clock source */
  301. /* Type: DPLL */
  302. static struct dpll_data dpll2_dd = {
  303. .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
  304. .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
  305. .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
  306. .clk_bypass = &dpll2_fck,
  307. .clk_ref = &sys_ck,
  308. .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
  309. .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
  310. .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
  311. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
  312. (1 << DPLL_LOW_POWER_BYPASS),
  313. .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
  314. .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
  315. .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
  316. .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
  317. .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
  318. .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
  319. .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
  320. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  321. .min_divider = 1,
  322. .max_divider = OMAP3_MAX_DPLL_DIV,
  323. };
  324. static struct clk dpll2_ck = {
  325. .name = "dpll2_ck",
  326. .ops = &clkops_omap3_noncore_dpll_ops,
  327. .parent = &sys_ck,
  328. .dpll_data = &dpll2_dd,
  329. .round_rate = &omap2_dpll_round_rate,
  330. .set_rate = &omap3_noncore_dpll_set_rate,
  331. .clkdm_name = "dpll2_clkdm",
  332. .recalc = &omap3_dpll_recalc,
  333. };
  334. static const struct clksel div16_dpll2_m2x2_clksel[] = {
  335. { .parent = &dpll2_ck, .rates = div16_dpll_rates },
  336. { .parent = NULL }
  337. };
  338. /*
  339. * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
  340. * or CLKOUTX2. CLKOUT seems most plausible.
  341. */
  342. static struct clk dpll2_m2_ck = {
  343. .name = "dpll2_m2_ck",
  344. .ops = &clkops_null,
  345. .parent = &dpll2_ck,
  346. .init = &omap2_init_clksel_parent,
  347. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
  348. OMAP3430_CM_CLKSEL2_PLL),
  349. .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
  350. .clksel = div16_dpll2_m2x2_clksel,
  351. .clkdm_name = "dpll2_clkdm",
  352. .recalc = &omap2_clksel_recalc,
  353. };
  354. /*
  355. * DPLL3
  356. * Source clock for all interfaces and for some device fclks
  357. * REVISIT: Also supports fast relock bypass - not included below
  358. */
  359. static struct dpll_data dpll3_dd = {
  360. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  361. .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
  362. .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
  363. .clk_bypass = &sys_ck,
  364. .clk_ref = &sys_ck,
  365. .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
  366. .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  367. .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
  368. .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
  369. .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
  370. .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
  371. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
  372. .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
  373. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
  374. .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
  375. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  376. .min_divider = 1,
  377. .max_divider = OMAP3_MAX_DPLL_DIV,
  378. };
  379. static struct clk dpll3_ck = {
  380. .name = "dpll3_ck",
  381. .ops = &clkops_omap3_core_dpll_ops,
  382. .parent = &sys_ck,
  383. .dpll_data = &dpll3_dd,
  384. .round_rate = &omap2_dpll_round_rate,
  385. .clkdm_name = "dpll3_clkdm",
  386. .recalc = &omap3_dpll_recalc,
  387. };
  388. /*
  389. * This virtual clock provides the CLKOUTX2 output from the DPLL if the
  390. * DPLL isn't bypassed
  391. */
  392. static struct clk dpll3_x2_ck = {
  393. .name = "dpll3_x2_ck",
  394. .ops = &clkops_null,
  395. .parent = &dpll3_ck,
  396. .clkdm_name = "dpll3_clkdm",
  397. .recalc = &omap3_clkoutx2_recalc,
  398. };
  399. static const struct clksel_rate div31_dpll3_rates[] = {
  400. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  401. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  402. { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
  403. { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
  404. { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
  405. { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
  406. { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
  407. { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
  408. { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
  409. { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
  410. { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
  411. { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
  412. { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
  413. { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
  414. { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
  415. { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
  416. { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
  417. { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
  418. { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
  419. { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
  420. { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
  421. { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
  422. { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
  423. { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
  424. { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
  425. { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
  426. { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
  427. { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
  428. { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
  429. { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
  430. { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
  431. { .div = 0 },
  432. };
  433. static const struct clksel div31_dpll3m2_clksel[] = {
  434. { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
  435. { .parent = NULL }
  436. };
  437. /* DPLL3 output M2 - primary control point for CORE speed */
  438. static struct clk dpll3_m2_ck = {
  439. .name = "dpll3_m2_ck",
  440. .ops = &clkops_null,
  441. .parent = &dpll3_ck,
  442. .init = &omap2_init_clksel_parent,
  443. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  444. .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
  445. .clksel = div31_dpll3m2_clksel,
  446. .clkdm_name = "dpll3_clkdm",
  447. .round_rate = &omap2_clksel_round_rate,
  448. .set_rate = &omap3_core_dpll_m2_set_rate,
  449. .recalc = &omap2_clksel_recalc,
  450. };
  451. static struct clk core_ck = {
  452. .name = "core_ck",
  453. .ops = &clkops_null,
  454. .parent = &dpll3_m2_ck,
  455. .recalc = &followparent_recalc,
  456. };
  457. static struct clk dpll3_m2x2_ck = {
  458. .name = "dpll3_m2x2_ck",
  459. .ops = &clkops_null,
  460. .parent = &dpll3_m2_ck,
  461. .clkdm_name = "dpll3_clkdm",
  462. .recalc = &omap3_clkoutx2_recalc,
  463. };
  464. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  465. static const struct clksel div16_dpll3_clksel[] = {
  466. { .parent = &dpll3_ck, .rates = div16_dpll_rates },
  467. { .parent = NULL }
  468. };
  469. /* This virtual clock is the source for dpll3_m3x2_ck */
  470. static struct clk dpll3_m3_ck = {
  471. .name = "dpll3_m3_ck",
  472. .ops = &clkops_null,
  473. .parent = &dpll3_ck,
  474. .init = &omap2_init_clksel_parent,
  475. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  476. .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
  477. .clksel = div16_dpll3_clksel,
  478. .clkdm_name = "dpll3_clkdm",
  479. .recalc = &omap2_clksel_recalc,
  480. };
  481. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  482. static struct clk dpll3_m3x2_ck = {
  483. .name = "dpll3_m3x2_ck",
  484. .ops = &clkops_omap2_dflt_wait,
  485. .parent = &dpll3_m3_ck,
  486. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  487. .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
  488. .flags = INVERT_ENABLE,
  489. .clkdm_name = "dpll3_clkdm",
  490. .recalc = &omap3_clkoutx2_recalc,
  491. };
  492. static struct clk emu_core_alwon_ck = {
  493. .name = "emu_core_alwon_ck",
  494. .ops = &clkops_null,
  495. .parent = &dpll3_m3x2_ck,
  496. .clkdm_name = "dpll3_clkdm",
  497. .recalc = &followparent_recalc,
  498. };
  499. /* DPLL4 */
  500. /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
  501. /* Type: DPLL */
  502. static struct dpll_data dpll4_dd;
  503. static struct dpll_data dpll4_dd_34xx __initdata = {
  504. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
  505. .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
  506. .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
  507. .clk_bypass = &sys_ck,
  508. .clk_ref = &sys_ck,
  509. .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
  510. .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  511. .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
  512. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
  513. .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
  514. .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
  515. .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
  516. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
  517. .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
  518. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
  519. .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
  520. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  521. .min_divider = 1,
  522. .max_divider = OMAP3_MAX_DPLL_DIV,
  523. };
  524. static struct dpll_data dpll4_dd_3630 __initdata = {
  525. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
  526. .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
  527. .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
  528. .clk_bypass = &sys_ck,
  529. .clk_ref = &sys_ck,
  530. .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  531. .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
  532. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
  533. .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
  534. .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
  535. .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
  536. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
  537. .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
  538. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
  539. .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
  540. .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
  541. .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
  542. .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
  543. .min_divider = 1,
  544. .max_divider = OMAP3_MAX_DPLL_DIV,
  545. .flags = DPLL_J_TYPE
  546. };
  547. static struct clk dpll4_ck = {
  548. .name = "dpll4_ck",
  549. .ops = &clkops_omap3_noncore_dpll_ops,
  550. .parent = &sys_ck,
  551. .dpll_data = &dpll4_dd,
  552. .round_rate = &omap2_dpll_round_rate,
  553. .set_rate = &omap3_dpll4_set_rate,
  554. .clkdm_name = "dpll4_clkdm",
  555. .recalc = &omap3_dpll_recalc,
  556. };
  557. /*
  558. * This virtual clock provides the CLKOUTX2 output from the DPLL if the
  559. * DPLL isn't bypassed --
  560. * XXX does this serve any downstream clocks?
  561. */
  562. static struct clk dpll4_x2_ck = {
  563. .name = "dpll4_x2_ck",
  564. .ops = &clkops_null,
  565. .parent = &dpll4_ck,
  566. .clkdm_name = "dpll4_clkdm",
  567. .recalc = &omap3_clkoutx2_recalc,
  568. };
  569. static const struct clksel dpll4_clksel[] = {
  570. { .parent = &dpll4_ck, .rates = dpll4_rates },
  571. { .parent = NULL }
  572. };
  573. /* This virtual clock is the source for dpll4_m2x2_ck */
  574. static struct clk dpll4_m2_ck = {
  575. .name = "dpll4_m2_ck",
  576. .ops = &clkops_null,
  577. .parent = &dpll4_ck,
  578. .init = &omap2_init_clksel_parent,
  579. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
  580. .clksel_mask = OMAP3630_DIV_96M_MASK,
  581. .clksel = dpll4_clksel,
  582. .clkdm_name = "dpll4_clkdm",
  583. .recalc = &omap2_clksel_recalc,
  584. };
  585. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  586. static struct clk dpll4_m2x2_ck = {
  587. .name = "dpll4_m2x2_ck",
  588. .ops = &clkops_omap2_dflt_wait,
  589. .parent = &dpll4_m2_ck,
  590. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  591. .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
  592. .flags = INVERT_ENABLE,
  593. .clkdm_name = "dpll4_clkdm",
  594. .recalc = &omap3_clkoutx2_recalc,
  595. };
  596. /*
  597. * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
  598. * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
  599. * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
  600. * CM_96K_(F)CLK.
  601. */
  602. /* Adding 192MHz Clock node needed by SGX */
  603. static struct clk omap_192m_alwon_fck = {
  604. .name = "omap_192m_alwon_fck",
  605. .ops = &clkops_null,
  606. .parent = &dpll4_m2x2_ck,
  607. .recalc = &followparent_recalc,
  608. };
  609. static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
  610. { .div = 1, .val = 1, .flags = RATE_IN_36XX },
  611. { .div = 2, .val = 2, .flags = RATE_IN_36XX },
  612. { .div = 0 }
  613. };
  614. static const struct clksel omap_96m_alwon_fck_clksel[] = {
  615. { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
  616. { .parent = NULL }
  617. };
  618. static const struct clksel_rate omap_96m_dpll_rates[] = {
  619. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  620. { .div = 0 }
  621. };
  622. static const struct clksel_rate omap_96m_sys_rates[] = {
  623. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  624. { .div = 0 }
  625. };
  626. static struct clk omap_96m_alwon_fck = {
  627. .name = "omap_96m_alwon_fck",
  628. .ops = &clkops_null,
  629. .parent = &dpll4_m2x2_ck,
  630. .recalc = &followparent_recalc,
  631. };
  632. static struct clk omap_96m_alwon_fck_3630 = {
  633. .name = "omap_96m_alwon_fck",
  634. .parent = &omap_192m_alwon_fck,
  635. .init = &omap2_init_clksel_parent,
  636. .ops = &clkops_null,
  637. .recalc = &omap2_clksel_recalc,
  638. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  639. .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
  640. .clksel = omap_96m_alwon_fck_clksel
  641. };
  642. static struct clk cm_96m_fck = {
  643. .name = "cm_96m_fck",
  644. .ops = &clkops_null,
  645. .parent = &omap_96m_alwon_fck,
  646. .recalc = &followparent_recalc,
  647. };
  648. static const struct clksel omap_96m_fck_clksel[] = {
  649. { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
  650. { .parent = &sys_ck, .rates = omap_96m_sys_rates },
  651. { .parent = NULL }
  652. };
  653. static struct clk omap_96m_fck = {
  654. .name = "omap_96m_fck",
  655. .ops = &clkops_null,
  656. .parent = &sys_ck,
  657. .init = &omap2_init_clksel_parent,
  658. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  659. .clksel_mask = OMAP3430_SOURCE_96M_MASK,
  660. .clksel = omap_96m_fck_clksel,
  661. .recalc = &omap2_clksel_recalc,
  662. };
  663. /* This virtual clock is the source for dpll4_m3x2_ck */
  664. static struct clk dpll4_m3_ck = {
  665. .name = "dpll4_m3_ck",
  666. .ops = &clkops_null,
  667. .parent = &dpll4_ck,
  668. .init = &omap2_init_clksel_parent,
  669. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
  670. .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
  671. .clksel = dpll4_clksel,
  672. .clkdm_name = "dpll4_clkdm",
  673. .recalc = &omap2_clksel_recalc,
  674. };
  675. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  676. static struct clk dpll4_m3x2_ck = {
  677. .name = "dpll4_m3x2_ck",
  678. .ops = &clkops_omap2_dflt_wait,
  679. .parent = &dpll4_m3_ck,
  680. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  681. .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
  682. .flags = INVERT_ENABLE,
  683. .clkdm_name = "dpll4_clkdm",
  684. .recalc = &omap3_clkoutx2_recalc,
  685. };
  686. static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
  687. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  688. { .div = 0 }
  689. };
  690. static const struct clksel_rate omap_54m_alt_rates[] = {
  691. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  692. { .div = 0 }
  693. };
  694. static const struct clksel omap_54m_clksel[] = {
  695. { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
  696. { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
  697. { .parent = NULL }
  698. };
  699. static struct clk omap_54m_fck = {
  700. .name = "omap_54m_fck",
  701. .ops = &clkops_null,
  702. .init = &omap2_init_clksel_parent,
  703. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  704. .clksel_mask = OMAP3430_SOURCE_54M_MASK,
  705. .clksel = omap_54m_clksel,
  706. .recalc = &omap2_clksel_recalc,
  707. };
  708. static const struct clksel_rate omap_48m_cm96m_rates[] = {
  709. { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
  710. { .div = 0 }
  711. };
  712. static const struct clksel_rate omap_48m_alt_rates[] = {
  713. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  714. { .div = 0 }
  715. };
  716. static const struct clksel omap_48m_clksel[] = {
  717. { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
  718. { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
  719. { .parent = NULL }
  720. };
  721. static struct clk omap_48m_fck = {
  722. .name = "omap_48m_fck",
  723. .ops = &clkops_null,
  724. .init = &omap2_init_clksel_parent,
  725. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  726. .clksel_mask = OMAP3430_SOURCE_48M_MASK,
  727. .clksel = omap_48m_clksel,
  728. .recalc = &omap2_clksel_recalc,
  729. };
  730. static struct clk omap_12m_fck = {
  731. .name = "omap_12m_fck",
  732. .ops = &clkops_null,
  733. .parent = &omap_48m_fck,
  734. .fixed_div = 4,
  735. .recalc = &omap_fixed_divisor_recalc,
  736. };
  737. /* This virtual clock is the source for dpll4_m4x2_ck */
  738. static struct clk dpll4_m4_ck = {
  739. .name = "dpll4_m4_ck",
  740. .ops = &clkops_null,
  741. .parent = &dpll4_ck,
  742. .init = &omap2_init_clksel_parent,
  743. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
  744. .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
  745. .clksel = dpll4_clksel,
  746. .clkdm_name = "dpll4_clkdm",
  747. .recalc = &omap2_clksel_recalc,
  748. .set_rate = &omap2_clksel_set_rate,
  749. .round_rate = &omap2_clksel_round_rate,
  750. };
  751. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  752. static struct clk dpll4_m4x2_ck = {
  753. .name = "dpll4_m4x2_ck",
  754. .ops = &clkops_omap2_dflt_wait,
  755. .parent = &dpll4_m4_ck,
  756. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  757. .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
  758. .flags = INVERT_ENABLE,
  759. .clkdm_name = "dpll4_clkdm",
  760. .recalc = &omap3_clkoutx2_recalc,
  761. };
  762. /* This virtual clock is the source for dpll4_m5x2_ck */
  763. static struct clk dpll4_m5_ck = {
  764. .name = "dpll4_m5_ck",
  765. .ops = &clkops_null,
  766. .parent = &dpll4_ck,
  767. .init = &omap2_init_clksel_parent,
  768. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
  769. .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
  770. .clksel = dpll4_clksel,
  771. .clkdm_name = "dpll4_clkdm",
  772. .set_rate = &omap2_clksel_set_rate,
  773. .round_rate = &omap2_clksel_round_rate,
  774. .recalc = &omap2_clksel_recalc,
  775. };
  776. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  777. static struct clk dpll4_m5x2_ck = {
  778. .name = "dpll4_m5x2_ck",
  779. .ops = &clkops_omap2_dflt_wait,
  780. .parent = &dpll4_m5_ck,
  781. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  782. .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
  783. .flags = INVERT_ENABLE,
  784. .clkdm_name = "dpll4_clkdm",
  785. .recalc = &omap3_clkoutx2_recalc,
  786. };
  787. /* This virtual clock is the source for dpll4_m6x2_ck */
  788. static struct clk dpll4_m6_ck = {
  789. .name = "dpll4_m6_ck",
  790. .ops = &clkops_null,
  791. .parent = &dpll4_ck,
  792. .init = &omap2_init_clksel_parent,
  793. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  794. .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
  795. .clksel = dpll4_clksel,
  796. .clkdm_name = "dpll4_clkdm",
  797. .recalc = &omap2_clksel_recalc,
  798. };
  799. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  800. static struct clk dpll4_m6x2_ck = {
  801. .name = "dpll4_m6x2_ck",
  802. .ops = &clkops_omap2_dflt_wait,
  803. .parent = &dpll4_m6_ck,
  804. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  805. .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
  806. .flags = INVERT_ENABLE,
  807. .clkdm_name = "dpll4_clkdm",
  808. .recalc = &omap3_clkoutx2_recalc,
  809. };
  810. static struct clk emu_per_alwon_ck = {
  811. .name = "emu_per_alwon_ck",
  812. .ops = &clkops_null,
  813. .parent = &dpll4_m6x2_ck,
  814. .clkdm_name = "dpll4_clkdm",
  815. .recalc = &followparent_recalc,
  816. };
  817. /* DPLL5 */
  818. /* Supplies 120MHz clock, USIM source clock */
  819. /* Type: DPLL */
  820. /* 3430ES2 only */
  821. static struct dpll_data dpll5_dd = {
  822. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
  823. .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
  824. .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
  825. .clk_bypass = &sys_ck,
  826. .clk_ref = &sys_ck,
  827. .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
  828. .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
  829. .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
  830. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
  831. .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
  832. .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
  833. .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
  834. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
  835. .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
  836. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
  837. .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
  838. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  839. .min_divider = 1,
  840. .max_divider = OMAP3_MAX_DPLL_DIV,
  841. };
  842. static struct clk dpll5_ck = {
  843. .name = "dpll5_ck",
  844. .ops = &clkops_omap3_noncore_dpll_ops,
  845. .parent = &sys_ck,
  846. .dpll_data = &dpll5_dd,
  847. .round_rate = &omap2_dpll_round_rate,
  848. .set_rate = &omap3_noncore_dpll_set_rate,
  849. .clkdm_name = "dpll5_clkdm",
  850. .recalc = &omap3_dpll_recalc,
  851. };
  852. static const struct clksel div16_dpll5_clksel[] = {
  853. { .parent = &dpll5_ck, .rates = div16_dpll_rates },
  854. { .parent = NULL }
  855. };
  856. static struct clk dpll5_m2_ck = {
  857. .name = "dpll5_m2_ck",
  858. .ops = &clkops_null,
  859. .parent = &dpll5_ck,
  860. .init = &omap2_init_clksel_parent,
  861. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
  862. .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
  863. .clksel = div16_dpll5_clksel,
  864. .clkdm_name = "dpll5_clkdm",
  865. .recalc = &omap2_clksel_recalc,
  866. };
  867. /* CM EXTERNAL CLOCK OUTPUTS */
  868. static const struct clksel_rate clkout2_src_core_rates[] = {
  869. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  870. { .div = 0 }
  871. };
  872. static const struct clksel_rate clkout2_src_sys_rates[] = {
  873. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  874. { .div = 0 }
  875. };
  876. static const struct clksel_rate clkout2_src_96m_rates[] = {
  877. { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
  878. { .div = 0 }
  879. };
  880. static const struct clksel_rate clkout2_src_54m_rates[] = {
  881. { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
  882. { .div = 0 }
  883. };
  884. static const struct clksel clkout2_src_clksel[] = {
  885. { .parent = &core_ck, .rates = clkout2_src_core_rates },
  886. { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
  887. { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
  888. { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
  889. { .parent = NULL }
  890. };
  891. static struct clk clkout2_src_ck = {
  892. .name = "clkout2_src_ck",
  893. .ops = &clkops_omap2_dflt,
  894. .init = &omap2_init_clksel_parent,
  895. .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
  896. .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
  897. .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
  898. .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
  899. .clksel = clkout2_src_clksel,
  900. .clkdm_name = "core_clkdm",
  901. .recalc = &omap2_clksel_recalc,
  902. };
  903. static const struct clksel_rate sys_clkout2_rates[] = {
  904. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  905. { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
  906. { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
  907. { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
  908. { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
  909. { .div = 0 },
  910. };
  911. static const struct clksel sys_clkout2_clksel[] = {
  912. { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
  913. { .parent = NULL },
  914. };
  915. static struct clk sys_clkout2 = {
  916. .name = "sys_clkout2",
  917. .ops = &clkops_null,
  918. .init = &omap2_init_clksel_parent,
  919. .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
  920. .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
  921. .clksel = sys_clkout2_clksel,
  922. .recalc = &omap2_clksel_recalc,
  923. .round_rate = &omap2_clksel_round_rate,
  924. .set_rate = &omap2_clksel_set_rate
  925. };
  926. /* CM OUTPUT CLOCKS */
  927. static struct clk corex2_fck = {
  928. .name = "corex2_fck",
  929. .ops = &clkops_null,
  930. .parent = &dpll3_m2x2_ck,
  931. .recalc = &followparent_recalc,
  932. };
  933. /* DPLL power domain clock controls */
  934. static const struct clksel_rate div4_rates[] = {
  935. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  936. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  937. { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
  938. { .div = 0 }
  939. };
  940. static const struct clksel div4_core_clksel[] = {
  941. { .parent = &core_ck, .rates = div4_rates },
  942. { .parent = NULL }
  943. };
  944. /*
  945. * REVISIT: Are these in DPLL power domain or CM power domain? docs
  946. * may be inconsistent here?
  947. */
  948. static struct clk dpll1_fck = {
  949. .name = "dpll1_fck",
  950. .ops = &clkops_null,
  951. .parent = &core_ck,
  952. .init = &omap2_init_clksel_parent,
  953. .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
  954. .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
  955. .clksel = div4_core_clksel,
  956. .recalc = &omap2_clksel_recalc,
  957. };
  958. static struct clk mpu_ck = {
  959. .name = "mpu_ck",
  960. .ops = &clkops_null,
  961. .parent = &dpll1_x2m2_ck,
  962. .clkdm_name = "mpu_clkdm",
  963. .recalc = &followparent_recalc,
  964. };
  965. /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
  966. static const struct clksel_rate arm_fck_rates[] = {
  967. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  968. { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
  969. { .div = 0 },
  970. };
  971. static const struct clksel arm_fck_clksel[] = {
  972. { .parent = &mpu_ck, .rates = arm_fck_rates },
  973. { .parent = NULL }
  974. };
  975. static struct clk arm_fck = {
  976. .name = "arm_fck",
  977. .ops = &clkops_null,
  978. .parent = &mpu_ck,
  979. .init = &omap2_init_clksel_parent,
  980. .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
  981. .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
  982. .clksel = arm_fck_clksel,
  983. .clkdm_name = "mpu_clkdm",
  984. .recalc = &omap2_clksel_recalc,
  985. };
  986. /* XXX What about neon_clkdm ? */
  987. /*
  988. * REVISIT: This clock is never specifically defined in the 3430 TRM,
  989. * although it is referenced - so this is a guess
  990. */
  991. static struct clk emu_mpu_alwon_ck = {
  992. .name = "emu_mpu_alwon_ck",
  993. .ops = &clkops_null,
  994. .parent = &mpu_ck,
  995. .recalc = &followparent_recalc,
  996. };
  997. static struct clk dpll2_fck = {
  998. .name = "dpll2_fck",
  999. .ops = &clkops_null,
  1000. .parent = &core_ck,
  1001. .init = &omap2_init_clksel_parent,
  1002. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
  1003. .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
  1004. .clksel = div4_core_clksel,
  1005. .recalc = &omap2_clksel_recalc,
  1006. };
  1007. static struct clk iva2_ck = {
  1008. .name = "iva2_ck",
  1009. .ops = &clkops_omap2_dflt_wait,
  1010. .parent = &dpll2_m2_ck,
  1011. .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
  1012. .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
  1013. .clkdm_name = "iva2_clkdm",
  1014. .recalc = &followparent_recalc,
  1015. };
  1016. /* Common interface clocks */
  1017. static const struct clksel div2_core_clksel[] = {
  1018. { .parent = &core_ck, .rates = div2_rates },
  1019. { .parent = NULL }
  1020. };
  1021. static struct clk l3_ick = {
  1022. .name = "l3_ick",
  1023. .ops = &clkops_null,
  1024. .parent = &core_ck,
  1025. .init = &omap2_init_clksel_parent,
  1026. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1027. .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
  1028. .clksel = div2_core_clksel,
  1029. .clkdm_name = "core_l3_clkdm",
  1030. .recalc = &omap2_clksel_recalc,
  1031. };
  1032. static const struct clksel div2_l3_clksel[] = {
  1033. { .parent = &l3_ick, .rates = div2_rates },
  1034. { .parent = NULL }
  1035. };
  1036. static struct clk l4_ick = {
  1037. .name = "l4_ick",
  1038. .ops = &clkops_null,
  1039. .parent = &l3_ick,
  1040. .init = &omap2_init_clksel_parent,
  1041. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1042. .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
  1043. .clksel = div2_l3_clksel,
  1044. .clkdm_name = "core_l4_clkdm",
  1045. .recalc = &omap2_clksel_recalc,
  1046. };
  1047. static const struct clksel div2_l4_clksel[] = {
  1048. { .parent = &l4_ick, .rates = div2_rates },
  1049. { .parent = NULL }
  1050. };
  1051. static struct clk rm_ick = {
  1052. .name = "rm_ick",
  1053. .ops = &clkops_null,
  1054. .parent = &l4_ick,
  1055. .init = &omap2_init_clksel_parent,
  1056. .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
  1057. .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
  1058. .clksel = div2_l4_clksel,
  1059. .recalc = &omap2_clksel_recalc,
  1060. };
  1061. /* GFX power domain */
  1062. /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
  1063. static const struct clksel gfx_l3_clksel[] = {
  1064. { .parent = &l3_ick, .rates = gfx_l3_rates },
  1065. { .parent = NULL }
  1066. };
  1067. /*
  1068. * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
  1069. * This interface clock does not have a CM_AUTOIDLE bit
  1070. */
  1071. static struct clk gfx_l3_ck = {
  1072. .name = "gfx_l3_ck",
  1073. .ops = &clkops_omap2_dflt_wait,
  1074. .parent = &l3_ick,
  1075. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
  1076. .enable_bit = OMAP_EN_GFX_SHIFT,
  1077. .recalc = &followparent_recalc,
  1078. };
  1079. static struct clk gfx_l3_fck = {
  1080. .name = "gfx_l3_fck",
  1081. .ops = &clkops_null,
  1082. .parent = &gfx_l3_ck,
  1083. .init = &omap2_init_clksel_parent,
  1084. .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
  1085. .clksel_mask = OMAP_CLKSEL_GFX_MASK,
  1086. .clksel = gfx_l3_clksel,
  1087. .clkdm_name = "gfx_3430es1_clkdm",
  1088. .recalc = &omap2_clksel_recalc,
  1089. };
  1090. static struct clk gfx_l3_ick = {
  1091. .name = "gfx_l3_ick",
  1092. .ops = &clkops_null,
  1093. .parent = &gfx_l3_ck,
  1094. .clkdm_name = "gfx_3430es1_clkdm",
  1095. .recalc = &followparent_recalc,
  1096. };
  1097. static struct clk gfx_cg1_ck = {
  1098. .name = "gfx_cg1_ck",
  1099. .ops = &clkops_omap2_dflt_wait,
  1100. .parent = &gfx_l3_fck, /* REVISIT: correct? */
  1101. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
  1102. .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
  1103. .clkdm_name = "gfx_3430es1_clkdm",
  1104. .recalc = &followparent_recalc,
  1105. };
  1106. static struct clk gfx_cg2_ck = {
  1107. .name = "gfx_cg2_ck",
  1108. .ops = &clkops_omap2_dflt_wait,
  1109. .parent = &gfx_l3_fck, /* REVISIT: correct? */
  1110. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
  1111. .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
  1112. .clkdm_name = "gfx_3430es1_clkdm",
  1113. .recalc = &followparent_recalc,
  1114. };
  1115. /* SGX power domain - 3430ES2 only */
  1116. static const struct clksel_rate sgx_core_rates[] = {
  1117. { .div = 2, .val = 5, .flags = RATE_IN_36XX },
  1118. { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
  1119. { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
  1120. { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
  1121. { .div = 0 },
  1122. };
  1123. static const struct clksel_rate sgx_192m_rates[] = {
  1124. { .div = 1, .val = 4, .flags = RATE_IN_36XX },
  1125. { .div = 0 },
  1126. };
  1127. static const struct clksel_rate sgx_corex2_rates[] = {
  1128. { .div = 3, .val = 6, .flags = RATE_IN_36XX },
  1129. { .div = 5, .val = 7, .flags = RATE_IN_36XX },
  1130. { .div = 0 },
  1131. };
  1132. static const struct clksel_rate sgx_96m_rates[] = {
  1133. { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
  1134. { .div = 0 },
  1135. };
  1136. static const struct clksel sgx_clksel[] = {
  1137. { .parent = &core_ck, .rates = sgx_core_rates },
  1138. { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
  1139. { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
  1140. { .parent = &corex2_fck, .rates = sgx_corex2_rates },
  1141. { .parent = NULL }
  1142. };
  1143. static struct clk sgx_fck = {
  1144. .name = "sgx_fck",
  1145. .ops = &clkops_omap2_dflt_wait,
  1146. .init = &omap2_init_clksel_parent,
  1147. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
  1148. .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
  1149. .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
  1150. .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
  1151. .clksel = sgx_clksel,
  1152. .clkdm_name = "sgx_clkdm",
  1153. .recalc = &omap2_clksel_recalc,
  1154. .set_rate = &omap2_clksel_set_rate,
  1155. .round_rate = &omap2_clksel_round_rate
  1156. };
  1157. /* This interface clock does not have a CM_AUTOIDLE bit */
  1158. static struct clk sgx_ick = {
  1159. .name = "sgx_ick",
  1160. .ops = &clkops_omap2_dflt_wait,
  1161. .parent = &l3_ick,
  1162. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
  1163. .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
  1164. .clkdm_name = "sgx_clkdm",
  1165. .recalc = &followparent_recalc,
  1166. };
  1167. /* CORE power domain */
  1168. static struct clk d2d_26m_fck = {
  1169. .name = "d2d_26m_fck",
  1170. .ops = &clkops_omap2_dflt_wait,
  1171. .parent = &sys_ck,
  1172. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1173. .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
  1174. .clkdm_name = "d2d_clkdm",
  1175. .recalc = &followparent_recalc,
  1176. };
  1177. static struct clk modem_fck = {
  1178. .name = "modem_fck",
  1179. .ops = &clkops_omap2_mdmclk_dflt_wait,
  1180. .parent = &sys_ck,
  1181. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1182. .enable_bit = OMAP3430_EN_MODEM_SHIFT,
  1183. .clkdm_name = "d2d_clkdm",
  1184. .recalc = &followparent_recalc,
  1185. };
  1186. static struct clk sad2d_ick = {
  1187. .name = "sad2d_ick",
  1188. .ops = &clkops_omap2_iclk_dflt_wait,
  1189. .parent = &l3_ick,
  1190. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1191. .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
  1192. .clkdm_name = "d2d_clkdm",
  1193. .recalc = &followparent_recalc,
  1194. };
  1195. static struct clk mad2d_ick = {
  1196. .name = "mad2d_ick",
  1197. .ops = &clkops_omap2_iclk_dflt_wait,
  1198. .parent = &l3_ick,
  1199. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
  1200. .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
  1201. .clkdm_name = "d2d_clkdm",
  1202. .recalc = &followparent_recalc,
  1203. };
  1204. static const struct clksel omap343x_gpt_clksel[] = {
  1205. { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
  1206. { .parent = &sys_ck, .rates = gpt_sys_rates },
  1207. { .parent = NULL}
  1208. };
  1209. static struct clk gpt10_fck = {
  1210. .name = "gpt10_fck",
  1211. .ops = &clkops_omap2_dflt_wait,
  1212. .parent = &sys_ck,
  1213. .init = &omap2_init_clksel_parent,
  1214. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1215. .enable_bit = OMAP3430_EN_GPT10_SHIFT,
  1216. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1217. .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
  1218. .clksel = omap343x_gpt_clksel,
  1219. .clkdm_name = "core_l4_clkdm",
  1220. .recalc = &omap2_clksel_recalc,
  1221. };
  1222. static struct clk gpt11_fck = {
  1223. .name = "gpt11_fck",
  1224. .ops = &clkops_omap2_dflt_wait,
  1225. .parent = &sys_ck,
  1226. .init = &omap2_init_clksel_parent,
  1227. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1228. .enable_bit = OMAP3430_EN_GPT11_SHIFT,
  1229. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1230. .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
  1231. .clksel = omap343x_gpt_clksel,
  1232. .clkdm_name = "core_l4_clkdm",
  1233. .recalc = &omap2_clksel_recalc,
  1234. };
  1235. static struct clk cpefuse_fck = {
  1236. .name = "cpefuse_fck",
  1237. .ops = &clkops_omap2_dflt,
  1238. .parent = &sys_ck,
  1239. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
  1240. .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
  1241. .recalc = &followparent_recalc,
  1242. };
  1243. static struct clk ts_fck = {
  1244. .name = "ts_fck",
  1245. .ops = &clkops_omap2_dflt,
  1246. .parent = &omap_32k_fck,
  1247. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
  1248. .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
  1249. .recalc = &followparent_recalc,
  1250. };
  1251. static struct clk usbtll_fck = {
  1252. .name = "usbtll_fck",
  1253. .ops = &clkops_omap2_dflt_wait,
  1254. .parent = &dpll5_m2_ck,
  1255. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
  1256. .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
  1257. .recalc = &followparent_recalc,
  1258. };
  1259. /* CORE 96M FCLK-derived clocks */
  1260. static struct clk core_96m_fck = {
  1261. .name = "core_96m_fck",
  1262. .ops = &clkops_null,
  1263. .parent = &omap_96m_fck,
  1264. .clkdm_name = "core_l4_clkdm",
  1265. .recalc = &followparent_recalc,
  1266. };
  1267. static struct clk mmchs3_fck = {
  1268. .name = "mmchs3_fck",
  1269. .ops = &clkops_omap2_dflt_wait,
  1270. .parent = &core_96m_fck,
  1271. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1272. .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
  1273. .clkdm_name = "core_l4_clkdm",
  1274. .recalc = &followparent_recalc,
  1275. };
  1276. static struct clk mmchs2_fck = {
  1277. .name = "mmchs2_fck",
  1278. .ops = &clkops_omap2_dflt_wait,
  1279. .parent = &core_96m_fck,
  1280. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1281. .enable_bit = OMAP3430_EN_MMC2_SHIFT,
  1282. .clkdm_name = "core_l4_clkdm",
  1283. .recalc = &followparent_recalc,
  1284. };
  1285. static struct clk mspro_fck = {
  1286. .name = "mspro_fck",
  1287. .ops = &clkops_omap2_dflt_wait,
  1288. .parent = &core_96m_fck,
  1289. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1290. .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
  1291. .clkdm_name = "core_l4_clkdm",
  1292. .recalc = &followparent_recalc,
  1293. };
  1294. static struct clk mmchs1_fck = {
  1295. .name = "mmchs1_fck",
  1296. .ops = &clkops_omap2_dflt_wait,
  1297. .parent = &core_96m_fck,
  1298. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1299. .enable_bit = OMAP3430_EN_MMC1_SHIFT,
  1300. .clkdm_name = "core_l4_clkdm",
  1301. .recalc = &followparent_recalc,
  1302. };
  1303. static struct clk i2c3_fck = {
  1304. .name = "i2c3_fck",
  1305. .ops = &clkops_omap2_dflt_wait,
  1306. .parent = &core_96m_fck,
  1307. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1308. .enable_bit = OMAP3430_EN_I2C3_SHIFT,
  1309. .clkdm_name = "core_l4_clkdm",
  1310. .recalc = &followparent_recalc,
  1311. };
  1312. static struct clk i2c2_fck = {
  1313. .name = "i2c2_fck",
  1314. .ops = &clkops_omap2_dflt_wait,
  1315. .parent = &core_96m_fck,
  1316. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1317. .enable_bit = OMAP3430_EN_I2C2_SHIFT,
  1318. .clkdm_name = "core_l4_clkdm",
  1319. .recalc = &followparent_recalc,
  1320. };
  1321. static struct clk i2c1_fck = {
  1322. .name = "i2c1_fck",
  1323. .ops = &clkops_omap2_dflt_wait,
  1324. .parent = &core_96m_fck,
  1325. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1326. .enable_bit = OMAP3430_EN_I2C1_SHIFT,
  1327. .clkdm_name = "core_l4_clkdm",
  1328. .recalc = &followparent_recalc,
  1329. };
  1330. /*
  1331. * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
  1332. * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
  1333. */
  1334. static const struct clksel_rate common_mcbsp_96m_rates[] = {
  1335. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  1336. { .div = 0 }
  1337. };
  1338. static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
  1339. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  1340. { .div = 0 }
  1341. };
  1342. static const struct clksel mcbsp_15_clksel[] = {
  1343. { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
  1344. { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
  1345. { .parent = NULL }
  1346. };
  1347. static struct clk mcbsp5_fck = {
  1348. .name = "mcbsp5_fck",
  1349. .ops = &clkops_omap2_dflt_wait,
  1350. .init = &omap2_init_clksel_parent,
  1351. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1352. .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
  1353. .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
  1354. .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
  1355. .clksel = mcbsp_15_clksel,
  1356. .clkdm_name = "core_l4_clkdm",
  1357. .recalc = &omap2_clksel_recalc,
  1358. };
  1359. static struct clk mcbsp1_fck = {
  1360. .name = "mcbsp1_fck",
  1361. .ops = &clkops_omap2_dflt_wait,
  1362. .init = &omap2_init_clksel_parent,
  1363. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1364. .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
  1365. .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
  1366. .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
  1367. .clksel = mcbsp_15_clksel,
  1368. .clkdm_name = "core_l4_clkdm",
  1369. .recalc = &omap2_clksel_recalc,
  1370. };
  1371. /* CORE_48M_FCK-derived clocks */
  1372. static struct clk core_48m_fck = {
  1373. .name = "core_48m_fck",
  1374. .ops = &clkops_null,
  1375. .parent = &omap_48m_fck,
  1376. .clkdm_name = "core_l4_clkdm",
  1377. .recalc = &followparent_recalc,
  1378. };
  1379. static struct clk mcspi4_fck = {
  1380. .name = "mcspi4_fck",
  1381. .ops = &clkops_omap2_dflt_wait,
  1382. .parent = &core_48m_fck,
  1383. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1384. .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
  1385. .recalc = &followparent_recalc,
  1386. .clkdm_name = "core_l4_clkdm",
  1387. };
  1388. static struct clk mcspi3_fck = {
  1389. .name = "mcspi3_fck",
  1390. .ops = &clkops_omap2_dflt_wait,
  1391. .parent = &core_48m_fck,
  1392. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1393. .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
  1394. .recalc = &followparent_recalc,
  1395. .clkdm_name = "core_l4_clkdm",
  1396. };
  1397. static struct clk mcspi2_fck = {
  1398. .name = "mcspi2_fck",
  1399. .ops = &clkops_omap2_dflt_wait,
  1400. .parent = &core_48m_fck,
  1401. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1402. .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
  1403. .recalc = &followparent_recalc,
  1404. .clkdm_name = "core_l4_clkdm",
  1405. };
  1406. static struct clk mcspi1_fck = {
  1407. .name = "mcspi1_fck",
  1408. .ops = &clkops_omap2_dflt_wait,
  1409. .parent = &core_48m_fck,
  1410. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1411. .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
  1412. .recalc = &followparent_recalc,
  1413. .clkdm_name = "core_l4_clkdm",
  1414. };
  1415. static struct clk uart2_fck = {
  1416. .name = "uart2_fck",
  1417. .ops = &clkops_omap2_dflt_wait,
  1418. .parent = &core_48m_fck,
  1419. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1420. .enable_bit = OMAP3430_EN_UART2_SHIFT,
  1421. .clkdm_name = "core_l4_clkdm",
  1422. .recalc = &followparent_recalc,
  1423. };
  1424. static struct clk uart1_fck = {
  1425. .name = "uart1_fck",
  1426. .ops = &clkops_omap2_dflt_wait,
  1427. .parent = &core_48m_fck,
  1428. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1429. .enable_bit = OMAP3430_EN_UART1_SHIFT,
  1430. .clkdm_name = "core_l4_clkdm",
  1431. .recalc = &followparent_recalc,
  1432. };
  1433. static struct clk fshostusb_fck = {
  1434. .name = "fshostusb_fck",
  1435. .ops = &clkops_omap2_dflt_wait,
  1436. .parent = &core_48m_fck,
  1437. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1438. .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
  1439. .recalc = &followparent_recalc,
  1440. };
  1441. /* CORE_12M_FCK based clocks */
  1442. static struct clk core_12m_fck = {
  1443. .name = "core_12m_fck",
  1444. .ops = &clkops_null,
  1445. .parent = &omap_12m_fck,
  1446. .clkdm_name = "core_l4_clkdm",
  1447. .recalc = &followparent_recalc,
  1448. };
  1449. static struct clk hdq_fck = {
  1450. .name = "hdq_fck",
  1451. .ops = &clkops_omap2_dflt_wait,
  1452. .parent = &core_12m_fck,
  1453. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1454. .enable_bit = OMAP3430_EN_HDQ_SHIFT,
  1455. .recalc = &followparent_recalc,
  1456. };
  1457. /* DPLL3-derived clock */
  1458. static const struct clksel_rate ssi_ssr_corex2_rates[] = {
  1459. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  1460. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  1461. { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
  1462. { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
  1463. { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
  1464. { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
  1465. { .div = 0 }
  1466. };
  1467. static const struct clksel ssi_ssr_clksel[] = {
  1468. { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
  1469. { .parent = NULL }
  1470. };
  1471. static struct clk ssi_ssr_fck_3430es1 = {
  1472. .name = "ssi_ssr_fck",
  1473. .ops = &clkops_omap2_dflt,
  1474. .init = &omap2_init_clksel_parent,
  1475. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1476. .enable_bit = OMAP3430_EN_SSI_SHIFT,
  1477. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1478. .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
  1479. .clksel = ssi_ssr_clksel,
  1480. .clkdm_name = "core_l4_clkdm",
  1481. .recalc = &omap2_clksel_recalc,
  1482. };
  1483. static struct clk ssi_ssr_fck_3430es2 = {
  1484. .name = "ssi_ssr_fck",
  1485. .ops = &clkops_omap3430es2_ssi_wait,
  1486. .init = &omap2_init_clksel_parent,
  1487. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1488. .enable_bit = OMAP3430_EN_SSI_SHIFT,
  1489. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1490. .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
  1491. .clksel = ssi_ssr_clksel,
  1492. .clkdm_name = "core_l4_clkdm",
  1493. .recalc = &omap2_clksel_recalc,
  1494. };
  1495. static struct clk ssi_sst_fck_3430es1 = {
  1496. .name = "ssi_sst_fck",
  1497. .ops = &clkops_null,
  1498. .parent = &ssi_ssr_fck_3430es1,
  1499. .fixed_div = 2,
  1500. .recalc = &omap_fixed_divisor_recalc,
  1501. };
  1502. static struct clk ssi_sst_fck_3430es2 = {
  1503. .name = "ssi_sst_fck",
  1504. .ops = &clkops_null,
  1505. .parent = &ssi_ssr_fck_3430es2,
  1506. .fixed_div = 2,
  1507. .recalc = &omap_fixed_divisor_recalc,
  1508. };
  1509. /* CORE_L3_ICK based clocks */
  1510. /*
  1511. * XXX must add clk_enable/clk_disable for these if standard code won't
  1512. * handle it
  1513. */
  1514. static struct clk core_l3_ick = {
  1515. .name = "core_l3_ick",
  1516. .ops = &clkops_null,
  1517. .parent = &l3_ick,
  1518. .clkdm_name = "core_l3_clkdm",
  1519. .recalc = &followparent_recalc,
  1520. };
  1521. static struct clk hsotgusb_ick_3430es1 = {
  1522. .name = "hsotgusb_ick",
  1523. .ops = &clkops_omap2_iclk_dflt,
  1524. .parent = &core_l3_ick,
  1525. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1526. .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
  1527. .clkdm_name = "core_l3_clkdm",
  1528. .recalc = &followparent_recalc,
  1529. };
  1530. static struct clk hsotgusb_ick_3430es2 = {
  1531. .name = "hsotgusb_ick",
  1532. .ops = &clkops_omap3430es2_iclk_hsotgusb_wait,
  1533. .parent = &core_l3_ick,
  1534. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1535. .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
  1536. .clkdm_name = "core_l3_clkdm",
  1537. .recalc = &followparent_recalc,
  1538. };
  1539. /* This interface clock does not have a CM_AUTOIDLE bit */
  1540. static struct clk sdrc_ick = {
  1541. .name = "sdrc_ick",
  1542. .ops = &clkops_omap2_dflt_wait,
  1543. .parent = &core_l3_ick,
  1544. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1545. .enable_bit = OMAP3430_EN_SDRC_SHIFT,
  1546. .flags = ENABLE_ON_INIT,
  1547. .clkdm_name = "core_l3_clkdm",
  1548. .recalc = &followparent_recalc,
  1549. };
  1550. static struct clk gpmc_fck = {
  1551. .name = "gpmc_fck",
  1552. .ops = &clkops_null,
  1553. .parent = &core_l3_ick,
  1554. .flags = ENABLE_ON_INIT, /* huh? */
  1555. .clkdm_name = "core_l3_clkdm",
  1556. .recalc = &followparent_recalc,
  1557. };
  1558. /* SECURITY_L3_ICK based clocks */
  1559. static struct clk security_l3_ick = {
  1560. .name = "security_l3_ick",
  1561. .ops = &clkops_null,
  1562. .parent = &l3_ick,
  1563. .recalc = &followparent_recalc,
  1564. };
  1565. static struct clk pka_ick = {
  1566. .name = "pka_ick",
  1567. .ops = &clkops_omap2_iclk_dflt_wait,
  1568. .parent = &security_l3_ick,
  1569. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1570. .enable_bit = OMAP3430_EN_PKA_SHIFT,
  1571. .recalc = &followparent_recalc,
  1572. };
  1573. /* CORE_L4_ICK based clocks */
  1574. static struct clk core_l4_ick = {
  1575. .name = "core_l4_ick",
  1576. .ops = &clkops_null,
  1577. .parent = &l4_ick,
  1578. .clkdm_name = "core_l4_clkdm",
  1579. .recalc = &followparent_recalc,
  1580. };
  1581. static struct clk usbtll_ick = {
  1582. .name = "usbtll_ick",
  1583. .ops = &clkops_omap2_iclk_dflt_wait,
  1584. .parent = &core_l4_ick,
  1585. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
  1586. .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
  1587. .clkdm_name = "core_l4_clkdm",
  1588. .recalc = &followparent_recalc,
  1589. };
  1590. static struct clk mmchs3_ick = {
  1591. .name = "mmchs3_ick",
  1592. .ops = &clkops_omap2_iclk_dflt_wait,
  1593. .parent = &core_l4_ick,
  1594. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1595. .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
  1596. .clkdm_name = "core_l4_clkdm",
  1597. .recalc = &followparent_recalc,
  1598. };
  1599. /* Intersystem Communication Registers - chassis mode only */
  1600. static struct clk icr_ick = {
  1601. .name = "icr_ick",
  1602. .ops = &clkops_omap2_iclk_dflt_wait,
  1603. .parent = &core_l4_ick,
  1604. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1605. .enable_bit = OMAP3430_EN_ICR_SHIFT,
  1606. .clkdm_name = "core_l4_clkdm",
  1607. .recalc = &followparent_recalc,
  1608. };
  1609. static struct clk aes2_ick = {
  1610. .name = "aes2_ick",
  1611. .ops = &clkops_omap2_iclk_dflt_wait,
  1612. .parent = &core_l4_ick,
  1613. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1614. .enable_bit = OMAP3430_EN_AES2_SHIFT,
  1615. .clkdm_name = "core_l4_clkdm",
  1616. .recalc = &followparent_recalc,
  1617. };
  1618. static struct clk sha12_ick = {
  1619. .name = "sha12_ick",
  1620. .ops = &clkops_omap2_iclk_dflt_wait,
  1621. .parent = &core_l4_ick,
  1622. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1623. .enable_bit = OMAP3430_EN_SHA12_SHIFT,
  1624. .clkdm_name = "core_l4_clkdm",
  1625. .recalc = &followparent_recalc,
  1626. };
  1627. static struct clk des2_ick = {
  1628. .name = "des2_ick",
  1629. .ops = &clkops_omap2_iclk_dflt_wait,
  1630. .parent = &core_l4_ick,
  1631. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1632. .enable_bit = OMAP3430_EN_DES2_SHIFT,
  1633. .clkdm_name = "core_l4_clkdm",
  1634. .recalc = &followparent_recalc,
  1635. };
  1636. static struct clk mmchs2_ick = {
  1637. .name = "mmchs2_ick",
  1638. .ops = &clkops_omap2_iclk_dflt_wait,
  1639. .parent = &core_l4_ick,
  1640. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1641. .enable_bit = OMAP3430_EN_MMC2_SHIFT,
  1642. .clkdm_name = "core_l4_clkdm",
  1643. .recalc = &followparent_recalc,
  1644. };
  1645. static struct clk mmchs1_ick = {
  1646. .name = "mmchs1_ick",
  1647. .ops = &clkops_omap2_iclk_dflt_wait,
  1648. .parent = &core_l4_ick,
  1649. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1650. .enable_bit = OMAP3430_EN_MMC1_SHIFT,
  1651. .clkdm_name = "core_l4_clkdm",
  1652. .recalc = &followparent_recalc,
  1653. };
  1654. static struct clk mspro_ick = {
  1655. .name = "mspro_ick",
  1656. .ops = &clkops_omap2_iclk_dflt_wait,
  1657. .parent = &core_l4_ick,
  1658. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1659. .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
  1660. .clkdm_name = "core_l4_clkdm",
  1661. .recalc = &followparent_recalc,
  1662. };
  1663. static struct clk hdq_ick = {
  1664. .name = "hdq_ick",
  1665. .ops = &clkops_omap2_iclk_dflt_wait,
  1666. .parent = &core_l4_ick,
  1667. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1668. .enable_bit = OMAP3430_EN_HDQ_SHIFT,
  1669. .clkdm_name = "core_l4_clkdm",
  1670. .recalc = &followparent_recalc,
  1671. };
  1672. static struct clk mcspi4_ick = {
  1673. .name = "mcspi4_ick",
  1674. .ops = &clkops_omap2_iclk_dflt_wait,
  1675. .parent = &core_l4_ick,
  1676. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1677. .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
  1678. .clkdm_name = "core_l4_clkdm",
  1679. .recalc = &followparent_recalc,
  1680. };
  1681. static struct clk mcspi3_ick = {
  1682. .name = "mcspi3_ick",
  1683. .ops = &clkops_omap2_iclk_dflt_wait,
  1684. .parent = &core_l4_ick,
  1685. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1686. .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
  1687. .clkdm_name = "core_l4_clkdm",
  1688. .recalc = &followparent_recalc,
  1689. };
  1690. static struct clk mcspi2_ick = {
  1691. .name = "mcspi2_ick",
  1692. .ops = &clkops_omap2_iclk_dflt_wait,
  1693. .parent = &core_l4_ick,
  1694. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1695. .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
  1696. .clkdm_name = "core_l4_clkdm",
  1697. .recalc = &followparent_recalc,
  1698. };
  1699. static struct clk mcspi1_ick = {
  1700. .name = "mcspi1_ick",
  1701. .ops = &clkops_omap2_iclk_dflt_wait,
  1702. .parent = &core_l4_ick,
  1703. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1704. .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
  1705. .clkdm_name = "core_l4_clkdm",
  1706. .recalc = &followparent_recalc,
  1707. };
  1708. static struct clk i2c3_ick = {
  1709. .name = "i2c3_ick",
  1710. .ops = &clkops_omap2_iclk_dflt_wait,
  1711. .parent = &core_l4_ick,
  1712. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1713. .enable_bit = OMAP3430_EN_I2C3_SHIFT,
  1714. .clkdm_name = "core_l4_clkdm",
  1715. .recalc = &followparent_recalc,
  1716. };
  1717. static struct clk i2c2_ick = {
  1718. .name = "i2c2_ick",
  1719. .ops = &clkops_omap2_iclk_dflt_wait,
  1720. .parent = &core_l4_ick,
  1721. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1722. .enable_bit = OMAP3430_EN_I2C2_SHIFT,
  1723. .clkdm_name = "core_l4_clkdm",
  1724. .recalc = &followparent_recalc,
  1725. };
  1726. static struct clk i2c1_ick = {
  1727. .name = "i2c1_ick",
  1728. .ops = &clkops_omap2_iclk_dflt_wait,
  1729. .parent = &core_l4_ick,
  1730. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1731. .enable_bit = OMAP3430_EN_I2C1_SHIFT,
  1732. .clkdm_name = "core_l4_clkdm",
  1733. .recalc = &followparent_recalc,
  1734. };
  1735. static struct clk uart2_ick = {
  1736. .name = "uart2_ick",
  1737. .ops = &clkops_omap2_iclk_dflt_wait,
  1738. .parent = &core_l4_ick,
  1739. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1740. .enable_bit = OMAP3430_EN_UART2_SHIFT,
  1741. .clkdm_name = "core_l4_clkdm",
  1742. .recalc = &followparent_recalc,
  1743. };
  1744. static struct clk uart1_ick = {
  1745. .name = "uart1_ick",
  1746. .ops = &clkops_omap2_iclk_dflt_wait,
  1747. .parent = &core_l4_ick,
  1748. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1749. .enable_bit = OMAP3430_EN_UART1_SHIFT,
  1750. .clkdm_name = "core_l4_clkdm",
  1751. .recalc = &followparent_recalc,
  1752. };
  1753. static struct clk gpt11_ick = {
  1754. .name = "gpt11_ick",
  1755. .ops = &clkops_omap2_iclk_dflt_wait,
  1756. .parent = &core_l4_ick,
  1757. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1758. .enable_bit = OMAP3430_EN_GPT11_SHIFT,
  1759. .clkdm_name = "core_l4_clkdm",
  1760. .recalc = &followparent_recalc,
  1761. };
  1762. static struct clk gpt10_ick = {
  1763. .name = "gpt10_ick",
  1764. .ops = &clkops_omap2_iclk_dflt_wait,
  1765. .parent = &core_l4_ick,
  1766. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1767. .enable_bit = OMAP3430_EN_GPT10_SHIFT,
  1768. .clkdm_name = "core_l4_clkdm",
  1769. .recalc = &followparent_recalc,
  1770. };
  1771. static struct clk mcbsp5_ick = {
  1772. .name = "mcbsp5_ick",
  1773. .ops = &clkops_omap2_iclk_dflt_wait,
  1774. .parent = &core_l4_ick,
  1775. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1776. .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
  1777. .clkdm_name = "core_l4_clkdm",
  1778. .recalc = &followparent_recalc,
  1779. };
  1780. static struct clk mcbsp1_ick = {
  1781. .name = "mcbsp1_ick",
  1782. .ops = &clkops_omap2_iclk_dflt_wait,
  1783. .parent = &core_l4_ick,
  1784. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1785. .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
  1786. .clkdm_name = "core_l4_clkdm",
  1787. .recalc = &followparent_recalc,
  1788. };
  1789. static struct clk fac_ick = {
  1790. .name = "fac_ick",
  1791. .ops = &clkops_omap2_iclk_dflt_wait,
  1792. .parent = &core_l4_ick,
  1793. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1794. .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
  1795. .clkdm_name = "core_l4_clkdm",
  1796. .recalc = &followparent_recalc,
  1797. };
  1798. static struct clk mailboxes_ick = {
  1799. .name = "mailboxes_ick",
  1800. .ops = &clkops_omap2_iclk_dflt_wait,
  1801. .parent = &core_l4_ick,
  1802. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1803. .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
  1804. .clkdm_name = "core_l4_clkdm",
  1805. .recalc = &followparent_recalc,
  1806. };
  1807. static struct clk omapctrl_ick = {
  1808. .name = "omapctrl_ick",
  1809. .ops = &clkops_omap2_iclk_dflt_wait,
  1810. .parent = &core_l4_ick,
  1811. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1812. .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
  1813. .flags = ENABLE_ON_INIT,
  1814. .recalc = &followparent_recalc,
  1815. };
  1816. /* SSI_L4_ICK based clocks */
  1817. static struct clk ssi_l4_ick = {
  1818. .name = "ssi_l4_ick",
  1819. .ops = &clkops_null,
  1820. .parent = &l4_ick,
  1821. .clkdm_name = "core_l4_clkdm",
  1822. .recalc = &followparent_recalc,
  1823. };
  1824. static struct clk ssi_ick_3430es1 = {
  1825. .name = "ssi_ick",
  1826. .ops = &clkops_omap2_iclk_dflt,
  1827. .parent = &ssi_l4_ick,
  1828. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1829. .enable_bit = OMAP3430_EN_SSI_SHIFT,
  1830. .clkdm_name = "core_l4_clkdm",
  1831. .recalc = &followparent_recalc,
  1832. };
  1833. static struct clk ssi_ick_3430es2 = {
  1834. .name = "ssi_ick",
  1835. .ops = &clkops_omap3430es2_iclk_ssi_wait,
  1836. .parent = &ssi_l4_ick,
  1837. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1838. .enable_bit = OMAP3430_EN_SSI_SHIFT,
  1839. .clkdm_name = "core_l4_clkdm",
  1840. .recalc = &followparent_recalc,
  1841. };
  1842. /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
  1843. * but l4_ick makes more sense to me */
  1844. static const struct clksel usb_l4_clksel[] = {
  1845. { .parent = &l4_ick, .rates = div2_rates },
  1846. { .parent = NULL },
  1847. };
  1848. static struct clk usb_l4_ick = {
  1849. .name = "usb_l4_ick",
  1850. .ops = &clkops_omap2_iclk_dflt_wait,
  1851. .parent = &l4_ick,
  1852. .init = &omap2_init_clksel_parent,
  1853. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1854. .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
  1855. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1856. .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
  1857. .clksel = usb_l4_clksel,
  1858. .recalc = &omap2_clksel_recalc,
  1859. };
  1860. /* SECURITY_L4_ICK2 based clocks */
  1861. static struct clk security_l4_ick2 = {
  1862. .name = "security_l4_ick2",
  1863. .ops = &clkops_null,
  1864. .parent = &l4_ick,
  1865. .recalc = &followparent_recalc,
  1866. };
  1867. static struct clk aes1_ick = {
  1868. .name = "aes1_ick",
  1869. .ops = &clkops_omap2_iclk_dflt_wait,
  1870. .parent = &security_l4_ick2,
  1871. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1872. .enable_bit = OMAP3430_EN_AES1_SHIFT,
  1873. .recalc = &followparent_recalc,
  1874. };
  1875. static struct clk rng_ick = {
  1876. .name = "rng_ick",
  1877. .ops = &clkops_omap2_iclk_dflt_wait,
  1878. .parent = &security_l4_ick2,
  1879. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1880. .enable_bit = OMAP3430_EN_RNG_SHIFT,
  1881. .recalc = &followparent_recalc,
  1882. };
  1883. static struct clk sha11_ick = {
  1884. .name = "sha11_ick",
  1885. .ops = &clkops_omap2_iclk_dflt_wait,
  1886. .parent = &security_l4_ick2,
  1887. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1888. .enable_bit = OMAP3430_EN_SHA11_SHIFT,
  1889. .recalc = &followparent_recalc,
  1890. };
  1891. static struct clk des1_ick = {
  1892. .name = "des1_ick",
  1893. .ops = &clkops_omap2_iclk_dflt_wait,
  1894. .parent = &security_l4_ick2,
  1895. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1896. .enable_bit = OMAP3430_EN_DES1_SHIFT,
  1897. .recalc = &followparent_recalc,
  1898. };
  1899. /* DSS */
  1900. static struct clk dss1_alwon_fck_3430es1 = {
  1901. .name = "dss1_alwon_fck",
  1902. .ops = &clkops_omap2_dflt,
  1903. .parent = &dpll4_m4x2_ck,
  1904. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  1905. .enable_bit = OMAP3430_EN_DSS1_SHIFT,
  1906. .clkdm_name = "dss_clkdm",
  1907. .recalc = &followparent_recalc,
  1908. };
  1909. static struct clk dss1_alwon_fck_3430es2 = {
  1910. .name = "dss1_alwon_fck",
  1911. .ops = &clkops_omap3430es2_dss_usbhost_wait,
  1912. .parent = &dpll4_m4x2_ck,
  1913. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  1914. .enable_bit = OMAP3430_EN_DSS1_SHIFT,
  1915. .clkdm_name = "dss_clkdm",
  1916. .recalc = &followparent_recalc,
  1917. };
  1918. static struct clk dss_tv_fck = {
  1919. .name = "dss_tv_fck",
  1920. .ops = &clkops_omap2_dflt,
  1921. .parent = &omap_54m_fck,
  1922. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  1923. .enable_bit = OMAP3430_EN_TV_SHIFT,
  1924. .clkdm_name = "dss_clkdm",
  1925. .recalc = &followparent_recalc,
  1926. };
  1927. static struct clk dss_96m_fck = {
  1928. .name = "dss_96m_fck",
  1929. .ops = &clkops_omap2_dflt,
  1930. .parent = &omap_96m_fck,
  1931. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  1932. .enable_bit = OMAP3430_EN_TV_SHIFT,
  1933. .clkdm_name = "dss_clkdm",
  1934. .recalc = &followparent_recalc,
  1935. };
  1936. static struct clk dss2_alwon_fck = {
  1937. .name = "dss2_alwon_fck",
  1938. .ops = &clkops_omap2_dflt,
  1939. .parent = &sys_ck,
  1940. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  1941. .enable_bit = OMAP3430_EN_DSS2_SHIFT,
  1942. .clkdm_name = "dss_clkdm",
  1943. .recalc = &followparent_recalc,
  1944. };
  1945. static struct clk dss_ick_3430es1 = {
  1946. /* Handles both L3 and L4 clocks */
  1947. .name = "dss_ick",
  1948. .ops = &clkops_omap2_iclk_dflt,
  1949. .parent = &l4_ick,
  1950. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
  1951. .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
  1952. .clkdm_name = "dss_clkdm",
  1953. .recalc = &followparent_recalc,
  1954. };
  1955. static struct clk dss_ick_3430es2 = {
  1956. /* Handles both L3 and L4 clocks */
  1957. .name = "dss_ick",
  1958. .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
  1959. .parent = &l4_ick,
  1960. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
  1961. .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
  1962. .clkdm_name = "dss_clkdm",
  1963. .recalc = &followparent_recalc,
  1964. };
  1965. /* CAM */
  1966. static struct clk cam_mclk = {
  1967. .name = "cam_mclk",
  1968. .ops = &clkops_omap2_dflt,
  1969. .parent = &dpll4_m5x2_ck,
  1970. .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
  1971. .enable_bit = OMAP3430_EN_CAM_SHIFT,
  1972. .clkdm_name = "cam_clkdm",
  1973. .recalc = &followparent_recalc,
  1974. };
  1975. static struct clk cam_ick = {
  1976. /* Handles both L3 and L4 clocks */
  1977. .name = "cam_ick",
  1978. .ops = &clkops_omap2_iclk_dflt,
  1979. .parent = &l4_ick,
  1980. .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
  1981. .enable_bit = OMAP3430_EN_CAM_SHIFT,
  1982. .clkdm_name = "cam_clkdm",
  1983. .recalc = &followparent_recalc,
  1984. };
  1985. static struct clk csi2_96m_fck = {
  1986. .name = "csi2_96m_fck",
  1987. .ops = &clkops_omap2_dflt,
  1988. .parent = &core_96m_fck,
  1989. .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
  1990. .enable_bit = OMAP3430_EN_CSI2_SHIFT,
  1991. .clkdm_name = "cam_clkdm",
  1992. .recalc = &followparent_recalc,
  1993. };
  1994. /* USBHOST - 3430ES2 only */
  1995. static struct clk usbhost_120m_fck = {
  1996. .name = "usbhost_120m_fck",
  1997. .ops = &clkops_omap2_dflt,
  1998. .parent = &dpll5_m2_ck,
  1999. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
  2000. .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
  2001. .clkdm_name = "usbhost_clkdm",
  2002. .recalc = &followparent_recalc,
  2003. };
  2004. static struct clk usbhost_48m_fck = {
  2005. .name = "usbhost_48m_fck",
  2006. .ops = &clkops_omap3430es2_dss_usbhost_wait,
  2007. .parent = &omap_48m_fck,
  2008. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
  2009. .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
  2010. .clkdm_name = "usbhost_clkdm",
  2011. .recalc = &followparent_recalc,
  2012. };
  2013. static struct clk usbhost_ick = {
  2014. /* Handles both L3 and L4 clocks */
  2015. .name = "usbhost_ick",
  2016. .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
  2017. .parent = &l4_ick,
  2018. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
  2019. .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
  2020. .clkdm_name = "usbhost_clkdm",
  2021. .recalc = &followparent_recalc,
  2022. };
  2023. /* WKUP */
  2024. static const struct clksel_rate usim_96m_rates[] = {
  2025. { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
  2026. { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
  2027. { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
  2028. { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
  2029. { .div = 0 },
  2030. };
  2031. static const struct clksel_rate usim_120m_rates[] = {
  2032. { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
  2033. { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
  2034. { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
  2035. { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
  2036. { .div = 0 },
  2037. };
  2038. static const struct clksel usim_clksel[] = {
  2039. { .parent = &omap_96m_fck, .rates = usim_96m_rates },
  2040. { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
  2041. { .parent = &sys_ck, .rates = div2_rates },
  2042. { .parent = NULL },
  2043. };
  2044. /* 3430ES2 only */
  2045. static struct clk usim_fck = {
  2046. .name = "usim_fck",
  2047. .ops = &clkops_omap2_dflt_wait,
  2048. .init = &omap2_init_clksel_parent,
  2049. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2050. .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
  2051. .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
  2052. .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
  2053. .clksel = usim_clksel,
  2054. .recalc = &omap2_clksel_recalc,
  2055. };
  2056. /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
  2057. static struct clk gpt1_fck = {
  2058. .name = "gpt1_fck",
  2059. .ops = &clkops_omap2_dflt_wait,
  2060. .init = &omap2_init_clksel_parent,
  2061. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2062. .enable_bit = OMAP3430_EN_GPT1_SHIFT,
  2063. .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
  2064. .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
  2065. .clksel = omap343x_gpt_clksel,
  2066. .clkdm_name = "wkup_clkdm",
  2067. .recalc = &omap2_clksel_recalc,
  2068. };
  2069. static struct clk wkup_32k_fck = {
  2070. .name = "wkup_32k_fck",
  2071. .ops = &clkops_null,
  2072. .parent = &omap_32k_fck,
  2073. .clkdm_name = "wkup_clkdm",
  2074. .recalc = &followparent_recalc,
  2075. };
  2076. static struct clk gpio1_dbck = {
  2077. .name = "gpio1_dbck",
  2078. .ops = &clkops_omap2_dflt,
  2079. .parent = &wkup_32k_fck,
  2080. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2081. .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
  2082. .clkdm_name = "wkup_clkdm",
  2083. .recalc = &followparent_recalc,
  2084. };
  2085. static struct clk wdt2_fck = {
  2086. .name = "wdt2_fck",
  2087. .ops = &clkops_omap2_dflt_wait,
  2088. .parent = &wkup_32k_fck,
  2089. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2090. .enable_bit = OMAP3430_EN_WDT2_SHIFT,
  2091. .clkdm_name = "wkup_clkdm",
  2092. .recalc = &followparent_recalc,
  2093. };
  2094. static struct clk wkup_l4_ick = {
  2095. .name = "wkup_l4_ick",
  2096. .ops = &clkops_null,
  2097. .parent = &sys_ck,
  2098. .clkdm_name = "wkup_clkdm",
  2099. .recalc = &followparent_recalc,
  2100. };
  2101. /* 3430ES2 only */
  2102. /* Never specifically named in the TRM, so we have to infer a likely name */
  2103. static struct clk usim_ick = {
  2104. .name = "usim_ick",
  2105. .ops = &clkops_omap2_iclk_dflt_wait,
  2106. .parent = &wkup_l4_ick,
  2107. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2108. .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
  2109. .clkdm_name = "wkup_clkdm",
  2110. .recalc = &followparent_recalc,
  2111. };
  2112. static struct clk wdt2_ick = {
  2113. .name = "wdt2_ick",
  2114. .ops = &clkops_omap2_iclk_dflt_wait,
  2115. .parent = &wkup_l4_ick,
  2116. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2117. .enable_bit = OMAP3430_EN_WDT2_SHIFT,
  2118. .clkdm_name = "wkup_clkdm",
  2119. .recalc = &followparent_recalc,
  2120. };
  2121. static struct clk wdt1_ick = {
  2122. .name = "wdt1_ick",
  2123. .ops = &clkops_omap2_iclk_dflt_wait,
  2124. .parent = &wkup_l4_ick,
  2125. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2126. .enable_bit = OMAP3430_EN_WDT1_SHIFT,
  2127. .clkdm_name = "wkup_clkdm",
  2128. .recalc = &followparent_recalc,
  2129. };
  2130. static struct clk gpio1_ick = {
  2131. .name = "gpio1_ick",
  2132. .ops = &clkops_omap2_iclk_dflt_wait,
  2133. .parent = &wkup_l4_ick,
  2134. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2135. .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
  2136. .clkdm_name = "wkup_clkdm",
  2137. .recalc = &followparent_recalc,
  2138. };
  2139. static struct clk omap_32ksync_ick = {
  2140. .name = "omap_32ksync_ick",
  2141. .ops = &clkops_omap2_iclk_dflt_wait,
  2142. .parent = &wkup_l4_ick,
  2143. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2144. .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
  2145. .clkdm_name = "wkup_clkdm",
  2146. .recalc = &followparent_recalc,
  2147. };
  2148. /* XXX This clock no longer exists in 3430 TRM rev F */
  2149. static struct clk gpt12_ick = {
  2150. .name = "gpt12_ick",
  2151. .ops = &clkops_omap2_iclk_dflt_wait,
  2152. .parent = &wkup_l4_ick,
  2153. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2154. .enable_bit = OMAP3430_EN_GPT12_SHIFT,
  2155. .clkdm_name = "wkup_clkdm",
  2156. .recalc = &followparent_recalc,
  2157. };
  2158. static struct clk gpt1_ick = {
  2159. .name = "gpt1_ick",
  2160. .ops = &clkops_omap2_iclk_dflt_wait,
  2161. .parent = &wkup_l4_ick,
  2162. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2163. .enable_bit = OMAP3430_EN_GPT1_SHIFT,
  2164. .clkdm_name = "wkup_clkdm",
  2165. .recalc = &followparent_recalc,
  2166. };
  2167. /* PER clock domain */
  2168. static struct clk per_96m_fck = {
  2169. .name = "per_96m_fck",
  2170. .ops = &clkops_null,
  2171. .parent = &omap_96m_alwon_fck,
  2172. .clkdm_name = "per_clkdm",
  2173. .recalc = &followparent_recalc,
  2174. };
  2175. static struct clk per_48m_fck = {
  2176. .name = "per_48m_fck",
  2177. .ops = &clkops_null,
  2178. .parent = &omap_48m_fck,
  2179. .clkdm_name = "per_clkdm",
  2180. .recalc = &followparent_recalc,
  2181. };
  2182. static struct clk uart3_fck = {
  2183. .name = "uart3_fck",
  2184. .ops = &clkops_omap2_dflt_wait,
  2185. .parent = &per_48m_fck,
  2186. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2187. .enable_bit = OMAP3430_EN_UART3_SHIFT,
  2188. .clkdm_name = "per_clkdm",
  2189. .recalc = &followparent_recalc,
  2190. };
  2191. static struct clk uart4_fck = {
  2192. .name = "uart4_fck",
  2193. .ops = &clkops_omap2_dflt_wait,
  2194. .parent = &per_48m_fck,
  2195. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2196. .enable_bit = OMAP3630_EN_UART4_SHIFT,
  2197. .clkdm_name = "per_clkdm",
  2198. .recalc = &followparent_recalc,
  2199. };
  2200. static struct clk uart4_fck_am35xx = {
  2201. .name = "uart4_fck",
  2202. .ops = &clkops_omap2_dflt_wait,
  2203. .parent = &per_48m_fck,
  2204. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  2205. .enable_bit = OMAP3430_EN_UART4_SHIFT,
  2206. .clkdm_name = "core_l4_clkdm",
  2207. .recalc = &followparent_recalc,
  2208. };
  2209. static struct clk gpt2_fck = {
  2210. .name = "gpt2_fck",
  2211. .ops = &clkops_omap2_dflt_wait,
  2212. .init = &omap2_init_clksel_parent,
  2213. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2214. .enable_bit = OMAP3430_EN_GPT2_SHIFT,
  2215. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2216. .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
  2217. .clksel = omap343x_gpt_clksel,
  2218. .clkdm_name = "per_clkdm",
  2219. .recalc = &omap2_clksel_recalc,
  2220. };
  2221. static struct clk gpt3_fck = {
  2222. .name = "gpt3_fck",
  2223. .ops = &clkops_omap2_dflt_wait,
  2224. .init = &omap2_init_clksel_parent,
  2225. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2226. .enable_bit = OMAP3430_EN_GPT3_SHIFT,
  2227. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2228. .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
  2229. .clksel = omap343x_gpt_clksel,
  2230. .clkdm_name = "per_clkdm",
  2231. .recalc = &omap2_clksel_recalc,
  2232. };
  2233. static struct clk gpt4_fck = {
  2234. .name = "gpt4_fck",
  2235. .ops = &clkops_omap2_dflt_wait,
  2236. .init = &omap2_init_clksel_parent,
  2237. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2238. .enable_bit = OMAP3430_EN_GPT4_SHIFT,
  2239. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2240. .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
  2241. .clksel = omap343x_gpt_clksel,
  2242. .clkdm_name = "per_clkdm",
  2243. .recalc = &omap2_clksel_recalc,
  2244. };
  2245. static struct clk gpt5_fck = {
  2246. .name = "gpt5_fck",
  2247. .ops = &clkops_omap2_dflt_wait,
  2248. .init = &omap2_init_clksel_parent,
  2249. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2250. .enable_bit = OMAP3430_EN_GPT5_SHIFT,
  2251. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2252. .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
  2253. .clksel = omap343x_gpt_clksel,
  2254. .clkdm_name = "per_clkdm",
  2255. .recalc = &omap2_clksel_recalc,
  2256. };
  2257. static struct clk gpt6_fck = {
  2258. .name = "gpt6_fck",
  2259. .ops = &clkops_omap2_dflt_wait,
  2260. .init = &omap2_init_clksel_parent,
  2261. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2262. .enable_bit = OMAP3430_EN_GPT6_SHIFT,
  2263. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2264. .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
  2265. .clksel = omap343x_gpt_clksel,
  2266. .clkdm_name = "per_clkdm",
  2267. .recalc = &omap2_clksel_recalc,
  2268. };
  2269. static struct clk gpt7_fck = {
  2270. .name = "gpt7_fck",
  2271. .ops = &clkops_omap2_dflt_wait,
  2272. .init = &omap2_init_clksel_parent,
  2273. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2274. .enable_bit = OMAP3430_EN_GPT7_SHIFT,
  2275. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2276. .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
  2277. .clksel = omap343x_gpt_clksel,
  2278. .clkdm_name = "per_clkdm",
  2279. .recalc = &omap2_clksel_recalc,
  2280. };
  2281. static struct clk gpt8_fck = {
  2282. .name = "gpt8_fck",
  2283. .ops = &clkops_omap2_dflt_wait,
  2284. .init = &omap2_init_clksel_parent,
  2285. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2286. .enable_bit = OMAP3430_EN_GPT8_SHIFT,
  2287. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2288. .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
  2289. .clksel = omap343x_gpt_clksel,
  2290. .clkdm_name = "per_clkdm",
  2291. .recalc = &omap2_clksel_recalc,
  2292. };
  2293. static struct clk gpt9_fck = {
  2294. .name = "gpt9_fck",
  2295. .ops = &clkops_omap2_dflt_wait,
  2296. .init = &omap2_init_clksel_parent,
  2297. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2298. .enable_bit = OMAP3430_EN_GPT9_SHIFT,
  2299. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2300. .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
  2301. .clksel = omap343x_gpt_clksel,
  2302. .clkdm_name = "per_clkdm",
  2303. .recalc = &omap2_clksel_recalc,
  2304. };
  2305. static struct clk per_32k_alwon_fck = {
  2306. .name = "per_32k_alwon_fck",
  2307. .ops = &clkops_null,
  2308. .parent = &omap_32k_fck,
  2309. .clkdm_name = "per_clkdm",
  2310. .recalc = &followparent_recalc,
  2311. };
  2312. static struct clk gpio6_dbck = {
  2313. .name = "gpio6_dbck",
  2314. .ops = &clkops_omap2_dflt,
  2315. .parent = &per_32k_alwon_fck,
  2316. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2317. .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
  2318. .clkdm_name = "per_clkdm",
  2319. .recalc = &followparent_recalc,
  2320. };
  2321. static struct clk gpio5_dbck = {
  2322. .name = "gpio5_dbck",
  2323. .ops = &clkops_omap2_dflt,
  2324. .parent = &per_32k_alwon_fck,
  2325. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2326. .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
  2327. .clkdm_name = "per_clkdm",
  2328. .recalc = &followparent_recalc,
  2329. };
  2330. static struct clk gpio4_dbck = {
  2331. .name = "gpio4_dbck",
  2332. .ops = &clkops_omap2_dflt,
  2333. .parent = &per_32k_alwon_fck,
  2334. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2335. .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
  2336. .clkdm_name = "per_clkdm",
  2337. .recalc = &followparent_recalc,
  2338. };
  2339. static struct clk gpio3_dbck = {
  2340. .name = "gpio3_dbck",
  2341. .ops = &clkops_omap2_dflt,
  2342. .parent = &per_32k_alwon_fck,
  2343. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2344. .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
  2345. .clkdm_name = "per_clkdm",
  2346. .recalc = &followparent_recalc,
  2347. };
  2348. static struct clk gpio2_dbck = {
  2349. .name = "gpio2_dbck",
  2350. .ops = &clkops_omap2_dflt,
  2351. .parent = &per_32k_alwon_fck,
  2352. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2353. .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
  2354. .clkdm_name = "per_clkdm",
  2355. .recalc = &followparent_recalc,
  2356. };
  2357. static struct clk wdt3_fck = {
  2358. .name = "wdt3_fck",
  2359. .ops = &clkops_omap2_dflt_wait,
  2360. .parent = &per_32k_alwon_fck,
  2361. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2362. .enable_bit = OMAP3430_EN_WDT3_SHIFT,
  2363. .clkdm_name = "per_clkdm",
  2364. .recalc = &followparent_recalc,
  2365. };
  2366. static struct clk per_l4_ick = {
  2367. .name = "per_l4_ick",
  2368. .ops = &clkops_null,
  2369. .parent = &l4_ick,
  2370. .clkdm_name = "per_clkdm",
  2371. .recalc = &followparent_recalc,
  2372. };
  2373. static struct clk gpio6_ick = {
  2374. .name = "gpio6_ick",
  2375. .ops = &clkops_omap2_iclk_dflt_wait,
  2376. .parent = &per_l4_ick,
  2377. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2378. .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
  2379. .clkdm_name = "per_clkdm",
  2380. .recalc = &followparent_recalc,
  2381. };
  2382. static struct clk gpio5_ick = {
  2383. .name = "gpio5_ick",
  2384. .ops = &clkops_omap2_iclk_dflt_wait,
  2385. .parent = &per_l4_ick,
  2386. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2387. .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
  2388. .clkdm_name = "per_clkdm",
  2389. .recalc = &followparent_recalc,
  2390. };
  2391. static struct clk gpio4_ick = {
  2392. .name = "gpio4_ick",
  2393. .ops = &clkops_omap2_iclk_dflt_wait,
  2394. .parent = &per_l4_ick,
  2395. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2396. .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
  2397. .clkdm_name = "per_clkdm",
  2398. .recalc = &followparent_recalc,
  2399. };
  2400. static struct clk gpio3_ick = {
  2401. .name = "gpio3_ick",
  2402. .ops = &clkops_omap2_iclk_dflt_wait,
  2403. .parent = &per_l4_ick,
  2404. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2405. .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
  2406. .clkdm_name = "per_clkdm",
  2407. .recalc = &followparent_recalc,
  2408. };
  2409. static struct clk gpio2_ick = {
  2410. .name = "gpio2_ick",
  2411. .ops = &clkops_omap2_iclk_dflt_wait,
  2412. .parent = &per_l4_ick,
  2413. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2414. .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
  2415. .clkdm_name = "per_clkdm",
  2416. .recalc = &followparent_recalc,
  2417. };
  2418. static struct clk wdt3_ick = {
  2419. .name = "wdt3_ick",
  2420. .ops = &clkops_omap2_iclk_dflt_wait,
  2421. .parent = &per_l4_ick,
  2422. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2423. .enable_bit = OMAP3430_EN_WDT3_SHIFT,
  2424. .clkdm_name = "per_clkdm",
  2425. .recalc = &followparent_recalc,
  2426. };
  2427. static struct clk uart3_ick = {
  2428. .name = "uart3_ick",
  2429. .ops = &clkops_omap2_iclk_dflt_wait,
  2430. .parent = &per_l4_ick,
  2431. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2432. .enable_bit = OMAP3430_EN_UART3_SHIFT,
  2433. .clkdm_name = "per_clkdm",
  2434. .recalc = &followparent_recalc,
  2435. };
  2436. static struct clk uart4_ick = {
  2437. .name = "uart4_ick",
  2438. .ops = &clkops_omap2_iclk_dflt_wait,
  2439. .parent = &per_l4_ick,
  2440. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2441. .enable_bit = OMAP3630_EN_UART4_SHIFT,
  2442. .clkdm_name = "per_clkdm",
  2443. .recalc = &followparent_recalc,
  2444. };
  2445. static struct clk gpt9_ick = {
  2446. .name = "gpt9_ick",
  2447. .ops = &clkops_omap2_iclk_dflt_wait,
  2448. .parent = &per_l4_ick,
  2449. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2450. .enable_bit = OMAP3430_EN_GPT9_SHIFT,
  2451. .clkdm_name = "per_clkdm",
  2452. .recalc = &followparent_recalc,
  2453. };
  2454. static struct clk gpt8_ick = {
  2455. .name = "gpt8_ick",
  2456. .ops = &clkops_omap2_iclk_dflt_wait,
  2457. .parent = &per_l4_ick,
  2458. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2459. .enable_bit = OMAP3430_EN_GPT8_SHIFT,
  2460. .clkdm_name = "per_clkdm",
  2461. .recalc = &followparent_recalc,
  2462. };
  2463. static struct clk gpt7_ick = {
  2464. .name = "gpt7_ick",
  2465. .ops = &clkops_omap2_iclk_dflt_wait,
  2466. .parent = &per_l4_ick,
  2467. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2468. .enable_bit = OMAP3430_EN_GPT7_SHIFT,
  2469. .clkdm_name = "per_clkdm",
  2470. .recalc = &followparent_recalc,
  2471. };
  2472. static struct clk gpt6_ick = {
  2473. .name = "gpt6_ick",
  2474. .ops = &clkops_omap2_iclk_dflt_wait,
  2475. .parent = &per_l4_ick,
  2476. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2477. .enable_bit = OMAP3430_EN_GPT6_SHIFT,
  2478. .clkdm_name = "per_clkdm",
  2479. .recalc = &followparent_recalc,
  2480. };
  2481. static struct clk gpt5_ick = {
  2482. .name = "gpt5_ick",
  2483. .ops = &clkops_omap2_iclk_dflt_wait,
  2484. .parent = &per_l4_ick,
  2485. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2486. .enable_bit = OMAP3430_EN_GPT5_SHIFT,
  2487. .clkdm_name = "per_clkdm",
  2488. .recalc = &followparent_recalc,
  2489. };
  2490. static struct clk gpt4_ick = {
  2491. .name = "gpt4_ick",
  2492. .ops = &clkops_omap2_iclk_dflt_wait,
  2493. .parent = &per_l4_ick,
  2494. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2495. .enable_bit = OMAP3430_EN_GPT4_SHIFT,
  2496. .clkdm_name = "per_clkdm",
  2497. .recalc = &followparent_recalc,
  2498. };
  2499. static struct clk gpt3_ick = {
  2500. .name = "gpt3_ick",
  2501. .ops = &clkops_omap2_iclk_dflt_wait,
  2502. .parent = &per_l4_ick,
  2503. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2504. .enable_bit = OMAP3430_EN_GPT3_SHIFT,
  2505. .clkdm_name = "per_clkdm",
  2506. .recalc = &followparent_recalc,
  2507. };
  2508. static struct clk gpt2_ick = {
  2509. .name = "gpt2_ick",
  2510. .ops = &clkops_omap2_iclk_dflt_wait,
  2511. .parent = &per_l4_ick,
  2512. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2513. .enable_bit = OMAP3430_EN_GPT2_SHIFT,
  2514. .clkdm_name = "per_clkdm",
  2515. .recalc = &followparent_recalc,
  2516. };
  2517. static struct clk mcbsp2_ick = {
  2518. .name = "mcbsp2_ick",
  2519. .ops = &clkops_omap2_iclk_dflt_wait,
  2520. .parent = &per_l4_ick,
  2521. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2522. .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
  2523. .clkdm_name = "per_clkdm",
  2524. .recalc = &followparent_recalc,
  2525. };
  2526. static struct clk mcbsp3_ick = {
  2527. .name = "mcbsp3_ick",
  2528. .ops = &clkops_omap2_iclk_dflt_wait,
  2529. .parent = &per_l4_ick,
  2530. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2531. .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
  2532. .clkdm_name = "per_clkdm",
  2533. .recalc = &followparent_recalc,
  2534. };
  2535. static struct clk mcbsp4_ick = {
  2536. .name = "mcbsp4_ick",
  2537. .ops = &clkops_omap2_iclk_dflt_wait,
  2538. .parent = &per_l4_ick,
  2539. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2540. .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
  2541. .clkdm_name = "per_clkdm",
  2542. .recalc = &followparent_recalc,
  2543. };
  2544. static const struct clksel mcbsp_234_clksel[] = {
  2545. { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
  2546. { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
  2547. { .parent = NULL }
  2548. };
  2549. static struct clk mcbsp2_fck = {
  2550. .name = "mcbsp2_fck",
  2551. .ops = &clkops_omap2_dflt_wait,
  2552. .init = &omap2_init_clksel_parent,
  2553. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2554. .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
  2555. .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
  2556. .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
  2557. .clksel = mcbsp_234_clksel,
  2558. .clkdm_name = "per_clkdm",
  2559. .recalc = &omap2_clksel_recalc,
  2560. };
  2561. static struct clk mcbsp3_fck = {
  2562. .name = "mcbsp3_fck",
  2563. .ops = &clkops_omap2_dflt_wait,
  2564. .init = &omap2_init_clksel_parent,
  2565. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2566. .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
  2567. .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
  2568. .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
  2569. .clksel = mcbsp_234_clksel,
  2570. .clkdm_name = "per_clkdm",
  2571. .recalc = &omap2_clksel_recalc,
  2572. };
  2573. static struct clk mcbsp4_fck = {
  2574. .name = "mcbsp4_fck",
  2575. .ops = &clkops_omap2_dflt_wait,
  2576. .init = &omap2_init_clksel_parent,
  2577. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2578. .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
  2579. .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
  2580. .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
  2581. .clksel = mcbsp_234_clksel,
  2582. .clkdm_name = "per_clkdm",
  2583. .recalc = &omap2_clksel_recalc,
  2584. };
  2585. /* EMU clocks */
  2586. /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
  2587. static const struct clksel_rate emu_src_sys_rates[] = {
  2588. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  2589. { .div = 0 },
  2590. };
  2591. static const struct clksel_rate emu_src_core_rates[] = {
  2592. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  2593. { .div = 0 },
  2594. };
  2595. static const struct clksel_rate emu_src_per_rates[] = {
  2596. { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
  2597. { .div = 0 },
  2598. };
  2599. static const struct clksel_rate emu_src_mpu_rates[] = {
  2600. { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
  2601. { .div = 0 },
  2602. };
  2603. static const struct clksel emu_src_clksel[] = {
  2604. { .parent = &sys_ck, .rates = emu_src_sys_rates },
  2605. { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
  2606. { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
  2607. { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
  2608. { .parent = NULL },
  2609. };
  2610. /*
  2611. * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
  2612. * to switch the source of some of the EMU clocks.
  2613. * XXX Are there CLKEN bits for these EMU clks?
  2614. */
  2615. static struct clk emu_src_ck = {
  2616. .name = "emu_src_ck",
  2617. .ops = &clkops_null,
  2618. .init = &omap2_init_clksel_parent,
  2619. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  2620. .clksel_mask = OMAP3430_MUX_CTRL_MASK,
  2621. .clksel = emu_src_clksel,
  2622. .clkdm_name = "emu_clkdm",
  2623. .recalc = &omap2_clksel_recalc,
  2624. };
  2625. static const struct clksel_rate pclk_emu_rates[] = {
  2626. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  2627. { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
  2628. { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
  2629. { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
  2630. { .div = 0 },
  2631. };
  2632. static const struct clksel pclk_emu_clksel[] = {
  2633. { .parent = &emu_src_ck, .rates = pclk_emu_rates },
  2634. { .parent = NULL },
  2635. };
  2636. static struct clk pclk_fck = {
  2637. .name = "pclk_fck",
  2638. .ops = &clkops_null,
  2639. .init = &omap2_init_clksel_parent,
  2640. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  2641. .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
  2642. .clksel = pclk_emu_clksel,
  2643. .clkdm_name = "emu_clkdm",
  2644. .recalc = &omap2_clksel_recalc,
  2645. };
  2646. static const struct clksel_rate pclkx2_emu_rates[] = {
  2647. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  2648. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  2649. { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
  2650. { .div = 0 },
  2651. };
  2652. static const struct clksel pclkx2_emu_clksel[] = {
  2653. { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
  2654. { .parent = NULL },
  2655. };
  2656. static struct clk pclkx2_fck = {
  2657. .name = "pclkx2_fck",
  2658. .ops = &clkops_null,
  2659. .init = &omap2_init_clksel_parent,
  2660. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  2661. .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
  2662. .clksel = pclkx2_emu_clksel,
  2663. .clkdm_name = "emu_clkdm",
  2664. .recalc = &omap2_clksel_recalc,
  2665. };
  2666. static const struct clksel atclk_emu_clksel[] = {
  2667. { .parent = &emu_src_ck, .rates = div2_rates },
  2668. { .parent = NULL },
  2669. };
  2670. static struct clk atclk_fck = {
  2671. .name = "atclk_fck",
  2672. .ops = &clkops_null,
  2673. .init = &omap2_init_clksel_parent,
  2674. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  2675. .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
  2676. .clksel = atclk_emu_clksel,
  2677. .clkdm_name = "emu_clkdm",
  2678. .recalc = &omap2_clksel_recalc,
  2679. };
  2680. static struct clk traceclk_src_fck = {
  2681. .name = "traceclk_src_fck",
  2682. .ops = &clkops_null,
  2683. .init = &omap2_init_clksel_parent,
  2684. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  2685. .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
  2686. .clksel = emu_src_clksel,
  2687. .clkdm_name = "emu_clkdm",
  2688. .recalc = &omap2_clksel_recalc,
  2689. };
  2690. static const struct clksel_rate traceclk_rates[] = {
  2691. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  2692. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  2693. { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
  2694. { .div = 0 },
  2695. };
  2696. static const struct clksel traceclk_clksel[] = {
  2697. { .parent = &traceclk_src_fck, .rates = traceclk_rates },
  2698. { .parent = NULL },
  2699. };
  2700. static struct clk traceclk_fck = {
  2701. .name = "traceclk_fck",
  2702. .ops = &clkops_null,
  2703. .init = &omap2_init_clksel_parent,
  2704. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  2705. .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
  2706. .clksel = traceclk_clksel,
  2707. .clkdm_name = "emu_clkdm",
  2708. .recalc = &omap2_clksel_recalc,
  2709. };
  2710. /* SR clocks */
  2711. /* SmartReflex fclk (VDD1) */
  2712. static struct clk sr1_fck = {
  2713. .name = "sr1_fck",
  2714. .ops = &clkops_omap2_dflt_wait,
  2715. .parent = &sys_ck,
  2716. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2717. .enable_bit = OMAP3430_EN_SR1_SHIFT,
  2718. .clkdm_name = "wkup_clkdm",
  2719. .recalc = &followparent_recalc,
  2720. };
  2721. /* SmartReflex fclk (VDD2) */
  2722. static struct clk sr2_fck = {
  2723. .name = "sr2_fck",
  2724. .ops = &clkops_omap2_dflt_wait,
  2725. .parent = &sys_ck,
  2726. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2727. .enable_bit = OMAP3430_EN_SR2_SHIFT,
  2728. .clkdm_name = "wkup_clkdm",
  2729. .recalc = &followparent_recalc,
  2730. };
  2731. static struct clk sr_l4_ick = {
  2732. .name = "sr_l4_ick",
  2733. .ops = &clkops_null, /* RMK: missing? */
  2734. .parent = &l4_ick,
  2735. .clkdm_name = "core_l4_clkdm",
  2736. .recalc = &followparent_recalc,
  2737. };
  2738. /* SECURE_32K_FCK clocks */
  2739. static struct clk gpt12_fck = {
  2740. .name = "gpt12_fck",
  2741. .ops = &clkops_null,
  2742. .parent = &secure_32k_fck,
  2743. .clkdm_name = "wkup_clkdm",
  2744. .recalc = &followparent_recalc,
  2745. };
  2746. static struct clk wdt1_fck = {
  2747. .name = "wdt1_fck",
  2748. .ops = &clkops_null,
  2749. .parent = &secure_32k_fck,
  2750. .clkdm_name = "wkup_clkdm",
  2751. .recalc = &followparent_recalc,
  2752. };
  2753. /* Clocks for AM35XX */
  2754. static struct clk ipss_ick = {
  2755. .name = "ipss_ick",
  2756. .ops = &clkops_am35xx_ipss_wait,
  2757. .parent = &core_l3_ick,
  2758. .clkdm_name = "core_l3_clkdm",
  2759. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  2760. .enable_bit = AM35XX_EN_IPSS_SHIFT,
  2761. .recalc = &followparent_recalc,
  2762. };
  2763. static struct clk emac_ick = {
  2764. .name = "emac_ick",
  2765. .ops = &clkops_am35xx_ipss_module_wait,
  2766. .parent = &ipss_ick,
  2767. .clkdm_name = "core_l3_clkdm",
  2768. .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
  2769. .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
  2770. .recalc = &followparent_recalc,
  2771. };
  2772. static struct clk rmii_ck = {
  2773. .name = "rmii_ck",
  2774. .ops = &clkops_null,
  2775. .rate = 50000000,
  2776. };
  2777. static struct clk emac_fck = {
  2778. .name = "emac_fck",
  2779. .ops = &clkops_omap2_dflt,
  2780. .parent = &rmii_ck,
  2781. .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
  2782. .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
  2783. .recalc = &followparent_recalc,
  2784. };
  2785. static struct clk hsotgusb_ick_am35xx = {
  2786. .name = "hsotgusb_ick",
  2787. .ops = &clkops_am35xx_ipss_module_wait,
  2788. .parent = &ipss_ick,
  2789. .clkdm_name = "core_l3_clkdm",
  2790. .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
  2791. .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
  2792. .recalc = &followparent_recalc,
  2793. };
  2794. static struct clk hsotgusb_fck_am35xx = {
  2795. .name = "hsotgusb_fck",
  2796. .ops = &clkops_omap2_dflt,
  2797. .parent = &sys_ck,
  2798. .clkdm_name = "core_l3_clkdm",
  2799. .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
  2800. .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
  2801. .recalc = &followparent_recalc,
  2802. };
  2803. static struct clk hecc_ck = {
  2804. .name = "hecc_ck",
  2805. .ops = &clkops_am35xx_ipss_module_wait,
  2806. .parent = &sys_ck,
  2807. .clkdm_name = "core_l3_clkdm",
  2808. .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
  2809. .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
  2810. .recalc = &followparent_recalc,
  2811. };
  2812. static struct clk vpfe_ick = {
  2813. .name = "vpfe_ick",
  2814. .ops = &clkops_am35xx_ipss_module_wait,
  2815. .parent = &ipss_ick,
  2816. .clkdm_name = "core_l3_clkdm",
  2817. .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
  2818. .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
  2819. .recalc = &followparent_recalc,
  2820. };
  2821. static struct clk pclk_ck = {
  2822. .name = "pclk_ck",
  2823. .ops = &clkops_null,
  2824. .rate = 27000000,
  2825. };
  2826. static struct clk vpfe_fck = {
  2827. .name = "vpfe_fck",
  2828. .ops = &clkops_omap2_dflt,
  2829. .parent = &pclk_ck,
  2830. .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
  2831. .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
  2832. .recalc = &followparent_recalc,
  2833. };
  2834. /*
  2835. * The UART1/2 functional clock acts as the functional
  2836. * clock for UART4. No separate fclk control available.
  2837. */
  2838. static struct clk uart4_ick_am35xx = {
  2839. .name = "uart4_ick",
  2840. .ops = &clkops_omap2_iclk_dflt_wait,
  2841. .parent = &core_l4_ick,
  2842. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  2843. .enable_bit = AM35XX_EN_UART4_SHIFT,
  2844. .clkdm_name = "core_l4_clkdm",
  2845. .recalc = &followparent_recalc,
  2846. };
  2847. static struct clk dummy_apb_pclk = {
  2848. .name = "apb_pclk",
  2849. .ops = &clkops_null,
  2850. };
  2851. /*
  2852. * clkdev
  2853. */
  2854. /* XXX At some point we should rename this file to clock3xxx_data.c */
  2855. static struct omap_clk omap3xxx_clks[] = {
  2856. CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
  2857. CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
  2858. CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
  2859. CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
  2860. CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  2861. CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
  2862. CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
  2863. CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
  2864. CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
  2865. CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
  2866. CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
  2867. CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX),
  2868. CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX),
  2869. CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX),
  2870. CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX),
  2871. CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX),
  2872. CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
  2873. CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
  2874. CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
  2875. CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
  2876. CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
  2877. CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX),
  2878. CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX),
  2879. CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
  2880. CLK(NULL, "core_ck", &core_ck, CK_3XXX),
  2881. CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
  2882. CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
  2883. CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
  2884. CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
  2885. CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
  2886. CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
  2887. CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
  2888. CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
  2889. CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
  2890. CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
  2891. CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
  2892. CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
  2893. CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
  2894. CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
  2895. CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
  2896. CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
  2897. CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
  2898. CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
  2899. CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
  2900. CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
  2901. CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
  2902. CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
  2903. CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
  2904. CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
  2905. CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
  2906. CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
  2907. CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  2908. CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  2909. CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
  2910. CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
  2911. CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
  2912. CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
  2913. CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
  2914. CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
  2915. CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
  2916. CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
  2917. CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
  2918. CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
  2919. CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
  2920. CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
  2921. CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
  2922. CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
  2923. CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
  2924. CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
  2925. CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
  2926. CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX),
  2927. CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX),
  2928. CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
  2929. CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
  2930. CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
  2931. CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX),
  2932. CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
  2933. CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
  2934. CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  2935. CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  2936. CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  2937. CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  2938. CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
  2939. CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
  2940. CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
  2941. CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  2942. CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
  2943. CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
  2944. CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX),
  2945. CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX),
  2946. CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX),
  2947. CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX),
  2948. CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX),
  2949. CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX),
  2950. CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
  2951. CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX),
  2952. CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX),
  2953. CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX),
  2954. CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX),
  2955. CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
  2956. CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
  2957. CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
  2958. CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
  2959. CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
  2960. CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
  2961. CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
  2962. CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
  2963. CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
  2964. CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
  2965. CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
  2966. CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
  2967. CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
  2968. CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
  2969. CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
  2970. CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX),
  2971. CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
  2972. CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  2973. CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  2974. CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  2975. CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
  2976. CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
  2977. CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
  2978. CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
  2979. CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
  2980. CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
  2981. CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
  2982. CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
  2983. CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
  2984. CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
  2985. CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
  2986. CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
  2987. CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
  2988. CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
  2989. CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
  2990. CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
  2991. CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
  2992. CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
  2993. CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
  2994. CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
  2995. CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
  2996. CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
  2997. CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
  2998. CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
  2999. CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX),
  3000. CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
  3001. CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
  3002. CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
  3003. CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
  3004. CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX),
  3005. CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
  3006. CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
  3007. CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
  3008. CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
  3009. CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  3010. CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX),
  3011. CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
  3012. CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
  3013. CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
  3014. CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  3015. CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
  3016. CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
  3017. CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
  3018. CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  3019. CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  3020. CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  3021. CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
  3022. CLK("usbhs_omap", "utmi_p1_gfclk", &dummy_ck, CK_3XXX),
  3023. CLK("usbhs_omap", "utmi_p2_gfclk", &dummy_ck, CK_3XXX),
  3024. CLK("usbhs_omap", "xclk60mhsp1_ck", &dummy_ck, CK_3XXX),
  3025. CLK("usbhs_omap", "xclk60mhsp2_ck", &dummy_ck, CK_3XXX),
  3026. CLK("usbhs_omap", "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX),
  3027. CLK("usbhs_omap", "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
  3028. CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
  3029. CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
  3030. CLK("usbhs_omap", "init_60m_fclk", &dummy_ck, CK_3XXX),
  3031. CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
  3032. CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
  3033. CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
  3034. CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
  3035. CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX),
  3036. CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
  3037. CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
  3038. CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
  3039. CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
  3040. CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
  3041. CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
  3042. CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
  3043. CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
  3044. CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX),
  3045. CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX),
  3046. CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX),
  3047. CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
  3048. CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
  3049. CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
  3050. CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
  3051. CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_3505 | CK_3517),
  3052. CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
  3053. CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
  3054. CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
  3055. CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
  3056. CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
  3057. CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
  3058. CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
  3059. CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
  3060. CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
  3061. CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
  3062. CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
  3063. CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
  3064. CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
  3065. CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
  3066. CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
  3067. CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
  3068. CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
  3069. CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
  3070. CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
  3071. CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
  3072. CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
  3073. CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
  3074. CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
  3075. CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX),
  3076. CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
  3077. CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
  3078. CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
  3079. CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
  3080. CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
  3081. CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
  3082. CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
  3083. CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
  3084. CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
  3085. CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
  3086. CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
  3087. CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
  3088. CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
  3089. CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
  3090. CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
  3091. CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
  3092. CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
  3093. CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
  3094. CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
  3095. CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
  3096. CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
  3097. CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
  3098. CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
  3099. CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
  3100. CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
  3101. CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
  3102. CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
  3103. CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
  3104. CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
  3105. CLK("davinci_emac", "emac_clk", &emac_ick, CK_AM35XX),
  3106. CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX),
  3107. CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
  3108. CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
  3109. CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
  3110. CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
  3111. CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
  3112. CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
  3113. CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX),
  3114. CLK("omap_timer.2", "32k_ck", &omap_32k_fck, CK_3XXX),
  3115. CLK("omap_timer.3", "32k_ck", &omap_32k_fck, CK_3XXX),
  3116. CLK("omap_timer.4", "32k_ck", &omap_32k_fck, CK_3XXX),
  3117. CLK("omap_timer.5", "32k_ck", &omap_32k_fck, CK_3XXX),
  3118. CLK("omap_timer.6", "32k_ck", &omap_32k_fck, CK_3XXX),
  3119. CLK("omap_timer.7", "32k_ck", &omap_32k_fck, CK_3XXX),
  3120. CLK("omap_timer.8", "32k_ck", &omap_32k_fck, CK_3XXX),
  3121. CLK("omap_timer.9", "32k_ck", &omap_32k_fck, CK_3XXX),
  3122. CLK("omap_timer.10", "32k_ck", &omap_32k_fck, CK_3XXX),
  3123. CLK("omap_timer.11", "32k_ck", &omap_32k_fck, CK_3XXX),
  3124. CLK("omap_timer.12", "32k_ck", &omap_32k_fck, CK_3XXX),
  3125. CLK("omap_timer.1", "sys_ck", &sys_ck, CK_3XXX),
  3126. CLK("omap_timer.2", "sys_ck", &sys_ck, CK_3XXX),
  3127. CLK("omap_timer.3", "sys_ck", &sys_ck, CK_3XXX),
  3128. CLK("omap_timer.4", "sys_ck", &sys_ck, CK_3XXX),
  3129. CLK("omap_timer.5", "sys_ck", &sys_ck, CK_3XXX),
  3130. CLK("omap_timer.6", "sys_ck", &sys_ck, CK_3XXX),
  3131. CLK("omap_timer.7", "sys_ck", &sys_ck, CK_3XXX),
  3132. CLK("omap_timer.8", "sys_ck", &sys_ck, CK_3XXX),
  3133. CLK("omap_timer.9", "sys_ck", &sys_ck, CK_3XXX),
  3134. CLK("omap_timer.10", "sys_ck", &sys_ck, CK_3XXX),
  3135. CLK("omap_timer.11", "sys_ck", &sys_ck, CK_3XXX),
  3136. CLK("omap_timer.12", "sys_ck", &sys_ck, CK_3XXX),
  3137. };
  3138. int __init omap3xxx_clk_init(void)
  3139. {
  3140. struct omap_clk *c;
  3141. u32 cpu_clkflg = 0;
  3142. /*
  3143. * 3505 must be tested before 3517, since 3517 returns true
  3144. * for both AM3517 chips and AM3517 family chips, which
  3145. * includes 3505. Unfortunately there's no obvious family
  3146. * test for 3517/3505 :-(
  3147. */
  3148. if (cpu_is_omap3505()) {
  3149. cpu_mask = RATE_IN_34XX;
  3150. cpu_clkflg = CK_3505;
  3151. } else if (cpu_is_omap3517()) {
  3152. cpu_mask = RATE_IN_34XX;
  3153. cpu_clkflg = CK_3517;
  3154. } else if (cpu_is_omap3505()) {
  3155. cpu_mask = RATE_IN_34XX;
  3156. cpu_clkflg = CK_3505;
  3157. } else if (cpu_is_omap3630()) {
  3158. cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
  3159. cpu_clkflg = CK_36XX;
  3160. } else if (cpu_is_ti816x()) {
  3161. cpu_mask = RATE_IN_TI816X;
  3162. cpu_clkflg = CK_TI816X;
  3163. } else if (cpu_is_am33xx()) {
  3164. cpu_mask = RATE_IN_AM33XX;
  3165. } else if (cpu_is_ti814x()) {
  3166. cpu_mask = RATE_IN_TI814X;
  3167. } else if (cpu_is_omap34xx()) {
  3168. if (omap_rev() == OMAP3430_REV_ES1_0) {
  3169. cpu_mask = RATE_IN_3430ES1;
  3170. cpu_clkflg = CK_3430ES1;
  3171. } else {
  3172. /*
  3173. * Assume that anything that we haven't matched yet
  3174. * has 3430ES2-type clocks.
  3175. */
  3176. cpu_mask = RATE_IN_3430ES2PLUS;
  3177. cpu_clkflg = CK_3430ES2PLUS;
  3178. }
  3179. } else {
  3180. WARN(1, "clock: could not identify OMAP3 variant\n");
  3181. }
  3182. if (omap3_has_192mhz_clk())
  3183. omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
  3184. if (cpu_is_omap3630()) {
  3185. /*
  3186. * XXX This type of dynamic rewriting of the clock tree is
  3187. * deprecated and should be revised soon.
  3188. *
  3189. * For 3630: override clkops_omap2_dflt_wait for the
  3190. * clocks affected from PWRDN reset Limitation
  3191. */
  3192. dpll3_m3x2_ck.ops =
  3193. &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
  3194. dpll4_m2x2_ck.ops =
  3195. &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
  3196. dpll4_m3x2_ck.ops =
  3197. &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
  3198. dpll4_m4x2_ck.ops =
  3199. &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
  3200. dpll4_m5x2_ck.ops =
  3201. &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
  3202. dpll4_m6x2_ck.ops =
  3203. &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
  3204. }
  3205. /*
  3206. * XXX This type of dynamic rewriting of the clock tree is
  3207. * deprecated and should be revised soon.
  3208. */
  3209. if (cpu_is_omap3630())
  3210. dpll4_dd = dpll4_dd_3630;
  3211. else
  3212. dpll4_dd = dpll4_dd_34xx;
  3213. clk_init(&omap2_clk_functions);
  3214. for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
  3215. c++)
  3216. clk_preinit(c->lk.clk);
  3217. for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
  3218. c++)
  3219. if (c->cpu & cpu_clkflg) {
  3220. clkdev_add(&c->lk);
  3221. clk_register(c->lk.clk);
  3222. omap2_init_clk_clkdm(c->lk.clk);
  3223. }
  3224. /* Disable autoidle on all clocks; let the PM code enable it later */
  3225. omap_clk_disable_autoidle_all();
  3226. recalculate_root_clocks();
  3227. pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
  3228. (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
  3229. (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
  3230. /*
  3231. * Only enable those clocks we will need, let the drivers
  3232. * enable other clocks as necessary
  3233. */
  3234. clk_enable_init_clocks();
  3235. /*
  3236. * Lock DPLL5 -- here only until other device init code can
  3237. * handle this
  3238. */
  3239. if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
  3240. omap3_clk_lock_dpll5();
  3241. /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
  3242. sdrc_ick_p = clk_get(NULL, "sdrc_ick");
  3243. arm_fck_p = clk_get(NULL, "arm_fck");
  3244. return 0;
  3245. }