mci.c 16 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/dma-mapping.h>
  17. #include <linux/slab.h>
  18. #include "ath9k.h"
  19. #include "mci.h"
  20. static const u8 ath_mci_duty_cycle[] = { 55, 50, 60, 70, 80, 85, 90, 95, 98 };
  21. static struct ath_mci_profile_info*
  22. ath_mci_find_profile(struct ath_mci_profile *mci,
  23. struct ath_mci_profile_info *info)
  24. {
  25. struct ath_mci_profile_info *entry;
  26. if (list_empty(&mci->info))
  27. return NULL;
  28. list_for_each_entry(entry, &mci->info, list) {
  29. if (entry->conn_handle == info->conn_handle)
  30. return entry;
  31. }
  32. return NULL;
  33. }
  34. static bool ath_mci_add_profile(struct ath_common *common,
  35. struct ath_mci_profile *mci,
  36. struct ath_mci_profile_info *info)
  37. {
  38. struct ath_mci_profile_info *entry;
  39. if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
  40. (info->type == MCI_GPM_COEX_PROFILE_VOICE))
  41. return false;
  42. if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
  43. (info->type != MCI_GPM_COEX_PROFILE_VOICE))
  44. return false;
  45. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  46. if (!entry)
  47. return false;
  48. memcpy(entry, info, 10);
  49. INC_PROF(mci, info);
  50. list_add_tail(&entry->list, &mci->info);
  51. return true;
  52. }
  53. static void ath_mci_del_profile(struct ath_common *common,
  54. struct ath_mci_profile *mci,
  55. struct ath_mci_profile_info *entry)
  56. {
  57. if (!entry)
  58. return;
  59. DEC_PROF(mci, entry);
  60. list_del(&entry->list);
  61. kfree(entry);
  62. }
  63. void ath_mci_flush_profile(struct ath_mci_profile *mci)
  64. {
  65. struct ath_mci_profile_info *info, *tinfo;
  66. mci->aggr_limit = 0;
  67. if (list_empty(&mci->info))
  68. return;
  69. list_for_each_entry_safe(info, tinfo, &mci->info, list) {
  70. list_del(&info->list);
  71. DEC_PROF(mci, info);
  72. kfree(info);
  73. }
  74. }
  75. static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
  76. {
  77. struct ath_mci_profile *mci = &btcoex->mci;
  78. u32 wlan_airtime = btcoex->btcoex_period *
  79. (100 - btcoex->duty_cycle) / 100;
  80. /*
  81. * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
  82. * When wlan_airtime is less than 4ms, aggregation limit has to be
  83. * adjusted half of wlan_airtime to ensure that the aggregation can fit
  84. * without collision with BT traffic.
  85. */
  86. if ((wlan_airtime <= 4) &&
  87. (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime))))
  88. mci->aggr_limit = 2 * wlan_airtime;
  89. }
  90. static void ath_mci_update_scheme(struct ath_softc *sc)
  91. {
  92. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  93. struct ath_btcoex *btcoex = &sc->btcoex;
  94. struct ath_mci_profile *mci = &btcoex->mci;
  95. struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
  96. struct ath_mci_profile_info *info;
  97. u32 num_profile = NUM_PROF(mci);
  98. if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
  99. goto skip_tuning;
  100. btcoex->duty_cycle = ath_mci_duty_cycle[num_profile];
  101. if (num_profile == 1) {
  102. info = list_first_entry(&mci->info,
  103. struct ath_mci_profile_info,
  104. list);
  105. if (mci->num_sco) {
  106. if (info->T == 12)
  107. mci->aggr_limit = 8;
  108. else if (info->T == 6) {
  109. mci->aggr_limit = 6;
  110. btcoex->duty_cycle = 30;
  111. }
  112. ath_dbg(common, MCI,
  113. "Single SCO, aggregation limit %d 1/4 ms\n",
  114. mci->aggr_limit);
  115. } else if (mci->num_pan || mci->num_other_acl) {
  116. /*
  117. * For single PAN/FTP profile, allocate 35% for BT
  118. * to improve WLAN throughput.
  119. */
  120. btcoex->duty_cycle = 35;
  121. btcoex->btcoex_period = 53;
  122. ath_dbg(common, MCI,
  123. "Single PAN/FTP bt period %d ms dutycycle %d\n",
  124. btcoex->duty_cycle, btcoex->btcoex_period);
  125. } else if (mci->num_hid) {
  126. btcoex->duty_cycle = 30;
  127. mci->aggr_limit = 6;
  128. ath_dbg(common, MCI,
  129. "Multiple attempt/timeout single HID "
  130. "aggregation limit 1.5 ms dutycycle 30%%\n");
  131. }
  132. } else if (num_profile == 2) {
  133. if (mci->num_hid == 2)
  134. btcoex->duty_cycle = 30;
  135. mci->aggr_limit = 6;
  136. ath_dbg(common, MCI,
  137. "Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
  138. btcoex->duty_cycle);
  139. } else if (num_profile >= 3) {
  140. mci->aggr_limit = 4;
  141. ath_dbg(common, MCI,
  142. "Three or more profiles aggregation limit 1 ms\n");
  143. }
  144. skip_tuning:
  145. if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
  146. if (IS_CHAN_HT(sc->sc_ah->curchan))
  147. ath_mci_adjust_aggr_limit(btcoex);
  148. else
  149. btcoex->btcoex_period >>= 1;
  150. }
  151. ath9k_hw_btcoex_disable(sc->sc_ah);
  152. ath9k_btcoex_timer_pause(sc);
  153. if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
  154. return;
  155. btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_BDR_DUTY_CYCLE : 0);
  156. if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
  157. btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
  158. btcoex->btcoex_no_stomp = btcoex->btcoex_period * 1000 *
  159. (100 - btcoex->duty_cycle) / 100;
  160. ath9k_hw_btcoex_enable(sc->sc_ah);
  161. ath9k_btcoex_timer_resume(sc);
  162. }
  163. static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  164. {
  165. struct ath_hw *ah = sc->sc_ah;
  166. struct ath_common *common = ath9k_hw_common(ah);
  167. u32 payload[4] = {0, 0, 0, 0};
  168. switch (opcode) {
  169. case MCI_GPM_BT_CAL_REQ:
  170. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) {
  171. ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START, NULL);
  172. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  173. } else {
  174. ath_dbg(common, MCI, "MCI State mismatch: %d\n",
  175. ar9003_mci_state(ah, MCI_STATE_BT, NULL));
  176. }
  177. break;
  178. case MCI_GPM_BT_CAL_DONE:
  179. ar9003_mci_state(ah, MCI_STATE_BT, NULL);
  180. break;
  181. case MCI_GPM_BT_CAL_GRANT:
  182. MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
  183. ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
  184. 16, false, true);
  185. break;
  186. default:
  187. ath_dbg(common, MCI, "Unknown GPM CAL message\n");
  188. break;
  189. }
  190. }
  191. static void ath9k_mci_work(struct work_struct *work)
  192. {
  193. struct ath_softc *sc = container_of(work, struct ath_softc, mci_work);
  194. ath_mci_update_scheme(sc);
  195. }
  196. static void ath_mci_process_profile(struct ath_softc *sc,
  197. struct ath_mci_profile_info *info)
  198. {
  199. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  200. struct ath_btcoex *btcoex = &sc->btcoex;
  201. struct ath_mci_profile *mci = &btcoex->mci;
  202. struct ath_mci_profile_info *entry = NULL;
  203. entry = ath_mci_find_profile(mci, info);
  204. if (entry)
  205. memcpy(entry, info, 10);
  206. if (info->start) {
  207. if (!entry && !ath_mci_add_profile(common, mci, info))
  208. return;
  209. } else
  210. ath_mci_del_profile(common, mci, entry);
  211. btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
  212. mci->aggr_limit = mci->num_sco ? 6 : 0;
  213. btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)];
  214. if (NUM_PROF(mci))
  215. btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
  216. else
  217. btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
  218. ATH_BTCOEX_STOMP_LOW;
  219. ieee80211_queue_work(sc->hw, &sc->mci_work);
  220. }
  221. static void ath_mci_process_status(struct ath_softc *sc,
  222. struct ath_mci_profile_status *status)
  223. {
  224. struct ath_btcoex *btcoex = &sc->btcoex;
  225. struct ath_mci_profile *mci = &btcoex->mci;
  226. struct ath_mci_profile_info info;
  227. int i = 0, old_num_mgmt = mci->num_mgmt;
  228. /* Link status type are not handled */
  229. if (status->is_link)
  230. return;
  231. info.conn_handle = status->conn_handle;
  232. if (ath_mci_find_profile(mci, &info))
  233. return;
  234. if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
  235. return;
  236. if (status->is_critical)
  237. __set_bit(status->conn_handle, mci->status);
  238. else
  239. __clear_bit(status->conn_handle, mci->status);
  240. mci->num_mgmt = 0;
  241. do {
  242. if (test_bit(i, mci->status))
  243. mci->num_mgmt++;
  244. } while (++i < ATH_MCI_MAX_PROFILE);
  245. if (old_num_mgmt != mci->num_mgmt)
  246. ieee80211_queue_work(sc->hw, &sc->mci_work);
  247. }
  248. static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  249. {
  250. struct ath_hw *ah = sc->sc_ah;
  251. struct ath_mci_profile_info profile_info;
  252. struct ath_mci_profile_status profile_status;
  253. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  254. u32 version;
  255. u8 major;
  256. u8 minor;
  257. u32 seq_num;
  258. switch (opcode) {
  259. case MCI_GPM_COEX_VERSION_QUERY:
  260. version = ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION,
  261. NULL);
  262. break;
  263. case MCI_GPM_COEX_VERSION_RESPONSE:
  264. major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
  265. minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
  266. version = (major << 8) + minor;
  267. version = ar9003_mci_state(ah, MCI_STATE_SET_BT_COEX_VERSION,
  268. &version);
  269. break;
  270. case MCI_GPM_COEX_STATUS_QUERY:
  271. ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_CHANNELS, NULL);
  272. break;
  273. case MCI_GPM_COEX_BT_PROFILE_INFO:
  274. memcpy(&profile_info,
  275. (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
  276. if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) ||
  277. (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
  278. ath_dbg(common, MCI,
  279. "Illegal profile type = %d, state = %d\n",
  280. profile_info.type,
  281. profile_info.start);
  282. break;
  283. }
  284. ath_mci_process_profile(sc, &profile_info);
  285. break;
  286. case MCI_GPM_COEX_BT_STATUS_UPDATE:
  287. profile_status.is_link = *(rx_payload +
  288. MCI_GPM_COEX_B_STATUS_TYPE);
  289. profile_status.conn_handle = *(rx_payload +
  290. MCI_GPM_COEX_B_STATUS_LINKID);
  291. profile_status.is_critical = *(rx_payload +
  292. MCI_GPM_COEX_B_STATUS_STATE);
  293. seq_num = *((u32 *)(rx_payload + 12));
  294. ath_dbg(common, MCI,
  295. "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%d\n",
  296. profile_status.is_link, profile_status.conn_handle,
  297. profile_status.is_critical, seq_num);
  298. ath_mci_process_status(sc, &profile_status);
  299. break;
  300. default:
  301. ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
  302. break;
  303. }
  304. }
  305. int ath_mci_setup(struct ath_softc *sc)
  306. {
  307. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  308. struct ath_mci_coex *mci = &sc->mci_coex;
  309. struct ath_mci_buf *buf = &mci->sched_buf;
  310. buf->bf_addr = dma_alloc_coherent(sc->dev,
  311. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  312. &buf->bf_paddr, GFP_KERNEL);
  313. if (buf->bf_addr == NULL) {
  314. ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
  315. return -ENOMEM;
  316. }
  317. memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
  318. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);
  319. mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
  320. mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
  321. mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
  322. mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
  323. ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
  324. mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
  325. mci->sched_buf.bf_paddr);
  326. INIT_WORK(&sc->mci_work, ath9k_mci_work);
  327. ath_dbg(common, MCI, "MCI Initialized\n");
  328. return 0;
  329. }
  330. void ath_mci_cleanup(struct ath_softc *sc)
  331. {
  332. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  333. struct ath_hw *ah = sc->sc_ah;
  334. struct ath_mci_coex *mci = &sc->mci_coex;
  335. struct ath_mci_buf *buf = &mci->sched_buf;
  336. if (buf->bf_addr)
  337. dma_free_coherent(sc->dev,
  338. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  339. buf->bf_addr, buf->bf_paddr);
  340. ar9003_mci_cleanup(ah);
  341. ath_dbg(common, MCI, "MCI De-Initialized\n");
  342. }
  343. void ath_mci_intr(struct ath_softc *sc)
  344. {
  345. struct ath_mci_coex *mci = &sc->mci_coex;
  346. struct ath_hw *ah = sc->sc_ah;
  347. struct ath_common *common = ath9k_hw_common(ah);
  348. u32 mci_int, mci_int_rxmsg;
  349. u32 offset, subtype, opcode;
  350. u32 *pgpm;
  351. u32 more_data = MCI_GPM_MORE;
  352. bool skip_gpm = false;
  353. ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
  354. if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) == 0) {
  355. ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET, NULL);
  356. return;
  357. }
  358. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
  359. u32 payload[4] = { 0xffffffff, 0xffffffff,
  360. 0xffffffff, 0xffffff00};
  361. /*
  362. * The following REMOTE_RESET and SYS_WAKING used to sent
  363. * only when BT wake up. Now they are always sent, as a
  364. * recovery method to reset BT MCI's RX alignment.
  365. */
  366. ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
  367. payload, 16, true, false);
  368. ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
  369. NULL, 0, true, false);
  370. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
  371. ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE, NULL);
  372. /*
  373. * always do this for recovery and 2G/5G toggling and LNA_TRANS
  374. */
  375. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, NULL);
  376. }
  377. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
  378. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
  379. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_SLEEP) {
  380. if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) !=
  381. MCI_BT_SLEEP)
  382. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE,
  383. NULL);
  384. }
  385. }
  386. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
  387. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
  388. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) {
  389. if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) !=
  390. MCI_BT_AWAKE)
  391. ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP,
  392. NULL);
  393. }
  394. }
  395. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  396. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
  397. ar9003_mci_state(ah, MCI_STATE_RECOVER_RX, NULL);
  398. skip_gpm = true;
  399. }
  400. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
  401. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
  402. offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET,
  403. NULL);
  404. }
  405. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
  406. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
  407. while (more_data == MCI_GPM_MORE) {
  408. pgpm = mci->gpm_buf.bf_addr;
  409. offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET,
  410. &more_data);
  411. if (offset == MCI_GPM_INVALID)
  412. break;
  413. pgpm += (offset >> 2);
  414. /*
  415. * The first dword is timer.
  416. * The real data starts from 2nd dword.
  417. */
  418. subtype = MCI_GPM_TYPE(pgpm);
  419. opcode = MCI_GPM_OPCODE(pgpm);
  420. if (skip_gpm)
  421. goto recycle;
  422. if (MCI_GPM_IS_CAL_TYPE(subtype)) {
  423. ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
  424. } else {
  425. switch (subtype) {
  426. case MCI_GPM_COEX_AGENT:
  427. ath_mci_msg(sc, opcode, (u8 *)pgpm);
  428. break;
  429. default:
  430. break;
  431. }
  432. }
  433. recycle:
  434. MCI_GPM_RECYCLE(pgpm);
  435. }
  436. }
  437. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
  438. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
  439. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
  440. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
  441. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
  442. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
  443. int value_dbm = ar9003_mci_state(ah,
  444. MCI_STATE_CONT_RSSI_POWER, NULL);
  445. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
  446. if (ar9003_mci_state(ah, MCI_STATE_CONT_TXRX, NULL))
  447. ath_dbg(common, MCI,
  448. "MCI CONT_INFO: (tx) pri = %d, pwr = %d dBm\n",
  449. ar9003_mci_state(ah,
  450. MCI_STATE_CONT_PRIORITY, NULL),
  451. value_dbm);
  452. else
  453. ath_dbg(common, MCI,
  454. "MCI CONT_INFO: (rx) pri = %d,pwr = %d dBm\n",
  455. ar9003_mci_state(ah,
  456. MCI_STATE_CONT_PRIORITY, NULL),
  457. value_dbm);
  458. }
  459. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
  460. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
  461. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
  462. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
  463. }
  464. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  465. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT))
  466. mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
  467. AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
  468. }
  469. void ath_mci_enable(struct ath_softc *sc)
  470. {
  471. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  472. if (!common->btcoex_enabled)
  473. return;
  474. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
  475. sc->sc_ah->imask |= ATH9K_INT_MCI;
  476. }