dev-spi.c 4.5 KB

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  1. /* linux/arch/arm/mach-s5p64x0/dev-spi.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  7. * Jaswinder Singh <jassi.brar@samsung.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/platform_device.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/gpio.h>
  16. #include <mach/dma.h>
  17. #include <mach/map.h>
  18. #include <mach/irqs.h>
  19. #include <mach/regs-clock.h>
  20. #include <mach/spi-clocks.h>
  21. #include <plat/cpu.h>
  22. #include <plat/s3c64xx-spi.h>
  23. #include <plat/gpio-cfg.h>
  24. /* SPI Controller platform_devices */
  25. /* Since we emulate multi-cs capability, we do not touch the CS.
  26. * The emulated CS is toggled by board specific mechanism, as it can
  27. * be either some immediate GPIO or some signal out of some other
  28. * chip in between ... or some yet another way.
  29. * We simply do not assume anything about CS.
  30. */
  31. static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
  32. {
  33. unsigned int base;
  34. switch (pdev->id) {
  35. case 0:
  36. base = S5P6440_GPC(0);
  37. break;
  38. case 1:
  39. base = S5P6440_GPC(4);
  40. break;
  41. default:
  42. dev_err(&pdev->dev, "Invalid SPI Controller number!");
  43. return -EINVAL;
  44. }
  45. s3c_gpio_cfgall_range(base, 3,
  46. S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  47. return 0;
  48. }
  49. static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
  50. {
  51. unsigned int base;
  52. switch (pdev->id) {
  53. case 0:
  54. base = S5P6450_GPC(0);
  55. break;
  56. case 1:
  57. base = S5P6450_GPC(4);
  58. break;
  59. default:
  60. dev_err(&pdev->dev, "Invalid SPI Controller number!");
  61. return -EINVAL;
  62. }
  63. s3c_gpio_cfgall_range(base, 3,
  64. S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  65. return 0;
  66. }
  67. static struct resource s5p64x0_spi0_resource[] = {
  68. [0] = {
  69. .start = S5P64X0_PA_SPI0,
  70. .end = S5P64X0_PA_SPI0 + 0x100 - 1,
  71. .flags = IORESOURCE_MEM,
  72. },
  73. [1] = {
  74. .start = DMACH_SPI0_TX,
  75. .end = DMACH_SPI0_TX,
  76. .flags = IORESOURCE_DMA,
  77. },
  78. [2] = {
  79. .start = DMACH_SPI0_RX,
  80. .end = DMACH_SPI0_RX,
  81. .flags = IORESOURCE_DMA,
  82. },
  83. [3] = {
  84. .start = IRQ_SPI0,
  85. .end = IRQ_SPI0,
  86. .flags = IORESOURCE_IRQ,
  87. },
  88. };
  89. static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
  90. .cfg_gpio = s5p6440_spi_cfg_gpio,
  91. .fifo_lvl_mask = 0x1ff,
  92. .rx_lvl_offset = 15,
  93. .tx_st_done = 25,
  94. };
  95. static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
  96. .cfg_gpio = s5p6450_spi_cfg_gpio,
  97. .fifo_lvl_mask = 0x1ff,
  98. .rx_lvl_offset = 15,
  99. .tx_st_done = 25,
  100. };
  101. static u64 spi_dmamask = DMA_BIT_MASK(32);
  102. struct platform_device s5p64x0_device_spi0 = {
  103. .name = "s3c64xx-spi",
  104. .id = 0,
  105. .num_resources = ARRAY_SIZE(s5p64x0_spi0_resource),
  106. .resource = s5p64x0_spi0_resource,
  107. .dev = {
  108. .dma_mask = &spi_dmamask,
  109. .coherent_dma_mask = DMA_BIT_MASK(32),
  110. },
  111. };
  112. static struct resource s5p64x0_spi1_resource[] = {
  113. [0] = {
  114. .start = S5P64X0_PA_SPI1,
  115. .end = S5P64X0_PA_SPI1 + 0x100 - 1,
  116. .flags = IORESOURCE_MEM,
  117. },
  118. [1] = {
  119. .start = DMACH_SPI1_TX,
  120. .end = DMACH_SPI1_TX,
  121. .flags = IORESOURCE_DMA,
  122. },
  123. [2] = {
  124. .start = DMACH_SPI1_RX,
  125. .end = DMACH_SPI1_RX,
  126. .flags = IORESOURCE_DMA,
  127. },
  128. [3] = {
  129. .start = IRQ_SPI1,
  130. .end = IRQ_SPI1,
  131. .flags = IORESOURCE_IRQ,
  132. },
  133. };
  134. static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
  135. .cfg_gpio = s5p6440_spi_cfg_gpio,
  136. .fifo_lvl_mask = 0x7f,
  137. .rx_lvl_offset = 15,
  138. .tx_st_done = 25,
  139. };
  140. static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
  141. .cfg_gpio = s5p6450_spi_cfg_gpio,
  142. .fifo_lvl_mask = 0x7f,
  143. .rx_lvl_offset = 15,
  144. .tx_st_done = 25,
  145. };
  146. struct platform_device s5p64x0_device_spi1 = {
  147. .name = "s3c64xx-spi",
  148. .id = 1,
  149. .num_resources = ARRAY_SIZE(s5p64x0_spi1_resource),
  150. .resource = s5p64x0_spi1_resource,
  151. .dev = {
  152. .dma_mask = &spi_dmamask,
  153. .coherent_dma_mask = DMA_BIT_MASK(32),
  154. },
  155. };
  156. void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
  157. {
  158. struct s3c64xx_spi_info *pd;
  159. /* Reject invalid configuration */
  160. if (!num_cs || src_clk_nr < 0
  161. || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
  162. printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
  163. return;
  164. }
  165. switch (cntrlr) {
  166. case 0:
  167. if (soc_is_s5p6450())
  168. pd = &s5p6450_spi0_pdata;
  169. else
  170. pd = &s5p6440_spi0_pdata;
  171. s5p64x0_device_spi0.dev.platform_data = pd;
  172. break;
  173. case 1:
  174. if (soc_is_s5p6450())
  175. pd = &s5p6450_spi1_pdata;
  176. else
  177. pd = &s5p6440_spi1_pdata;
  178. s5p64x0_device_spi1.dev.platform_data = pd;
  179. break;
  180. default:
  181. printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
  182. __func__, cntrlr);
  183. return;
  184. }
  185. pd->num_cs = num_cs;
  186. pd->src_clk_nr = src_clk_nr;
  187. }