i40e_main.c 199 KB

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  1. /*******************************************************************************
  2. *
  3. * Intel Ethernet Controller XL710 Family Linux Driver
  4. * Copyright(c) 2013 Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program; if not, write to the Free Software Foundation, Inc.,
  17. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18. *
  19. * The full GNU General Public License is included in this distribution in
  20. * the file called "COPYING".
  21. *
  22. * Contact Information:
  23. * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25. *
  26. ******************************************************************************/
  27. /* Local includes */
  28. #include "i40e.h"
  29. const char i40e_driver_name[] = "i40e";
  30. static const char i40e_driver_string[] =
  31. "Intel(R) Ethernet Connection XL710 Network Driver";
  32. #define DRV_KERN "-k"
  33. #define DRV_VERSION_MAJOR 0
  34. #define DRV_VERSION_MINOR 3
  35. #define DRV_VERSION_BUILD 9
  36. #define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
  37. __stringify(DRV_VERSION_MINOR) "." \
  38. __stringify(DRV_VERSION_BUILD) DRV_KERN
  39. const char i40e_driver_version_str[] = DRV_VERSION;
  40. static const char i40e_copyright[] = "Copyright (c) 2013 Intel Corporation.";
  41. /* a bit of forward declarations */
  42. static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
  43. static void i40e_handle_reset_warning(struct i40e_pf *pf);
  44. static int i40e_add_vsi(struct i40e_vsi *vsi);
  45. static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
  46. static int i40e_setup_pf_switch(struct i40e_pf *pf);
  47. static int i40e_setup_misc_vector(struct i40e_pf *pf);
  48. static void i40e_determine_queue_usage(struct i40e_pf *pf);
  49. static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
  50. /* i40e_pci_tbl - PCI Device ID Table
  51. *
  52. * Last entry must be all 0s
  53. *
  54. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  55. * Class, Class Mask, private data (not used) }
  56. */
  57. static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
  58. {PCI_VDEVICE(INTEL, I40E_SFP_XL710_DEVICE_ID), 0},
  59. {PCI_VDEVICE(INTEL, I40E_SFP_X710_DEVICE_ID), 0},
  60. {PCI_VDEVICE(INTEL, I40E_QEMU_DEVICE_ID), 0},
  61. {PCI_VDEVICE(INTEL, I40E_KX_A_DEVICE_ID), 0},
  62. {PCI_VDEVICE(INTEL, I40E_KX_B_DEVICE_ID), 0},
  63. {PCI_VDEVICE(INTEL, I40E_KX_C_DEVICE_ID), 0},
  64. {PCI_VDEVICE(INTEL, I40E_KX_D_DEVICE_ID), 0},
  65. {PCI_VDEVICE(INTEL, I40E_QSFP_A_DEVICE_ID), 0},
  66. {PCI_VDEVICE(INTEL, I40E_QSFP_B_DEVICE_ID), 0},
  67. {PCI_VDEVICE(INTEL, I40E_QSFP_C_DEVICE_ID), 0},
  68. /* required last entry */
  69. {0, }
  70. };
  71. MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
  72. #define I40E_MAX_VF_COUNT 128
  73. static int debug = -1;
  74. module_param(debug, int, 0);
  75. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  76. MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
  77. MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
  78. MODULE_LICENSE("GPL");
  79. MODULE_VERSION(DRV_VERSION);
  80. /**
  81. * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
  82. * @hw: pointer to the HW structure
  83. * @mem: ptr to mem struct to fill out
  84. * @size: size of memory requested
  85. * @alignment: what to align the allocation to
  86. **/
  87. int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
  88. u64 size, u32 alignment)
  89. {
  90. struct i40e_pf *pf = (struct i40e_pf *)hw->back;
  91. mem->size = ALIGN(size, alignment);
  92. mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
  93. &mem->pa, GFP_KERNEL);
  94. if (!mem->va)
  95. return -ENOMEM;
  96. return 0;
  97. }
  98. /**
  99. * i40e_free_dma_mem_d - OS specific memory free for shared code
  100. * @hw: pointer to the HW structure
  101. * @mem: ptr to mem struct to free
  102. **/
  103. int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
  104. {
  105. struct i40e_pf *pf = (struct i40e_pf *)hw->back;
  106. dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
  107. mem->va = NULL;
  108. mem->pa = 0;
  109. mem->size = 0;
  110. return 0;
  111. }
  112. /**
  113. * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
  114. * @hw: pointer to the HW structure
  115. * @mem: ptr to mem struct to fill out
  116. * @size: size of memory requested
  117. **/
  118. int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
  119. u32 size)
  120. {
  121. mem->size = size;
  122. mem->va = kzalloc(size, GFP_KERNEL);
  123. if (!mem->va)
  124. return -ENOMEM;
  125. return 0;
  126. }
  127. /**
  128. * i40e_free_virt_mem_d - OS specific memory free for shared code
  129. * @hw: pointer to the HW structure
  130. * @mem: ptr to mem struct to free
  131. **/
  132. int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
  133. {
  134. /* it's ok to kfree a NULL pointer */
  135. kfree(mem->va);
  136. mem->va = NULL;
  137. mem->size = 0;
  138. return 0;
  139. }
  140. /**
  141. * i40e_get_lump - find a lump of free generic resource
  142. * @pf: board private structure
  143. * @pile: the pile of resource to search
  144. * @needed: the number of items needed
  145. * @id: an owner id to stick on the items assigned
  146. *
  147. * Returns the base item index of the lump, or negative for error
  148. *
  149. * The search_hint trick and lack of advanced fit-finding only work
  150. * because we're highly likely to have all the same size lump requests.
  151. * Linear search time and any fragmentation should be minimal.
  152. **/
  153. static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
  154. u16 needed, u16 id)
  155. {
  156. int ret = -ENOMEM;
  157. int i, j;
  158. if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
  159. dev_info(&pf->pdev->dev,
  160. "param err: pile=%p needed=%d id=0x%04x\n",
  161. pile, needed, id);
  162. return -EINVAL;
  163. }
  164. /* start the linear search with an imperfect hint */
  165. i = pile->search_hint;
  166. while (i < pile->num_entries) {
  167. /* skip already allocated entries */
  168. if (pile->list[i] & I40E_PILE_VALID_BIT) {
  169. i++;
  170. continue;
  171. }
  172. /* do we have enough in this lump? */
  173. for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
  174. if (pile->list[i+j] & I40E_PILE_VALID_BIT)
  175. break;
  176. }
  177. if (j == needed) {
  178. /* there was enough, so assign it to the requestor */
  179. for (j = 0; j < needed; j++)
  180. pile->list[i+j] = id | I40E_PILE_VALID_BIT;
  181. ret = i;
  182. pile->search_hint = i + j;
  183. break;
  184. } else {
  185. /* not enough, so skip over it and continue looking */
  186. i += j;
  187. }
  188. }
  189. return ret;
  190. }
  191. /**
  192. * i40e_put_lump - return a lump of generic resource
  193. * @pile: the pile of resource to search
  194. * @index: the base item index
  195. * @id: the owner id of the items assigned
  196. *
  197. * Returns the count of items in the lump
  198. **/
  199. static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
  200. {
  201. int valid_id = (id | I40E_PILE_VALID_BIT);
  202. int count = 0;
  203. int i;
  204. if (!pile || index >= pile->num_entries)
  205. return -EINVAL;
  206. for (i = index;
  207. i < pile->num_entries && pile->list[i] == valid_id;
  208. i++) {
  209. pile->list[i] = 0;
  210. count++;
  211. }
  212. if (count && index < pile->search_hint)
  213. pile->search_hint = index;
  214. return count;
  215. }
  216. /**
  217. * i40e_service_event_schedule - Schedule the service task to wake up
  218. * @pf: board private structure
  219. *
  220. * If not already scheduled, this puts the task into the work queue
  221. **/
  222. static void i40e_service_event_schedule(struct i40e_pf *pf)
  223. {
  224. if (!test_bit(__I40E_DOWN, &pf->state) &&
  225. !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
  226. !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
  227. schedule_work(&pf->service_task);
  228. }
  229. /**
  230. * i40e_tx_timeout - Respond to a Tx Hang
  231. * @netdev: network interface device structure
  232. *
  233. * If any port has noticed a Tx timeout, it is likely that the whole
  234. * device is munged, not just the one netdev port, so go for the full
  235. * reset.
  236. **/
  237. static void i40e_tx_timeout(struct net_device *netdev)
  238. {
  239. struct i40e_netdev_priv *np = netdev_priv(netdev);
  240. struct i40e_vsi *vsi = np->vsi;
  241. struct i40e_pf *pf = vsi->back;
  242. pf->tx_timeout_count++;
  243. if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
  244. pf->tx_timeout_recovery_level = 0;
  245. pf->tx_timeout_last_recovery = jiffies;
  246. netdev_info(netdev, "tx_timeout recovery level %d\n",
  247. pf->tx_timeout_recovery_level);
  248. switch (pf->tx_timeout_recovery_level) {
  249. case 0:
  250. /* disable and re-enable queues for the VSI */
  251. if (in_interrupt()) {
  252. set_bit(__I40E_REINIT_REQUESTED, &pf->state);
  253. set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
  254. } else {
  255. i40e_vsi_reinit_locked(vsi);
  256. }
  257. break;
  258. case 1:
  259. set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
  260. break;
  261. case 2:
  262. set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
  263. break;
  264. case 3:
  265. set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
  266. break;
  267. default:
  268. netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
  269. i40e_down(vsi);
  270. break;
  271. }
  272. i40e_service_event_schedule(pf);
  273. pf->tx_timeout_recovery_level++;
  274. }
  275. /**
  276. * i40e_release_rx_desc - Store the new tail and head values
  277. * @rx_ring: ring to bump
  278. * @val: new head index
  279. **/
  280. static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
  281. {
  282. rx_ring->next_to_use = val;
  283. /* Force memory writes to complete before letting h/w
  284. * know there are new descriptors to fetch. (Only
  285. * applicable for weak-ordered memory model archs,
  286. * such as IA-64).
  287. */
  288. wmb();
  289. writel(val, rx_ring->tail);
  290. }
  291. /**
  292. * i40e_get_vsi_stats_struct - Get System Network Statistics
  293. * @vsi: the VSI we care about
  294. *
  295. * Returns the address of the device statistics structure.
  296. * The statistics are actually updated from the service task.
  297. **/
  298. struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
  299. {
  300. return &vsi->net_stats;
  301. }
  302. /**
  303. * i40e_get_netdev_stats_struct - Get statistics for netdev interface
  304. * @netdev: network interface device structure
  305. *
  306. * Returns the address of the device statistics structure.
  307. * The statistics are actually updated from the service task.
  308. **/
  309. static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
  310. struct net_device *netdev,
  311. struct rtnl_link_stats64 *storage)
  312. {
  313. struct i40e_netdev_priv *np = netdev_priv(netdev);
  314. struct i40e_vsi *vsi = np->vsi;
  315. *storage = *i40e_get_vsi_stats_struct(vsi);
  316. return storage;
  317. }
  318. /**
  319. * i40e_vsi_reset_stats - Resets all stats of the given vsi
  320. * @vsi: the VSI to have its stats reset
  321. **/
  322. void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
  323. {
  324. struct rtnl_link_stats64 *ns;
  325. int i;
  326. if (!vsi)
  327. return;
  328. ns = i40e_get_vsi_stats_struct(vsi);
  329. memset(ns, 0, sizeof(*ns));
  330. memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
  331. memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
  332. memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
  333. if (vsi->rx_rings)
  334. for (i = 0; i < vsi->num_queue_pairs; i++) {
  335. memset(&vsi->rx_rings[i].stats, 0 ,
  336. sizeof(vsi->rx_rings[i].stats));
  337. memset(&vsi->rx_rings[i].rx_stats, 0 ,
  338. sizeof(vsi->rx_rings[i].rx_stats));
  339. memset(&vsi->tx_rings[i].stats, 0 ,
  340. sizeof(vsi->tx_rings[i].stats));
  341. memset(&vsi->tx_rings[i].tx_stats, 0,
  342. sizeof(vsi->tx_rings[i].tx_stats));
  343. }
  344. vsi->stat_offsets_loaded = false;
  345. }
  346. /**
  347. * i40e_pf_reset_stats - Reset all of the stats for the given pf
  348. * @pf: the PF to be reset
  349. **/
  350. void i40e_pf_reset_stats(struct i40e_pf *pf)
  351. {
  352. memset(&pf->stats, 0, sizeof(pf->stats));
  353. memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
  354. pf->stat_offsets_loaded = false;
  355. }
  356. /**
  357. * i40e_stat_update48 - read and update a 48 bit stat from the chip
  358. * @hw: ptr to the hardware info
  359. * @hireg: the high 32 bit reg to read
  360. * @loreg: the low 32 bit reg to read
  361. * @offset_loaded: has the initial offset been loaded yet
  362. * @offset: ptr to current offset value
  363. * @stat: ptr to the stat
  364. *
  365. * Since the device stats are not reset at PFReset, they likely will not
  366. * be zeroed when the driver starts. We'll save the first values read
  367. * and use them as offsets to be subtracted from the raw values in order
  368. * to report stats that count from zero. In the process, we also manage
  369. * the potential roll-over.
  370. **/
  371. static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
  372. bool offset_loaded, u64 *offset, u64 *stat)
  373. {
  374. u64 new_data;
  375. if (hw->device_id == I40E_QEMU_DEVICE_ID) {
  376. new_data = rd32(hw, loreg);
  377. new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
  378. } else {
  379. new_data = rd64(hw, loreg);
  380. }
  381. if (!offset_loaded)
  382. *offset = new_data;
  383. if (likely(new_data >= *offset))
  384. *stat = new_data - *offset;
  385. else
  386. *stat = (new_data + ((u64)1 << 48)) - *offset;
  387. *stat &= 0xFFFFFFFFFFFFULL;
  388. }
  389. /**
  390. * i40e_stat_update32 - read and update a 32 bit stat from the chip
  391. * @hw: ptr to the hardware info
  392. * @reg: the hw reg to read
  393. * @offset_loaded: has the initial offset been loaded yet
  394. * @offset: ptr to current offset value
  395. * @stat: ptr to the stat
  396. **/
  397. static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
  398. bool offset_loaded, u64 *offset, u64 *stat)
  399. {
  400. u32 new_data;
  401. new_data = rd32(hw, reg);
  402. if (!offset_loaded)
  403. *offset = new_data;
  404. if (likely(new_data >= *offset))
  405. *stat = (u32)(new_data - *offset);
  406. else
  407. *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
  408. }
  409. /**
  410. * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
  411. * @vsi: the VSI to be updated
  412. **/
  413. void i40e_update_eth_stats(struct i40e_vsi *vsi)
  414. {
  415. int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
  416. struct i40e_pf *pf = vsi->back;
  417. struct i40e_hw *hw = &pf->hw;
  418. struct i40e_eth_stats *oes;
  419. struct i40e_eth_stats *es; /* device's eth stats */
  420. es = &vsi->eth_stats;
  421. oes = &vsi->eth_stats_offsets;
  422. /* Gather up the stats that the hw collects */
  423. i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
  424. vsi->stat_offsets_loaded,
  425. &oes->tx_errors, &es->tx_errors);
  426. i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
  427. vsi->stat_offsets_loaded,
  428. &oes->rx_discards, &es->rx_discards);
  429. i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
  430. I40E_GLV_GORCL(stat_idx),
  431. vsi->stat_offsets_loaded,
  432. &oes->rx_bytes, &es->rx_bytes);
  433. i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
  434. I40E_GLV_UPRCL(stat_idx),
  435. vsi->stat_offsets_loaded,
  436. &oes->rx_unicast, &es->rx_unicast);
  437. i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
  438. I40E_GLV_MPRCL(stat_idx),
  439. vsi->stat_offsets_loaded,
  440. &oes->rx_multicast, &es->rx_multicast);
  441. i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
  442. I40E_GLV_BPRCL(stat_idx),
  443. vsi->stat_offsets_loaded,
  444. &oes->rx_broadcast, &es->rx_broadcast);
  445. i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
  446. I40E_GLV_GOTCL(stat_idx),
  447. vsi->stat_offsets_loaded,
  448. &oes->tx_bytes, &es->tx_bytes);
  449. i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
  450. I40E_GLV_UPTCL(stat_idx),
  451. vsi->stat_offsets_loaded,
  452. &oes->tx_unicast, &es->tx_unicast);
  453. i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
  454. I40E_GLV_MPTCL(stat_idx),
  455. vsi->stat_offsets_loaded,
  456. &oes->tx_multicast, &es->tx_multicast);
  457. i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
  458. I40E_GLV_BPTCL(stat_idx),
  459. vsi->stat_offsets_loaded,
  460. &oes->tx_broadcast, &es->tx_broadcast);
  461. vsi->stat_offsets_loaded = true;
  462. }
  463. /**
  464. * i40e_update_veb_stats - Update Switch component statistics
  465. * @veb: the VEB being updated
  466. **/
  467. static void i40e_update_veb_stats(struct i40e_veb *veb)
  468. {
  469. struct i40e_pf *pf = veb->pf;
  470. struct i40e_hw *hw = &pf->hw;
  471. struct i40e_eth_stats *oes;
  472. struct i40e_eth_stats *es; /* device's eth stats */
  473. int idx = 0;
  474. idx = veb->stats_idx;
  475. es = &veb->stats;
  476. oes = &veb->stats_offsets;
  477. /* Gather up the stats that the hw collects */
  478. i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
  479. veb->stat_offsets_loaded,
  480. &oes->tx_discards, &es->tx_discards);
  481. i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
  482. veb->stat_offsets_loaded,
  483. &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
  484. i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
  485. veb->stat_offsets_loaded,
  486. &oes->rx_bytes, &es->rx_bytes);
  487. i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
  488. veb->stat_offsets_loaded,
  489. &oes->rx_unicast, &es->rx_unicast);
  490. i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
  491. veb->stat_offsets_loaded,
  492. &oes->rx_multicast, &es->rx_multicast);
  493. i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
  494. veb->stat_offsets_loaded,
  495. &oes->rx_broadcast, &es->rx_broadcast);
  496. i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
  497. veb->stat_offsets_loaded,
  498. &oes->tx_bytes, &es->tx_bytes);
  499. i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
  500. veb->stat_offsets_loaded,
  501. &oes->tx_unicast, &es->tx_unicast);
  502. i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
  503. veb->stat_offsets_loaded,
  504. &oes->tx_multicast, &es->tx_multicast);
  505. i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
  506. veb->stat_offsets_loaded,
  507. &oes->tx_broadcast, &es->tx_broadcast);
  508. veb->stat_offsets_loaded = true;
  509. }
  510. /**
  511. * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
  512. * @pf: the corresponding PF
  513. *
  514. * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
  515. **/
  516. static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
  517. {
  518. struct i40e_hw_port_stats *osd = &pf->stats_offsets;
  519. struct i40e_hw_port_stats *nsd = &pf->stats;
  520. struct i40e_hw *hw = &pf->hw;
  521. u64 xoff = 0;
  522. u16 i, v;
  523. if ((hw->fc.current_mode != I40E_FC_FULL) &&
  524. (hw->fc.current_mode != I40E_FC_RX_PAUSE))
  525. return;
  526. xoff = nsd->link_xoff_rx;
  527. i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
  528. pf->stat_offsets_loaded,
  529. &osd->link_xoff_rx, &nsd->link_xoff_rx);
  530. /* No new LFC xoff rx */
  531. if (!(nsd->link_xoff_rx - xoff))
  532. return;
  533. /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
  534. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  535. struct i40e_vsi *vsi = pf->vsi[v];
  536. if (!vsi)
  537. continue;
  538. for (i = 0; i < vsi->num_queue_pairs; i++) {
  539. struct i40e_ring *ring = &vsi->tx_rings[i];
  540. clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
  541. }
  542. }
  543. }
  544. /**
  545. * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
  546. * @pf: the corresponding PF
  547. *
  548. * Update the Rx XOFF counter (PAUSE frames) in PFC mode
  549. **/
  550. static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
  551. {
  552. struct i40e_hw_port_stats *osd = &pf->stats_offsets;
  553. struct i40e_hw_port_stats *nsd = &pf->stats;
  554. bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
  555. struct i40e_dcbx_config *dcb_cfg;
  556. struct i40e_hw *hw = &pf->hw;
  557. u16 i, v;
  558. u8 tc;
  559. dcb_cfg = &hw->local_dcbx_config;
  560. /* See if DCB enabled with PFC TC */
  561. if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
  562. !(dcb_cfg->pfc.pfcenable)) {
  563. i40e_update_link_xoff_rx(pf);
  564. return;
  565. }
  566. for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
  567. u64 prio_xoff = nsd->priority_xoff_rx[i];
  568. i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
  569. pf->stat_offsets_loaded,
  570. &osd->priority_xoff_rx[i],
  571. &nsd->priority_xoff_rx[i]);
  572. /* No new PFC xoff rx */
  573. if (!(nsd->priority_xoff_rx[i] - prio_xoff))
  574. continue;
  575. /* Get the TC for given priority */
  576. tc = dcb_cfg->etscfg.prioritytable[i];
  577. xoff[tc] = true;
  578. }
  579. /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
  580. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  581. struct i40e_vsi *vsi = pf->vsi[v];
  582. if (!vsi)
  583. continue;
  584. for (i = 0; i < vsi->num_queue_pairs; i++) {
  585. struct i40e_ring *ring = &vsi->tx_rings[i];
  586. tc = ring->dcb_tc;
  587. if (xoff[tc])
  588. clear_bit(__I40E_HANG_CHECK_ARMED,
  589. &ring->state);
  590. }
  591. }
  592. }
  593. /**
  594. * i40e_update_stats - Update the board statistics counters.
  595. * @vsi: the VSI to be updated
  596. *
  597. * There are a few instances where we store the same stat in a
  598. * couple of different structs. This is partly because we have
  599. * the netdev stats that need to be filled out, which is slightly
  600. * different from the "eth_stats" defined by the chip and used in
  601. * VF communications. We sort it all out here in a central place.
  602. **/
  603. void i40e_update_stats(struct i40e_vsi *vsi)
  604. {
  605. struct i40e_pf *pf = vsi->back;
  606. struct i40e_hw *hw = &pf->hw;
  607. struct rtnl_link_stats64 *ons;
  608. struct rtnl_link_stats64 *ns; /* netdev stats */
  609. struct i40e_eth_stats *oes;
  610. struct i40e_eth_stats *es; /* device's eth stats */
  611. u32 tx_restart, tx_busy;
  612. u32 rx_page, rx_buf;
  613. u64 rx_p, rx_b;
  614. u64 tx_p, tx_b;
  615. int i;
  616. u16 q;
  617. if (test_bit(__I40E_DOWN, &vsi->state) ||
  618. test_bit(__I40E_CONFIG_BUSY, &pf->state))
  619. return;
  620. ns = i40e_get_vsi_stats_struct(vsi);
  621. ons = &vsi->net_stats_offsets;
  622. es = &vsi->eth_stats;
  623. oes = &vsi->eth_stats_offsets;
  624. /* Gather up the netdev and vsi stats that the driver collects
  625. * on the fly during packet processing
  626. */
  627. rx_b = rx_p = 0;
  628. tx_b = tx_p = 0;
  629. tx_restart = tx_busy = 0;
  630. rx_page = 0;
  631. rx_buf = 0;
  632. for (q = 0; q < vsi->num_queue_pairs; q++) {
  633. struct i40e_ring *p;
  634. p = &vsi->rx_rings[q];
  635. rx_b += p->stats.bytes;
  636. rx_p += p->stats.packets;
  637. rx_buf += p->rx_stats.alloc_rx_buff_failed;
  638. rx_page += p->rx_stats.alloc_rx_page_failed;
  639. p = &vsi->tx_rings[q];
  640. tx_b += p->stats.bytes;
  641. tx_p += p->stats.packets;
  642. tx_restart += p->tx_stats.restart_queue;
  643. tx_busy += p->tx_stats.tx_busy;
  644. }
  645. vsi->tx_restart = tx_restart;
  646. vsi->tx_busy = tx_busy;
  647. vsi->rx_page_failed = rx_page;
  648. vsi->rx_buf_failed = rx_buf;
  649. ns->rx_packets = rx_p;
  650. ns->rx_bytes = rx_b;
  651. ns->tx_packets = tx_p;
  652. ns->tx_bytes = tx_b;
  653. i40e_update_eth_stats(vsi);
  654. /* update netdev stats from eth stats */
  655. ons->rx_errors = oes->rx_errors;
  656. ns->rx_errors = es->rx_errors;
  657. ons->tx_errors = oes->tx_errors;
  658. ns->tx_errors = es->tx_errors;
  659. ons->multicast = oes->rx_multicast;
  660. ns->multicast = es->rx_multicast;
  661. ons->tx_dropped = oes->tx_discards;
  662. ns->tx_dropped = es->tx_discards;
  663. /* Get the port data only if this is the main PF VSI */
  664. if (vsi == pf->vsi[pf->lan_vsi]) {
  665. struct i40e_hw_port_stats *nsd = &pf->stats;
  666. struct i40e_hw_port_stats *osd = &pf->stats_offsets;
  667. i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
  668. I40E_GLPRT_GORCL(hw->port),
  669. pf->stat_offsets_loaded,
  670. &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
  671. i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
  672. I40E_GLPRT_GOTCL(hw->port),
  673. pf->stat_offsets_loaded,
  674. &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
  675. i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
  676. pf->stat_offsets_loaded,
  677. &osd->eth.rx_discards,
  678. &nsd->eth.rx_discards);
  679. i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
  680. pf->stat_offsets_loaded,
  681. &osd->eth.tx_discards,
  682. &nsd->eth.tx_discards);
  683. i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
  684. I40E_GLPRT_MPRCL(hw->port),
  685. pf->stat_offsets_loaded,
  686. &osd->eth.rx_multicast,
  687. &nsd->eth.rx_multicast);
  688. i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
  689. pf->stat_offsets_loaded,
  690. &osd->tx_dropped_link_down,
  691. &nsd->tx_dropped_link_down);
  692. i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
  693. pf->stat_offsets_loaded,
  694. &osd->crc_errors, &nsd->crc_errors);
  695. ns->rx_crc_errors = nsd->crc_errors;
  696. i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
  697. pf->stat_offsets_loaded,
  698. &osd->illegal_bytes, &nsd->illegal_bytes);
  699. ns->rx_errors = nsd->crc_errors
  700. + nsd->illegal_bytes;
  701. i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
  702. pf->stat_offsets_loaded,
  703. &osd->mac_local_faults,
  704. &nsd->mac_local_faults);
  705. i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
  706. pf->stat_offsets_loaded,
  707. &osd->mac_remote_faults,
  708. &nsd->mac_remote_faults);
  709. i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
  710. pf->stat_offsets_loaded,
  711. &osd->rx_length_errors,
  712. &nsd->rx_length_errors);
  713. ns->rx_length_errors = nsd->rx_length_errors;
  714. i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
  715. pf->stat_offsets_loaded,
  716. &osd->link_xon_rx, &nsd->link_xon_rx);
  717. i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
  718. pf->stat_offsets_loaded,
  719. &osd->link_xon_tx, &nsd->link_xon_tx);
  720. i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
  721. i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
  722. pf->stat_offsets_loaded,
  723. &osd->link_xoff_tx, &nsd->link_xoff_tx);
  724. for (i = 0; i < 8; i++) {
  725. i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
  726. pf->stat_offsets_loaded,
  727. &osd->priority_xon_rx[i],
  728. &nsd->priority_xon_rx[i]);
  729. i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
  730. pf->stat_offsets_loaded,
  731. &osd->priority_xon_tx[i],
  732. &nsd->priority_xon_tx[i]);
  733. i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
  734. pf->stat_offsets_loaded,
  735. &osd->priority_xoff_tx[i],
  736. &nsd->priority_xoff_tx[i]);
  737. i40e_stat_update32(hw,
  738. I40E_GLPRT_RXON2OFFCNT(hw->port, i),
  739. pf->stat_offsets_loaded,
  740. &osd->priority_xon_2_xoff[i],
  741. &nsd->priority_xon_2_xoff[i]);
  742. }
  743. i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
  744. I40E_GLPRT_PRC64L(hw->port),
  745. pf->stat_offsets_loaded,
  746. &osd->rx_size_64, &nsd->rx_size_64);
  747. i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
  748. I40E_GLPRT_PRC127L(hw->port),
  749. pf->stat_offsets_loaded,
  750. &osd->rx_size_127, &nsd->rx_size_127);
  751. i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
  752. I40E_GLPRT_PRC255L(hw->port),
  753. pf->stat_offsets_loaded,
  754. &osd->rx_size_255, &nsd->rx_size_255);
  755. i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
  756. I40E_GLPRT_PRC511L(hw->port),
  757. pf->stat_offsets_loaded,
  758. &osd->rx_size_511, &nsd->rx_size_511);
  759. i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
  760. I40E_GLPRT_PRC1023L(hw->port),
  761. pf->stat_offsets_loaded,
  762. &osd->rx_size_1023, &nsd->rx_size_1023);
  763. i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
  764. I40E_GLPRT_PRC1522L(hw->port),
  765. pf->stat_offsets_loaded,
  766. &osd->rx_size_1522, &nsd->rx_size_1522);
  767. i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
  768. I40E_GLPRT_PRC9522L(hw->port),
  769. pf->stat_offsets_loaded,
  770. &osd->rx_size_big, &nsd->rx_size_big);
  771. i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
  772. I40E_GLPRT_PTC64L(hw->port),
  773. pf->stat_offsets_loaded,
  774. &osd->tx_size_64, &nsd->tx_size_64);
  775. i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
  776. I40E_GLPRT_PTC127L(hw->port),
  777. pf->stat_offsets_loaded,
  778. &osd->tx_size_127, &nsd->tx_size_127);
  779. i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
  780. I40E_GLPRT_PTC255L(hw->port),
  781. pf->stat_offsets_loaded,
  782. &osd->tx_size_255, &nsd->tx_size_255);
  783. i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
  784. I40E_GLPRT_PTC511L(hw->port),
  785. pf->stat_offsets_loaded,
  786. &osd->tx_size_511, &nsd->tx_size_511);
  787. i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
  788. I40E_GLPRT_PTC1023L(hw->port),
  789. pf->stat_offsets_loaded,
  790. &osd->tx_size_1023, &nsd->tx_size_1023);
  791. i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
  792. I40E_GLPRT_PTC1522L(hw->port),
  793. pf->stat_offsets_loaded,
  794. &osd->tx_size_1522, &nsd->tx_size_1522);
  795. i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
  796. I40E_GLPRT_PTC9522L(hw->port),
  797. pf->stat_offsets_loaded,
  798. &osd->tx_size_big, &nsd->tx_size_big);
  799. i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
  800. pf->stat_offsets_loaded,
  801. &osd->rx_undersize, &nsd->rx_undersize);
  802. i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
  803. pf->stat_offsets_loaded,
  804. &osd->rx_fragments, &nsd->rx_fragments);
  805. i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
  806. pf->stat_offsets_loaded,
  807. &osd->rx_oversize, &nsd->rx_oversize);
  808. i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
  809. pf->stat_offsets_loaded,
  810. &osd->rx_jabber, &nsd->rx_jabber);
  811. }
  812. pf->stat_offsets_loaded = true;
  813. }
  814. /**
  815. * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
  816. * @vsi: the VSI to be searched
  817. * @macaddr: the MAC address
  818. * @vlan: the vlan
  819. * @is_vf: make sure its a vf filter, else doesn't matter
  820. * @is_netdev: make sure its a netdev filter, else doesn't matter
  821. *
  822. * Returns ptr to the filter object or NULL
  823. **/
  824. static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
  825. u8 *macaddr, s16 vlan,
  826. bool is_vf, bool is_netdev)
  827. {
  828. struct i40e_mac_filter *f;
  829. if (!vsi || !macaddr)
  830. return NULL;
  831. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  832. if ((ether_addr_equal(macaddr, f->macaddr)) &&
  833. (vlan == f->vlan) &&
  834. (!is_vf || f->is_vf) &&
  835. (!is_netdev || f->is_netdev))
  836. return f;
  837. }
  838. return NULL;
  839. }
  840. /**
  841. * i40e_find_mac - Find a mac addr in the macvlan filters list
  842. * @vsi: the VSI to be searched
  843. * @macaddr: the MAC address we are searching for
  844. * @is_vf: make sure its a vf filter, else doesn't matter
  845. * @is_netdev: make sure its a netdev filter, else doesn't matter
  846. *
  847. * Returns the first filter with the provided MAC address or NULL if
  848. * MAC address was not found
  849. **/
  850. struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
  851. bool is_vf, bool is_netdev)
  852. {
  853. struct i40e_mac_filter *f;
  854. if (!vsi || !macaddr)
  855. return NULL;
  856. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  857. if ((ether_addr_equal(macaddr, f->macaddr)) &&
  858. (!is_vf || f->is_vf) &&
  859. (!is_netdev || f->is_netdev))
  860. return f;
  861. }
  862. return NULL;
  863. }
  864. /**
  865. * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
  866. * @vsi: the VSI to be searched
  867. *
  868. * Returns true if VSI is in vlan mode or false otherwise
  869. **/
  870. bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
  871. {
  872. struct i40e_mac_filter *f;
  873. /* Only -1 for all the filters denotes not in vlan mode
  874. * so we have to go through all the list in order to make sure
  875. */
  876. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  877. if (f->vlan >= 0)
  878. return true;
  879. }
  880. return false;
  881. }
  882. /**
  883. * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
  884. * @vsi: the VSI to be searched
  885. * @macaddr: the mac address to be filtered
  886. * @is_vf: true if it is a vf
  887. * @is_netdev: true if it is a netdev
  888. *
  889. * Goes through all the macvlan filters and adds a
  890. * macvlan filter for each unique vlan that already exists
  891. *
  892. * Returns first filter found on success, else NULL
  893. **/
  894. struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
  895. bool is_vf, bool is_netdev)
  896. {
  897. struct i40e_mac_filter *f;
  898. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  899. if (!i40e_find_filter(vsi, macaddr, f->vlan,
  900. is_vf, is_netdev)) {
  901. if (!i40e_add_filter(vsi, macaddr, f->vlan,
  902. is_vf, is_netdev))
  903. return NULL;
  904. }
  905. }
  906. return list_first_entry_or_null(&vsi->mac_filter_list,
  907. struct i40e_mac_filter, list);
  908. }
  909. /**
  910. * i40e_add_filter - Add a mac/vlan filter to the VSI
  911. * @vsi: the VSI to be searched
  912. * @macaddr: the MAC address
  913. * @vlan: the vlan
  914. * @is_vf: make sure its a vf filter, else doesn't matter
  915. * @is_netdev: make sure its a netdev filter, else doesn't matter
  916. *
  917. * Returns ptr to the filter object or NULL when no memory available.
  918. **/
  919. struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
  920. u8 *macaddr, s16 vlan,
  921. bool is_vf, bool is_netdev)
  922. {
  923. struct i40e_mac_filter *f;
  924. if (!vsi || !macaddr)
  925. return NULL;
  926. f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
  927. if (!f) {
  928. f = kzalloc(sizeof(*f), GFP_ATOMIC);
  929. if (!f)
  930. goto add_filter_out;
  931. memcpy(f->macaddr, macaddr, ETH_ALEN);
  932. f->vlan = vlan;
  933. f->changed = true;
  934. INIT_LIST_HEAD(&f->list);
  935. list_add(&f->list, &vsi->mac_filter_list);
  936. }
  937. /* increment counter and add a new flag if needed */
  938. if (is_vf) {
  939. if (!f->is_vf) {
  940. f->is_vf = true;
  941. f->counter++;
  942. }
  943. } else if (is_netdev) {
  944. if (!f->is_netdev) {
  945. f->is_netdev = true;
  946. f->counter++;
  947. }
  948. } else {
  949. f->counter++;
  950. }
  951. /* changed tells sync_filters_subtask to
  952. * push the filter down to the firmware
  953. */
  954. if (f->changed) {
  955. vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
  956. vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
  957. }
  958. add_filter_out:
  959. return f;
  960. }
  961. /**
  962. * i40e_del_filter - Remove a mac/vlan filter from the VSI
  963. * @vsi: the VSI to be searched
  964. * @macaddr: the MAC address
  965. * @vlan: the vlan
  966. * @is_vf: make sure it's a vf filter, else doesn't matter
  967. * @is_netdev: make sure it's a netdev filter, else doesn't matter
  968. **/
  969. void i40e_del_filter(struct i40e_vsi *vsi,
  970. u8 *macaddr, s16 vlan,
  971. bool is_vf, bool is_netdev)
  972. {
  973. struct i40e_mac_filter *f;
  974. if (!vsi || !macaddr)
  975. return;
  976. f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
  977. if (!f || f->counter == 0)
  978. return;
  979. if (is_vf) {
  980. if (f->is_vf) {
  981. f->is_vf = false;
  982. f->counter--;
  983. }
  984. } else if (is_netdev) {
  985. if (f->is_netdev) {
  986. f->is_netdev = false;
  987. f->counter--;
  988. }
  989. } else {
  990. /* make sure we don't remove a filter in use by vf or netdev */
  991. int min_f = 0;
  992. min_f += (f->is_vf ? 1 : 0);
  993. min_f += (f->is_netdev ? 1 : 0);
  994. if (f->counter > min_f)
  995. f->counter--;
  996. }
  997. /* counter == 0 tells sync_filters_subtask to
  998. * remove the filter from the firmware's list
  999. */
  1000. if (f->counter == 0) {
  1001. f->changed = true;
  1002. vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
  1003. vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
  1004. }
  1005. }
  1006. /**
  1007. * i40e_set_mac - NDO callback to set mac address
  1008. * @netdev: network interface device structure
  1009. * @p: pointer to an address structure
  1010. *
  1011. * Returns 0 on success, negative on failure
  1012. **/
  1013. static int i40e_set_mac(struct net_device *netdev, void *p)
  1014. {
  1015. struct i40e_netdev_priv *np = netdev_priv(netdev);
  1016. struct i40e_vsi *vsi = np->vsi;
  1017. struct sockaddr *addr = p;
  1018. struct i40e_mac_filter *f;
  1019. if (!is_valid_ether_addr(addr->sa_data))
  1020. return -EADDRNOTAVAIL;
  1021. netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
  1022. if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
  1023. return 0;
  1024. if (vsi->type == I40E_VSI_MAIN) {
  1025. i40e_status ret;
  1026. ret = i40e_aq_mac_address_write(&vsi->back->hw,
  1027. I40E_AQC_WRITE_TYPE_LAA_ONLY,
  1028. addr->sa_data, NULL);
  1029. if (ret) {
  1030. netdev_info(netdev,
  1031. "Addr change for Main VSI failed: %d\n",
  1032. ret);
  1033. return -EADDRNOTAVAIL;
  1034. }
  1035. memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
  1036. }
  1037. /* In order to be sure to not drop any packets, add the new address
  1038. * then delete the old one.
  1039. */
  1040. f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
  1041. if (!f)
  1042. return -ENOMEM;
  1043. i40e_sync_vsi_filters(vsi);
  1044. i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
  1045. i40e_sync_vsi_filters(vsi);
  1046. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  1047. return 0;
  1048. }
  1049. /**
  1050. * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
  1051. * @vsi: the VSI being setup
  1052. * @ctxt: VSI context structure
  1053. * @enabled_tc: Enabled TCs bitmap
  1054. * @is_add: True if called before Add VSI
  1055. *
  1056. * Setup VSI queue mapping for enabled traffic classes.
  1057. **/
  1058. static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
  1059. struct i40e_vsi_context *ctxt,
  1060. u8 enabled_tc,
  1061. bool is_add)
  1062. {
  1063. struct i40e_pf *pf = vsi->back;
  1064. u16 sections = 0;
  1065. u8 netdev_tc = 0;
  1066. u16 numtc = 0;
  1067. u16 qcount;
  1068. u8 offset;
  1069. u16 qmap;
  1070. int i;
  1071. sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
  1072. offset = 0;
  1073. if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
  1074. /* Find numtc from enabled TC bitmap */
  1075. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  1076. if (enabled_tc & (1 << i)) /* TC is enabled */
  1077. numtc++;
  1078. }
  1079. if (!numtc) {
  1080. dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
  1081. numtc = 1;
  1082. }
  1083. } else {
  1084. /* At least TC0 is enabled in case of non-DCB case */
  1085. numtc = 1;
  1086. }
  1087. vsi->tc_config.numtc = numtc;
  1088. vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
  1089. /* Setup queue offset/count for all TCs for given VSI */
  1090. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  1091. /* See if the given TC is enabled for the given VSI */
  1092. if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
  1093. int pow, num_qps;
  1094. vsi->tc_config.tc_info[i].qoffset = offset;
  1095. switch (vsi->type) {
  1096. case I40E_VSI_MAIN:
  1097. if (i == 0)
  1098. qcount = pf->rss_size;
  1099. else
  1100. qcount = pf->num_tc_qps;
  1101. vsi->tc_config.tc_info[i].qcount = qcount;
  1102. break;
  1103. case I40E_VSI_FDIR:
  1104. case I40E_VSI_SRIOV:
  1105. case I40E_VSI_VMDQ2:
  1106. default:
  1107. qcount = vsi->alloc_queue_pairs;
  1108. vsi->tc_config.tc_info[i].qcount = qcount;
  1109. WARN_ON(i != 0);
  1110. break;
  1111. }
  1112. /* find the power-of-2 of the number of queue pairs */
  1113. num_qps = vsi->tc_config.tc_info[i].qcount;
  1114. pow = 0;
  1115. while (num_qps &&
  1116. ((1 << pow) < vsi->tc_config.tc_info[i].qcount)) {
  1117. pow++;
  1118. num_qps >>= 1;
  1119. }
  1120. vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
  1121. qmap =
  1122. (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
  1123. (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
  1124. offset += vsi->tc_config.tc_info[i].qcount;
  1125. } else {
  1126. /* TC is not enabled so set the offset to
  1127. * default queue and allocate one queue
  1128. * for the given TC.
  1129. */
  1130. vsi->tc_config.tc_info[i].qoffset = 0;
  1131. vsi->tc_config.tc_info[i].qcount = 1;
  1132. vsi->tc_config.tc_info[i].netdev_tc = 0;
  1133. qmap = 0;
  1134. }
  1135. ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
  1136. }
  1137. /* Set actual Tx/Rx queue pairs */
  1138. vsi->num_queue_pairs = offset;
  1139. /* Scheduler section valid can only be set for ADD VSI */
  1140. if (is_add) {
  1141. sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
  1142. ctxt->info.up_enable_bits = enabled_tc;
  1143. }
  1144. if (vsi->type == I40E_VSI_SRIOV) {
  1145. ctxt->info.mapping_flags |=
  1146. cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
  1147. for (i = 0; i < vsi->num_queue_pairs; i++)
  1148. ctxt->info.queue_mapping[i] =
  1149. cpu_to_le16(vsi->base_queue + i);
  1150. } else {
  1151. ctxt->info.mapping_flags |=
  1152. cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
  1153. ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
  1154. }
  1155. ctxt->info.valid_sections |= cpu_to_le16(sections);
  1156. }
  1157. /**
  1158. * i40e_set_rx_mode - NDO callback to set the netdev filters
  1159. * @netdev: network interface device structure
  1160. **/
  1161. static void i40e_set_rx_mode(struct net_device *netdev)
  1162. {
  1163. struct i40e_netdev_priv *np = netdev_priv(netdev);
  1164. struct i40e_mac_filter *f, *ftmp;
  1165. struct i40e_vsi *vsi = np->vsi;
  1166. struct netdev_hw_addr *uca;
  1167. struct netdev_hw_addr *mca;
  1168. struct netdev_hw_addr *ha;
  1169. /* add addr if not already in the filter list */
  1170. netdev_for_each_uc_addr(uca, netdev) {
  1171. if (!i40e_find_mac(vsi, uca->addr, false, true)) {
  1172. if (i40e_is_vsi_in_vlan(vsi))
  1173. i40e_put_mac_in_vlan(vsi, uca->addr,
  1174. false, true);
  1175. else
  1176. i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
  1177. false, true);
  1178. }
  1179. }
  1180. netdev_for_each_mc_addr(mca, netdev) {
  1181. if (!i40e_find_mac(vsi, mca->addr, false, true)) {
  1182. if (i40e_is_vsi_in_vlan(vsi))
  1183. i40e_put_mac_in_vlan(vsi, mca->addr,
  1184. false, true);
  1185. else
  1186. i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
  1187. false, true);
  1188. }
  1189. }
  1190. /* remove filter if not in netdev list */
  1191. list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
  1192. bool found = false;
  1193. if (!f->is_netdev)
  1194. continue;
  1195. if (is_multicast_ether_addr(f->macaddr)) {
  1196. netdev_for_each_mc_addr(mca, netdev) {
  1197. if (ether_addr_equal(mca->addr, f->macaddr)) {
  1198. found = true;
  1199. break;
  1200. }
  1201. }
  1202. } else {
  1203. netdev_for_each_uc_addr(uca, netdev) {
  1204. if (ether_addr_equal(uca->addr, f->macaddr)) {
  1205. found = true;
  1206. break;
  1207. }
  1208. }
  1209. for_each_dev_addr(netdev, ha) {
  1210. if (ether_addr_equal(ha->addr, f->macaddr)) {
  1211. found = true;
  1212. break;
  1213. }
  1214. }
  1215. }
  1216. if (!found)
  1217. i40e_del_filter(
  1218. vsi, f->macaddr, I40E_VLAN_ANY, false, true);
  1219. }
  1220. /* check for other flag changes */
  1221. if (vsi->current_netdev_flags != vsi->netdev->flags) {
  1222. vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
  1223. vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
  1224. }
  1225. }
  1226. /**
  1227. * i40e_sync_vsi_filters - Update the VSI filter list to the HW
  1228. * @vsi: ptr to the VSI
  1229. *
  1230. * Push any outstanding VSI filter changes through the AdminQ.
  1231. *
  1232. * Returns 0 or error value
  1233. **/
  1234. int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
  1235. {
  1236. struct i40e_mac_filter *f, *ftmp;
  1237. bool promisc_forced_on = false;
  1238. bool add_happened = false;
  1239. int filter_list_len = 0;
  1240. u32 changed_flags = 0;
  1241. i40e_status aq_ret = 0;
  1242. struct i40e_pf *pf;
  1243. int num_add = 0;
  1244. int num_del = 0;
  1245. u16 cmd_flags;
  1246. /* empty array typed pointers, kcalloc later */
  1247. struct i40e_aqc_add_macvlan_element_data *add_list;
  1248. struct i40e_aqc_remove_macvlan_element_data *del_list;
  1249. while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
  1250. usleep_range(1000, 2000);
  1251. pf = vsi->back;
  1252. if (vsi->netdev) {
  1253. changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
  1254. vsi->current_netdev_flags = vsi->netdev->flags;
  1255. }
  1256. if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
  1257. vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
  1258. filter_list_len = pf->hw.aq.asq_buf_size /
  1259. sizeof(struct i40e_aqc_remove_macvlan_element_data);
  1260. del_list = kcalloc(filter_list_len,
  1261. sizeof(struct i40e_aqc_remove_macvlan_element_data),
  1262. GFP_KERNEL);
  1263. if (!del_list)
  1264. return -ENOMEM;
  1265. list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
  1266. if (!f->changed)
  1267. continue;
  1268. if (f->counter != 0)
  1269. continue;
  1270. f->changed = false;
  1271. cmd_flags = 0;
  1272. /* add to delete list */
  1273. memcpy(del_list[num_del].mac_addr,
  1274. f->macaddr, ETH_ALEN);
  1275. del_list[num_del].vlan_tag =
  1276. cpu_to_le16((u16)(f->vlan ==
  1277. I40E_VLAN_ANY ? 0 : f->vlan));
  1278. /* vlan0 as wild card to allow packets from all vlans */
  1279. if (f->vlan == I40E_VLAN_ANY ||
  1280. (vsi->netdev && !(vsi->netdev->features &
  1281. NETIF_F_HW_VLAN_CTAG_FILTER)))
  1282. cmd_flags |= I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
  1283. cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
  1284. del_list[num_del].flags = cmd_flags;
  1285. num_del++;
  1286. /* unlink from filter list */
  1287. list_del(&f->list);
  1288. kfree(f);
  1289. /* flush a full buffer */
  1290. if (num_del == filter_list_len) {
  1291. aq_ret = i40e_aq_remove_macvlan(&pf->hw,
  1292. vsi->seid, del_list, num_del,
  1293. NULL);
  1294. num_del = 0;
  1295. memset(del_list, 0, sizeof(*del_list));
  1296. if (aq_ret)
  1297. dev_info(&pf->pdev->dev,
  1298. "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
  1299. aq_ret,
  1300. pf->hw.aq.asq_last_status);
  1301. }
  1302. }
  1303. if (num_del) {
  1304. aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
  1305. del_list, num_del, NULL);
  1306. num_del = 0;
  1307. if (aq_ret)
  1308. dev_info(&pf->pdev->dev,
  1309. "ignoring delete macvlan error, err %d, aq_err %d\n",
  1310. aq_ret, pf->hw.aq.asq_last_status);
  1311. }
  1312. kfree(del_list);
  1313. del_list = NULL;
  1314. /* do all the adds now */
  1315. filter_list_len = pf->hw.aq.asq_buf_size /
  1316. sizeof(struct i40e_aqc_add_macvlan_element_data),
  1317. add_list = kcalloc(filter_list_len,
  1318. sizeof(struct i40e_aqc_add_macvlan_element_data),
  1319. GFP_KERNEL);
  1320. if (!add_list)
  1321. return -ENOMEM;
  1322. list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
  1323. if (!f->changed)
  1324. continue;
  1325. if (f->counter == 0)
  1326. continue;
  1327. f->changed = false;
  1328. add_happened = true;
  1329. cmd_flags = 0;
  1330. /* add to add array */
  1331. memcpy(add_list[num_add].mac_addr,
  1332. f->macaddr, ETH_ALEN);
  1333. add_list[num_add].vlan_tag =
  1334. cpu_to_le16(
  1335. (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
  1336. add_list[num_add].queue_number = 0;
  1337. cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
  1338. /* vlan0 as wild card to allow packets from all vlans */
  1339. if (f->vlan == I40E_VLAN_ANY || (vsi->netdev &&
  1340. !(vsi->netdev->features &
  1341. NETIF_F_HW_VLAN_CTAG_FILTER)))
  1342. cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
  1343. add_list[num_add].flags = cpu_to_le16(cmd_flags);
  1344. num_add++;
  1345. /* flush a full buffer */
  1346. if (num_add == filter_list_len) {
  1347. aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
  1348. add_list, num_add,
  1349. NULL);
  1350. num_add = 0;
  1351. if (aq_ret)
  1352. break;
  1353. memset(add_list, 0, sizeof(*add_list));
  1354. }
  1355. }
  1356. if (num_add) {
  1357. aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
  1358. add_list, num_add, NULL);
  1359. num_add = 0;
  1360. }
  1361. kfree(add_list);
  1362. add_list = NULL;
  1363. if (add_happened && (!aq_ret)) {
  1364. /* do nothing */;
  1365. } else if (add_happened && (aq_ret)) {
  1366. dev_info(&pf->pdev->dev,
  1367. "add filter failed, err %d, aq_err %d\n",
  1368. aq_ret, pf->hw.aq.asq_last_status);
  1369. if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
  1370. !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
  1371. &vsi->state)) {
  1372. promisc_forced_on = true;
  1373. set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
  1374. &vsi->state);
  1375. dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
  1376. }
  1377. }
  1378. }
  1379. /* check for changes in promiscuous modes */
  1380. if (changed_flags & IFF_ALLMULTI) {
  1381. bool cur_multipromisc;
  1382. cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
  1383. aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
  1384. vsi->seid,
  1385. cur_multipromisc,
  1386. NULL);
  1387. if (aq_ret)
  1388. dev_info(&pf->pdev->dev,
  1389. "set multi promisc failed, err %d, aq_err %d\n",
  1390. aq_ret, pf->hw.aq.asq_last_status);
  1391. }
  1392. if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
  1393. bool cur_promisc;
  1394. cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
  1395. test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
  1396. &vsi->state));
  1397. aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
  1398. vsi->seid,
  1399. cur_promisc, NULL);
  1400. if (aq_ret)
  1401. dev_info(&pf->pdev->dev,
  1402. "set uni promisc failed, err %d, aq_err %d\n",
  1403. aq_ret, pf->hw.aq.asq_last_status);
  1404. }
  1405. clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
  1406. return 0;
  1407. }
  1408. /**
  1409. * i40e_sync_filters_subtask - Sync the VSI filter list with HW
  1410. * @pf: board private structure
  1411. **/
  1412. static void i40e_sync_filters_subtask(struct i40e_pf *pf)
  1413. {
  1414. int v;
  1415. if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
  1416. return;
  1417. pf->flags &= ~I40E_FLAG_FILTER_SYNC;
  1418. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  1419. if (pf->vsi[v] &&
  1420. (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
  1421. i40e_sync_vsi_filters(pf->vsi[v]);
  1422. }
  1423. }
  1424. /**
  1425. * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
  1426. * @netdev: network interface device structure
  1427. * @new_mtu: new value for maximum frame size
  1428. *
  1429. * Returns 0 on success, negative on failure
  1430. **/
  1431. static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
  1432. {
  1433. struct i40e_netdev_priv *np = netdev_priv(netdev);
  1434. int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
  1435. struct i40e_vsi *vsi = np->vsi;
  1436. /* MTU < 68 is an error and causes problems on some kernels */
  1437. if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
  1438. return -EINVAL;
  1439. netdev_info(netdev, "changing MTU from %d to %d\n",
  1440. netdev->mtu, new_mtu);
  1441. netdev->mtu = new_mtu;
  1442. if (netif_running(netdev))
  1443. i40e_vsi_reinit_locked(vsi);
  1444. return 0;
  1445. }
  1446. /**
  1447. * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
  1448. * @vsi: the vsi being adjusted
  1449. **/
  1450. void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
  1451. {
  1452. struct i40e_vsi_context ctxt;
  1453. i40e_status ret;
  1454. if ((vsi->info.valid_sections &
  1455. cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
  1456. ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
  1457. return; /* already enabled */
  1458. vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
  1459. vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
  1460. I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
  1461. ctxt.seid = vsi->seid;
  1462. memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
  1463. ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
  1464. if (ret) {
  1465. dev_info(&vsi->back->pdev->dev,
  1466. "%s: update vsi failed, aq_err=%d\n",
  1467. __func__, vsi->back->hw.aq.asq_last_status);
  1468. }
  1469. }
  1470. /**
  1471. * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
  1472. * @vsi: the vsi being adjusted
  1473. **/
  1474. void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
  1475. {
  1476. struct i40e_vsi_context ctxt;
  1477. i40e_status ret;
  1478. if ((vsi->info.valid_sections &
  1479. cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
  1480. ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
  1481. I40E_AQ_VSI_PVLAN_EMOD_MASK))
  1482. return; /* already disabled */
  1483. vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
  1484. vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
  1485. I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
  1486. ctxt.seid = vsi->seid;
  1487. memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
  1488. ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
  1489. if (ret) {
  1490. dev_info(&vsi->back->pdev->dev,
  1491. "%s: update vsi failed, aq_err=%d\n",
  1492. __func__, vsi->back->hw.aq.asq_last_status);
  1493. }
  1494. }
  1495. /**
  1496. * i40e_vlan_rx_register - Setup or shutdown vlan offload
  1497. * @netdev: network interface to be adjusted
  1498. * @features: netdev features to test if VLAN offload is enabled or not
  1499. **/
  1500. static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
  1501. {
  1502. struct i40e_netdev_priv *np = netdev_priv(netdev);
  1503. struct i40e_vsi *vsi = np->vsi;
  1504. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1505. i40e_vlan_stripping_enable(vsi);
  1506. else
  1507. i40e_vlan_stripping_disable(vsi);
  1508. }
  1509. /**
  1510. * i40e_vsi_add_vlan - Add vsi membership for given vlan
  1511. * @vsi: the vsi being configured
  1512. * @vid: vlan id to be added (0 = untagged only , -1 = any)
  1513. **/
  1514. int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
  1515. {
  1516. struct i40e_mac_filter *f, *add_f;
  1517. bool is_netdev, is_vf;
  1518. int ret;
  1519. is_vf = (vsi->type == I40E_VSI_SRIOV);
  1520. is_netdev = !!(vsi->netdev);
  1521. if (is_netdev) {
  1522. add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
  1523. is_vf, is_netdev);
  1524. if (!add_f) {
  1525. dev_info(&vsi->back->pdev->dev,
  1526. "Could not add vlan filter %d for %pM\n",
  1527. vid, vsi->netdev->dev_addr);
  1528. return -ENOMEM;
  1529. }
  1530. }
  1531. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  1532. add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
  1533. if (!add_f) {
  1534. dev_info(&vsi->back->pdev->dev,
  1535. "Could not add vlan filter %d for %pM\n",
  1536. vid, f->macaddr);
  1537. return -ENOMEM;
  1538. }
  1539. }
  1540. ret = i40e_sync_vsi_filters(vsi);
  1541. if (ret) {
  1542. dev_info(&vsi->back->pdev->dev,
  1543. "Could not sync filters for vid %d\n", vid);
  1544. return ret;
  1545. }
  1546. /* Now if we add a vlan tag, make sure to check if it is the first
  1547. * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
  1548. * with 0, so we now accept untagged and specified tagged traffic
  1549. * (and not any taged and untagged)
  1550. */
  1551. if (vid > 0) {
  1552. if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
  1553. I40E_VLAN_ANY,
  1554. is_vf, is_netdev)) {
  1555. i40e_del_filter(vsi, vsi->netdev->dev_addr,
  1556. I40E_VLAN_ANY, is_vf, is_netdev);
  1557. add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
  1558. is_vf, is_netdev);
  1559. if (!add_f) {
  1560. dev_info(&vsi->back->pdev->dev,
  1561. "Could not add filter 0 for %pM\n",
  1562. vsi->netdev->dev_addr);
  1563. return -ENOMEM;
  1564. }
  1565. }
  1566. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  1567. if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
  1568. is_vf, is_netdev)) {
  1569. i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
  1570. is_vf, is_netdev);
  1571. add_f = i40e_add_filter(vsi, f->macaddr,
  1572. 0, is_vf, is_netdev);
  1573. if (!add_f) {
  1574. dev_info(&vsi->back->pdev->dev,
  1575. "Could not add filter 0 for %pM\n",
  1576. f->macaddr);
  1577. return -ENOMEM;
  1578. }
  1579. }
  1580. }
  1581. ret = i40e_sync_vsi_filters(vsi);
  1582. }
  1583. return ret;
  1584. }
  1585. /**
  1586. * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
  1587. * @vsi: the vsi being configured
  1588. * @vid: vlan id to be removed (0 = untagged only , -1 = any)
  1589. *
  1590. * Return: 0 on success or negative otherwise
  1591. **/
  1592. int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
  1593. {
  1594. struct net_device *netdev = vsi->netdev;
  1595. struct i40e_mac_filter *f, *add_f;
  1596. bool is_vf, is_netdev;
  1597. int filter_count = 0;
  1598. int ret;
  1599. is_vf = (vsi->type == I40E_VSI_SRIOV);
  1600. is_netdev = !!(netdev);
  1601. if (is_netdev)
  1602. i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
  1603. list_for_each_entry(f, &vsi->mac_filter_list, list)
  1604. i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
  1605. ret = i40e_sync_vsi_filters(vsi);
  1606. if (ret) {
  1607. dev_info(&vsi->back->pdev->dev, "Could not sync filters\n");
  1608. return ret;
  1609. }
  1610. /* go through all the filters for this VSI and if there is only
  1611. * vid == 0 it means there are no other filters, so vid 0 must
  1612. * be replaced with -1. This signifies that we should from now
  1613. * on accept any traffic (with any tag present, or untagged)
  1614. */
  1615. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  1616. if (is_netdev) {
  1617. if (f->vlan &&
  1618. ether_addr_equal(netdev->dev_addr, f->macaddr))
  1619. filter_count++;
  1620. }
  1621. if (f->vlan)
  1622. filter_count++;
  1623. }
  1624. if (!filter_count && is_netdev) {
  1625. i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
  1626. f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
  1627. is_vf, is_netdev);
  1628. if (!f) {
  1629. dev_info(&vsi->back->pdev->dev,
  1630. "Could not add filter %d for %pM\n",
  1631. I40E_VLAN_ANY, netdev->dev_addr);
  1632. return -ENOMEM;
  1633. }
  1634. }
  1635. if (!filter_count) {
  1636. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  1637. i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
  1638. add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
  1639. is_vf, is_netdev);
  1640. if (!add_f) {
  1641. dev_info(&vsi->back->pdev->dev,
  1642. "Could not add filter %d for %pM\n",
  1643. I40E_VLAN_ANY, f->macaddr);
  1644. return -ENOMEM;
  1645. }
  1646. }
  1647. }
  1648. return i40e_sync_vsi_filters(vsi);
  1649. }
  1650. /**
  1651. * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
  1652. * @netdev: network interface to be adjusted
  1653. * @vid: vlan id to be added
  1654. *
  1655. * net_device_ops implementation for adding vlan ids
  1656. **/
  1657. static int i40e_vlan_rx_add_vid(struct net_device *netdev,
  1658. __always_unused __be16 proto, u16 vid)
  1659. {
  1660. struct i40e_netdev_priv *np = netdev_priv(netdev);
  1661. struct i40e_vsi *vsi = np->vsi;
  1662. int ret = 0;
  1663. if (vid > 4095)
  1664. return -EINVAL;
  1665. netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
  1666. /* If the network stack called us with vid = 0, we should
  1667. * indicate to i40e_vsi_add_vlan() that we want to receive
  1668. * any traffic (i.e. with any vlan tag, or untagged)
  1669. */
  1670. ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);
  1671. if (!ret && (vid < VLAN_N_VID))
  1672. set_bit(vid, vsi->active_vlans);
  1673. return ret;
  1674. }
  1675. /**
  1676. * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
  1677. * @netdev: network interface to be adjusted
  1678. * @vid: vlan id to be removed
  1679. *
  1680. * net_device_ops implementation for adding vlan ids
  1681. **/
  1682. static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
  1683. __always_unused __be16 proto, u16 vid)
  1684. {
  1685. struct i40e_netdev_priv *np = netdev_priv(netdev);
  1686. struct i40e_vsi *vsi = np->vsi;
  1687. netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
  1688. /* return code is ignored as there is nothing a user
  1689. * can do about failure to remove and a log message was
  1690. * already printed from the other function
  1691. */
  1692. i40e_vsi_kill_vlan(vsi, vid);
  1693. clear_bit(vid, vsi->active_vlans);
  1694. return 0;
  1695. }
  1696. /**
  1697. * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
  1698. * @vsi: the vsi being brought back up
  1699. **/
  1700. static void i40e_restore_vlan(struct i40e_vsi *vsi)
  1701. {
  1702. u16 vid;
  1703. if (!vsi->netdev)
  1704. return;
  1705. i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
  1706. for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
  1707. i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
  1708. vid);
  1709. }
  1710. /**
  1711. * i40e_vsi_add_pvid - Add pvid for the VSI
  1712. * @vsi: the vsi being adjusted
  1713. * @vid: the vlan id to set as a PVID
  1714. **/
  1715. int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
  1716. {
  1717. struct i40e_vsi_context ctxt;
  1718. i40e_status aq_ret;
  1719. vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
  1720. vsi->info.pvid = cpu_to_le16(vid);
  1721. vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
  1722. vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
  1723. ctxt.seid = vsi->seid;
  1724. memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
  1725. aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
  1726. if (aq_ret) {
  1727. dev_info(&vsi->back->pdev->dev,
  1728. "%s: update vsi failed, aq_err=%d\n",
  1729. __func__, vsi->back->hw.aq.asq_last_status);
  1730. return -ENOENT;
  1731. }
  1732. return 0;
  1733. }
  1734. /**
  1735. * i40e_vsi_remove_pvid - Remove the pvid from the VSI
  1736. * @vsi: the vsi being adjusted
  1737. *
  1738. * Just use the vlan_rx_register() service to put it back to normal
  1739. **/
  1740. void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
  1741. {
  1742. vsi->info.pvid = 0;
  1743. i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
  1744. }
  1745. /**
  1746. * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
  1747. * @vsi: ptr to the VSI
  1748. *
  1749. * If this function returns with an error, then it's possible one or
  1750. * more of the rings is populated (while the rest are not). It is the
  1751. * callers duty to clean those orphaned rings.
  1752. *
  1753. * Return 0 on success, negative on failure
  1754. **/
  1755. static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
  1756. {
  1757. int i, err = 0;
  1758. for (i = 0; i < vsi->num_queue_pairs && !err; i++)
  1759. err = i40e_setup_tx_descriptors(&vsi->tx_rings[i]);
  1760. return err;
  1761. }
  1762. /**
  1763. * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
  1764. * @vsi: ptr to the VSI
  1765. *
  1766. * Free VSI's transmit software resources
  1767. **/
  1768. static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
  1769. {
  1770. int i;
  1771. for (i = 0; i < vsi->num_queue_pairs; i++)
  1772. if (vsi->tx_rings[i].desc)
  1773. i40e_free_tx_resources(&vsi->tx_rings[i]);
  1774. }
  1775. /**
  1776. * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
  1777. * @vsi: ptr to the VSI
  1778. *
  1779. * If this function returns with an error, then it's possible one or
  1780. * more of the rings is populated (while the rest are not). It is the
  1781. * callers duty to clean those orphaned rings.
  1782. *
  1783. * Return 0 on success, negative on failure
  1784. **/
  1785. static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
  1786. {
  1787. int i, err = 0;
  1788. for (i = 0; i < vsi->num_queue_pairs && !err; i++)
  1789. err = i40e_setup_rx_descriptors(&vsi->rx_rings[i]);
  1790. return err;
  1791. }
  1792. /**
  1793. * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
  1794. * @vsi: ptr to the VSI
  1795. *
  1796. * Free all receive software resources
  1797. **/
  1798. static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
  1799. {
  1800. int i;
  1801. for (i = 0; i < vsi->num_queue_pairs; i++)
  1802. if (vsi->rx_rings[i].desc)
  1803. i40e_free_rx_resources(&vsi->rx_rings[i]);
  1804. }
  1805. /**
  1806. * i40e_configure_tx_ring - Configure a transmit ring context and rest
  1807. * @ring: The Tx ring to configure
  1808. *
  1809. * Configure the Tx descriptor ring in the HMC context.
  1810. **/
  1811. static int i40e_configure_tx_ring(struct i40e_ring *ring)
  1812. {
  1813. struct i40e_vsi *vsi = ring->vsi;
  1814. u16 pf_q = vsi->base_queue + ring->queue_index;
  1815. struct i40e_hw *hw = &vsi->back->hw;
  1816. struct i40e_hmc_obj_txq tx_ctx;
  1817. i40e_status err = 0;
  1818. u32 qtx_ctl = 0;
  1819. /* some ATR related tx ring init */
  1820. if (vsi->back->flags & I40E_FLAG_FDIR_ATR_ENABLED) {
  1821. ring->atr_sample_rate = vsi->back->atr_sample_rate;
  1822. ring->atr_count = 0;
  1823. } else {
  1824. ring->atr_sample_rate = 0;
  1825. }
  1826. /* initialize XPS */
  1827. if (ring->q_vector && ring->netdev &&
  1828. !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
  1829. netif_set_xps_queue(ring->netdev,
  1830. &ring->q_vector->affinity_mask,
  1831. ring->queue_index);
  1832. /* clear the context structure first */
  1833. memset(&tx_ctx, 0, sizeof(tx_ctx));
  1834. tx_ctx.new_context = 1;
  1835. tx_ctx.base = (ring->dma / 128);
  1836. tx_ctx.qlen = ring->count;
  1837. tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FDIR_ENABLED |
  1838. I40E_FLAG_FDIR_ATR_ENABLED));
  1839. /* As part of VSI creation/update, FW allocates certain
  1840. * Tx arbitration queue sets for each TC enabled for
  1841. * the VSI. The FW returns the handles to these queue
  1842. * sets as part of the response buffer to Add VSI,
  1843. * Update VSI, etc. AQ commands. It is expected that
  1844. * these queue set handles be associated with the Tx
  1845. * queues by the driver as part of the TX queue context
  1846. * initialization. This has to be done regardless of
  1847. * DCB as by default everything is mapped to TC0.
  1848. */
  1849. tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
  1850. tx_ctx.rdylist_act = 0;
  1851. /* clear the context in the HMC */
  1852. err = i40e_clear_lan_tx_queue_context(hw, pf_q);
  1853. if (err) {
  1854. dev_info(&vsi->back->pdev->dev,
  1855. "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
  1856. ring->queue_index, pf_q, err);
  1857. return -ENOMEM;
  1858. }
  1859. /* set the context in the HMC */
  1860. err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
  1861. if (err) {
  1862. dev_info(&vsi->back->pdev->dev,
  1863. "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
  1864. ring->queue_index, pf_q, err);
  1865. return -ENOMEM;
  1866. }
  1867. /* Now associate this queue with this PCI function */
  1868. qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
  1869. qtx_ctl |= ((hw->hmc.hmc_fn_id << I40E_QTX_CTL_PF_INDX_SHIFT)
  1870. & I40E_QTX_CTL_PF_INDX_MASK);
  1871. wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
  1872. i40e_flush(hw);
  1873. clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
  1874. /* cache tail off for easier writes later */
  1875. ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
  1876. return 0;
  1877. }
  1878. /**
  1879. * i40e_configure_rx_ring - Configure a receive ring context
  1880. * @ring: The Rx ring to configure
  1881. *
  1882. * Configure the Rx descriptor ring in the HMC context.
  1883. **/
  1884. static int i40e_configure_rx_ring(struct i40e_ring *ring)
  1885. {
  1886. struct i40e_vsi *vsi = ring->vsi;
  1887. u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
  1888. u16 pf_q = vsi->base_queue + ring->queue_index;
  1889. struct i40e_hw *hw = &vsi->back->hw;
  1890. struct i40e_hmc_obj_rxq rx_ctx;
  1891. i40e_status err = 0;
  1892. ring->state = 0;
  1893. /* clear the context structure first */
  1894. memset(&rx_ctx, 0, sizeof(rx_ctx));
  1895. ring->rx_buf_len = vsi->rx_buf_len;
  1896. ring->rx_hdr_len = vsi->rx_hdr_len;
  1897. rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
  1898. rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
  1899. rx_ctx.base = (ring->dma / 128);
  1900. rx_ctx.qlen = ring->count;
  1901. if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
  1902. set_ring_16byte_desc_enabled(ring);
  1903. rx_ctx.dsize = 0;
  1904. } else {
  1905. rx_ctx.dsize = 1;
  1906. }
  1907. rx_ctx.dtype = vsi->dtype;
  1908. if (vsi->dtype) {
  1909. set_ring_ps_enabled(ring);
  1910. rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
  1911. I40E_RX_SPLIT_IP |
  1912. I40E_RX_SPLIT_TCP_UDP |
  1913. I40E_RX_SPLIT_SCTP;
  1914. } else {
  1915. rx_ctx.hsplit_0 = 0;
  1916. }
  1917. rx_ctx.rxmax = min_t(u16, vsi->max_frame,
  1918. (chain_len * ring->rx_buf_len));
  1919. rx_ctx.tphrdesc_ena = 1;
  1920. rx_ctx.tphwdesc_ena = 1;
  1921. rx_ctx.tphdata_ena = 1;
  1922. rx_ctx.tphhead_ena = 1;
  1923. rx_ctx.lrxqthresh = 2;
  1924. rx_ctx.crcstrip = 1;
  1925. rx_ctx.l2tsel = 1;
  1926. rx_ctx.showiv = 1;
  1927. /* clear the context in the HMC */
  1928. err = i40e_clear_lan_rx_queue_context(hw, pf_q);
  1929. if (err) {
  1930. dev_info(&vsi->back->pdev->dev,
  1931. "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
  1932. ring->queue_index, pf_q, err);
  1933. return -ENOMEM;
  1934. }
  1935. /* set the context in the HMC */
  1936. err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
  1937. if (err) {
  1938. dev_info(&vsi->back->pdev->dev,
  1939. "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
  1940. ring->queue_index, pf_q, err);
  1941. return -ENOMEM;
  1942. }
  1943. /* cache tail for quicker writes, and clear the reg before use */
  1944. ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
  1945. writel(0, ring->tail);
  1946. i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
  1947. return 0;
  1948. }
  1949. /**
  1950. * i40e_vsi_configure_tx - Configure the VSI for Tx
  1951. * @vsi: VSI structure describing this set of rings and resources
  1952. *
  1953. * Configure the Tx VSI for operation.
  1954. **/
  1955. static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
  1956. {
  1957. int err = 0;
  1958. u16 i;
  1959. for (i = 0; (i < vsi->num_queue_pairs) && (!err); i++)
  1960. err = i40e_configure_tx_ring(&vsi->tx_rings[i]);
  1961. return err;
  1962. }
  1963. /**
  1964. * i40e_vsi_configure_rx - Configure the VSI for Rx
  1965. * @vsi: the VSI being configured
  1966. *
  1967. * Configure the Rx VSI for operation.
  1968. **/
  1969. static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
  1970. {
  1971. int err = 0;
  1972. u16 i;
  1973. if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
  1974. vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
  1975. + ETH_FCS_LEN + VLAN_HLEN;
  1976. else
  1977. vsi->max_frame = I40E_RXBUFFER_2048;
  1978. /* figure out correct receive buffer length */
  1979. switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
  1980. I40E_FLAG_RX_PS_ENABLED)) {
  1981. case I40E_FLAG_RX_1BUF_ENABLED:
  1982. vsi->rx_hdr_len = 0;
  1983. vsi->rx_buf_len = vsi->max_frame;
  1984. vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
  1985. break;
  1986. case I40E_FLAG_RX_PS_ENABLED:
  1987. vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
  1988. vsi->rx_buf_len = I40E_RXBUFFER_2048;
  1989. vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
  1990. break;
  1991. default:
  1992. vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
  1993. vsi->rx_buf_len = I40E_RXBUFFER_2048;
  1994. vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
  1995. break;
  1996. }
  1997. /* round up for the chip's needs */
  1998. vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
  1999. (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
  2000. vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
  2001. (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
  2002. /* set up individual rings */
  2003. for (i = 0; i < vsi->num_queue_pairs && !err; i++)
  2004. err = i40e_configure_rx_ring(&vsi->rx_rings[i]);
  2005. return err;
  2006. }
  2007. /**
  2008. * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
  2009. * @vsi: ptr to the VSI
  2010. **/
  2011. static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
  2012. {
  2013. u16 qoffset, qcount;
  2014. int i, n;
  2015. if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
  2016. return;
  2017. for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
  2018. if (!(vsi->tc_config.enabled_tc & (1 << n)))
  2019. continue;
  2020. qoffset = vsi->tc_config.tc_info[n].qoffset;
  2021. qcount = vsi->tc_config.tc_info[n].qcount;
  2022. for (i = qoffset; i < (qoffset + qcount); i++) {
  2023. struct i40e_ring *rx_ring = &vsi->rx_rings[i];
  2024. struct i40e_ring *tx_ring = &vsi->tx_rings[i];
  2025. rx_ring->dcb_tc = n;
  2026. tx_ring->dcb_tc = n;
  2027. }
  2028. }
  2029. }
  2030. /**
  2031. * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
  2032. * @vsi: ptr to the VSI
  2033. **/
  2034. static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
  2035. {
  2036. if (vsi->netdev)
  2037. i40e_set_rx_mode(vsi->netdev);
  2038. }
  2039. /**
  2040. * i40e_vsi_configure - Set up the VSI for action
  2041. * @vsi: the VSI being configured
  2042. **/
  2043. static int i40e_vsi_configure(struct i40e_vsi *vsi)
  2044. {
  2045. int err;
  2046. i40e_set_vsi_rx_mode(vsi);
  2047. i40e_restore_vlan(vsi);
  2048. i40e_vsi_config_dcb_rings(vsi);
  2049. err = i40e_vsi_configure_tx(vsi);
  2050. if (!err)
  2051. err = i40e_vsi_configure_rx(vsi);
  2052. return err;
  2053. }
  2054. /**
  2055. * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
  2056. * @vsi: the VSI being configured
  2057. **/
  2058. static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
  2059. {
  2060. struct i40e_pf *pf = vsi->back;
  2061. struct i40e_q_vector *q_vector;
  2062. struct i40e_hw *hw = &pf->hw;
  2063. u16 vector;
  2064. int i, q;
  2065. u32 val;
  2066. u32 qp;
  2067. /* The interrupt indexing is offset by 1 in the PFINT_ITRn
  2068. * and PFINT_LNKLSTn registers, e.g.:
  2069. * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
  2070. */
  2071. qp = vsi->base_queue;
  2072. vector = vsi->base_vector;
  2073. q_vector = vsi->q_vectors;
  2074. for (i = 0; i < vsi->num_q_vectors; i++, q_vector++, vector++) {
  2075. q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
  2076. q_vector->rx.latency_range = I40E_LOW_LATENCY;
  2077. wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
  2078. q_vector->rx.itr);
  2079. q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
  2080. q_vector->tx.latency_range = I40E_LOW_LATENCY;
  2081. wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
  2082. q_vector->tx.itr);
  2083. /* Linked list for the queuepairs assigned to this vector */
  2084. wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
  2085. for (q = 0; q < q_vector->num_ringpairs; q++) {
  2086. val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
  2087. (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
  2088. (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
  2089. (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
  2090. (I40E_QUEUE_TYPE_TX
  2091. << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
  2092. wr32(hw, I40E_QINT_RQCTL(qp), val);
  2093. val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
  2094. (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
  2095. (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
  2096. ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
  2097. (I40E_QUEUE_TYPE_RX
  2098. << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
  2099. /* Terminate the linked list */
  2100. if (q == (q_vector->num_ringpairs - 1))
  2101. val |= (I40E_QUEUE_END_OF_LIST
  2102. << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
  2103. wr32(hw, I40E_QINT_TQCTL(qp), val);
  2104. qp++;
  2105. }
  2106. }
  2107. i40e_flush(hw);
  2108. }
  2109. /**
  2110. * i40e_enable_misc_int_causes - enable the non-queue interrupts
  2111. * @hw: ptr to the hardware info
  2112. **/
  2113. static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
  2114. {
  2115. u32 val;
  2116. /* clear things first */
  2117. wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
  2118. rd32(hw, I40E_PFINT_ICR0); /* read to clear */
  2119. val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
  2120. I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
  2121. I40E_PFINT_ICR0_ENA_GRST_MASK |
  2122. I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
  2123. I40E_PFINT_ICR0_ENA_GPIO_MASK |
  2124. I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
  2125. I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
  2126. I40E_PFINT_ICR0_ENA_VFLR_MASK |
  2127. I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
  2128. wr32(hw, I40E_PFINT_ICR0_ENA, val);
  2129. /* SW_ITR_IDX = 0, but don't change INTENA */
  2130. wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK |
  2131. I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK);
  2132. /* OTHER_ITR_IDX = 0 */
  2133. wr32(hw, I40E_PFINT_STAT_CTL0, 0);
  2134. }
  2135. /**
  2136. * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
  2137. * @vsi: the VSI being configured
  2138. **/
  2139. static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
  2140. {
  2141. struct i40e_q_vector *q_vector = vsi->q_vectors;
  2142. struct i40e_pf *pf = vsi->back;
  2143. struct i40e_hw *hw = &pf->hw;
  2144. u32 val;
  2145. /* set the ITR configuration */
  2146. q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
  2147. q_vector->rx.latency_range = I40E_LOW_LATENCY;
  2148. wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
  2149. q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
  2150. q_vector->tx.latency_range = I40E_LOW_LATENCY;
  2151. wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
  2152. i40e_enable_misc_int_causes(hw);
  2153. /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
  2154. wr32(hw, I40E_PFINT_LNKLST0, 0);
  2155. /* Associate the queue pair to the vector and enable the q int */
  2156. val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
  2157. (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
  2158. (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
  2159. wr32(hw, I40E_QINT_RQCTL(0), val);
  2160. val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
  2161. (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
  2162. (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
  2163. wr32(hw, I40E_QINT_TQCTL(0), val);
  2164. i40e_flush(hw);
  2165. }
  2166. /**
  2167. * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
  2168. * @pf: board private structure
  2169. **/
  2170. static void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
  2171. {
  2172. struct i40e_hw *hw = &pf->hw;
  2173. u32 val;
  2174. val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
  2175. I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
  2176. (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
  2177. wr32(hw, I40E_PFINT_DYN_CTL0, val);
  2178. i40e_flush(hw);
  2179. }
  2180. /**
  2181. * i40e_irq_dynamic_enable - Enable default interrupt generation settings
  2182. * @vsi: pointer to a vsi
  2183. * @vector: enable a particular Hw Interrupt vector
  2184. **/
  2185. void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
  2186. {
  2187. struct i40e_pf *pf = vsi->back;
  2188. struct i40e_hw *hw = &pf->hw;
  2189. u32 val;
  2190. val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
  2191. I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
  2192. (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
  2193. wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
  2194. i40e_flush(hw);
  2195. }
  2196. /**
  2197. * i40e_msix_clean_rings - MSIX mode Interrupt Handler
  2198. * @irq: interrupt number
  2199. * @data: pointer to a q_vector
  2200. **/
  2201. static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
  2202. {
  2203. struct i40e_q_vector *q_vector = data;
  2204. if (!q_vector->tx.ring[0] && !q_vector->rx.ring[0])
  2205. return IRQ_HANDLED;
  2206. napi_schedule(&q_vector->napi);
  2207. return IRQ_HANDLED;
  2208. }
  2209. /**
  2210. * i40e_fdir_clean_rings - Interrupt Handler for FDIR rings
  2211. * @irq: interrupt number
  2212. * @data: pointer to a q_vector
  2213. **/
  2214. static irqreturn_t i40e_fdir_clean_rings(int irq, void *data)
  2215. {
  2216. struct i40e_q_vector *q_vector = data;
  2217. if (!q_vector->tx.ring[0] && !q_vector->rx.ring[0])
  2218. return IRQ_HANDLED;
  2219. pr_info("fdir ring cleaning needed\n");
  2220. return IRQ_HANDLED;
  2221. }
  2222. /**
  2223. * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
  2224. * @vsi: the VSI being configured
  2225. * @basename: name for the vector
  2226. *
  2227. * Allocates MSI-X vectors and requests interrupts from the kernel.
  2228. **/
  2229. static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
  2230. {
  2231. int q_vectors = vsi->num_q_vectors;
  2232. struct i40e_pf *pf = vsi->back;
  2233. int base = vsi->base_vector;
  2234. int rx_int_idx = 0;
  2235. int tx_int_idx = 0;
  2236. int vector, err;
  2237. for (vector = 0; vector < q_vectors; vector++) {
  2238. struct i40e_q_vector *q_vector = &(vsi->q_vectors[vector]);
  2239. if (q_vector->tx.ring[0] && q_vector->rx.ring[0]) {
  2240. snprintf(q_vector->name, sizeof(q_vector->name) - 1,
  2241. "%s-%s-%d", basename, "TxRx", rx_int_idx++);
  2242. tx_int_idx++;
  2243. } else if (q_vector->rx.ring[0]) {
  2244. snprintf(q_vector->name, sizeof(q_vector->name) - 1,
  2245. "%s-%s-%d", basename, "rx", rx_int_idx++);
  2246. } else if (q_vector->tx.ring[0]) {
  2247. snprintf(q_vector->name, sizeof(q_vector->name) - 1,
  2248. "%s-%s-%d", basename, "tx", tx_int_idx++);
  2249. } else {
  2250. /* skip this unused q_vector */
  2251. continue;
  2252. }
  2253. err = request_irq(pf->msix_entries[base + vector].vector,
  2254. vsi->irq_handler,
  2255. 0,
  2256. q_vector->name,
  2257. q_vector);
  2258. if (err) {
  2259. dev_info(&pf->pdev->dev,
  2260. "%s: request_irq failed, error: %d\n",
  2261. __func__, err);
  2262. goto free_queue_irqs;
  2263. }
  2264. /* assign the mask for this irq */
  2265. irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
  2266. &q_vector->affinity_mask);
  2267. }
  2268. return 0;
  2269. free_queue_irqs:
  2270. while (vector) {
  2271. vector--;
  2272. irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
  2273. NULL);
  2274. free_irq(pf->msix_entries[base + vector].vector,
  2275. &(vsi->q_vectors[vector]));
  2276. }
  2277. return err;
  2278. }
  2279. /**
  2280. * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
  2281. * @vsi: the VSI being un-configured
  2282. **/
  2283. static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
  2284. {
  2285. struct i40e_pf *pf = vsi->back;
  2286. struct i40e_hw *hw = &pf->hw;
  2287. int base = vsi->base_vector;
  2288. int i;
  2289. for (i = 0; i < vsi->num_queue_pairs; i++) {
  2290. wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i].reg_idx), 0);
  2291. wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i].reg_idx), 0);
  2292. }
  2293. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  2294. for (i = vsi->base_vector;
  2295. i < (vsi->num_q_vectors + vsi->base_vector); i++)
  2296. wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
  2297. i40e_flush(hw);
  2298. for (i = 0; i < vsi->num_q_vectors; i++)
  2299. synchronize_irq(pf->msix_entries[i + base].vector);
  2300. } else {
  2301. /* Legacy and MSI mode - this stops all interrupt handling */
  2302. wr32(hw, I40E_PFINT_ICR0_ENA, 0);
  2303. wr32(hw, I40E_PFINT_DYN_CTL0, 0);
  2304. i40e_flush(hw);
  2305. synchronize_irq(pf->pdev->irq);
  2306. }
  2307. }
  2308. /**
  2309. * i40e_vsi_enable_irq - Enable IRQ for the given VSI
  2310. * @vsi: the VSI being configured
  2311. **/
  2312. static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
  2313. {
  2314. struct i40e_pf *pf = vsi->back;
  2315. int i;
  2316. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  2317. for (i = vsi->base_vector;
  2318. i < (vsi->num_q_vectors + vsi->base_vector); i++)
  2319. i40e_irq_dynamic_enable(vsi, i);
  2320. } else {
  2321. i40e_irq_dynamic_enable_icr0(pf);
  2322. }
  2323. return 0;
  2324. }
  2325. /**
  2326. * i40e_stop_misc_vector - Stop the vector that handles non-queue events
  2327. * @pf: board private structure
  2328. **/
  2329. static void i40e_stop_misc_vector(struct i40e_pf *pf)
  2330. {
  2331. /* Disable ICR 0 */
  2332. wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
  2333. i40e_flush(&pf->hw);
  2334. }
  2335. /**
  2336. * i40e_intr - MSI/Legacy and non-queue interrupt handler
  2337. * @irq: interrupt number
  2338. * @data: pointer to a q_vector
  2339. *
  2340. * This is the handler used for all MSI/Legacy interrupts, and deals
  2341. * with both queue and non-queue interrupts. This is also used in
  2342. * MSIX mode to handle the non-queue interrupts.
  2343. **/
  2344. static irqreturn_t i40e_intr(int irq, void *data)
  2345. {
  2346. struct i40e_pf *pf = (struct i40e_pf *)data;
  2347. struct i40e_hw *hw = &pf->hw;
  2348. u32 icr0, icr0_remaining;
  2349. u32 val, ena_mask;
  2350. icr0 = rd32(hw, I40E_PFINT_ICR0);
  2351. /* if sharing a legacy IRQ, we might get called w/o an intr pending */
  2352. if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
  2353. return IRQ_NONE;
  2354. val = rd32(hw, I40E_PFINT_DYN_CTL0);
  2355. val = val | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK;
  2356. wr32(hw, I40E_PFINT_DYN_CTL0, val);
  2357. ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
  2358. /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
  2359. if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
  2360. /* temporarily disable queue cause for NAPI processing */
  2361. u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
  2362. qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
  2363. wr32(hw, I40E_QINT_RQCTL(0), qval);
  2364. qval = rd32(hw, I40E_QINT_TQCTL(0));
  2365. qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
  2366. wr32(hw, I40E_QINT_TQCTL(0), qval);
  2367. i40e_flush(hw);
  2368. if (!test_bit(__I40E_DOWN, &pf->state))
  2369. napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0].napi);
  2370. }
  2371. if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
  2372. ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
  2373. set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
  2374. }
  2375. if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
  2376. ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
  2377. set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
  2378. }
  2379. if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
  2380. ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
  2381. set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
  2382. }
  2383. if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
  2384. if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
  2385. set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
  2386. ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
  2387. val = rd32(hw, I40E_GLGEN_RSTAT);
  2388. val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
  2389. >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
  2390. if (val & I40E_RESET_CORER)
  2391. pf->corer_count++;
  2392. else if (val & I40E_RESET_GLOBR)
  2393. pf->globr_count++;
  2394. else if (val & I40E_RESET_EMPR)
  2395. pf->empr_count++;
  2396. }
  2397. /* If a critical error is pending we have no choice but to reset the
  2398. * device.
  2399. * Report and mask out any remaining unexpected interrupts.
  2400. */
  2401. icr0_remaining = icr0 & ena_mask;
  2402. if (icr0_remaining) {
  2403. dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
  2404. icr0_remaining);
  2405. if ((icr0_remaining & I40E_PFINT_ICR0_HMC_ERR_MASK) ||
  2406. (icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
  2407. (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
  2408. (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK) ||
  2409. (icr0_remaining & I40E_PFINT_ICR0_MAL_DETECT_MASK)) {
  2410. if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
  2411. dev_info(&pf->pdev->dev, "HMC error interrupt\n");
  2412. } else {
  2413. dev_info(&pf->pdev->dev, "device will be reset\n");
  2414. set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
  2415. i40e_service_event_schedule(pf);
  2416. }
  2417. }
  2418. ena_mask &= ~icr0_remaining;
  2419. }
  2420. /* re-enable interrupt causes */
  2421. wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
  2422. i40e_flush(hw);
  2423. if (!test_bit(__I40E_DOWN, &pf->state)) {
  2424. i40e_service_event_schedule(pf);
  2425. i40e_irq_dynamic_enable_icr0(pf);
  2426. }
  2427. return IRQ_HANDLED;
  2428. }
  2429. /**
  2430. * i40e_map_vector_to_rxq - Assigns the Rx queue to the vector
  2431. * @vsi: the VSI being configured
  2432. * @v_idx: vector index
  2433. * @r_idx: rx queue index
  2434. **/
  2435. static void map_vector_to_rxq(struct i40e_vsi *vsi, int v_idx, int r_idx)
  2436. {
  2437. struct i40e_q_vector *q_vector = &(vsi->q_vectors[v_idx]);
  2438. struct i40e_ring *rx_ring = &(vsi->rx_rings[r_idx]);
  2439. rx_ring->q_vector = q_vector;
  2440. q_vector->rx.ring[q_vector->rx.count] = rx_ring;
  2441. q_vector->rx.count++;
  2442. q_vector->rx.latency_range = I40E_LOW_LATENCY;
  2443. q_vector->vsi = vsi;
  2444. }
  2445. /**
  2446. * i40e_map_vector_to_txq - Assigns the Tx queue to the vector
  2447. * @vsi: the VSI being configured
  2448. * @v_idx: vector index
  2449. * @t_idx: tx queue index
  2450. **/
  2451. static void map_vector_to_txq(struct i40e_vsi *vsi, int v_idx, int t_idx)
  2452. {
  2453. struct i40e_q_vector *q_vector = &(vsi->q_vectors[v_idx]);
  2454. struct i40e_ring *tx_ring = &(vsi->tx_rings[t_idx]);
  2455. tx_ring->q_vector = q_vector;
  2456. q_vector->tx.ring[q_vector->tx.count] = tx_ring;
  2457. q_vector->tx.count++;
  2458. q_vector->tx.latency_range = I40E_LOW_LATENCY;
  2459. q_vector->num_ringpairs++;
  2460. q_vector->vsi = vsi;
  2461. }
  2462. /**
  2463. * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
  2464. * @vsi: the VSI being configured
  2465. *
  2466. * This function maps descriptor rings to the queue-specific vectors
  2467. * we were allotted through the MSI-X enabling code. Ideally, we'd have
  2468. * one vector per queue pair, but on a constrained vector budget, we
  2469. * group the queue pairs as "efficiently" as possible.
  2470. **/
  2471. static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
  2472. {
  2473. int qp_remaining = vsi->num_queue_pairs;
  2474. int q_vectors = vsi->num_q_vectors;
  2475. int qp_per_vector;
  2476. int v_start = 0;
  2477. int qp_idx = 0;
  2478. /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
  2479. * group them so there are multiple queues per vector.
  2480. */
  2481. for (; v_start < q_vectors && qp_remaining; v_start++) {
  2482. qp_per_vector = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
  2483. for (; qp_per_vector;
  2484. qp_per_vector--, qp_idx++, qp_remaining--) {
  2485. map_vector_to_rxq(vsi, v_start, qp_idx);
  2486. map_vector_to_txq(vsi, v_start, qp_idx);
  2487. }
  2488. }
  2489. }
  2490. /**
  2491. * i40e_vsi_request_irq - Request IRQ from the OS
  2492. * @vsi: the VSI being configured
  2493. * @basename: name for the vector
  2494. **/
  2495. static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
  2496. {
  2497. struct i40e_pf *pf = vsi->back;
  2498. int err;
  2499. if (pf->flags & I40E_FLAG_MSIX_ENABLED)
  2500. err = i40e_vsi_request_irq_msix(vsi, basename);
  2501. else if (pf->flags & I40E_FLAG_MSI_ENABLED)
  2502. err = request_irq(pf->pdev->irq, i40e_intr, 0,
  2503. pf->misc_int_name, pf);
  2504. else
  2505. err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
  2506. pf->misc_int_name, pf);
  2507. if (err)
  2508. dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
  2509. return err;
  2510. }
  2511. #ifdef CONFIG_NET_POLL_CONTROLLER
  2512. /**
  2513. * i40e_netpoll - A Polling 'interrupt'handler
  2514. * @netdev: network interface device structure
  2515. *
  2516. * This is used by netconsole to send skbs without having to re-enable
  2517. * interrupts. It's not called while the normal interrupt routine is executing.
  2518. **/
  2519. static void i40e_netpoll(struct net_device *netdev)
  2520. {
  2521. struct i40e_netdev_priv *np = netdev_priv(netdev);
  2522. struct i40e_vsi *vsi = np->vsi;
  2523. struct i40e_pf *pf = vsi->back;
  2524. int i;
  2525. /* if interface is down do nothing */
  2526. if (test_bit(__I40E_DOWN, &vsi->state))
  2527. return;
  2528. pf->flags |= I40E_FLAG_IN_NETPOLL;
  2529. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  2530. for (i = 0; i < vsi->num_q_vectors; i++)
  2531. i40e_msix_clean_rings(0, &vsi->q_vectors[i]);
  2532. } else {
  2533. i40e_intr(pf->pdev->irq, netdev);
  2534. }
  2535. pf->flags &= ~I40E_FLAG_IN_NETPOLL;
  2536. }
  2537. #endif
  2538. /**
  2539. * i40e_vsi_control_tx - Start or stop a VSI's rings
  2540. * @vsi: the VSI being configured
  2541. * @enable: start or stop the rings
  2542. **/
  2543. static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
  2544. {
  2545. struct i40e_pf *pf = vsi->back;
  2546. struct i40e_hw *hw = &pf->hw;
  2547. int i, j, pf_q;
  2548. u32 tx_reg;
  2549. pf_q = vsi->base_queue;
  2550. for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
  2551. j = 1000;
  2552. do {
  2553. usleep_range(1000, 2000);
  2554. tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
  2555. } while (j-- && ((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT)
  2556. ^ (tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)) & 1);
  2557. if (enable) {
  2558. /* is STAT set ? */
  2559. if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) {
  2560. dev_info(&pf->pdev->dev,
  2561. "Tx %d already enabled\n", i);
  2562. continue;
  2563. }
  2564. } else {
  2565. /* is !STAT set ? */
  2566. if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) {
  2567. dev_info(&pf->pdev->dev,
  2568. "Tx %d already disabled\n", i);
  2569. continue;
  2570. }
  2571. }
  2572. /* turn on/off the queue */
  2573. if (enable)
  2574. tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK |
  2575. I40E_QTX_ENA_QENA_STAT_MASK;
  2576. else
  2577. tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
  2578. wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
  2579. /* wait for the change to finish */
  2580. for (j = 0; j < 10; j++) {
  2581. tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
  2582. if (enable) {
  2583. if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
  2584. break;
  2585. } else {
  2586. if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
  2587. break;
  2588. }
  2589. udelay(10);
  2590. }
  2591. if (j >= 10) {
  2592. dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
  2593. pf_q, (enable ? "en" : "dis"));
  2594. return -ETIMEDOUT;
  2595. }
  2596. }
  2597. return 0;
  2598. }
  2599. /**
  2600. * i40e_vsi_control_rx - Start or stop a VSI's rings
  2601. * @vsi: the VSI being configured
  2602. * @enable: start or stop the rings
  2603. **/
  2604. static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
  2605. {
  2606. struct i40e_pf *pf = vsi->back;
  2607. struct i40e_hw *hw = &pf->hw;
  2608. int i, j, pf_q;
  2609. u32 rx_reg;
  2610. pf_q = vsi->base_queue;
  2611. for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
  2612. j = 1000;
  2613. do {
  2614. usleep_range(1000, 2000);
  2615. rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
  2616. } while (j-- && ((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT)
  2617. ^ (rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT)) & 1);
  2618. if (enable) {
  2619. /* is STAT set ? */
  2620. if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
  2621. continue;
  2622. } else {
  2623. /* is !STAT set ? */
  2624. if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
  2625. continue;
  2626. }
  2627. /* turn on/off the queue */
  2628. if (enable)
  2629. rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK |
  2630. I40E_QRX_ENA_QENA_STAT_MASK;
  2631. else
  2632. rx_reg &= ~(I40E_QRX_ENA_QENA_REQ_MASK |
  2633. I40E_QRX_ENA_QENA_STAT_MASK);
  2634. wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
  2635. /* wait for the change to finish */
  2636. for (j = 0; j < 10; j++) {
  2637. rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
  2638. if (enable) {
  2639. if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
  2640. break;
  2641. } else {
  2642. if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
  2643. break;
  2644. }
  2645. udelay(10);
  2646. }
  2647. if (j >= 10) {
  2648. dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
  2649. pf_q, (enable ? "en" : "dis"));
  2650. return -ETIMEDOUT;
  2651. }
  2652. }
  2653. return 0;
  2654. }
  2655. /**
  2656. * i40e_vsi_control_rings - Start or stop a VSI's rings
  2657. * @vsi: the VSI being configured
  2658. * @enable: start or stop the rings
  2659. **/
  2660. static int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
  2661. {
  2662. int ret;
  2663. /* do rx first for enable and last for disable */
  2664. if (request) {
  2665. ret = i40e_vsi_control_rx(vsi, request);
  2666. if (ret)
  2667. return ret;
  2668. ret = i40e_vsi_control_tx(vsi, request);
  2669. } else {
  2670. ret = i40e_vsi_control_tx(vsi, request);
  2671. if (ret)
  2672. return ret;
  2673. ret = i40e_vsi_control_rx(vsi, request);
  2674. }
  2675. return ret;
  2676. }
  2677. /**
  2678. * i40e_vsi_free_irq - Free the irq association with the OS
  2679. * @vsi: the VSI being configured
  2680. **/
  2681. static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
  2682. {
  2683. struct i40e_pf *pf = vsi->back;
  2684. struct i40e_hw *hw = &pf->hw;
  2685. int base = vsi->base_vector;
  2686. u32 val, qp;
  2687. int i;
  2688. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  2689. if (!vsi->q_vectors)
  2690. return;
  2691. for (i = 0; i < vsi->num_q_vectors; i++) {
  2692. u16 vector = i + base;
  2693. /* free only the irqs that were actually requested */
  2694. if (vsi->q_vectors[i].num_ringpairs == 0)
  2695. continue;
  2696. /* clear the affinity_mask in the IRQ descriptor */
  2697. irq_set_affinity_hint(pf->msix_entries[vector].vector,
  2698. NULL);
  2699. free_irq(pf->msix_entries[vector].vector,
  2700. &vsi->q_vectors[i]);
  2701. /* Tear down the interrupt queue link list
  2702. *
  2703. * We know that they come in pairs and always
  2704. * the Rx first, then the Tx. To clear the
  2705. * link list, stick the EOL value into the
  2706. * next_q field of the registers.
  2707. */
  2708. val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
  2709. qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
  2710. >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
  2711. val |= I40E_QUEUE_END_OF_LIST
  2712. << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
  2713. wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
  2714. while (qp != I40E_QUEUE_END_OF_LIST) {
  2715. u32 next;
  2716. val = rd32(hw, I40E_QINT_RQCTL(qp));
  2717. val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
  2718. I40E_QINT_RQCTL_MSIX0_INDX_MASK |
  2719. I40E_QINT_RQCTL_CAUSE_ENA_MASK |
  2720. I40E_QINT_RQCTL_INTEVENT_MASK);
  2721. val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
  2722. I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
  2723. wr32(hw, I40E_QINT_RQCTL(qp), val);
  2724. val = rd32(hw, I40E_QINT_TQCTL(qp));
  2725. next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
  2726. >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
  2727. val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
  2728. I40E_QINT_TQCTL_MSIX0_INDX_MASK |
  2729. I40E_QINT_TQCTL_CAUSE_ENA_MASK |
  2730. I40E_QINT_TQCTL_INTEVENT_MASK);
  2731. val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
  2732. I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
  2733. wr32(hw, I40E_QINT_TQCTL(qp), val);
  2734. qp = next;
  2735. }
  2736. }
  2737. } else {
  2738. free_irq(pf->pdev->irq, pf);
  2739. val = rd32(hw, I40E_PFINT_LNKLST0);
  2740. qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
  2741. >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
  2742. val |= I40E_QUEUE_END_OF_LIST
  2743. << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
  2744. wr32(hw, I40E_PFINT_LNKLST0, val);
  2745. val = rd32(hw, I40E_QINT_RQCTL(qp));
  2746. val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
  2747. I40E_QINT_RQCTL_MSIX0_INDX_MASK |
  2748. I40E_QINT_RQCTL_CAUSE_ENA_MASK |
  2749. I40E_QINT_RQCTL_INTEVENT_MASK);
  2750. val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
  2751. I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
  2752. wr32(hw, I40E_QINT_RQCTL(qp), val);
  2753. val = rd32(hw, I40E_QINT_TQCTL(qp));
  2754. val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
  2755. I40E_QINT_TQCTL_MSIX0_INDX_MASK |
  2756. I40E_QINT_TQCTL_CAUSE_ENA_MASK |
  2757. I40E_QINT_TQCTL_INTEVENT_MASK);
  2758. val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
  2759. I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
  2760. wr32(hw, I40E_QINT_TQCTL(qp), val);
  2761. }
  2762. }
  2763. /**
  2764. * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
  2765. * @vsi: the VSI being un-configured
  2766. *
  2767. * This frees the memory allocated to the q_vectors and
  2768. * deletes references to the NAPI struct.
  2769. **/
  2770. static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
  2771. {
  2772. int v_idx;
  2773. for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) {
  2774. struct i40e_q_vector *q_vector = &vsi->q_vectors[v_idx];
  2775. int r_idx;
  2776. if (!q_vector)
  2777. continue;
  2778. /* disassociate q_vector from rings */
  2779. for (r_idx = 0; r_idx < q_vector->tx.count; r_idx++)
  2780. q_vector->tx.ring[r_idx]->q_vector = NULL;
  2781. for (r_idx = 0; r_idx < q_vector->rx.count; r_idx++)
  2782. q_vector->rx.ring[r_idx]->q_vector = NULL;
  2783. /* only VSI w/ an associated netdev is set up w/ NAPI */
  2784. if (vsi->netdev)
  2785. netif_napi_del(&q_vector->napi);
  2786. }
  2787. kfree(vsi->q_vectors);
  2788. }
  2789. /**
  2790. * i40e_reset_interrupt_capability - Disable interrupt setup in OS
  2791. * @pf: board private structure
  2792. **/
  2793. static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
  2794. {
  2795. /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
  2796. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  2797. pci_disable_msix(pf->pdev);
  2798. kfree(pf->msix_entries);
  2799. pf->msix_entries = NULL;
  2800. } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
  2801. pci_disable_msi(pf->pdev);
  2802. }
  2803. pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
  2804. }
  2805. /**
  2806. * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
  2807. * @pf: board private structure
  2808. *
  2809. * We go through and clear interrupt specific resources and reset the structure
  2810. * to pre-load conditions
  2811. **/
  2812. static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
  2813. {
  2814. int i;
  2815. i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
  2816. for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
  2817. if (pf->vsi[i])
  2818. i40e_vsi_free_q_vectors(pf->vsi[i]);
  2819. i40e_reset_interrupt_capability(pf);
  2820. }
  2821. /**
  2822. * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
  2823. * @vsi: the VSI being configured
  2824. **/
  2825. static void i40e_napi_enable_all(struct i40e_vsi *vsi)
  2826. {
  2827. int q_idx;
  2828. if (!vsi->netdev)
  2829. return;
  2830. for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
  2831. napi_enable(&vsi->q_vectors[q_idx].napi);
  2832. }
  2833. /**
  2834. * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
  2835. * @vsi: the VSI being configured
  2836. **/
  2837. static void i40e_napi_disable_all(struct i40e_vsi *vsi)
  2838. {
  2839. int q_idx;
  2840. if (!vsi->netdev)
  2841. return;
  2842. for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
  2843. napi_disable(&vsi->q_vectors[q_idx].napi);
  2844. }
  2845. /**
  2846. * i40e_quiesce_vsi - Pause a given VSI
  2847. * @vsi: the VSI being paused
  2848. **/
  2849. static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
  2850. {
  2851. if (test_bit(__I40E_DOWN, &vsi->state))
  2852. return;
  2853. set_bit(__I40E_NEEDS_RESTART, &vsi->state);
  2854. if (vsi->netdev && netif_running(vsi->netdev)) {
  2855. vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
  2856. } else {
  2857. set_bit(__I40E_DOWN, &vsi->state);
  2858. i40e_down(vsi);
  2859. }
  2860. }
  2861. /**
  2862. * i40e_unquiesce_vsi - Resume a given VSI
  2863. * @vsi: the VSI being resumed
  2864. **/
  2865. static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
  2866. {
  2867. if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
  2868. return;
  2869. clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
  2870. if (vsi->netdev && netif_running(vsi->netdev))
  2871. vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
  2872. else
  2873. i40e_up(vsi); /* this clears the DOWN bit */
  2874. }
  2875. /**
  2876. * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
  2877. * @pf: the PF
  2878. **/
  2879. static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
  2880. {
  2881. int v;
  2882. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  2883. if (pf->vsi[v])
  2884. i40e_quiesce_vsi(pf->vsi[v]);
  2885. }
  2886. }
  2887. /**
  2888. * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
  2889. * @pf: the PF
  2890. **/
  2891. static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
  2892. {
  2893. int v;
  2894. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  2895. if (pf->vsi[v])
  2896. i40e_unquiesce_vsi(pf->vsi[v]);
  2897. }
  2898. }
  2899. /**
  2900. * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
  2901. * @dcbcfg: the corresponding DCBx configuration structure
  2902. *
  2903. * Return the number of TCs from given DCBx configuration
  2904. **/
  2905. static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
  2906. {
  2907. u8 num_tc = 0;
  2908. int i;
  2909. /* Scan the ETS Config Priority Table to find
  2910. * traffic class enabled for a given priority
  2911. * and use the traffic class index to get the
  2912. * number of traffic classes enabled
  2913. */
  2914. for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
  2915. if (dcbcfg->etscfg.prioritytable[i] > num_tc)
  2916. num_tc = dcbcfg->etscfg.prioritytable[i];
  2917. }
  2918. /* Traffic class index starts from zero so
  2919. * increment to return the actual count
  2920. */
  2921. return num_tc + 1;
  2922. }
  2923. /**
  2924. * i40e_dcb_get_enabled_tc - Get enabled traffic classes
  2925. * @dcbcfg: the corresponding DCBx configuration structure
  2926. *
  2927. * Query the current DCB configuration and return the number of
  2928. * traffic classes enabled from the given DCBX config
  2929. **/
  2930. static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
  2931. {
  2932. u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
  2933. u8 enabled_tc = 1;
  2934. u8 i;
  2935. for (i = 0; i < num_tc; i++)
  2936. enabled_tc |= 1 << i;
  2937. return enabled_tc;
  2938. }
  2939. /**
  2940. * i40e_pf_get_num_tc - Get enabled traffic classes for PF
  2941. * @pf: PF being queried
  2942. *
  2943. * Return number of traffic classes enabled for the given PF
  2944. **/
  2945. static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
  2946. {
  2947. struct i40e_hw *hw = &pf->hw;
  2948. u8 i, enabled_tc;
  2949. u8 num_tc = 0;
  2950. struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
  2951. /* If DCB is not enabled then always in single TC */
  2952. if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
  2953. return 1;
  2954. /* MFP mode return count of enabled TCs for this PF */
  2955. if (pf->flags & I40E_FLAG_MFP_ENABLED) {
  2956. enabled_tc = pf->hw.func_caps.enabled_tcmap;
  2957. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  2958. if (enabled_tc & (1 << i))
  2959. num_tc++;
  2960. }
  2961. return num_tc;
  2962. }
  2963. /* SFP mode will be enabled for all TCs on port */
  2964. return i40e_dcb_get_num_tc(dcbcfg);
  2965. }
  2966. /**
  2967. * i40e_pf_get_default_tc - Get bitmap for first enabled TC
  2968. * @pf: PF being queried
  2969. *
  2970. * Return a bitmap for first enabled traffic class for this PF.
  2971. **/
  2972. static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
  2973. {
  2974. u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
  2975. u8 i = 0;
  2976. if (!enabled_tc)
  2977. return 0x1; /* TC0 */
  2978. /* Find the first enabled TC */
  2979. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  2980. if (enabled_tc & (1 << i))
  2981. break;
  2982. }
  2983. return 1 << i;
  2984. }
  2985. /**
  2986. * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
  2987. * @pf: PF being queried
  2988. *
  2989. * Return a bitmap for enabled traffic classes for this PF.
  2990. **/
  2991. static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
  2992. {
  2993. /* If DCB is not enabled for this PF then just return default TC */
  2994. if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
  2995. return i40e_pf_get_default_tc(pf);
  2996. /* MFP mode will have enabled TCs set by FW */
  2997. if (pf->flags & I40E_FLAG_MFP_ENABLED)
  2998. return pf->hw.func_caps.enabled_tcmap;
  2999. /* SFP mode we want PF to be enabled for all TCs */
  3000. return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
  3001. }
  3002. /**
  3003. * i40e_vsi_get_bw_info - Query VSI BW Information
  3004. * @vsi: the VSI being queried
  3005. *
  3006. * Returns 0 on success, negative value on failure
  3007. **/
  3008. static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
  3009. {
  3010. struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
  3011. struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
  3012. struct i40e_pf *pf = vsi->back;
  3013. struct i40e_hw *hw = &pf->hw;
  3014. i40e_status aq_ret;
  3015. u32 tc_bw_max;
  3016. int i;
  3017. /* Get the VSI level BW configuration */
  3018. aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
  3019. if (aq_ret) {
  3020. dev_info(&pf->pdev->dev,
  3021. "couldn't get pf vsi bw config, err %d, aq_err %d\n",
  3022. aq_ret, pf->hw.aq.asq_last_status);
  3023. return -EINVAL;
  3024. }
  3025. /* Get the VSI level BW configuration per TC */
  3026. aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
  3027. NULL);
  3028. if (aq_ret) {
  3029. dev_info(&pf->pdev->dev,
  3030. "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
  3031. aq_ret, pf->hw.aq.asq_last_status);
  3032. return -EINVAL;
  3033. }
  3034. if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
  3035. dev_info(&pf->pdev->dev,
  3036. "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
  3037. bw_config.tc_valid_bits,
  3038. bw_ets_config.tc_valid_bits);
  3039. /* Still continuing */
  3040. }
  3041. vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
  3042. vsi->bw_max_quanta = bw_config.max_bw;
  3043. tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
  3044. (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
  3045. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  3046. vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
  3047. vsi->bw_ets_limit_credits[i] =
  3048. le16_to_cpu(bw_ets_config.credits[i]);
  3049. /* 3 bits out of 4 for each TC */
  3050. vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
  3051. }
  3052. return 0;
  3053. }
  3054. /**
  3055. * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
  3056. * @vsi: the VSI being configured
  3057. * @enabled_tc: TC bitmap
  3058. * @bw_credits: BW shared credits per TC
  3059. *
  3060. * Returns 0 on success, negative value on failure
  3061. **/
  3062. static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
  3063. u8 *bw_share)
  3064. {
  3065. struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
  3066. i40e_status aq_ret;
  3067. int i;
  3068. bw_data.tc_valid_bits = enabled_tc;
  3069. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
  3070. bw_data.tc_bw_credits[i] = bw_share[i];
  3071. aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
  3072. NULL);
  3073. if (aq_ret) {
  3074. dev_info(&vsi->back->pdev->dev,
  3075. "%s: AQ command Config VSI BW allocation per TC failed = %d\n",
  3076. __func__, vsi->back->hw.aq.asq_last_status);
  3077. return -EINVAL;
  3078. }
  3079. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
  3080. vsi->info.qs_handle[i] = bw_data.qs_handles[i];
  3081. return 0;
  3082. }
  3083. /**
  3084. * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
  3085. * @vsi: the VSI being configured
  3086. * @enabled_tc: TC map to be enabled
  3087. *
  3088. **/
  3089. static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
  3090. {
  3091. struct net_device *netdev = vsi->netdev;
  3092. struct i40e_pf *pf = vsi->back;
  3093. struct i40e_hw *hw = &pf->hw;
  3094. u8 netdev_tc = 0;
  3095. int i;
  3096. struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
  3097. if (!netdev)
  3098. return;
  3099. if (!enabled_tc) {
  3100. netdev_reset_tc(netdev);
  3101. return;
  3102. }
  3103. /* Set up actual enabled TCs on the VSI */
  3104. if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
  3105. return;
  3106. /* set per TC queues for the VSI */
  3107. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  3108. /* Only set TC queues for enabled tcs
  3109. *
  3110. * e.g. For a VSI that has TC0 and TC3 enabled the
  3111. * enabled_tc bitmap would be 0x00001001; the driver
  3112. * will set the numtc for netdev as 2 that will be
  3113. * referenced by the netdev layer as TC 0 and 1.
  3114. */
  3115. if (vsi->tc_config.enabled_tc & (1 << i))
  3116. netdev_set_tc_queue(netdev,
  3117. vsi->tc_config.tc_info[i].netdev_tc,
  3118. vsi->tc_config.tc_info[i].qcount,
  3119. vsi->tc_config.tc_info[i].qoffset);
  3120. }
  3121. /* Assign UP2TC map for the VSI */
  3122. for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
  3123. /* Get the actual TC# for the UP */
  3124. u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
  3125. /* Get the mapped netdev TC# for the UP */
  3126. netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
  3127. netdev_set_prio_tc_map(netdev, i, netdev_tc);
  3128. }
  3129. }
  3130. /**
  3131. * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
  3132. * @vsi: the VSI being configured
  3133. * @ctxt: the ctxt buffer returned from AQ VSI update param command
  3134. **/
  3135. static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
  3136. struct i40e_vsi_context *ctxt)
  3137. {
  3138. /* copy just the sections touched not the entire info
  3139. * since not all sections are valid as returned by
  3140. * update vsi params
  3141. */
  3142. vsi->info.mapping_flags = ctxt->info.mapping_flags;
  3143. memcpy(&vsi->info.queue_mapping,
  3144. &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
  3145. memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
  3146. sizeof(vsi->info.tc_mapping));
  3147. }
  3148. /**
  3149. * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
  3150. * @vsi: VSI to be configured
  3151. * @enabled_tc: TC bitmap
  3152. *
  3153. * This configures a particular VSI for TCs that are mapped to the
  3154. * given TC bitmap. It uses default bandwidth share for TCs across
  3155. * VSIs to configure TC for a particular VSI.
  3156. *
  3157. * NOTE:
  3158. * It is expected that the VSI queues have been quisced before calling
  3159. * this function.
  3160. **/
  3161. static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
  3162. {
  3163. u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
  3164. struct i40e_vsi_context ctxt;
  3165. int ret = 0;
  3166. int i;
  3167. /* Check if enabled_tc is same as existing or new TCs */
  3168. if (vsi->tc_config.enabled_tc == enabled_tc)
  3169. return ret;
  3170. /* Enable ETS TCs with equal BW Share for now across all VSIs */
  3171. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  3172. if (enabled_tc & (1 << i))
  3173. bw_share[i] = 1;
  3174. }
  3175. ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
  3176. if (ret) {
  3177. dev_info(&vsi->back->pdev->dev,
  3178. "Failed configuring TC map %d for VSI %d\n",
  3179. enabled_tc, vsi->seid);
  3180. goto out;
  3181. }
  3182. /* Update Queue Pairs Mapping for currently enabled UPs */
  3183. ctxt.seid = vsi->seid;
  3184. ctxt.pf_num = vsi->back->hw.pf_id;
  3185. ctxt.vf_num = 0;
  3186. ctxt.uplink_seid = vsi->uplink_seid;
  3187. memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
  3188. i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
  3189. /* Update the VSI after updating the VSI queue-mapping information */
  3190. ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
  3191. if (ret) {
  3192. dev_info(&vsi->back->pdev->dev,
  3193. "update vsi failed, aq_err=%d\n",
  3194. vsi->back->hw.aq.asq_last_status);
  3195. goto out;
  3196. }
  3197. /* update the local VSI info with updated queue map */
  3198. i40e_vsi_update_queue_map(vsi, &ctxt);
  3199. vsi->info.valid_sections = 0;
  3200. /* Update current VSI BW information */
  3201. ret = i40e_vsi_get_bw_info(vsi);
  3202. if (ret) {
  3203. dev_info(&vsi->back->pdev->dev,
  3204. "Failed updating vsi bw info, aq_err=%d\n",
  3205. vsi->back->hw.aq.asq_last_status);
  3206. goto out;
  3207. }
  3208. /* Update the netdev TC setup */
  3209. i40e_vsi_config_netdev_tc(vsi, enabled_tc);
  3210. out:
  3211. return ret;
  3212. }
  3213. /**
  3214. * i40e_up_complete - Finish the last steps of bringing up a connection
  3215. * @vsi: the VSI being configured
  3216. **/
  3217. static int i40e_up_complete(struct i40e_vsi *vsi)
  3218. {
  3219. struct i40e_pf *pf = vsi->back;
  3220. int err;
  3221. if (pf->flags & I40E_FLAG_MSIX_ENABLED)
  3222. i40e_vsi_configure_msix(vsi);
  3223. else
  3224. i40e_configure_msi_and_legacy(vsi);
  3225. /* start rings */
  3226. err = i40e_vsi_control_rings(vsi, true);
  3227. if (err)
  3228. return err;
  3229. clear_bit(__I40E_DOWN, &vsi->state);
  3230. i40e_napi_enable_all(vsi);
  3231. i40e_vsi_enable_irq(vsi);
  3232. if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
  3233. (vsi->netdev)) {
  3234. netdev_info(vsi->netdev, "NIC Link is Up\n");
  3235. netif_tx_start_all_queues(vsi->netdev);
  3236. netif_carrier_on(vsi->netdev);
  3237. } else if (vsi->netdev) {
  3238. netdev_info(vsi->netdev, "NIC Link is Down\n");
  3239. }
  3240. i40e_service_event_schedule(pf);
  3241. return 0;
  3242. }
  3243. /**
  3244. * i40e_vsi_reinit_locked - Reset the VSI
  3245. * @vsi: the VSI being configured
  3246. *
  3247. * Rebuild the ring structs after some configuration
  3248. * has changed, e.g. MTU size.
  3249. **/
  3250. static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
  3251. {
  3252. struct i40e_pf *pf = vsi->back;
  3253. WARN_ON(in_interrupt());
  3254. while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
  3255. usleep_range(1000, 2000);
  3256. i40e_down(vsi);
  3257. /* Give a VF some time to respond to the reset. The
  3258. * two second wait is based upon the watchdog cycle in
  3259. * the VF driver.
  3260. */
  3261. if (vsi->type == I40E_VSI_SRIOV)
  3262. msleep(2000);
  3263. i40e_up(vsi);
  3264. clear_bit(__I40E_CONFIG_BUSY, &pf->state);
  3265. }
  3266. /**
  3267. * i40e_up - Bring the connection back up after being down
  3268. * @vsi: the VSI being configured
  3269. **/
  3270. int i40e_up(struct i40e_vsi *vsi)
  3271. {
  3272. int err;
  3273. err = i40e_vsi_configure(vsi);
  3274. if (!err)
  3275. err = i40e_up_complete(vsi);
  3276. return err;
  3277. }
  3278. /**
  3279. * i40e_down - Shutdown the connection processing
  3280. * @vsi: the VSI being stopped
  3281. **/
  3282. void i40e_down(struct i40e_vsi *vsi)
  3283. {
  3284. int i;
  3285. /* It is assumed that the caller of this function
  3286. * sets the vsi->state __I40E_DOWN bit.
  3287. */
  3288. if (vsi->netdev) {
  3289. netif_carrier_off(vsi->netdev);
  3290. netif_tx_disable(vsi->netdev);
  3291. }
  3292. i40e_vsi_disable_irq(vsi);
  3293. i40e_vsi_control_rings(vsi, false);
  3294. i40e_napi_disable_all(vsi);
  3295. for (i = 0; i < vsi->num_queue_pairs; i++) {
  3296. i40e_clean_tx_ring(&vsi->tx_rings[i]);
  3297. i40e_clean_rx_ring(&vsi->rx_rings[i]);
  3298. }
  3299. }
  3300. /**
  3301. * i40e_setup_tc - configure multiple traffic classes
  3302. * @netdev: net device to configure
  3303. * @tc: number of traffic classes to enable
  3304. **/
  3305. static int i40e_setup_tc(struct net_device *netdev, u8 tc)
  3306. {
  3307. struct i40e_netdev_priv *np = netdev_priv(netdev);
  3308. struct i40e_vsi *vsi = np->vsi;
  3309. struct i40e_pf *pf = vsi->back;
  3310. u8 enabled_tc = 0;
  3311. int ret = -EINVAL;
  3312. int i;
  3313. /* Check if DCB enabled to continue */
  3314. if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
  3315. netdev_info(netdev, "DCB is not enabled for adapter\n");
  3316. goto exit;
  3317. }
  3318. /* Check if MFP enabled */
  3319. if (pf->flags & I40E_FLAG_MFP_ENABLED) {
  3320. netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
  3321. goto exit;
  3322. }
  3323. /* Check whether tc count is within enabled limit */
  3324. if (tc > i40e_pf_get_num_tc(pf)) {
  3325. netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
  3326. goto exit;
  3327. }
  3328. /* Generate TC map for number of tc requested */
  3329. for (i = 0; i < tc; i++)
  3330. enabled_tc |= (1 << i);
  3331. /* Requesting same TC configuration as already enabled */
  3332. if (enabled_tc == vsi->tc_config.enabled_tc)
  3333. return 0;
  3334. /* Quiesce VSI queues */
  3335. i40e_quiesce_vsi(vsi);
  3336. /* Configure VSI for enabled TCs */
  3337. ret = i40e_vsi_config_tc(vsi, enabled_tc);
  3338. if (ret) {
  3339. netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
  3340. vsi->seid);
  3341. goto exit;
  3342. }
  3343. /* Unquiesce VSI */
  3344. i40e_unquiesce_vsi(vsi);
  3345. exit:
  3346. return ret;
  3347. }
  3348. /**
  3349. * i40e_open - Called when a network interface is made active
  3350. * @netdev: network interface device structure
  3351. *
  3352. * The open entry point is called when a network interface is made
  3353. * active by the system (IFF_UP). At this point all resources needed
  3354. * for transmit and receive operations are allocated, the interrupt
  3355. * handler is registered with the OS, the netdev watchdog subtask is
  3356. * enabled, and the stack is notified that the interface is ready.
  3357. *
  3358. * Returns 0 on success, negative value on failure
  3359. **/
  3360. static int i40e_open(struct net_device *netdev)
  3361. {
  3362. struct i40e_netdev_priv *np = netdev_priv(netdev);
  3363. struct i40e_vsi *vsi = np->vsi;
  3364. struct i40e_pf *pf = vsi->back;
  3365. char int_name[IFNAMSIZ];
  3366. int err;
  3367. /* disallow open during test */
  3368. if (test_bit(__I40E_TESTING, &pf->state))
  3369. return -EBUSY;
  3370. netif_carrier_off(netdev);
  3371. /* allocate descriptors */
  3372. err = i40e_vsi_setup_tx_resources(vsi);
  3373. if (err)
  3374. goto err_setup_tx;
  3375. err = i40e_vsi_setup_rx_resources(vsi);
  3376. if (err)
  3377. goto err_setup_rx;
  3378. err = i40e_vsi_configure(vsi);
  3379. if (err)
  3380. goto err_setup_rx;
  3381. snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
  3382. dev_driver_string(&pf->pdev->dev), netdev->name);
  3383. err = i40e_vsi_request_irq(vsi, int_name);
  3384. if (err)
  3385. goto err_setup_rx;
  3386. err = i40e_up_complete(vsi);
  3387. if (err)
  3388. goto err_up_complete;
  3389. if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
  3390. err = i40e_aq_set_vsi_broadcast(&pf->hw, vsi->seid, true, NULL);
  3391. if (err)
  3392. netdev_info(netdev,
  3393. "couldn't set broadcast err %d aq_err %d\n",
  3394. err, pf->hw.aq.asq_last_status);
  3395. }
  3396. return 0;
  3397. err_up_complete:
  3398. i40e_down(vsi);
  3399. i40e_vsi_free_irq(vsi);
  3400. err_setup_rx:
  3401. i40e_vsi_free_rx_resources(vsi);
  3402. err_setup_tx:
  3403. i40e_vsi_free_tx_resources(vsi);
  3404. if (vsi == pf->vsi[pf->lan_vsi])
  3405. i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
  3406. return err;
  3407. }
  3408. /**
  3409. * i40e_close - Disables a network interface
  3410. * @netdev: network interface device structure
  3411. *
  3412. * The close entry point is called when an interface is de-activated
  3413. * by the OS. The hardware is still under the driver's control, but
  3414. * this netdev interface is disabled.
  3415. *
  3416. * Returns 0, this is not allowed to fail
  3417. **/
  3418. static int i40e_close(struct net_device *netdev)
  3419. {
  3420. struct i40e_netdev_priv *np = netdev_priv(netdev);
  3421. struct i40e_vsi *vsi = np->vsi;
  3422. if (test_and_set_bit(__I40E_DOWN, &vsi->state))
  3423. return 0;
  3424. i40e_down(vsi);
  3425. i40e_vsi_free_irq(vsi);
  3426. i40e_vsi_free_tx_resources(vsi);
  3427. i40e_vsi_free_rx_resources(vsi);
  3428. return 0;
  3429. }
  3430. /**
  3431. * i40e_do_reset - Start a PF or Core Reset sequence
  3432. * @pf: board private structure
  3433. * @reset_flags: which reset is requested
  3434. *
  3435. * The essential difference in resets is that the PF Reset
  3436. * doesn't clear the packet buffers, doesn't reset the PE
  3437. * firmware, and doesn't bother the other PFs on the chip.
  3438. **/
  3439. void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
  3440. {
  3441. u32 val;
  3442. WARN_ON(in_interrupt());
  3443. /* do the biggest reset indicated */
  3444. if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
  3445. /* Request a Global Reset
  3446. *
  3447. * This will start the chip's countdown to the actual full
  3448. * chip reset event, and a warning interrupt to be sent
  3449. * to all PFs, including the requestor. Our handler
  3450. * for the warning interrupt will deal with the shutdown
  3451. * and recovery of the switch setup.
  3452. */
  3453. dev_info(&pf->pdev->dev, "GlobalR requested\n");
  3454. val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
  3455. val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
  3456. wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
  3457. } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
  3458. /* Request a Core Reset
  3459. *
  3460. * Same as Global Reset, except does *not* include the MAC/PHY
  3461. */
  3462. dev_info(&pf->pdev->dev, "CoreR requested\n");
  3463. val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
  3464. val |= I40E_GLGEN_RTRIG_CORER_MASK;
  3465. wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
  3466. i40e_flush(&pf->hw);
  3467. } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
  3468. /* Request a PF Reset
  3469. *
  3470. * Resets only the PF-specific registers
  3471. *
  3472. * This goes directly to the tear-down and rebuild of
  3473. * the switch, since we need to do all the recovery as
  3474. * for the Core Reset.
  3475. */
  3476. dev_info(&pf->pdev->dev, "PFR requested\n");
  3477. i40e_handle_reset_warning(pf);
  3478. } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
  3479. int v;
  3480. /* Find the VSI(s) that requested a re-init */
  3481. dev_info(&pf->pdev->dev,
  3482. "VSI reinit requested\n");
  3483. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  3484. struct i40e_vsi *vsi = pf->vsi[v];
  3485. if (vsi != NULL &&
  3486. test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
  3487. i40e_vsi_reinit_locked(pf->vsi[v]);
  3488. clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
  3489. }
  3490. }
  3491. /* no further action needed, so return now */
  3492. return;
  3493. } else {
  3494. dev_info(&pf->pdev->dev,
  3495. "bad reset request 0x%08x\n", reset_flags);
  3496. return;
  3497. }
  3498. }
  3499. /**
  3500. * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
  3501. * @pf: board private structure
  3502. * @e: event info posted on ARQ
  3503. *
  3504. * Handler for LAN Queue Overflow Event generated by the firmware for PF
  3505. * and VF queues
  3506. **/
  3507. static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
  3508. struct i40e_arq_event_info *e)
  3509. {
  3510. struct i40e_aqc_lan_overflow *data =
  3511. (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
  3512. u32 queue = le32_to_cpu(data->prtdcb_rupto);
  3513. u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
  3514. struct i40e_hw *hw = &pf->hw;
  3515. struct i40e_vf *vf;
  3516. u16 vf_id;
  3517. dev_info(&pf->pdev->dev, "%s: Rx Queue Number = %d QTX_CTL=0x%08x\n",
  3518. __func__, queue, qtx_ctl);
  3519. /* Queue belongs to VF, find the VF and issue VF reset */
  3520. if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
  3521. >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
  3522. vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
  3523. >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
  3524. vf_id -= hw->func_caps.vf_base_id;
  3525. vf = &pf->vf[vf_id];
  3526. i40e_vc_notify_vf_reset(vf);
  3527. /* Allow VF to process pending reset notification */
  3528. msleep(20);
  3529. i40e_reset_vf(vf, false);
  3530. }
  3531. }
  3532. /**
  3533. * i40e_service_event_complete - Finish up the service event
  3534. * @pf: board private structure
  3535. **/
  3536. static void i40e_service_event_complete(struct i40e_pf *pf)
  3537. {
  3538. BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
  3539. /* flush memory to make sure state is correct before next watchog */
  3540. smp_mb__before_clear_bit();
  3541. clear_bit(__I40E_SERVICE_SCHED, &pf->state);
  3542. }
  3543. /**
  3544. * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
  3545. * @pf: board private structure
  3546. **/
  3547. static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
  3548. {
  3549. if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
  3550. return;
  3551. pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
  3552. /* if interface is down do nothing */
  3553. if (test_bit(__I40E_DOWN, &pf->state))
  3554. return;
  3555. }
  3556. /**
  3557. * i40e_vsi_link_event - notify VSI of a link event
  3558. * @vsi: vsi to be notified
  3559. * @link_up: link up or down
  3560. **/
  3561. static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
  3562. {
  3563. if (!vsi)
  3564. return;
  3565. switch (vsi->type) {
  3566. case I40E_VSI_MAIN:
  3567. if (!vsi->netdev || !vsi->netdev_registered)
  3568. break;
  3569. if (link_up) {
  3570. netif_carrier_on(vsi->netdev);
  3571. netif_tx_wake_all_queues(vsi->netdev);
  3572. } else {
  3573. netif_carrier_off(vsi->netdev);
  3574. netif_tx_stop_all_queues(vsi->netdev);
  3575. }
  3576. break;
  3577. case I40E_VSI_SRIOV:
  3578. break;
  3579. case I40E_VSI_VMDQ2:
  3580. case I40E_VSI_CTRL:
  3581. case I40E_VSI_MIRROR:
  3582. default:
  3583. /* there is no notification for other VSIs */
  3584. break;
  3585. }
  3586. }
  3587. /**
  3588. * i40e_veb_link_event - notify elements on the veb of a link event
  3589. * @veb: veb to be notified
  3590. * @link_up: link up or down
  3591. **/
  3592. static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
  3593. {
  3594. struct i40e_pf *pf;
  3595. int i;
  3596. if (!veb || !veb->pf)
  3597. return;
  3598. pf = veb->pf;
  3599. /* depth first... */
  3600. for (i = 0; i < I40E_MAX_VEB; i++)
  3601. if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
  3602. i40e_veb_link_event(pf->veb[i], link_up);
  3603. /* ... now the local VSIs */
  3604. for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
  3605. if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
  3606. i40e_vsi_link_event(pf->vsi[i], link_up);
  3607. }
  3608. /**
  3609. * i40e_link_event - Update netif_carrier status
  3610. * @pf: board private structure
  3611. **/
  3612. static void i40e_link_event(struct i40e_pf *pf)
  3613. {
  3614. bool new_link, old_link;
  3615. new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
  3616. old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
  3617. if (new_link == old_link)
  3618. return;
  3619. if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
  3620. netdev_info(pf->vsi[pf->lan_vsi]->netdev,
  3621. "NIC Link is %s\n", (new_link ? "Up" : "Down"));
  3622. /* Notify the base of the switch tree connected to
  3623. * the link. Floating VEBs are not notified.
  3624. */
  3625. if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
  3626. i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
  3627. else
  3628. i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
  3629. if (pf->vf)
  3630. i40e_vc_notify_link_state(pf);
  3631. }
  3632. /**
  3633. * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
  3634. * @pf: board private structure
  3635. *
  3636. * Set the per-queue flags to request a check for stuck queues in the irq
  3637. * clean functions, then force interrupts to be sure the irq clean is called.
  3638. **/
  3639. static void i40e_check_hang_subtask(struct i40e_pf *pf)
  3640. {
  3641. int i, v;
  3642. /* If we're down or resetting, just bail */
  3643. if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
  3644. return;
  3645. /* for each VSI/netdev
  3646. * for each Tx queue
  3647. * set the check flag
  3648. * for each q_vector
  3649. * force an interrupt
  3650. */
  3651. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  3652. struct i40e_vsi *vsi = pf->vsi[v];
  3653. int armed = 0;
  3654. if (!pf->vsi[v] ||
  3655. test_bit(__I40E_DOWN, &vsi->state) ||
  3656. (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
  3657. continue;
  3658. for (i = 0; i < vsi->num_queue_pairs; i++) {
  3659. set_check_for_tx_hang(&vsi->tx_rings[i]);
  3660. if (test_bit(__I40E_HANG_CHECK_ARMED,
  3661. &vsi->tx_rings[i].state))
  3662. armed++;
  3663. }
  3664. if (armed) {
  3665. if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
  3666. wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
  3667. (I40E_PFINT_DYN_CTL0_INTENA_MASK |
  3668. I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
  3669. } else {
  3670. u16 vec = vsi->base_vector - 1;
  3671. u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
  3672. I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
  3673. for (i = 0; i < vsi->num_q_vectors; i++, vec++)
  3674. wr32(&vsi->back->hw,
  3675. I40E_PFINT_DYN_CTLN(vec), val);
  3676. }
  3677. i40e_flush(&vsi->back->hw);
  3678. }
  3679. }
  3680. }
  3681. /**
  3682. * i40e_watchdog_subtask - Check and bring link up
  3683. * @pf: board private structure
  3684. **/
  3685. static void i40e_watchdog_subtask(struct i40e_pf *pf)
  3686. {
  3687. int i;
  3688. /* if interface is down do nothing */
  3689. if (test_bit(__I40E_DOWN, &pf->state) ||
  3690. test_bit(__I40E_CONFIG_BUSY, &pf->state))
  3691. return;
  3692. /* Update the stats for active netdevs so the network stack
  3693. * can look at updated numbers whenever it cares to
  3694. */
  3695. for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
  3696. if (pf->vsi[i] && pf->vsi[i]->netdev)
  3697. i40e_update_stats(pf->vsi[i]);
  3698. /* Update the stats for the active switching components */
  3699. for (i = 0; i < I40E_MAX_VEB; i++)
  3700. if (pf->veb[i])
  3701. i40e_update_veb_stats(pf->veb[i]);
  3702. }
  3703. /**
  3704. * i40e_reset_subtask - Set up for resetting the device and driver
  3705. * @pf: board private structure
  3706. **/
  3707. static void i40e_reset_subtask(struct i40e_pf *pf)
  3708. {
  3709. u32 reset_flags = 0;
  3710. if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
  3711. reset_flags |= (1 << __I40E_REINIT_REQUESTED);
  3712. clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
  3713. }
  3714. if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
  3715. reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
  3716. clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
  3717. }
  3718. if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
  3719. reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
  3720. clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
  3721. }
  3722. if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
  3723. reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
  3724. clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
  3725. }
  3726. /* If there's a recovery already waiting, it takes
  3727. * precedence before starting a new reset sequence.
  3728. */
  3729. if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
  3730. i40e_handle_reset_warning(pf);
  3731. return;
  3732. }
  3733. /* If we're already down or resetting, just bail */
  3734. if (reset_flags &&
  3735. !test_bit(__I40E_DOWN, &pf->state) &&
  3736. !test_bit(__I40E_CONFIG_BUSY, &pf->state))
  3737. i40e_do_reset(pf, reset_flags);
  3738. }
  3739. /**
  3740. * i40e_handle_link_event - Handle link event
  3741. * @pf: board private structure
  3742. * @e: event info posted on ARQ
  3743. **/
  3744. static void i40e_handle_link_event(struct i40e_pf *pf,
  3745. struct i40e_arq_event_info *e)
  3746. {
  3747. struct i40e_hw *hw = &pf->hw;
  3748. struct i40e_aqc_get_link_status *status =
  3749. (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
  3750. struct i40e_link_status *hw_link_info = &hw->phy.link_info;
  3751. /* save off old link status information */
  3752. memcpy(&pf->hw.phy.link_info_old, hw_link_info,
  3753. sizeof(pf->hw.phy.link_info_old));
  3754. /* update link status */
  3755. hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
  3756. hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
  3757. hw_link_info->link_info = status->link_info;
  3758. hw_link_info->an_info = status->an_info;
  3759. hw_link_info->ext_info = status->ext_info;
  3760. hw_link_info->lse_enable =
  3761. le16_to_cpu(status->command_flags) &
  3762. I40E_AQ_LSE_ENABLE;
  3763. /* process the event */
  3764. i40e_link_event(pf);
  3765. /* Do a new status request to re-enable LSE reporting
  3766. * and load new status information into the hw struct,
  3767. * then see if the status changed while processing the
  3768. * initial event.
  3769. */
  3770. i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
  3771. i40e_link_event(pf);
  3772. }
  3773. /**
  3774. * i40e_clean_adminq_subtask - Clean the AdminQ rings
  3775. * @pf: board private structure
  3776. **/
  3777. static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
  3778. {
  3779. struct i40e_arq_event_info event;
  3780. struct i40e_hw *hw = &pf->hw;
  3781. u16 pending, i = 0;
  3782. i40e_status ret;
  3783. u16 opcode;
  3784. u32 val;
  3785. if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
  3786. return;
  3787. event.msg_size = I40E_MAX_AQ_BUF_SIZE;
  3788. event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
  3789. if (!event.msg_buf)
  3790. return;
  3791. do {
  3792. ret = i40e_clean_arq_element(hw, &event, &pending);
  3793. if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
  3794. dev_info(&pf->pdev->dev, "No ARQ event found\n");
  3795. break;
  3796. } else if (ret) {
  3797. dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
  3798. break;
  3799. }
  3800. opcode = le16_to_cpu(event.desc.opcode);
  3801. switch (opcode) {
  3802. case i40e_aqc_opc_get_link_status:
  3803. i40e_handle_link_event(pf, &event);
  3804. break;
  3805. case i40e_aqc_opc_send_msg_to_pf:
  3806. ret = i40e_vc_process_vf_msg(pf,
  3807. le16_to_cpu(event.desc.retval),
  3808. le32_to_cpu(event.desc.cookie_high),
  3809. le32_to_cpu(event.desc.cookie_low),
  3810. event.msg_buf,
  3811. event.msg_size);
  3812. break;
  3813. case i40e_aqc_opc_lldp_update_mib:
  3814. dev_info(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
  3815. break;
  3816. case i40e_aqc_opc_event_lan_overflow:
  3817. dev_info(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
  3818. i40e_handle_lan_overflow_event(pf, &event);
  3819. break;
  3820. default:
  3821. dev_info(&pf->pdev->dev,
  3822. "ARQ Error: Unknown event %d received\n",
  3823. event.desc.opcode);
  3824. break;
  3825. }
  3826. } while (pending && (i++ < pf->adminq_work_limit));
  3827. clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
  3828. /* re-enable Admin queue interrupt cause */
  3829. val = rd32(hw, I40E_PFINT_ICR0_ENA);
  3830. val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
  3831. wr32(hw, I40E_PFINT_ICR0_ENA, val);
  3832. i40e_flush(hw);
  3833. kfree(event.msg_buf);
  3834. }
  3835. /**
  3836. * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
  3837. * @veb: pointer to the VEB instance
  3838. *
  3839. * This is a recursive function that first builds the attached VSIs then
  3840. * recurses in to build the next layer of VEB. We track the connections
  3841. * through our own index numbers because the seid's from the HW could
  3842. * change across the reset.
  3843. **/
  3844. static int i40e_reconstitute_veb(struct i40e_veb *veb)
  3845. {
  3846. struct i40e_vsi *ctl_vsi = NULL;
  3847. struct i40e_pf *pf = veb->pf;
  3848. int v, veb_idx;
  3849. int ret;
  3850. /* build VSI that owns this VEB, temporarily attached to base VEB */
  3851. for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
  3852. if (pf->vsi[v] &&
  3853. pf->vsi[v]->veb_idx == veb->idx &&
  3854. pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
  3855. ctl_vsi = pf->vsi[v];
  3856. break;
  3857. }
  3858. }
  3859. if (!ctl_vsi) {
  3860. dev_info(&pf->pdev->dev,
  3861. "missing owner VSI for veb_idx %d\n", veb->idx);
  3862. ret = -ENOENT;
  3863. goto end_reconstitute;
  3864. }
  3865. if (ctl_vsi != pf->vsi[pf->lan_vsi])
  3866. ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
  3867. ret = i40e_add_vsi(ctl_vsi);
  3868. if (ret) {
  3869. dev_info(&pf->pdev->dev,
  3870. "rebuild of owner VSI failed: %d\n", ret);
  3871. goto end_reconstitute;
  3872. }
  3873. i40e_vsi_reset_stats(ctl_vsi);
  3874. /* create the VEB in the switch and move the VSI onto the VEB */
  3875. ret = i40e_add_veb(veb, ctl_vsi);
  3876. if (ret)
  3877. goto end_reconstitute;
  3878. /* create the remaining VSIs attached to this VEB */
  3879. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  3880. if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
  3881. continue;
  3882. if (pf->vsi[v]->veb_idx == veb->idx) {
  3883. struct i40e_vsi *vsi = pf->vsi[v];
  3884. vsi->uplink_seid = veb->seid;
  3885. ret = i40e_add_vsi(vsi);
  3886. if (ret) {
  3887. dev_info(&pf->pdev->dev,
  3888. "rebuild of vsi_idx %d failed: %d\n",
  3889. v, ret);
  3890. goto end_reconstitute;
  3891. }
  3892. i40e_vsi_reset_stats(vsi);
  3893. }
  3894. }
  3895. /* create any VEBs attached to this VEB - RECURSION */
  3896. for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
  3897. if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
  3898. pf->veb[veb_idx]->uplink_seid = veb->seid;
  3899. ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
  3900. if (ret)
  3901. break;
  3902. }
  3903. }
  3904. end_reconstitute:
  3905. return ret;
  3906. }
  3907. /**
  3908. * i40e_get_capabilities - get info about the HW
  3909. * @pf: the PF struct
  3910. **/
  3911. static int i40e_get_capabilities(struct i40e_pf *pf)
  3912. {
  3913. struct i40e_aqc_list_capabilities_element_resp *cap_buf;
  3914. u16 data_size;
  3915. int buf_len;
  3916. int err;
  3917. buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
  3918. do {
  3919. cap_buf = kzalloc(buf_len, GFP_KERNEL);
  3920. if (!cap_buf)
  3921. return -ENOMEM;
  3922. /* this loads the data into the hw struct for us */
  3923. err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
  3924. &data_size,
  3925. i40e_aqc_opc_list_func_capabilities,
  3926. NULL);
  3927. /* data loaded, buffer no longer needed */
  3928. kfree(cap_buf);
  3929. if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
  3930. /* retry with a larger buffer */
  3931. buf_len = data_size;
  3932. } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
  3933. dev_info(&pf->pdev->dev,
  3934. "capability discovery failed: aq=%d\n",
  3935. pf->hw.aq.asq_last_status);
  3936. return -ENODEV;
  3937. }
  3938. } while (err);
  3939. if (pf->hw.debug_mask & I40E_DEBUG_USER)
  3940. dev_info(&pf->pdev->dev,
  3941. "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
  3942. pf->hw.pf_id, pf->hw.func_caps.num_vfs,
  3943. pf->hw.func_caps.num_msix_vectors,
  3944. pf->hw.func_caps.num_msix_vectors_vf,
  3945. pf->hw.func_caps.fd_filters_guaranteed,
  3946. pf->hw.func_caps.fd_filters_best_effort,
  3947. pf->hw.func_caps.num_tx_qp,
  3948. pf->hw.func_caps.num_vsis);
  3949. return 0;
  3950. }
  3951. /**
  3952. * i40e_fdir_setup - initialize the Flow Director resources
  3953. * @pf: board private structure
  3954. **/
  3955. static void i40e_fdir_setup(struct i40e_pf *pf)
  3956. {
  3957. struct i40e_vsi *vsi;
  3958. bool new_vsi = false;
  3959. int err, i;
  3960. if (!(pf->flags & (I40E_FLAG_FDIR_ENABLED|I40E_FLAG_FDIR_ATR_ENABLED)))
  3961. return;
  3962. pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
  3963. /* find existing or make new FDIR VSI */
  3964. vsi = NULL;
  3965. for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
  3966. if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
  3967. vsi = pf->vsi[i];
  3968. if (!vsi) {
  3969. vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->mac_seid, 0);
  3970. if (!vsi) {
  3971. dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
  3972. pf->flags &= ~I40E_FLAG_FDIR_ENABLED;
  3973. return;
  3974. }
  3975. new_vsi = true;
  3976. }
  3977. WARN_ON(vsi->base_queue != I40E_FDIR_RING);
  3978. i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_rings);
  3979. err = i40e_vsi_setup_tx_resources(vsi);
  3980. if (!err)
  3981. err = i40e_vsi_setup_rx_resources(vsi);
  3982. if (!err)
  3983. err = i40e_vsi_configure(vsi);
  3984. if (!err && new_vsi) {
  3985. char int_name[IFNAMSIZ + 9];
  3986. snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
  3987. dev_driver_string(&pf->pdev->dev));
  3988. err = i40e_vsi_request_irq(vsi, int_name);
  3989. }
  3990. if (!err)
  3991. err = i40e_up_complete(vsi);
  3992. clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
  3993. }
  3994. /**
  3995. * i40e_fdir_teardown - release the Flow Director resources
  3996. * @pf: board private structure
  3997. **/
  3998. static void i40e_fdir_teardown(struct i40e_pf *pf)
  3999. {
  4000. int i;
  4001. for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
  4002. if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
  4003. i40e_vsi_release(pf->vsi[i]);
  4004. break;
  4005. }
  4006. }
  4007. }
  4008. /**
  4009. * i40e_handle_reset_warning - prep for the core to reset
  4010. * @pf: board private structure
  4011. *
  4012. * Close up the VFs and other things in prep for a Core Reset,
  4013. * then get ready to rebuild the world.
  4014. **/
  4015. static void i40e_handle_reset_warning(struct i40e_pf *pf)
  4016. {
  4017. struct i40e_driver_version dv;
  4018. struct i40e_hw *hw = &pf->hw;
  4019. i40e_status ret;
  4020. u32 v;
  4021. clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
  4022. if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
  4023. return;
  4024. dev_info(&pf->pdev->dev, "Tearing down internal switch for reset\n");
  4025. i40e_vc_notify_reset(pf);
  4026. /* quiesce the VSIs and their queues that are not already DOWN */
  4027. i40e_pf_quiesce_all_vsi(pf);
  4028. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  4029. if (pf->vsi[v])
  4030. pf->vsi[v]->seid = 0;
  4031. }
  4032. i40e_shutdown_adminq(&pf->hw);
  4033. /* Now we wait for GRST to settle out.
  4034. * We don't have to delete the VEBs or VSIs from the hw switch
  4035. * because the reset will make them disappear.
  4036. */
  4037. ret = i40e_pf_reset(hw);
  4038. if (ret)
  4039. dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
  4040. pf->pfr_count++;
  4041. if (test_bit(__I40E_DOWN, &pf->state))
  4042. goto end_core_reset;
  4043. dev_info(&pf->pdev->dev, "Rebuilding internal switch\n");
  4044. /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
  4045. ret = i40e_init_adminq(&pf->hw);
  4046. if (ret) {
  4047. dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
  4048. goto end_core_reset;
  4049. }
  4050. ret = i40e_get_capabilities(pf);
  4051. if (ret) {
  4052. dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
  4053. ret);
  4054. goto end_core_reset;
  4055. }
  4056. /* call shutdown HMC */
  4057. ret = i40e_shutdown_lan_hmc(hw);
  4058. if (ret) {
  4059. dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
  4060. goto end_core_reset;
  4061. }
  4062. ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
  4063. hw->func_caps.num_rx_qp,
  4064. pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
  4065. if (ret) {
  4066. dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
  4067. goto end_core_reset;
  4068. }
  4069. ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
  4070. if (ret) {
  4071. dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
  4072. goto end_core_reset;
  4073. }
  4074. /* do basic switch setup */
  4075. ret = i40e_setup_pf_switch(pf);
  4076. if (ret)
  4077. goto end_core_reset;
  4078. /* Rebuild the VSIs and VEBs that existed before reset.
  4079. * They are still in our local switch element arrays, so only
  4080. * need to rebuild the switch model in the HW.
  4081. *
  4082. * If there were VEBs but the reconstitution failed, we'll try
  4083. * try to recover minimal use by getting the basic PF VSI working.
  4084. */
  4085. if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
  4086. dev_info(&pf->pdev->dev, "attempting to rebuild switch\n");
  4087. /* find the one VEB connected to the MAC, and find orphans */
  4088. for (v = 0; v < I40E_MAX_VEB; v++) {
  4089. if (!pf->veb[v])
  4090. continue;
  4091. if (pf->veb[v]->uplink_seid == pf->mac_seid ||
  4092. pf->veb[v]->uplink_seid == 0) {
  4093. ret = i40e_reconstitute_veb(pf->veb[v]);
  4094. if (!ret)
  4095. continue;
  4096. /* If Main VEB failed, we're in deep doodoo,
  4097. * so give up rebuilding the switch and set up
  4098. * for minimal rebuild of PF VSI.
  4099. * If orphan failed, we'll report the error
  4100. * but try to keep going.
  4101. */
  4102. if (pf->veb[v]->uplink_seid == pf->mac_seid) {
  4103. dev_info(&pf->pdev->dev,
  4104. "rebuild of switch failed: %d, will try to set up simple PF connection\n",
  4105. ret);
  4106. pf->vsi[pf->lan_vsi]->uplink_seid
  4107. = pf->mac_seid;
  4108. break;
  4109. } else if (pf->veb[v]->uplink_seid == 0) {
  4110. dev_info(&pf->pdev->dev,
  4111. "rebuild of orphan VEB failed: %d\n",
  4112. ret);
  4113. }
  4114. }
  4115. }
  4116. }
  4117. if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
  4118. dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
  4119. /* no VEB, so rebuild only the Main VSI */
  4120. ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
  4121. if (ret) {
  4122. dev_info(&pf->pdev->dev,
  4123. "rebuild of Main VSI failed: %d\n", ret);
  4124. goto end_core_reset;
  4125. }
  4126. }
  4127. /* reinit the misc interrupt */
  4128. if (pf->flags & I40E_FLAG_MSIX_ENABLED)
  4129. ret = i40e_setup_misc_vector(pf);
  4130. /* restart the VSIs that were rebuilt and running before the reset */
  4131. i40e_pf_unquiesce_all_vsi(pf);
  4132. /* tell the firmware that we're starting */
  4133. dv.major_version = DRV_VERSION_MAJOR;
  4134. dv.minor_version = DRV_VERSION_MINOR;
  4135. dv.build_version = DRV_VERSION_BUILD;
  4136. dv.subbuild_version = 0;
  4137. i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
  4138. dev_info(&pf->pdev->dev, "PF reset done\n");
  4139. end_core_reset:
  4140. clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
  4141. }
  4142. /**
  4143. * i40e_handle_mdd_event
  4144. * @pf: pointer to the pf structure
  4145. *
  4146. * Called from the MDD irq handler to identify possibly malicious vfs
  4147. **/
  4148. static void i40e_handle_mdd_event(struct i40e_pf *pf)
  4149. {
  4150. struct i40e_hw *hw = &pf->hw;
  4151. bool mdd_detected = false;
  4152. struct i40e_vf *vf;
  4153. u32 reg;
  4154. int i;
  4155. if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
  4156. return;
  4157. /* find what triggered the MDD event */
  4158. reg = rd32(hw, I40E_GL_MDET_TX);
  4159. if (reg & I40E_GL_MDET_TX_VALID_MASK) {
  4160. u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
  4161. >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
  4162. u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
  4163. >> I40E_GL_MDET_TX_EVENT_SHIFT;
  4164. u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
  4165. >> I40E_GL_MDET_TX_QUEUE_SHIFT;
  4166. dev_info(&pf->pdev->dev,
  4167. "Malicious Driver Detection TX event 0x%02x on q %d of function 0x%02x\n",
  4168. event, queue, func);
  4169. wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
  4170. mdd_detected = true;
  4171. }
  4172. reg = rd32(hw, I40E_GL_MDET_RX);
  4173. if (reg & I40E_GL_MDET_RX_VALID_MASK) {
  4174. u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
  4175. >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
  4176. u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
  4177. >> I40E_GL_MDET_RX_EVENT_SHIFT;
  4178. u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
  4179. >> I40E_GL_MDET_RX_QUEUE_SHIFT;
  4180. dev_info(&pf->pdev->dev,
  4181. "Malicious Driver Detection RX event 0x%02x on q %d of function 0x%02x\n",
  4182. event, queue, func);
  4183. wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
  4184. mdd_detected = true;
  4185. }
  4186. /* see if one of the VFs needs its hand slapped */
  4187. for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
  4188. vf = &(pf->vf[i]);
  4189. reg = rd32(hw, I40E_VP_MDET_TX(i));
  4190. if (reg & I40E_VP_MDET_TX_VALID_MASK) {
  4191. wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
  4192. vf->num_mdd_events++;
  4193. dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
  4194. }
  4195. reg = rd32(hw, I40E_VP_MDET_RX(i));
  4196. if (reg & I40E_VP_MDET_RX_VALID_MASK) {
  4197. wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
  4198. vf->num_mdd_events++;
  4199. dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
  4200. }
  4201. if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
  4202. dev_info(&pf->pdev->dev,
  4203. "Too many MDD events on VF %d, disabled\n", i);
  4204. dev_info(&pf->pdev->dev,
  4205. "Use PF Control I/F to re-enable the VF\n");
  4206. set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
  4207. }
  4208. }
  4209. /* re-enable mdd interrupt cause */
  4210. clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
  4211. reg = rd32(hw, I40E_PFINT_ICR0_ENA);
  4212. reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
  4213. wr32(hw, I40E_PFINT_ICR0_ENA, reg);
  4214. i40e_flush(hw);
  4215. }
  4216. /**
  4217. * i40e_service_task - Run the driver's async subtasks
  4218. * @work: pointer to work_struct containing our data
  4219. **/
  4220. static void i40e_service_task(struct work_struct *work)
  4221. {
  4222. struct i40e_pf *pf = container_of(work,
  4223. struct i40e_pf,
  4224. service_task);
  4225. unsigned long start_time = jiffies;
  4226. i40e_reset_subtask(pf);
  4227. i40e_handle_mdd_event(pf);
  4228. i40e_vc_process_vflr_event(pf);
  4229. i40e_watchdog_subtask(pf);
  4230. i40e_fdir_reinit_subtask(pf);
  4231. i40e_check_hang_subtask(pf);
  4232. i40e_sync_filters_subtask(pf);
  4233. i40e_clean_adminq_subtask(pf);
  4234. i40e_service_event_complete(pf);
  4235. /* If the tasks have taken longer than one timer cycle or there
  4236. * is more work to be done, reschedule the service task now
  4237. * rather than wait for the timer to tick again.
  4238. */
  4239. if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
  4240. test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
  4241. test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
  4242. test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
  4243. i40e_service_event_schedule(pf);
  4244. }
  4245. /**
  4246. * i40e_service_timer - timer callback
  4247. * @data: pointer to PF struct
  4248. **/
  4249. static void i40e_service_timer(unsigned long data)
  4250. {
  4251. struct i40e_pf *pf = (struct i40e_pf *)data;
  4252. mod_timer(&pf->service_timer,
  4253. round_jiffies(jiffies + pf->service_timer_period));
  4254. i40e_service_event_schedule(pf);
  4255. }
  4256. /**
  4257. * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
  4258. * @vsi: the VSI being configured
  4259. **/
  4260. static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
  4261. {
  4262. struct i40e_pf *pf = vsi->back;
  4263. switch (vsi->type) {
  4264. case I40E_VSI_MAIN:
  4265. vsi->alloc_queue_pairs = pf->num_lan_qps;
  4266. vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
  4267. I40E_REQ_DESCRIPTOR_MULTIPLE);
  4268. if (pf->flags & I40E_FLAG_MSIX_ENABLED)
  4269. vsi->num_q_vectors = pf->num_lan_msix;
  4270. else
  4271. vsi->num_q_vectors = 1;
  4272. break;
  4273. case I40E_VSI_FDIR:
  4274. vsi->alloc_queue_pairs = 1;
  4275. vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
  4276. I40E_REQ_DESCRIPTOR_MULTIPLE);
  4277. vsi->num_q_vectors = 1;
  4278. break;
  4279. case I40E_VSI_VMDQ2:
  4280. vsi->alloc_queue_pairs = pf->num_vmdq_qps;
  4281. vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
  4282. I40E_REQ_DESCRIPTOR_MULTIPLE);
  4283. vsi->num_q_vectors = pf->num_vmdq_msix;
  4284. break;
  4285. case I40E_VSI_SRIOV:
  4286. vsi->alloc_queue_pairs = pf->num_vf_qps;
  4287. vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
  4288. I40E_REQ_DESCRIPTOR_MULTIPLE);
  4289. break;
  4290. default:
  4291. WARN_ON(1);
  4292. return -ENODATA;
  4293. }
  4294. return 0;
  4295. }
  4296. /**
  4297. * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
  4298. * @pf: board private structure
  4299. * @type: type of VSI
  4300. *
  4301. * On error: returns error code (negative)
  4302. * On success: returns vsi index in PF (positive)
  4303. **/
  4304. static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
  4305. {
  4306. int ret = -ENODEV;
  4307. struct i40e_vsi *vsi;
  4308. int vsi_idx;
  4309. int i;
  4310. /* Need to protect the allocation of the VSIs at the PF level */
  4311. mutex_lock(&pf->switch_mutex);
  4312. /* VSI list may be fragmented if VSI creation/destruction has
  4313. * been happening. We can afford to do a quick scan to look
  4314. * for any free VSIs in the list.
  4315. *
  4316. * find next empty vsi slot, looping back around if necessary
  4317. */
  4318. i = pf->next_vsi;
  4319. while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
  4320. i++;
  4321. if (i >= pf->hw.func_caps.num_vsis) {
  4322. i = 0;
  4323. while (i < pf->next_vsi && pf->vsi[i])
  4324. i++;
  4325. }
  4326. if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
  4327. vsi_idx = i; /* Found one! */
  4328. } else {
  4329. ret = -ENODEV;
  4330. goto err_alloc_vsi; /* out of VSI slots! */
  4331. }
  4332. pf->next_vsi = ++i;
  4333. vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
  4334. if (!vsi) {
  4335. ret = -ENOMEM;
  4336. goto err_alloc_vsi;
  4337. }
  4338. vsi->type = type;
  4339. vsi->back = pf;
  4340. set_bit(__I40E_DOWN, &vsi->state);
  4341. vsi->flags = 0;
  4342. vsi->idx = vsi_idx;
  4343. vsi->rx_itr_setting = pf->rx_itr_default;
  4344. vsi->tx_itr_setting = pf->tx_itr_default;
  4345. vsi->netdev_registered = false;
  4346. vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
  4347. INIT_LIST_HEAD(&vsi->mac_filter_list);
  4348. i40e_set_num_rings_in_vsi(vsi);
  4349. /* Setup default MSIX irq handler for VSI */
  4350. i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
  4351. pf->vsi[vsi_idx] = vsi;
  4352. ret = vsi_idx;
  4353. err_alloc_vsi:
  4354. mutex_unlock(&pf->switch_mutex);
  4355. return ret;
  4356. }
  4357. /**
  4358. * i40e_vsi_clear - Deallocate the VSI provided
  4359. * @vsi: the VSI being un-configured
  4360. **/
  4361. static int i40e_vsi_clear(struct i40e_vsi *vsi)
  4362. {
  4363. struct i40e_pf *pf;
  4364. if (!vsi)
  4365. return 0;
  4366. if (!vsi->back)
  4367. goto free_vsi;
  4368. pf = vsi->back;
  4369. mutex_lock(&pf->switch_mutex);
  4370. if (!pf->vsi[vsi->idx]) {
  4371. dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
  4372. vsi->idx, vsi->idx, vsi, vsi->type);
  4373. goto unlock_vsi;
  4374. }
  4375. if (pf->vsi[vsi->idx] != vsi) {
  4376. dev_err(&pf->pdev->dev,
  4377. "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
  4378. pf->vsi[vsi->idx]->idx,
  4379. pf->vsi[vsi->idx],
  4380. pf->vsi[vsi->idx]->type,
  4381. vsi->idx, vsi, vsi->type);
  4382. goto unlock_vsi;
  4383. }
  4384. /* updates the pf for this cleared vsi */
  4385. i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
  4386. i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
  4387. pf->vsi[vsi->idx] = NULL;
  4388. if (vsi->idx < pf->next_vsi)
  4389. pf->next_vsi = vsi->idx;
  4390. unlock_vsi:
  4391. mutex_unlock(&pf->switch_mutex);
  4392. free_vsi:
  4393. kfree(vsi);
  4394. return 0;
  4395. }
  4396. /**
  4397. * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
  4398. * @vsi: the VSI being configured
  4399. **/
  4400. static int i40e_alloc_rings(struct i40e_vsi *vsi)
  4401. {
  4402. struct i40e_pf *pf = vsi->back;
  4403. int ret = 0;
  4404. int i;
  4405. vsi->rx_rings = kcalloc(vsi->alloc_queue_pairs,
  4406. sizeof(struct i40e_ring), GFP_KERNEL);
  4407. if (!vsi->rx_rings) {
  4408. ret = -ENOMEM;
  4409. goto err_alloc_rings;
  4410. }
  4411. vsi->tx_rings = kcalloc(vsi->alloc_queue_pairs,
  4412. sizeof(struct i40e_ring), GFP_KERNEL);
  4413. if (!vsi->tx_rings) {
  4414. ret = -ENOMEM;
  4415. kfree(vsi->rx_rings);
  4416. goto err_alloc_rings;
  4417. }
  4418. /* Set basic values in the rings to be used later during open() */
  4419. for (i = 0; i < vsi->alloc_queue_pairs; i++) {
  4420. struct i40e_ring *rx_ring = &vsi->rx_rings[i];
  4421. struct i40e_ring *tx_ring = &vsi->tx_rings[i];
  4422. tx_ring->queue_index = i;
  4423. tx_ring->reg_idx = vsi->base_queue + i;
  4424. tx_ring->ring_active = false;
  4425. tx_ring->vsi = vsi;
  4426. tx_ring->netdev = vsi->netdev;
  4427. tx_ring->dev = &pf->pdev->dev;
  4428. tx_ring->count = vsi->num_desc;
  4429. tx_ring->size = 0;
  4430. tx_ring->dcb_tc = 0;
  4431. rx_ring->queue_index = i;
  4432. rx_ring->reg_idx = vsi->base_queue + i;
  4433. rx_ring->ring_active = false;
  4434. rx_ring->vsi = vsi;
  4435. rx_ring->netdev = vsi->netdev;
  4436. rx_ring->dev = &pf->pdev->dev;
  4437. rx_ring->count = vsi->num_desc;
  4438. rx_ring->size = 0;
  4439. rx_ring->dcb_tc = 0;
  4440. if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
  4441. set_ring_16byte_desc_enabled(rx_ring);
  4442. else
  4443. clear_ring_16byte_desc_enabled(rx_ring);
  4444. }
  4445. err_alloc_rings:
  4446. return ret;
  4447. }
  4448. /**
  4449. * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
  4450. * @vsi: the VSI being cleaned
  4451. **/
  4452. static int i40e_vsi_clear_rings(struct i40e_vsi *vsi)
  4453. {
  4454. if (vsi) {
  4455. kfree(vsi->rx_rings);
  4456. kfree(vsi->tx_rings);
  4457. }
  4458. return 0;
  4459. }
  4460. /**
  4461. * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
  4462. * @pf: board private structure
  4463. * @vectors: the number of MSI-X vectors to request
  4464. *
  4465. * Returns the number of vectors reserved, or error
  4466. **/
  4467. static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
  4468. {
  4469. int err = 0;
  4470. pf->num_msix_entries = 0;
  4471. while (vectors >= I40E_MIN_MSIX) {
  4472. err = pci_enable_msix(pf->pdev, pf->msix_entries, vectors);
  4473. if (err == 0) {
  4474. /* good to go */
  4475. pf->num_msix_entries = vectors;
  4476. break;
  4477. } else if (err < 0) {
  4478. /* total failure */
  4479. dev_info(&pf->pdev->dev,
  4480. "MSI-X vector reservation failed: %d\n", err);
  4481. vectors = 0;
  4482. break;
  4483. } else {
  4484. /* err > 0 is the hint for retry */
  4485. dev_info(&pf->pdev->dev,
  4486. "MSI-X vectors wanted %d, retrying with %d\n",
  4487. vectors, err);
  4488. vectors = err;
  4489. }
  4490. }
  4491. if (vectors > 0 && vectors < I40E_MIN_MSIX) {
  4492. dev_info(&pf->pdev->dev,
  4493. "Couldn't get enough vectors, only %d available\n",
  4494. vectors);
  4495. vectors = 0;
  4496. }
  4497. return vectors;
  4498. }
  4499. /**
  4500. * i40e_init_msix - Setup the MSIX capability
  4501. * @pf: board private structure
  4502. *
  4503. * Work with the OS to set up the MSIX vectors needed.
  4504. *
  4505. * Returns 0 on success, negative on failure
  4506. **/
  4507. static int i40e_init_msix(struct i40e_pf *pf)
  4508. {
  4509. i40e_status err = 0;
  4510. struct i40e_hw *hw = &pf->hw;
  4511. int v_budget, i;
  4512. int vec;
  4513. if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
  4514. return -ENODEV;
  4515. /* The number of vectors we'll request will be comprised of:
  4516. * - Add 1 for "other" cause for Admin Queue events, etc.
  4517. * - The number of LAN queue pairs
  4518. * already adjusted for the NUMA node
  4519. * assumes symmetric Tx/Rx pairing
  4520. * - The number of VMDq pairs
  4521. * Once we count this up, try the request.
  4522. *
  4523. * If we can't get what we want, we'll simplify to nearly nothing
  4524. * and try again. If that still fails, we punt.
  4525. */
  4526. pf->num_lan_msix = pf->num_lan_qps;
  4527. pf->num_vmdq_msix = pf->num_vmdq_qps;
  4528. v_budget = 1 + pf->num_lan_msix;
  4529. v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
  4530. if (pf->flags & I40E_FLAG_FDIR_ENABLED)
  4531. v_budget++;
  4532. /* Scale down if necessary, and the rings will share vectors */
  4533. v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
  4534. pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
  4535. GFP_KERNEL);
  4536. if (!pf->msix_entries)
  4537. return -ENOMEM;
  4538. for (i = 0; i < v_budget; i++)
  4539. pf->msix_entries[i].entry = i;
  4540. vec = i40e_reserve_msix_vectors(pf, v_budget);
  4541. if (vec < I40E_MIN_MSIX) {
  4542. pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
  4543. kfree(pf->msix_entries);
  4544. pf->msix_entries = NULL;
  4545. return -ENODEV;
  4546. } else if (vec == I40E_MIN_MSIX) {
  4547. /* Adjust for minimal MSIX use */
  4548. dev_info(&pf->pdev->dev, "Features disabled, not enough MSIX vectors\n");
  4549. pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
  4550. pf->num_vmdq_vsis = 0;
  4551. pf->num_vmdq_qps = 0;
  4552. pf->num_vmdq_msix = 0;
  4553. pf->num_lan_qps = 1;
  4554. pf->num_lan_msix = 1;
  4555. } else if (vec != v_budget) {
  4556. /* Scale vector usage down */
  4557. pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
  4558. vec--; /* reserve the misc vector */
  4559. /* partition out the remaining vectors */
  4560. switch (vec) {
  4561. case 2:
  4562. pf->num_vmdq_vsis = 1;
  4563. pf->num_lan_msix = 1;
  4564. break;
  4565. case 3:
  4566. pf->num_vmdq_vsis = 1;
  4567. pf->num_lan_msix = 2;
  4568. break;
  4569. default:
  4570. pf->num_lan_msix = min_t(int, (vec / 2),
  4571. pf->num_lan_qps);
  4572. pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
  4573. I40E_DEFAULT_NUM_VMDQ_VSI);
  4574. break;
  4575. }
  4576. }
  4577. return err;
  4578. }
  4579. /**
  4580. * i40e_alloc_q_vectors - Allocate memory for interrupt vectors
  4581. * @vsi: the VSI being configured
  4582. *
  4583. * We allocate one q_vector per queue interrupt. If allocation fails we
  4584. * return -ENOMEM.
  4585. **/
  4586. static int i40e_alloc_q_vectors(struct i40e_vsi *vsi)
  4587. {
  4588. struct i40e_pf *pf = vsi->back;
  4589. int v_idx, num_q_vectors;
  4590. /* if not MSIX, give the one vector only to the LAN VSI */
  4591. if (pf->flags & I40E_FLAG_MSIX_ENABLED)
  4592. num_q_vectors = vsi->num_q_vectors;
  4593. else if (vsi == pf->vsi[pf->lan_vsi])
  4594. num_q_vectors = 1;
  4595. else
  4596. return -EINVAL;
  4597. vsi->q_vectors = kcalloc(num_q_vectors,
  4598. sizeof(struct i40e_q_vector),
  4599. GFP_KERNEL);
  4600. if (!vsi->q_vectors)
  4601. return -ENOMEM;
  4602. for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
  4603. vsi->q_vectors[v_idx].vsi = vsi;
  4604. vsi->q_vectors[v_idx].v_idx = v_idx;
  4605. cpumask_set_cpu(v_idx, &vsi->q_vectors[v_idx].affinity_mask);
  4606. if (vsi->netdev)
  4607. netif_napi_add(vsi->netdev, &vsi->q_vectors[v_idx].napi,
  4608. i40e_napi_poll, vsi->work_limit);
  4609. }
  4610. return 0;
  4611. }
  4612. /**
  4613. * i40e_init_interrupt_scheme - Determine proper interrupt scheme
  4614. * @pf: board private structure to initialize
  4615. **/
  4616. static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
  4617. {
  4618. int err = 0;
  4619. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  4620. err = i40e_init_msix(pf);
  4621. if (err) {
  4622. pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
  4623. I40E_FLAG_MQ_ENABLED |
  4624. I40E_FLAG_DCB_ENABLED |
  4625. I40E_FLAG_SRIOV_ENABLED |
  4626. I40E_FLAG_FDIR_ENABLED |
  4627. I40E_FLAG_FDIR_ATR_ENABLED |
  4628. I40E_FLAG_VMDQ_ENABLED);
  4629. /* rework the queue expectations without MSIX */
  4630. i40e_determine_queue_usage(pf);
  4631. }
  4632. }
  4633. if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
  4634. (pf->flags & I40E_FLAG_MSI_ENABLED)) {
  4635. err = pci_enable_msi(pf->pdev);
  4636. if (err) {
  4637. dev_info(&pf->pdev->dev,
  4638. "MSI init failed (%d), trying legacy.\n", err);
  4639. pf->flags &= ~I40E_FLAG_MSI_ENABLED;
  4640. }
  4641. }
  4642. /* track first vector for misc interrupts */
  4643. err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
  4644. }
  4645. /**
  4646. * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
  4647. * @pf: board private structure
  4648. *
  4649. * This sets up the handler for MSIX 0, which is used to manage the
  4650. * non-queue interrupts, e.g. AdminQ and errors. This is not used
  4651. * when in MSI or Legacy interrupt mode.
  4652. **/
  4653. static int i40e_setup_misc_vector(struct i40e_pf *pf)
  4654. {
  4655. struct i40e_hw *hw = &pf->hw;
  4656. int err = 0;
  4657. /* Only request the irq if this is the first time through, and
  4658. * not when we're rebuilding after a Reset
  4659. */
  4660. if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
  4661. err = request_irq(pf->msix_entries[0].vector,
  4662. i40e_intr, 0, pf->misc_int_name, pf);
  4663. if (err) {
  4664. dev_info(&pf->pdev->dev,
  4665. "request_irq for msix_misc failed: %d\n", err);
  4666. return -EFAULT;
  4667. }
  4668. }
  4669. i40e_enable_misc_int_causes(hw);
  4670. /* associate no queues to the misc vector */
  4671. wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
  4672. wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
  4673. i40e_flush(hw);
  4674. i40e_irq_dynamic_enable_icr0(pf);
  4675. return err;
  4676. }
  4677. /**
  4678. * i40e_config_rss - Prepare for RSS if used
  4679. * @pf: board private structure
  4680. **/
  4681. static int i40e_config_rss(struct i40e_pf *pf)
  4682. {
  4683. struct i40e_hw *hw = &pf->hw;
  4684. u32 lut = 0;
  4685. int i, j;
  4686. u64 hena;
  4687. /* Set of random keys generated using kernel random number generator */
  4688. static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
  4689. 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
  4690. 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
  4691. 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
  4692. /* Fill out hash function seed */
  4693. for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
  4694. wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
  4695. /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
  4696. hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
  4697. ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
  4698. hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
  4699. ((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
  4700. ((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) |
  4701. ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
  4702. ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
  4703. ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
  4704. ((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
  4705. ((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) |
  4706. ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4)|
  4707. ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6);
  4708. wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
  4709. wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
  4710. /* Populate the LUT with max no. of queues in round robin fashion */
  4711. for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
  4712. /* The assumption is that lan qp count will be the highest
  4713. * qp count for any PF VSI that needs RSS.
  4714. * If multiple VSIs need RSS support, all the qp counts
  4715. * for those VSIs should be a power of 2 for RSS to work.
  4716. * If LAN VSI is the only consumer for RSS then this requirement
  4717. * is not necessary.
  4718. */
  4719. if (j == pf->rss_size)
  4720. j = 0;
  4721. /* lut = 4-byte sliding window of 4 lut entries */
  4722. lut = (lut << 8) | (j &
  4723. ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
  4724. /* On i = 3, we have 4 entries in lut; write to the register */
  4725. if ((i & 3) == 3)
  4726. wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
  4727. }
  4728. i40e_flush(hw);
  4729. return 0;
  4730. }
  4731. /**
  4732. * i40e_sw_init - Initialize general software structures (struct i40e_pf)
  4733. * @pf: board private structure to initialize
  4734. *
  4735. * i40e_sw_init initializes the Adapter private data structure.
  4736. * Fields are initialized based on PCI device information and
  4737. * OS network device settings (MTU size).
  4738. **/
  4739. static int i40e_sw_init(struct i40e_pf *pf)
  4740. {
  4741. int err = 0;
  4742. int size;
  4743. pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
  4744. (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
  4745. if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
  4746. if (I40E_DEBUG_USER & debug)
  4747. pf->hw.debug_mask = debug;
  4748. pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
  4749. I40E_DEFAULT_MSG_ENABLE);
  4750. }
  4751. /* Set default capability flags */
  4752. pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
  4753. I40E_FLAG_MSI_ENABLED |
  4754. I40E_FLAG_MSIX_ENABLED |
  4755. I40E_FLAG_RX_PS_ENABLED |
  4756. I40E_FLAG_MQ_ENABLED |
  4757. I40E_FLAG_RX_1BUF_ENABLED;
  4758. pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
  4759. if (pf->hw.func_caps.rss) {
  4760. pf->flags |= I40E_FLAG_RSS_ENABLED;
  4761. pf->rss_size = min_t(int, pf->rss_size_max,
  4762. nr_cpus_node(numa_node_id()));
  4763. } else {
  4764. pf->rss_size = 1;
  4765. }
  4766. if (pf->hw.func_caps.dcb)
  4767. pf->num_tc_qps = I40E_DEFAULT_QUEUES_PER_TC;
  4768. else
  4769. pf->num_tc_qps = 0;
  4770. if (pf->hw.func_caps.fd) {
  4771. /* FW/NVM is not yet fixed in this regard */
  4772. if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
  4773. (pf->hw.func_caps.fd_filters_best_effort > 0)) {
  4774. pf->flags |= I40E_FLAG_FDIR_ATR_ENABLED;
  4775. dev_info(&pf->pdev->dev,
  4776. "Flow Director ATR mode Enabled\n");
  4777. pf->flags |= I40E_FLAG_FDIR_ENABLED;
  4778. dev_info(&pf->pdev->dev,
  4779. "Flow Director Side Band mode Enabled\n");
  4780. pf->fdir_pf_filter_count =
  4781. pf->hw.func_caps.fd_filters_guaranteed;
  4782. }
  4783. } else {
  4784. pf->fdir_pf_filter_count = 0;
  4785. }
  4786. if (pf->hw.func_caps.vmdq) {
  4787. pf->flags |= I40E_FLAG_VMDQ_ENABLED;
  4788. pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
  4789. pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
  4790. }
  4791. /* MFP mode enabled */
  4792. if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
  4793. pf->flags |= I40E_FLAG_MFP_ENABLED;
  4794. dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
  4795. }
  4796. #ifdef CONFIG_PCI_IOV
  4797. if (pf->hw.func_caps.num_vfs) {
  4798. pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
  4799. pf->flags |= I40E_FLAG_SRIOV_ENABLED;
  4800. pf->num_req_vfs = min_t(int,
  4801. pf->hw.func_caps.num_vfs,
  4802. I40E_MAX_VF_COUNT);
  4803. }
  4804. #endif /* CONFIG_PCI_IOV */
  4805. pf->eeprom_version = 0xDEAD;
  4806. pf->lan_veb = I40E_NO_VEB;
  4807. pf->lan_vsi = I40E_NO_VSI;
  4808. /* set up queue assignment tracking */
  4809. size = sizeof(struct i40e_lump_tracking)
  4810. + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
  4811. pf->qp_pile = kzalloc(size, GFP_KERNEL);
  4812. if (!pf->qp_pile) {
  4813. err = -ENOMEM;
  4814. goto sw_init_done;
  4815. }
  4816. pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
  4817. pf->qp_pile->search_hint = 0;
  4818. /* set up vector assignment tracking */
  4819. size = sizeof(struct i40e_lump_tracking)
  4820. + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
  4821. pf->irq_pile = kzalloc(size, GFP_KERNEL);
  4822. if (!pf->irq_pile) {
  4823. kfree(pf->qp_pile);
  4824. err = -ENOMEM;
  4825. goto sw_init_done;
  4826. }
  4827. pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
  4828. pf->irq_pile->search_hint = 0;
  4829. mutex_init(&pf->switch_mutex);
  4830. sw_init_done:
  4831. return err;
  4832. }
  4833. /**
  4834. * i40e_set_features - set the netdev feature flags
  4835. * @netdev: ptr to the netdev being adjusted
  4836. * @features: the feature set that the stack is suggesting
  4837. **/
  4838. static int i40e_set_features(struct net_device *netdev,
  4839. netdev_features_t features)
  4840. {
  4841. struct i40e_netdev_priv *np = netdev_priv(netdev);
  4842. struct i40e_vsi *vsi = np->vsi;
  4843. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  4844. i40e_vlan_stripping_enable(vsi);
  4845. else
  4846. i40e_vlan_stripping_disable(vsi);
  4847. return 0;
  4848. }
  4849. static const struct net_device_ops i40e_netdev_ops = {
  4850. .ndo_open = i40e_open,
  4851. .ndo_stop = i40e_close,
  4852. .ndo_start_xmit = i40e_lan_xmit_frame,
  4853. .ndo_get_stats64 = i40e_get_netdev_stats_struct,
  4854. .ndo_set_rx_mode = i40e_set_rx_mode,
  4855. .ndo_validate_addr = eth_validate_addr,
  4856. .ndo_set_mac_address = i40e_set_mac,
  4857. .ndo_change_mtu = i40e_change_mtu,
  4858. .ndo_tx_timeout = i40e_tx_timeout,
  4859. .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
  4860. .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
  4861. #ifdef CONFIG_NET_POLL_CONTROLLER
  4862. .ndo_poll_controller = i40e_netpoll,
  4863. #endif
  4864. .ndo_setup_tc = i40e_setup_tc,
  4865. .ndo_set_features = i40e_set_features,
  4866. .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
  4867. .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
  4868. .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
  4869. .ndo_get_vf_config = i40e_ndo_get_vf_config,
  4870. };
  4871. /**
  4872. * i40e_config_netdev - Setup the netdev flags
  4873. * @vsi: the VSI being configured
  4874. *
  4875. * Returns 0 on success, negative value on failure
  4876. **/
  4877. static int i40e_config_netdev(struct i40e_vsi *vsi)
  4878. {
  4879. struct i40e_pf *pf = vsi->back;
  4880. struct i40e_hw *hw = &pf->hw;
  4881. struct i40e_netdev_priv *np;
  4882. struct net_device *netdev;
  4883. u8 mac_addr[ETH_ALEN];
  4884. int etherdev_size;
  4885. etherdev_size = sizeof(struct i40e_netdev_priv);
  4886. netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
  4887. if (!netdev)
  4888. return -ENOMEM;
  4889. vsi->netdev = netdev;
  4890. np = netdev_priv(netdev);
  4891. np->vsi = vsi;
  4892. netdev->hw_enc_features = NETIF_F_IP_CSUM |
  4893. NETIF_F_GSO_UDP_TUNNEL |
  4894. NETIF_F_TSO |
  4895. NETIF_F_SG;
  4896. netdev->features = NETIF_F_SG |
  4897. NETIF_F_IP_CSUM |
  4898. NETIF_F_SCTP_CSUM |
  4899. NETIF_F_HIGHDMA |
  4900. NETIF_F_GSO_UDP_TUNNEL |
  4901. NETIF_F_HW_VLAN_CTAG_TX |
  4902. NETIF_F_HW_VLAN_CTAG_RX |
  4903. NETIF_F_HW_VLAN_CTAG_FILTER |
  4904. NETIF_F_IPV6_CSUM |
  4905. NETIF_F_TSO |
  4906. NETIF_F_TSO6 |
  4907. NETIF_F_RXCSUM |
  4908. NETIF_F_RXHASH |
  4909. 0;
  4910. /* copy netdev features into list of user selectable features */
  4911. netdev->hw_features |= netdev->features;
  4912. if (vsi->type == I40E_VSI_MAIN) {
  4913. SET_NETDEV_DEV(netdev, &pf->pdev->dev);
  4914. memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
  4915. } else {
  4916. /* relate the VSI_VMDQ name to the VSI_MAIN name */
  4917. snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
  4918. pf->vsi[pf->lan_vsi]->netdev->name);
  4919. random_ether_addr(mac_addr);
  4920. i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
  4921. }
  4922. memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
  4923. memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
  4924. /* vlan gets same features (except vlan offload)
  4925. * after any tweaks for specific VSI types
  4926. */
  4927. netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
  4928. NETIF_F_HW_VLAN_CTAG_RX |
  4929. NETIF_F_HW_VLAN_CTAG_FILTER);
  4930. netdev->priv_flags |= IFF_UNICAST_FLT;
  4931. netdev->priv_flags |= IFF_SUPP_NOFCS;
  4932. /* Setup netdev TC information */
  4933. i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
  4934. netdev->netdev_ops = &i40e_netdev_ops;
  4935. netdev->watchdog_timeo = 5 * HZ;
  4936. i40e_set_ethtool_ops(netdev);
  4937. return 0;
  4938. }
  4939. /**
  4940. * i40e_vsi_delete - Delete a VSI from the switch
  4941. * @vsi: the VSI being removed
  4942. *
  4943. * Returns 0 on success, negative value on failure
  4944. **/
  4945. static void i40e_vsi_delete(struct i40e_vsi *vsi)
  4946. {
  4947. /* remove default VSI is not allowed */
  4948. if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
  4949. return;
  4950. /* there is no HW VSI for FDIR */
  4951. if (vsi->type == I40E_VSI_FDIR)
  4952. return;
  4953. i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
  4954. return;
  4955. }
  4956. /**
  4957. * i40e_add_vsi - Add a VSI to the switch
  4958. * @vsi: the VSI being configured
  4959. *
  4960. * This initializes a VSI context depending on the VSI type to be added and
  4961. * passes it down to the add_vsi aq command.
  4962. **/
  4963. static int i40e_add_vsi(struct i40e_vsi *vsi)
  4964. {
  4965. int ret = -ENODEV;
  4966. struct i40e_mac_filter *f, *ftmp;
  4967. struct i40e_pf *pf = vsi->back;
  4968. struct i40e_hw *hw = &pf->hw;
  4969. struct i40e_vsi_context ctxt;
  4970. u8 enabled_tc = 0x1; /* TC0 enabled */
  4971. int f_count = 0;
  4972. memset(&ctxt, 0, sizeof(ctxt));
  4973. switch (vsi->type) {
  4974. case I40E_VSI_MAIN:
  4975. /* The PF's main VSI is already setup as part of the
  4976. * device initialization, so we'll not bother with
  4977. * the add_vsi call, but we will retrieve the current
  4978. * VSI context.
  4979. */
  4980. ctxt.seid = pf->main_vsi_seid;
  4981. ctxt.pf_num = pf->hw.pf_id;
  4982. ctxt.vf_num = 0;
  4983. ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
  4984. ctxt.flags = I40E_AQ_VSI_TYPE_PF;
  4985. if (ret) {
  4986. dev_info(&pf->pdev->dev,
  4987. "couldn't get pf vsi config, err %d, aq_err %d\n",
  4988. ret, pf->hw.aq.asq_last_status);
  4989. return -ENOENT;
  4990. }
  4991. memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
  4992. vsi->info.valid_sections = 0;
  4993. vsi->seid = ctxt.seid;
  4994. vsi->id = ctxt.vsi_number;
  4995. enabled_tc = i40e_pf_get_tc_map(pf);
  4996. /* MFP mode setup queue map and update VSI */
  4997. if (pf->flags & I40E_FLAG_MFP_ENABLED) {
  4998. memset(&ctxt, 0, sizeof(ctxt));
  4999. ctxt.seid = pf->main_vsi_seid;
  5000. ctxt.pf_num = pf->hw.pf_id;
  5001. ctxt.vf_num = 0;
  5002. i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
  5003. ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
  5004. if (ret) {
  5005. dev_info(&pf->pdev->dev,
  5006. "update vsi failed, aq_err=%d\n",
  5007. pf->hw.aq.asq_last_status);
  5008. ret = -ENOENT;
  5009. goto err;
  5010. }
  5011. /* update the local VSI info queue map */
  5012. i40e_vsi_update_queue_map(vsi, &ctxt);
  5013. vsi->info.valid_sections = 0;
  5014. } else {
  5015. /* Default/Main VSI is only enabled for TC0
  5016. * reconfigure it to enable all TCs that are
  5017. * available on the port in SFP mode.
  5018. */
  5019. ret = i40e_vsi_config_tc(vsi, enabled_tc);
  5020. if (ret) {
  5021. dev_info(&pf->pdev->dev,
  5022. "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
  5023. enabled_tc, ret,
  5024. pf->hw.aq.asq_last_status);
  5025. ret = -ENOENT;
  5026. }
  5027. }
  5028. break;
  5029. case I40E_VSI_FDIR:
  5030. /* no queue mapping or actual HW VSI needed */
  5031. vsi->info.valid_sections = 0;
  5032. vsi->seid = 0;
  5033. vsi->id = 0;
  5034. i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
  5035. return 0;
  5036. break;
  5037. case I40E_VSI_VMDQ2:
  5038. ctxt.pf_num = hw->pf_id;
  5039. ctxt.vf_num = 0;
  5040. ctxt.uplink_seid = vsi->uplink_seid;
  5041. ctxt.connection_type = 0x1; /* regular data port */
  5042. ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
  5043. ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
  5044. /* This VSI is connected to VEB so the switch_id
  5045. * should be set to zero by default.
  5046. */
  5047. ctxt.info.switch_id = 0;
  5048. ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
  5049. ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
  5050. /* Setup the VSI tx/rx queue map for TC0 only for now */
  5051. i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
  5052. break;
  5053. case I40E_VSI_SRIOV:
  5054. ctxt.pf_num = hw->pf_id;
  5055. ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
  5056. ctxt.uplink_seid = vsi->uplink_seid;
  5057. ctxt.connection_type = 0x1; /* regular data port */
  5058. ctxt.flags = I40E_AQ_VSI_TYPE_VF;
  5059. ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
  5060. /* This VSI is connected to VEB so the switch_id
  5061. * should be set to zero by default.
  5062. */
  5063. ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
  5064. ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
  5065. ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
  5066. /* Setup the VSI tx/rx queue map for TC0 only for now */
  5067. i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
  5068. break;
  5069. default:
  5070. return -ENODEV;
  5071. }
  5072. if (vsi->type != I40E_VSI_MAIN) {
  5073. ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
  5074. if (ret) {
  5075. dev_info(&vsi->back->pdev->dev,
  5076. "add vsi failed, aq_err=%d\n",
  5077. vsi->back->hw.aq.asq_last_status);
  5078. ret = -ENOENT;
  5079. goto err;
  5080. }
  5081. memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
  5082. vsi->info.valid_sections = 0;
  5083. vsi->seid = ctxt.seid;
  5084. vsi->id = ctxt.vsi_number;
  5085. }
  5086. /* If macvlan filters already exist, force them to get loaded */
  5087. list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
  5088. f->changed = true;
  5089. f_count++;
  5090. }
  5091. if (f_count) {
  5092. vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
  5093. pf->flags |= I40E_FLAG_FILTER_SYNC;
  5094. }
  5095. /* Update VSI BW information */
  5096. ret = i40e_vsi_get_bw_info(vsi);
  5097. if (ret) {
  5098. dev_info(&pf->pdev->dev,
  5099. "couldn't get vsi bw info, err %d, aq_err %d\n",
  5100. ret, pf->hw.aq.asq_last_status);
  5101. /* VSI is already added so not tearing that up */
  5102. ret = 0;
  5103. }
  5104. err:
  5105. return ret;
  5106. }
  5107. /**
  5108. * i40e_vsi_release - Delete a VSI and free its resources
  5109. * @vsi: the VSI being removed
  5110. *
  5111. * Returns 0 on success or < 0 on error
  5112. **/
  5113. int i40e_vsi_release(struct i40e_vsi *vsi)
  5114. {
  5115. struct i40e_mac_filter *f, *ftmp;
  5116. struct i40e_veb *veb = NULL;
  5117. struct i40e_pf *pf;
  5118. u16 uplink_seid;
  5119. int i, n;
  5120. pf = vsi->back;
  5121. /* release of a VEB-owner or last VSI is not allowed */
  5122. if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
  5123. dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
  5124. vsi->seid, vsi->uplink_seid);
  5125. return -ENODEV;
  5126. }
  5127. if (vsi == pf->vsi[pf->lan_vsi] &&
  5128. !test_bit(__I40E_DOWN, &pf->state)) {
  5129. dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
  5130. return -ENODEV;
  5131. }
  5132. uplink_seid = vsi->uplink_seid;
  5133. if (vsi->type != I40E_VSI_SRIOV) {
  5134. if (vsi->netdev_registered) {
  5135. vsi->netdev_registered = false;
  5136. if (vsi->netdev) {
  5137. /* results in a call to i40e_close() */
  5138. unregister_netdev(vsi->netdev);
  5139. free_netdev(vsi->netdev);
  5140. vsi->netdev = NULL;
  5141. }
  5142. } else {
  5143. if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
  5144. i40e_down(vsi);
  5145. i40e_vsi_free_irq(vsi);
  5146. i40e_vsi_free_tx_resources(vsi);
  5147. i40e_vsi_free_rx_resources(vsi);
  5148. }
  5149. i40e_vsi_disable_irq(vsi);
  5150. }
  5151. list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
  5152. i40e_del_filter(vsi, f->macaddr, f->vlan,
  5153. f->is_vf, f->is_netdev);
  5154. i40e_sync_vsi_filters(vsi);
  5155. i40e_vsi_delete(vsi);
  5156. i40e_vsi_free_q_vectors(vsi);
  5157. i40e_vsi_clear_rings(vsi);
  5158. i40e_vsi_clear(vsi);
  5159. /* If this was the last thing on the VEB, except for the
  5160. * controlling VSI, remove the VEB, which puts the controlling
  5161. * VSI onto the next level down in the switch.
  5162. *
  5163. * Well, okay, there's one more exception here: don't remove
  5164. * the orphan VEBs yet. We'll wait for an explicit remove request
  5165. * from up the network stack.
  5166. */
  5167. for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
  5168. if (pf->vsi[i] &&
  5169. pf->vsi[i]->uplink_seid == uplink_seid &&
  5170. (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
  5171. n++; /* count the VSIs */
  5172. }
  5173. }
  5174. for (i = 0; i < I40E_MAX_VEB; i++) {
  5175. if (!pf->veb[i])
  5176. continue;
  5177. if (pf->veb[i]->uplink_seid == uplink_seid)
  5178. n++; /* count the VEBs */
  5179. if (pf->veb[i]->seid == uplink_seid)
  5180. veb = pf->veb[i];
  5181. }
  5182. if (n == 0 && veb && veb->uplink_seid != 0)
  5183. i40e_veb_release(veb);
  5184. return 0;
  5185. }
  5186. /**
  5187. * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
  5188. * @vsi: ptr to the VSI
  5189. *
  5190. * This should only be called after i40e_vsi_mem_alloc() which allocates the
  5191. * corresponding SW VSI structure and initializes num_queue_pairs for the
  5192. * newly allocated VSI.
  5193. *
  5194. * Returns 0 on success or negative on failure
  5195. **/
  5196. static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
  5197. {
  5198. int ret = -ENOENT;
  5199. struct i40e_pf *pf = vsi->back;
  5200. if (vsi->q_vectors) {
  5201. dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
  5202. vsi->seid);
  5203. return -EEXIST;
  5204. }
  5205. if (vsi->base_vector) {
  5206. dev_info(&pf->pdev->dev,
  5207. "VSI %d has non-zero base vector %d\n",
  5208. vsi->seid, vsi->base_vector);
  5209. return -EEXIST;
  5210. }
  5211. ret = i40e_alloc_q_vectors(vsi);
  5212. if (ret) {
  5213. dev_info(&pf->pdev->dev,
  5214. "failed to allocate %d q_vector for VSI %d, ret=%d\n",
  5215. vsi->num_q_vectors, vsi->seid, ret);
  5216. vsi->num_q_vectors = 0;
  5217. goto vector_setup_out;
  5218. }
  5219. vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
  5220. vsi->num_q_vectors, vsi->idx);
  5221. if (vsi->base_vector < 0) {
  5222. dev_info(&pf->pdev->dev,
  5223. "failed to get q tracking for VSI %d, err=%d\n",
  5224. vsi->seid, vsi->base_vector);
  5225. i40e_vsi_free_q_vectors(vsi);
  5226. ret = -ENOENT;
  5227. goto vector_setup_out;
  5228. }
  5229. vector_setup_out:
  5230. return ret;
  5231. }
  5232. /**
  5233. * i40e_vsi_setup - Set up a VSI by a given type
  5234. * @pf: board private structure
  5235. * @type: VSI type
  5236. * @uplink_seid: the switch element to link to
  5237. * @param1: usage depends upon VSI type. For VF types, indicates VF id
  5238. *
  5239. * This allocates the sw VSI structure and its queue resources, then add a VSI
  5240. * to the identified VEB.
  5241. *
  5242. * Returns pointer to the successfully allocated and configure VSI sw struct on
  5243. * success, otherwise returns NULL on failure.
  5244. **/
  5245. struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
  5246. u16 uplink_seid, u32 param1)
  5247. {
  5248. struct i40e_vsi *vsi = NULL;
  5249. struct i40e_veb *veb = NULL;
  5250. int ret, i;
  5251. int v_idx;
  5252. /* The requested uplink_seid must be either
  5253. * - the PF's port seid
  5254. * no VEB is needed because this is the PF
  5255. * or this is a Flow Director special case VSI
  5256. * - seid of an existing VEB
  5257. * - seid of a VSI that owns an existing VEB
  5258. * - seid of a VSI that doesn't own a VEB
  5259. * a new VEB is created and the VSI becomes the owner
  5260. * - seid of the PF VSI, which is what creates the first VEB
  5261. * this is a special case of the previous
  5262. *
  5263. * Find which uplink_seid we were given and create a new VEB if needed
  5264. */
  5265. for (i = 0; i < I40E_MAX_VEB; i++) {
  5266. if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
  5267. veb = pf->veb[i];
  5268. break;
  5269. }
  5270. }
  5271. if (!veb && uplink_seid != pf->mac_seid) {
  5272. for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
  5273. if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
  5274. vsi = pf->vsi[i];
  5275. break;
  5276. }
  5277. }
  5278. if (!vsi) {
  5279. dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
  5280. uplink_seid);
  5281. return NULL;
  5282. }
  5283. if (vsi->uplink_seid == pf->mac_seid)
  5284. veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
  5285. vsi->tc_config.enabled_tc);
  5286. else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
  5287. veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
  5288. vsi->tc_config.enabled_tc);
  5289. for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
  5290. if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
  5291. veb = pf->veb[i];
  5292. }
  5293. if (!veb) {
  5294. dev_info(&pf->pdev->dev, "couldn't add VEB\n");
  5295. return NULL;
  5296. }
  5297. vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
  5298. uplink_seid = veb->seid;
  5299. }
  5300. /* get vsi sw struct */
  5301. v_idx = i40e_vsi_mem_alloc(pf, type);
  5302. if (v_idx < 0)
  5303. goto err_alloc;
  5304. vsi = pf->vsi[v_idx];
  5305. vsi->type = type;
  5306. vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
  5307. if (type == I40E_VSI_MAIN)
  5308. pf->lan_vsi = v_idx;
  5309. else if (type == I40E_VSI_SRIOV)
  5310. vsi->vf_id = param1;
  5311. /* assign it some queues */
  5312. ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
  5313. if (ret < 0) {
  5314. dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
  5315. vsi->seid, ret);
  5316. goto err_vsi;
  5317. }
  5318. vsi->base_queue = ret;
  5319. /* get a VSI from the hardware */
  5320. vsi->uplink_seid = uplink_seid;
  5321. ret = i40e_add_vsi(vsi);
  5322. if (ret)
  5323. goto err_vsi;
  5324. switch (vsi->type) {
  5325. /* setup the netdev if needed */
  5326. case I40E_VSI_MAIN:
  5327. case I40E_VSI_VMDQ2:
  5328. ret = i40e_config_netdev(vsi);
  5329. if (ret)
  5330. goto err_netdev;
  5331. ret = register_netdev(vsi->netdev);
  5332. if (ret)
  5333. goto err_netdev;
  5334. vsi->netdev_registered = true;
  5335. netif_carrier_off(vsi->netdev);
  5336. /* fall through */
  5337. case I40E_VSI_FDIR:
  5338. /* set up vectors and rings if needed */
  5339. ret = i40e_vsi_setup_vectors(vsi);
  5340. if (ret)
  5341. goto err_msix;
  5342. ret = i40e_alloc_rings(vsi);
  5343. if (ret)
  5344. goto err_rings;
  5345. /* map all of the rings to the q_vectors */
  5346. i40e_vsi_map_rings_to_vectors(vsi);
  5347. i40e_vsi_reset_stats(vsi);
  5348. break;
  5349. default:
  5350. /* no netdev or rings for the other VSI types */
  5351. break;
  5352. }
  5353. return vsi;
  5354. err_rings:
  5355. i40e_vsi_free_q_vectors(vsi);
  5356. err_msix:
  5357. if (vsi->netdev_registered) {
  5358. vsi->netdev_registered = false;
  5359. unregister_netdev(vsi->netdev);
  5360. free_netdev(vsi->netdev);
  5361. vsi->netdev = NULL;
  5362. }
  5363. err_netdev:
  5364. i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
  5365. err_vsi:
  5366. i40e_vsi_clear(vsi);
  5367. err_alloc:
  5368. return NULL;
  5369. }
  5370. /**
  5371. * i40e_veb_get_bw_info - Query VEB BW information
  5372. * @veb: the veb to query
  5373. *
  5374. * Query the Tx scheduler BW configuration data for given VEB
  5375. **/
  5376. static int i40e_veb_get_bw_info(struct i40e_veb *veb)
  5377. {
  5378. struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
  5379. struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
  5380. struct i40e_pf *pf = veb->pf;
  5381. struct i40e_hw *hw = &pf->hw;
  5382. u32 tc_bw_max;
  5383. int ret = 0;
  5384. int i;
  5385. ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
  5386. &bw_data, NULL);
  5387. if (ret) {
  5388. dev_info(&pf->pdev->dev,
  5389. "query veb bw config failed, aq_err=%d\n",
  5390. hw->aq.asq_last_status);
  5391. goto out;
  5392. }
  5393. ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
  5394. &ets_data, NULL);
  5395. if (ret) {
  5396. dev_info(&pf->pdev->dev,
  5397. "query veb bw ets config failed, aq_err=%d\n",
  5398. hw->aq.asq_last_status);
  5399. goto out;
  5400. }
  5401. veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
  5402. veb->bw_max_quanta = ets_data.tc_bw_max;
  5403. veb->is_abs_credits = bw_data.absolute_credits_enable;
  5404. tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
  5405. (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
  5406. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  5407. veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
  5408. veb->bw_tc_limit_credits[i] =
  5409. le16_to_cpu(bw_data.tc_bw_limits[i]);
  5410. veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
  5411. }
  5412. out:
  5413. return ret;
  5414. }
  5415. /**
  5416. * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
  5417. * @pf: board private structure
  5418. *
  5419. * On error: returns error code (negative)
  5420. * On success: returns vsi index in PF (positive)
  5421. **/
  5422. static int i40e_veb_mem_alloc(struct i40e_pf *pf)
  5423. {
  5424. int ret = -ENOENT;
  5425. struct i40e_veb *veb;
  5426. int i;
  5427. /* Need to protect the allocation of switch elements at the PF level */
  5428. mutex_lock(&pf->switch_mutex);
  5429. /* VEB list may be fragmented if VEB creation/destruction has
  5430. * been happening. We can afford to do a quick scan to look
  5431. * for any free slots in the list.
  5432. *
  5433. * find next empty veb slot, looping back around if necessary
  5434. */
  5435. i = 0;
  5436. while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
  5437. i++;
  5438. if (i >= I40E_MAX_VEB) {
  5439. ret = -ENOMEM;
  5440. goto err_alloc_veb; /* out of VEB slots! */
  5441. }
  5442. veb = kzalloc(sizeof(*veb), GFP_KERNEL);
  5443. if (!veb) {
  5444. ret = -ENOMEM;
  5445. goto err_alloc_veb;
  5446. }
  5447. veb->pf = pf;
  5448. veb->idx = i;
  5449. veb->enabled_tc = 1;
  5450. pf->veb[i] = veb;
  5451. ret = i;
  5452. err_alloc_veb:
  5453. mutex_unlock(&pf->switch_mutex);
  5454. return ret;
  5455. }
  5456. /**
  5457. * i40e_switch_branch_release - Delete a branch of the switch tree
  5458. * @branch: where to start deleting
  5459. *
  5460. * This uses recursion to find the tips of the branch to be
  5461. * removed, deleting until we get back to and can delete this VEB.
  5462. **/
  5463. static void i40e_switch_branch_release(struct i40e_veb *branch)
  5464. {
  5465. struct i40e_pf *pf = branch->pf;
  5466. u16 branch_seid = branch->seid;
  5467. u16 veb_idx = branch->idx;
  5468. int i;
  5469. /* release any VEBs on this VEB - RECURSION */
  5470. for (i = 0; i < I40E_MAX_VEB; i++) {
  5471. if (!pf->veb[i])
  5472. continue;
  5473. if (pf->veb[i]->uplink_seid == branch->seid)
  5474. i40e_switch_branch_release(pf->veb[i]);
  5475. }
  5476. /* Release the VSIs on this VEB, but not the owner VSI.
  5477. *
  5478. * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
  5479. * the VEB itself, so don't use (*branch) after this loop.
  5480. */
  5481. for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
  5482. if (!pf->vsi[i])
  5483. continue;
  5484. if (pf->vsi[i]->uplink_seid == branch_seid &&
  5485. (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
  5486. i40e_vsi_release(pf->vsi[i]);
  5487. }
  5488. }
  5489. /* There's one corner case where the VEB might not have been
  5490. * removed, so double check it here and remove it if needed.
  5491. * This case happens if the veb was created from the debugfs
  5492. * commands and no VSIs were added to it.
  5493. */
  5494. if (pf->veb[veb_idx])
  5495. i40e_veb_release(pf->veb[veb_idx]);
  5496. }
  5497. /**
  5498. * i40e_veb_clear - remove veb struct
  5499. * @veb: the veb to remove
  5500. **/
  5501. static void i40e_veb_clear(struct i40e_veb *veb)
  5502. {
  5503. if (!veb)
  5504. return;
  5505. if (veb->pf) {
  5506. struct i40e_pf *pf = veb->pf;
  5507. mutex_lock(&pf->switch_mutex);
  5508. if (pf->veb[veb->idx] == veb)
  5509. pf->veb[veb->idx] = NULL;
  5510. mutex_unlock(&pf->switch_mutex);
  5511. }
  5512. kfree(veb);
  5513. }
  5514. /**
  5515. * i40e_veb_release - Delete a VEB and free its resources
  5516. * @veb: the VEB being removed
  5517. **/
  5518. void i40e_veb_release(struct i40e_veb *veb)
  5519. {
  5520. struct i40e_vsi *vsi = NULL;
  5521. struct i40e_pf *pf;
  5522. int i, n = 0;
  5523. pf = veb->pf;
  5524. /* find the remaining VSI and check for extras */
  5525. for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
  5526. if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
  5527. n++;
  5528. vsi = pf->vsi[i];
  5529. }
  5530. }
  5531. if (n != 1) {
  5532. dev_info(&pf->pdev->dev,
  5533. "can't remove VEB %d with %d VSIs left\n",
  5534. veb->seid, n);
  5535. return;
  5536. }
  5537. /* move the remaining VSI to uplink veb */
  5538. vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
  5539. if (veb->uplink_seid) {
  5540. vsi->uplink_seid = veb->uplink_seid;
  5541. if (veb->uplink_seid == pf->mac_seid)
  5542. vsi->veb_idx = I40E_NO_VEB;
  5543. else
  5544. vsi->veb_idx = veb->veb_idx;
  5545. } else {
  5546. /* floating VEB */
  5547. vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
  5548. vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
  5549. }
  5550. i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
  5551. i40e_veb_clear(veb);
  5552. return;
  5553. }
  5554. /**
  5555. * i40e_add_veb - create the VEB in the switch
  5556. * @veb: the VEB to be instantiated
  5557. * @vsi: the controlling VSI
  5558. **/
  5559. static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
  5560. {
  5561. bool is_default = (vsi->idx == vsi->back->lan_vsi);
  5562. int ret;
  5563. /* get a VEB from the hardware */
  5564. ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
  5565. veb->enabled_tc, is_default, &veb->seid, NULL);
  5566. if (ret) {
  5567. dev_info(&veb->pf->pdev->dev,
  5568. "couldn't add VEB, err %d, aq_err %d\n",
  5569. ret, veb->pf->hw.aq.asq_last_status);
  5570. return -EPERM;
  5571. }
  5572. /* get statistics counter */
  5573. ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
  5574. &veb->stats_idx, NULL, NULL, NULL);
  5575. if (ret) {
  5576. dev_info(&veb->pf->pdev->dev,
  5577. "couldn't get VEB statistics idx, err %d, aq_err %d\n",
  5578. ret, veb->pf->hw.aq.asq_last_status);
  5579. return -EPERM;
  5580. }
  5581. ret = i40e_veb_get_bw_info(veb);
  5582. if (ret) {
  5583. dev_info(&veb->pf->pdev->dev,
  5584. "couldn't get VEB bw info, err %d, aq_err %d\n",
  5585. ret, veb->pf->hw.aq.asq_last_status);
  5586. i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
  5587. return -ENOENT;
  5588. }
  5589. vsi->uplink_seid = veb->seid;
  5590. vsi->veb_idx = veb->idx;
  5591. vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
  5592. return 0;
  5593. }
  5594. /**
  5595. * i40e_veb_setup - Set up a VEB
  5596. * @pf: board private structure
  5597. * @flags: VEB setup flags
  5598. * @uplink_seid: the switch element to link to
  5599. * @vsi_seid: the initial VSI seid
  5600. * @enabled_tc: Enabled TC bit-map
  5601. *
  5602. * This allocates the sw VEB structure and links it into the switch
  5603. * It is possible and legal for this to be a duplicate of an already
  5604. * existing VEB. It is also possible for both uplink and vsi seids
  5605. * to be zero, in order to create a floating VEB.
  5606. *
  5607. * Returns pointer to the successfully allocated VEB sw struct on
  5608. * success, otherwise returns NULL on failure.
  5609. **/
  5610. struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
  5611. u16 uplink_seid, u16 vsi_seid,
  5612. u8 enabled_tc)
  5613. {
  5614. struct i40e_veb *veb, *uplink_veb = NULL;
  5615. int vsi_idx, veb_idx;
  5616. int ret;
  5617. /* if one seid is 0, the other must be 0 to create a floating relay */
  5618. if ((uplink_seid == 0 || vsi_seid == 0) &&
  5619. (uplink_seid + vsi_seid != 0)) {
  5620. dev_info(&pf->pdev->dev,
  5621. "one, not both seid's are 0: uplink=%d vsi=%d\n",
  5622. uplink_seid, vsi_seid);
  5623. return NULL;
  5624. }
  5625. /* make sure there is such a vsi and uplink */
  5626. for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
  5627. if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
  5628. break;
  5629. if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
  5630. dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
  5631. vsi_seid);
  5632. return NULL;
  5633. }
  5634. if (uplink_seid && uplink_seid != pf->mac_seid) {
  5635. for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
  5636. if (pf->veb[veb_idx] &&
  5637. pf->veb[veb_idx]->seid == uplink_seid) {
  5638. uplink_veb = pf->veb[veb_idx];
  5639. break;
  5640. }
  5641. }
  5642. if (!uplink_veb) {
  5643. dev_info(&pf->pdev->dev,
  5644. "uplink seid %d not found\n", uplink_seid);
  5645. return NULL;
  5646. }
  5647. }
  5648. /* get veb sw struct */
  5649. veb_idx = i40e_veb_mem_alloc(pf);
  5650. if (veb_idx < 0)
  5651. goto err_alloc;
  5652. veb = pf->veb[veb_idx];
  5653. veb->flags = flags;
  5654. veb->uplink_seid = uplink_seid;
  5655. veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
  5656. veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
  5657. /* create the VEB in the switch */
  5658. ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
  5659. if (ret)
  5660. goto err_veb;
  5661. return veb;
  5662. err_veb:
  5663. i40e_veb_clear(veb);
  5664. err_alloc:
  5665. return NULL;
  5666. }
  5667. /**
  5668. * i40e_setup_pf_switch_element - set pf vars based on switch type
  5669. * @pf: board private structure
  5670. * @ele: element we are building info from
  5671. * @num_reported: total number of elements
  5672. * @printconfig: should we print the contents
  5673. *
  5674. * helper function to assist in extracting a few useful SEID values.
  5675. **/
  5676. static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
  5677. struct i40e_aqc_switch_config_element_resp *ele,
  5678. u16 num_reported, bool printconfig)
  5679. {
  5680. u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
  5681. u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
  5682. u8 element_type = ele->element_type;
  5683. u16 seid = le16_to_cpu(ele->seid);
  5684. if (printconfig)
  5685. dev_info(&pf->pdev->dev,
  5686. "type=%d seid=%d uplink=%d downlink=%d\n",
  5687. element_type, seid, uplink_seid, downlink_seid);
  5688. switch (element_type) {
  5689. case I40E_SWITCH_ELEMENT_TYPE_MAC:
  5690. pf->mac_seid = seid;
  5691. break;
  5692. case I40E_SWITCH_ELEMENT_TYPE_VEB:
  5693. /* Main VEB? */
  5694. if (uplink_seid != pf->mac_seid)
  5695. break;
  5696. if (pf->lan_veb == I40E_NO_VEB) {
  5697. int v;
  5698. /* find existing or else empty VEB */
  5699. for (v = 0; v < I40E_MAX_VEB; v++) {
  5700. if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
  5701. pf->lan_veb = v;
  5702. break;
  5703. }
  5704. }
  5705. if (pf->lan_veb == I40E_NO_VEB) {
  5706. v = i40e_veb_mem_alloc(pf);
  5707. if (v < 0)
  5708. break;
  5709. pf->lan_veb = v;
  5710. }
  5711. }
  5712. pf->veb[pf->lan_veb]->seid = seid;
  5713. pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
  5714. pf->veb[pf->lan_veb]->pf = pf;
  5715. pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
  5716. break;
  5717. case I40E_SWITCH_ELEMENT_TYPE_VSI:
  5718. if (num_reported != 1)
  5719. break;
  5720. /* This is immediately after a reset so we can assume this is
  5721. * the PF's VSI
  5722. */
  5723. pf->mac_seid = uplink_seid;
  5724. pf->pf_seid = downlink_seid;
  5725. pf->main_vsi_seid = seid;
  5726. if (printconfig)
  5727. dev_info(&pf->pdev->dev,
  5728. "pf_seid=%d main_vsi_seid=%d\n",
  5729. pf->pf_seid, pf->main_vsi_seid);
  5730. break;
  5731. case I40E_SWITCH_ELEMENT_TYPE_PF:
  5732. case I40E_SWITCH_ELEMENT_TYPE_VF:
  5733. case I40E_SWITCH_ELEMENT_TYPE_EMP:
  5734. case I40E_SWITCH_ELEMENT_TYPE_BMC:
  5735. case I40E_SWITCH_ELEMENT_TYPE_PE:
  5736. case I40E_SWITCH_ELEMENT_TYPE_PA:
  5737. /* ignore these for now */
  5738. break;
  5739. default:
  5740. dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
  5741. element_type, seid);
  5742. break;
  5743. }
  5744. }
  5745. /**
  5746. * i40e_fetch_switch_configuration - Get switch config from firmware
  5747. * @pf: board private structure
  5748. * @printconfig: should we print the contents
  5749. *
  5750. * Get the current switch configuration from the device and
  5751. * extract a few useful SEID values.
  5752. **/
  5753. int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
  5754. {
  5755. struct i40e_aqc_get_switch_config_resp *sw_config;
  5756. u16 next_seid = 0;
  5757. int ret = 0;
  5758. u8 *aq_buf;
  5759. int i;
  5760. aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
  5761. if (!aq_buf)
  5762. return -ENOMEM;
  5763. sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
  5764. do {
  5765. u16 num_reported, num_total;
  5766. ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
  5767. I40E_AQ_LARGE_BUF,
  5768. &next_seid, NULL);
  5769. if (ret) {
  5770. dev_info(&pf->pdev->dev,
  5771. "get switch config failed %d aq_err=%x\n",
  5772. ret, pf->hw.aq.asq_last_status);
  5773. kfree(aq_buf);
  5774. return -ENOENT;
  5775. }
  5776. num_reported = le16_to_cpu(sw_config->header.num_reported);
  5777. num_total = le16_to_cpu(sw_config->header.num_total);
  5778. if (printconfig)
  5779. dev_info(&pf->pdev->dev,
  5780. "header: %d reported %d total\n",
  5781. num_reported, num_total);
  5782. if (num_reported) {
  5783. int sz = sizeof(*sw_config) * num_reported;
  5784. kfree(pf->sw_config);
  5785. pf->sw_config = kzalloc(sz, GFP_KERNEL);
  5786. if (pf->sw_config)
  5787. memcpy(pf->sw_config, sw_config, sz);
  5788. }
  5789. for (i = 0; i < num_reported; i++) {
  5790. struct i40e_aqc_switch_config_element_resp *ele =
  5791. &sw_config->element[i];
  5792. i40e_setup_pf_switch_element(pf, ele, num_reported,
  5793. printconfig);
  5794. }
  5795. } while (next_seid != 0);
  5796. kfree(aq_buf);
  5797. return ret;
  5798. }
  5799. /**
  5800. * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
  5801. * @pf: board private structure
  5802. *
  5803. * Returns 0 on success, negative value on failure
  5804. **/
  5805. static int i40e_setup_pf_switch(struct i40e_pf *pf)
  5806. {
  5807. int ret;
  5808. /* find out what's out there already */
  5809. ret = i40e_fetch_switch_configuration(pf, false);
  5810. if (ret) {
  5811. dev_info(&pf->pdev->dev,
  5812. "couldn't fetch switch config, err %d, aq_err %d\n",
  5813. ret, pf->hw.aq.asq_last_status);
  5814. return ret;
  5815. }
  5816. i40e_pf_reset_stats(pf);
  5817. /* fdir VSI must happen first to be sure it gets queue 0, but only
  5818. * if there is enough room for the fdir VSI
  5819. */
  5820. if (pf->num_lan_qps > 1)
  5821. i40e_fdir_setup(pf);
  5822. /* first time setup */
  5823. if (pf->lan_vsi == I40E_NO_VSI) {
  5824. struct i40e_vsi *vsi = NULL;
  5825. u16 uplink_seid;
  5826. /* Set up the PF VSI associated with the PF's main VSI
  5827. * that is already in the HW switch
  5828. */
  5829. if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
  5830. uplink_seid = pf->veb[pf->lan_veb]->seid;
  5831. else
  5832. uplink_seid = pf->mac_seid;
  5833. vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
  5834. if (!vsi) {
  5835. dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
  5836. i40e_fdir_teardown(pf);
  5837. return -EAGAIN;
  5838. }
  5839. /* accommodate kcompat by copying the main VSI queue count
  5840. * into the pf, since this newer code pushes the pf queue
  5841. * info down a level into a VSI
  5842. */
  5843. pf->num_rx_queues = vsi->alloc_queue_pairs;
  5844. pf->num_tx_queues = vsi->alloc_queue_pairs;
  5845. } else {
  5846. /* force a reset of TC and queue layout configurations */
  5847. u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
  5848. pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
  5849. pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
  5850. i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
  5851. }
  5852. i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
  5853. /* Setup static PF queue filter control settings */
  5854. ret = i40e_setup_pf_filter_control(pf);
  5855. if (ret) {
  5856. dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
  5857. ret);
  5858. /* Failure here should not stop continuing other steps */
  5859. }
  5860. /* enable RSS in the HW, even for only one queue, as the stack can use
  5861. * the hash
  5862. */
  5863. if ((pf->flags & I40E_FLAG_RSS_ENABLED))
  5864. i40e_config_rss(pf);
  5865. /* fill in link information and enable LSE reporting */
  5866. i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
  5867. i40e_link_event(pf);
  5868. /* Initialize user-specifics link properties */
  5869. pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
  5870. I40E_AQ_AN_COMPLETED) ? true : false);
  5871. pf->hw.fc.requested_mode = I40E_FC_DEFAULT;
  5872. if (pf->hw.phy.link_info.an_info &
  5873. (I40E_AQ_LINK_PAUSE_TX | I40E_AQ_LINK_PAUSE_RX))
  5874. pf->hw.fc.current_mode = I40E_FC_FULL;
  5875. else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
  5876. pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
  5877. else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
  5878. pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
  5879. else
  5880. pf->hw.fc.current_mode = I40E_FC_DEFAULT;
  5881. return ret;
  5882. }
  5883. /**
  5884. * i40e_set_rss_size - helper to set rss_size
  5885. * @pf: board private structure
  5886. * @queues_left: how many queues
  5887. */
  5888. static u16 i40e_set_rss_size(struct i40e_pf *pf, int queues_left)
  5889. {
  5890. int num_tc0;
  5891. num_tc0 = min_t(int, queues_left, pf->rss_size_max);
  5892. num_tc0 = min_t(int, num_tc0, nr_cpus_node(numa_node_id()));
  5893. num_tc0 = rounddown_pow_of_two(num_tc0);
  5894. return num_tc0;
  5895. }
  5896. /**
  5897. * i40e_determine_queue_usage - Work out queue distribution
  5898. * @pf: board private structure
  5899. **/
  5900. static void i40e_determine_queue_usage(struct i40e_pf *pf)
  5901. {
  5902. int accum_tc_size;
  5903. int queues_left;
  5904. pf->num_lan_qps = 0;
  5905. pf->num_tc_qps = rounddown_pow_of_two(pf->num_tc_qps);
  5906. accum_tc_size = (I40E_MAX_TRAFFIC_CLASS - 1) * pf->num_tc_qps;
  5907. /* Find the max queues to be put into basic use. We'll always be
  5908. * using TC0, whether or not DCB is running, and TC0 will get the
  5909. * big RSS set.
  5910. */
  5911. queues_left = pf->hw.func_caps.num_tx_qp;
  5912. if (!((pf->flags & I40E_FLAG_MSIX_ENABLED) &&
  5913. (pf->flags & I40E_FLAG_MQ_ENABLED)) ||
  5914. !(pf->flags & (I40E_FLAG_RSS_ENABLED |
  5915. I40E_FLAG_FDIR_ENABLED | I40E_FLAG_DCB_ENABLED)) ||
  5916. (queues_left == 1)) {
  5917. /* one qp for PF, no queues for anything else */
  5918. queues_left = 0;
  5919. pf->rss_size = pf->num_lan_qps = 1;
  5920. /* make sure all the fancies are disabled */
  5921. pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
  5922. I40E_FLAG_MQ_ENABLED |
  5923. I40E_FLAG_FDIR_ENABLED |
  5924. I40E_FLAG_FDIR_ATR_ENABLED |
  5925. I40E_FLAG_DCB_ENABLED |
  5926. I40E_FLAG_SRIOV_ENABLED |
  5927. I40E_FLAG_VMDQ_ENABLED);
  5928. } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
  5929. !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
  5930. !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
  5931. pf->rss_size = i40e_set_rss_size(pf, queues_left);
  5932. queues_left -= pf->rss_size;
  5933. pf->num_lan_qps = pf->rss_size;
  5934. } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
  5935. !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
  5936. (pf->flags & I40E_FLAG_DCB_ENABLED)) {
  5937. /* save num_tc_qps queues for TCs 1 thru 7 and the rest
  5938. * are set up for RSS in TC0
  5939. */
  5940. queues_left -= accum_tc_size;
  5941. pf->rss_size = i40e_set_rss_size(pf, queues_left);
  5942. queues_left -= pf->rss_size;
  5943. if (queues_left < 0) {
  5944. dev_info(&pf->pdev->dev, "not enough queues for DCB\n");
  5945. return;
  5946. }
  5947. pf->num_lan_qps = pf->rss_size + accum_tc_size;
  5948. } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
  5949. (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
  5950. !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
  5951. queues_left -= 1; /* save 1 queue for FD */
  5952. pf->rss_size = i40e_set_rss_size(pf, queues_left);
  5953. queues_left -= pf->rss_size;
  5954. if (queues_left < 0) {
  5955. dev_info(&pf->pdev->dev, "not enough queues for Flow Director\n");
  5956. return;
  5957. }
  5958. pf->num_lan_qps = pf->rss_size;
  5959. } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
  5960. (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
  5961. (pf->flags & I40E_FLAG_DCB_ENABLED)) {
  5962. /* save 1 queue for TCs 1 thru 7,
  5963. * 1 queue for flow director,
  5964. * and the rest are set up for RSS in TC0
  5965. */
  5966. queues_left -= 1;
  5967. queues_left -= accum_tc_size;
  5968. pf->rss_size = i40e_set_rss_size(pf, queues_left);
  5969. queues_left -= pf->rss_size;
  5970. if (queues_left < 0) {
  5971. dev_info(&pf->pdev->dev, "not enough queues for DCB and Flow Director\n");
  5972. return;
  5973. }
  5974. pf->num_lan_qps = pf->rss_size + accum_tc_size;
  5975. } else {
  5976. dev_info(&pf->pdev->dev,
  5977. "Invalid configuration, flags=0x%08llx\n", pf->flags);
  5978. return;
  5979. }
  5980. if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
  5981. pf->num_vf_qps && pf->num_req_vfs && queues_left) {
  5982. pf->num_req_vfs = min_t(int, pf->num_req_vfs, (queues_left /
  5983. pf->num_vf_qps));
  5984. queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
  5985. }
  5986. if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
  5987. pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
  5988. pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
  5989. (queues_left / pf->num_vmdq_qps));
  5990. queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
  5991. }
  5992. return;
  5993. }
  5994. /**
  5995. * i40e_setup_pf_filter_control - Setup PF static filter control
  5996. * @pf: PF to be setup
  5997. *
  5998. * i40e_setup_pf_filter_control sets up a pf's initial filter control
  5999. * settings. If PE/FCoE are enabled then it will also set the per PF
  6000. * based filter sizes required for them. It also enables Flow director,
  6001. * ethertype and macvlan type filter settings for the pf.
  6002. *
  6003. * Returns 0 on success, negative on failure
  6004. **/
  6005. static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
  6006. {
  6007. struct i40e_filter_control_settings *settings = &pf->filter_settings;
  6008. settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
  6009. /* Flow Director is enabled */
  6010. if (pf->flags & (I40E_FLAG_FDIR_ENABLED | I40E_FLAG_FDIR_ATR_ENABLED))
  6011. settings->enable_fdir = true;
  6012. /* Ethtype and MACVLAN filters enabled for PF */
  6013. settings->enable_ethtype = true;
  6014. settings->enable_macvlan = true;
  6015. if (i40e_set_filter_control(&pf->hw, settings))
  6016. return -ENOENT;
  6017. return 0;
  6018. }
  6019. /**
  6020. * i40e_probe - Device initialization routine
  6021. * @pdev: PCI device information struct
  6022. * @ent: entry in i40e_pci_tbl
  6023. *
  6024. * i40e_probe initializes a pf identified by a pci_dev structure.
  6025. * The OS initialization, configuring of the pf private structure,
  6026. * and a hardware reset occur.
  6027. *
  6028. * Returns 0 on success, negative on failure
  6029. **/
  6030. static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6031. {
  6032. struct i40e_driver_version dv;
  6033. struct i40e_pf *pf;
  6034. struct i40e_hw *hw;
  6035. int err = 0;
  6036. u32 len;
  6037. err = pci_enable_device_mem(pdev);
  6038. if (err)
  6039. return err;
  6040. /* set up for high or low dma */
  6041. if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
  6042. /* coherent mask for the same size will always succeed if
  6043. * dma_set_mask does
  6044. */
  6045. dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
  6046. } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
  6047. dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
  6048. } else {
  6049. dev_err(&pdev->dev, "DMA configuration failed: %d\n", err);
  6050. err = -EIO;
  6051. goto err_dma;
  6052. }
  6053. /* set up pci connections */
  6054. err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
  6055. IORESOURCE_MEM), i40e_driver_name);
  6056. if (err) {
  6057. dev_info(&pdev->dev,
  6058. "pci_request_selected_regions failed %d\n", err);
  6059. goto err_pci_reg;
  6060. }
  6061. pci_enable_pcie_error_reporting(pdev);
  6062. pci_set_master(pdev);
  6063. /* Now that we have a PCI connection, we need to do the
  6064. * low level device setup. This is primarily setting up
  6065. * the Admin Queue structures and then querying for the
  6066. * device's current profile information.
  6067. */
  6068. pf = kzalloc(sizeof(*pf), GFP_KERNEL);
  6069. if (!pf) {
  6070. err = -ENOMEM;
  6071. goto err_pf_alloc;
  6072. }
  6073. pf->next_vsi = 0;
  6074. pf->pdev = pdev;
  6075. set_bit(__I40E_DOWN, &pf->state);
  6076. hw = &pf->hw;
  6077. hw->back = pf;
  6078. hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
  6079. pci_resource_len(pdev, 0));
  6080. if (!hw->hw_addr) {
  6081. err = -EIO;
  6082. dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
  6083. (unsigned int)pci_resource_start(pdev, 0),
  6084. (unsigned int)pci_resource_len(pdev, 0), err);
  6085. goto err_ioremap;
  6086. }
  6087. hw->vendor_id = pdev->vendor;
  6088. hw->device_id = pdev->device;
  6089. pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
  6090. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  6091. hw->subsystem_device_id = pdev->subsystem_device;
  6092. hw->bus.device = PCI_SLOT(pdev->devfn);
  6093. hw->bus.func = PCI_FUNC(pdev->devfn);
  6094. /* Reset here to make sure all is clean and to define PF 'n' */
  6095. err = i40e_pf_reset(hw);
  6096. if (err) {
  6097. dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
  6098. goto err_pf_reset;
  6099. }
  6100. pf->pfr_count++;
  6101. hw->aq.num_arq_entries = I40E_AQ_LEN;
  6102. hw->aq.num_asq_entries = I40E_AQ_LEN;
  6103. hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
  6104. hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
  6105. pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
  6106. snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
  6107. "%s-pf%d:misc",
  6108. dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
  6109. err = i40e_init_shared_code(hw);
  6110. if (err) {
  6111. dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
  6112. goto err_pf_reset;
  6113. }
  6114. err = i40e_init_adminq(hw);
  6115. dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
  6116. if (err) {
  6117. dev_info(&pdev->dev,
  6118. "init_adminq failed: %d expecting API %02x.%02x\n",
  6119. err,
  6120. I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
  6121. goto err_pf_reset;
  6122. }
  6123. err = i40e_get_capabilities(pf);
  6124. if (err)
  6125. goto err_adminq_setup;
  6126. err = i40e_sw_init(pf);
  6127. if (err) {
  6128. dev_info(&pdev->dev, "sw_init failed: %d\n", err);
  6129. goto err_sw_init;
  6130. }
  6131. err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
  6132. hw->func_caps.num_rx_qp,
  6133. pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
  6134. if (err) {
  6135. dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
  6136. goto err_init_lan_hmc;
  6137. }
  6138. err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
  6139. if (err) {
  6140. dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
  6141. err = -ENOENT;
  6142. goto err_configure_lan_hmc;
  6143. }
  6144. i40e_get_mac_addr(hw, hw->mac.addr);
  6145. if (i40e_validate_mac_addr(hw->mac.addr)) {
  6146. dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
  6147. err = -EIO;
  6148. goto err_mac_addr;
  6149. }
  6150. dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
  6151. memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
  6152. pci_set_drvdata(pdev, pf);
  6153. pci_save_state(pdev);
  6154. /* set up periodic task facility */
  6155. setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
  6156. pf->service_timer_period = HZ;
  6157. INIT_WORK(&pf->service_task, i40e_service_task);
  6158. clear_bit(__I40E_SERVICE_SCHED, &pf->state);
  6159. pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
  6160. pf->link_check_timeout = jiffies;
  6161. /* set up the main switch operations */
  6162. i40e_determine_queue_usage(pf);
  6163. i40e_init_interrupt_scheme(pf);
  6164. /* Set up the *vsi struct based on the number of VSIs in the HW,
  6165. * and set up our local tracking of the MAIN PF vsi.
  6166. */
  6167. len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
  6168. pf->vsi = kzalloc(len, GFP_KERNEL);
  6169. if (!pf->vsi)
  6170. goto err_switch_setup;
  6171. err = i40e_setup_pf_switch(pf);
  6172. if (err) {
  6173. dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
  6174. goto err_vsis;
  6175. }
  6176. /* The main driver is (mostly) up and happy. We need to set this state
  6177. * before setting up the misc vector or we get a race and the vector
  6178. * ends up disabled forever.
  6179. */
  6180. clear_bit(__I40E_DOWN, &pf->state);
  6181. /* In case of MSIX we are going to setup the misc vector right here
  6182. * to handle admin queue events etc. In case of legacy and MSI
  6183. * the misc functionality and queue processing is combined in
  6184. * the same vector and that gets setup at open.
  6185. */
  6186. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  6187. err = i40e_setup_misc_vector(pf);
  6188. if (err) {
  6189. dev_info(&pdev->dev,
  6190. "setup of misc vector failed: %d\n", err);
  6191. goto err_vsis;
  6192. }
  6193. }
  6194. /* prep for VF support */
  6195. if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
  6196. (pf->flags & I40E_FLAG_MSIX_ENABLED)) {
  6197. u32 val;
  6198. /* disable link interrupts for VFs */
  6199. val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
  6200. val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
  6201. wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
  6202. i40e_flush(hw);
  6203. }
  6204. i40e_dbg_pf_init(pf);
  6205. /* tell the firmware that we're starting */
  6206. dv.major_version = DRV_VERSION_MAJOR;
  6207. dv.minor_version = DRV_VERSION_MINOR;
  6208. dv.build_version = DRV_VERSION_BUILD;
  6209. dv.subbuild_version = 0;
  6210. i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
  6211. /* since everything's happy, start the service_task timer */
  6212. mod_timer(&pf->service_timer,
  6213. round_jiffies(jiffies + pf->service_timer_period));
  6214. return 0;
  6215. /* Unwind what we've done if something failed in the setup */
  6216. err_vsis:
  6217. set_bit(__I40E_DOWN, &pf->state);
  6218. err_switch_setup:
  6219. i40e_clear_interrupt_scheme(pf);
  6220. kfree(pf->vsi);
  6221. del_timer_sync(&pf->service_timer);
  6222. err_mac_addr:
  6223. err_configure_lan_hmc:
  6224. (void)i40e_shutdown_lan_hmc(hw);
  6225. err_init_lan_hmc:
  6226. kfree(pf->qp_pile);
  6227. kfree(pf->irq_pile);
  6228. err_sw_init:
  6229. err_adminq_setup:
  6230. (void)i40e_shutdown_adminq(hw);
  6231. err_pf_reset:
  6232. iounmap(hw->hw_addr);
  6233. err_ioremap:
  6234. kfree(pf);
  6235. err_pf_alloc:
  6236. pci_disable_pcie_error_reporting(pdev);
  6237. pci_release_selected_regions(pdev,
  6238. pci_select_bars(pdev, IORESOURCE_MEM));
  6239. err_pci_reg:
  6240. err_dma:
  6241. pci_disable_device(pdev);
  6242. return err;
  6243. }
  6244. /**
  6245. * i40e_remove - Device removal routine
  6246. * @pdev: PCI device information struct
  6247. *
  6248. * i40e_remove is called by the PCI subsystem to alert the driver
  6249. * that is should release a PCI device. This could be caused by a
  6250. * Hot-Plug event, or because the driver is going to be removed from
  6251. * memory.
  6252. **/
  6253. static void i40e_remove(struct pci_dev *pdev)
  6254. {
  6255. struct i40e_pf *pf = pci_get_drvdata(pdev);
  6256. i40e_status ret_code;
  6257. u32 reg;
  6258. int i;
  6259. i40e_dbg_pf_exit(pf);
  6260. if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
  6261. i40e_free_vfs(pf);
  6262. pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
  6263. }
  6264. /* no more scheduling of any task */
  6265. set_bit(__I40E_DOWN, &pf->state);
  6266. del_timer_sync(&pf->service_timer);
  6267. cancel_work_sync(&pf->service_task);
  6268. i40e_fdir_teardown(pf);
  6269. /* If there is a switch structure or any orphans, remove them.
  6270. * This will leave only the PF's VSI remaining.
  6271. */
  6272. for (i = 0; i < I40E_MAX_VEB; i++) {
  6273. if (!pf->veb[i])
  6274. continue;
  6275. if (pf->veb[i]->uplink_seid == pf->mac_seid ||
  6276. pf->veb[i]->uplink_seid == 0)
  6277. i40e_switch_branch_release(pf->veb[i]);
  6278. }
  6279. /* Now we can shutdown the PF's VSI, just before we kill
  6280. * adminq and hmc.
  6281. */
  6282. if (pf->vsi[pf->lan_vsi])
  6283. i40e_vsi_release(pf->vsi[pf->lan_vsi]);
  6284. i40e_stop_misc_vector(pf);
  6285. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  6286. synchronize_irq(pf->msix_entries[0].vector);
  6287. free_irq(pf->msix_entries[0].vector, pf);
  6288. }
  6289. /* shutdown and destroy the HMC */
  6290. ret_code = i40e_shutdown_lan_hmc(&pf->hw);
  6291. if (ret_code)
  6292. dev_warn(&pdev->dev,
  6293. "Failed to destroy the HMC resources: %d\n", ret_code);
  6294. /* shutdown the adminq */
  6295. i40e_aq_queue_shutdown(&pf->hw, true);
  6296. ret_code = i40e_shutdown_adminq(&pf->hw);
  6297. if (ret_code)
  6298. dev_warn(&pdev->dev,
  6299. "Failed to destroy the Admin Queue resources: %d\n",
  6300. ret_code);
  6301. /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
  6302. i40e_clear_interrupt_scheme(pf);
  6303. for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
  6304. if (pf->vsi[i]) {
  6305. i40e_vsi_clear_rings(pf->vsi[i]);
  6306. i40e_vsi_clear(pf->vsi[i]);
  6307. pf->vsi[i] = NULL;
  6308. }
  6309. }
  6310. for (i = 0; i < I40E_MAX_VEB; i++) {
  6311. kfree(pf->veb[i]);
  6312. pf->veb[i] = NULL;
  6313. }
  6314. kfree(pf->qp_pile);
  6315. kfree(pf->irq_pile);
  6316. kfree(pf->sw_config);
  6317. kfree(pf->vsi);
  6318. /* force a PF reset to clean anything leftover */
  6319. reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
  6320. wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
  6321. i40e_flush(&pf->hw);
  6322. iounmap(pf->hw.hw_addr);
  6323. kfree(pf);
  6324. pci_release_selected_regions(pdev,
  6325. pci_select_bars(pdev, IORESOURCE_MEM));
  6326. pci_disable_pcie_error_reporting(pdev);
  6327. pci_disable_device(pdev);
  6328. }
  6329. /**
  6330. * i40e_pci_error_detected - warning that something funky happened in PCI land
  6331. * @pdev: PCI device information struct
  6332. *
  6333. * Called to warn that something happened and the error handling steps
  6334. * are in progress. Allows the driver to quiesce things, be ready for
  6335. * remediation.
  6336. **/
  6337. static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
  6338. enum pci_channel_state error)
  6339. {
  6340. struct i40e_pf *pf = pci_get_drvdata(pdev);
  6341. dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
  6342. /* shutdown all operations */
  6343. i40e_pf_quiesce_all_vsi(pf);
  6344. /* Request a slot reset */
  6345. return PCI_ERS_RESULT_NEED_RESET;
  6346. }
  6347. /**
  6348. * i40e_pci_error_slot_reset - a PCI slot reset just happened
  6349. * @pdev: PCI device information struct
  6350. *
  6351. * Called to find if the driver can work with the device now that
  6352. * the pci slot has been reset. If a basic connection seems good
  6353. * (registers are readable and have sane content) then return a
  6354. * happy little PCI_ERS_RESULT_xxx.
  6355. **/
  6356. static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
  6357. {
  6358. struct i40e_pf *pf = pci_get_drvdata(pdev);
  6359. pci_ers_result_t result;
  6360. int err;
  6361. u32 reg;
  6362. dev_info(&pdev->dev, "%s\n", __func__);
  6363. if (pci_enable_device_mem(pdev)) {
  6364. dev_info(&pdev->dev,
  6365. "Cannot re-enable PCI device after reset.\n");
  6366. result = PCI_ERS_RESULT_DISCONNECT;
  6367. } else {
  6368. pci_set_master(pdev);
  6369. pci_restore_state(pdev);
  6370. pci_save_state(pdev);
  6371. pci_wake_from_d3(pdev, false);
  6372. reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
  6373. if (reg == 0)
  6374. result = PCI_ERS_RESULT_RECOVERED;
  6375. else
  6376. result = PCI_ERS_RESULT_DISCONNECT;
  6377. }
  6378. err = pci_cleanup_aer_uncorrect_error_status(pdev);
  6379. if (err) {
  6380. dev_info(&pdev->dev,
  6381. "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
  6382. err);
  6383. /* non-fatal, continue */
  6384. }
  6385. return result;
  6386. }
  6387. /**
  6388. * i40e_pci_error_resume - restart operations after PCI error recovery
  6389. * @pdev: PCI device information struct
  6390. *
  6391. * Called to allow the driver to bring things back up after PCI error
  6392. * and/or reset recovery has finished.
  6393. **/
  6394. static void i40e_pci_error_resume(struct pci_dev *pdev)
  6395. {
  6396. struct i40e_pf *pf = pci_get_drvdata(pdev);
  6397. dev_info(&pdev->dev, "%s\n", __func__);
  6398. i40e_handle_reset_warning(pf);
  6399. }
  6400. static const struct pci_error_handlers i40e_err_handler = {
  6401. .error_detected = i40e_pci_error_detected,
  6402. .slot_reset = i40e_pci_error_slot_reset,
  6403. .resume = i40e_pci_error_resume,
  6404. };
  6405. static struct pci_driver i40e_driver = {
  6406. .name = i40e_driver_name,
  6407. .id_table = i40e_pci_tbl,
  6408. .probe = i40e_probe,
  6409. .remove = i40e_remove,
  6410. .err_handler = &i40e_err_handler,
  6411. .sriov_configure = i40e_pci_sriov_configure,
  6412. };
  6413. /**
  6414. * i40e_init_module - Driver registration routine
  6415. *
  6416. * i40e_init_module is the first routine called when the driver is
  6417. * loaded. All it does is register with the PCI subsystem.
  6418. **/
  6419. static int __init i40e_init_module(void)
  6420. {
  6421. pr_info("%s: %s - version %s\n", i40e_driver_name,
  6422. i40e_driver_string, i40e_driver_version_str);
  6423. pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
  6424. i40e_dbg_init();
  6425. return pci_register_driver(&i40e_driver);
  6426. }
  6427. module_init(i40e_init_module);
  6428. /**
  6429. * i40e_exit_module - Driver exit cleanup routine
  6430. *
  6431. * i40e_exit_module is called just before the driver is removed
  6432. * from memory.
  6433. **/
  6434. static void __exit i40e_exit_module(void)
  6435. {
  6436. pci_unregister_driver(&i40e_driver);
  6437. i40e_dbg_exit();
  6438. }
  6439. module_exit(i40e_exit_module);