Kconfig 22 KB

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  1. #
  2. # For a description of the syntax of this configuration file,
  3. # see Documentation/kbuild/kconfig-language.txt.
  4. #
  5. mainmenu "Blackfin Kernel Configuration"
  6. config MMU
  7. bool
  8. default n
  9. config FPU
  10. bool
  11. default n
  12. config RWSEM_GENERIC_SPINLOCK
  13. bool
  14. default y
  15. config RWSEM_XCHGADD_ALGORITHM
  16. bool
  17. default n
  18. config BLACKFIN
  19. bool
  20. default y
  21. select HAVE_IDE
  22. select HAVE_OPROFILE
  23. config ZONE_DMA
  24. bool
  25. default y
  26. config GENERIC_FIND_NEXT_BIT
  27. bool
  28. default y
  29. config GENERIC_HWEIGHT
  30. bool
  31. default y
  32. config GENERIC_HARDIRQS
  33. bool
  34. default y
  35. config GENERIC_IRQ_PROBE
  36. bool
  37. default y
  38. config GENERIC_GPIO
  39. bool
  40. default y
  41. config FORCE_MAX_ZONEORDER
  42. int
  43. default "14"
  44. config GENERIC_CALIBRATE_DELAY
  45. bool
  46. default y
  47. config HARDWARE_PM
  48. def_bool y
  49. depends on OPROFILE
  50. source "init/Kconfig"
  51. source "kernel/Kconfig.preempt"
  52. menu "Blackfin Processor Options"
  53. comment "Processor and Board Settings"
  54. choice
  55. prompt "CPU"
  56. default BF533
  57. config BF522
  58. bool "BF522"
  59. help
  60. BF522 Processor Support.
  61. config BF523
  62. bool "BF523"
  63. help
  64. BF523 Processor Support.
  65. config BF524
  66. bool "BF524"
  67. help
  68. BF524 Processor Support.
  69. config BF525
  70. bool "BF525"
  71. help
  72. BF525 Processor Support.
  73. config BF526
  74. bool "BF526"
  75. help
  76. BF526 Processor Support.
  77. config BF527
  78. bool "BF527"
  79. help
  80. BF527 Processor Support.
  81. config BF531
  82. bool "BF531"
  83. help
  84. BF531 Processor Support.
  85. config BF532
  86. bool "BF532"
  87. help
  88. BF532 Processor Support.
  89. config BF533
  90. bool "BF533"
  91. help
  92. BF533 Processor Support.
  93. config BF534
  94. bool "BF534"
  95. help
  96. BF534 Processor Support.
  97. config BF536
  98. bool "BF536"
  99. help
  100. BF536 Processor Support.
  101. config BF537
  102. bool "BF537"
  103. help
  104. BF537 Processor Support.
  105. config BF542
  106. bool "BF542"
  107. help
  108. BF542 Processor Support.
  109. config BF544
  110. bool "BF544"
  111. help
  112. BF544 Processor Support.
  113. config BF547
  114. bool "BF547"
  115. help
  116. BF547 Processor Support.
  117. config BF548
  118. bool "BF548"
  119. help
  120. BF548 Processor Support.
  121. config BF549
  122. bool "BF549"
  123. help
  124. BF549 Processor Support.
  125. config BF561
  126. bool "BF561"
  127. help
  128. Not Supported Yet - Work in progress - BF561 Processor Support.
  129. endchoice
  130. choice
  131. prompt "Silicon Rev"
  132. default BF_REV_0_1 if BF527
  133. default BF_REV_0_2 if BF537
  134. default BF_REV_0_3 if BF533
  135. default BF_REV_0_0 if BF549
  136. config BF_REV_0_0
  137. bool "0.0"
  138. depends on (BF52x || BF54x)
  139. config BF_REV_0_1
  140. bool "0.1"
  141. depends on (BF52x || BF54x)
  142. config BF_REV_0_2
  143. bool "0.2"
  144. depends on (BF537 || BF536 || BF534)
  145. config BF_REV_0_3
  146. bool "0.3"
  147. depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  148. config BF_REV_0_4
  149. bool "0.4"
  150. depends on (BF561 || BF533 || BF532 || BF531)
  151. config BF_REV_0_5
  152. bool "0.5"
  153. depends on (BF561 || BF533 || BF532 || BF531)
  154. config BF_REV_ANY
  155. bool "any"
  156. config BF_REV_NONE
  157. bool "none"
  158. endchoice
  159. config BF52x
  160. bool
  161. depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
  162. default y
  163. config BF53x
  164. bool
  165. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  166. default y
  167. config BF54x
  168. bool
  169. depends on (BF542 || BF544 || BF547 || BF548 || BF549)
  170. default y
  171. config MEM_GENERIC_BOARD
  172. bool
  173. depends on GENERIC_BOARD
  174. default y
  175. config MEM_MT48LC64M4A2FB_7E
  176. bool
  177. depends on (BFIN533_STAMP)
  178. default y
  179. config MEM_MT48LC16M16A2TG_75
  180. bool
  181. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  182. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
  183. || H8606_HVSISTEMAS)
  184. default y
  185. config MEM_MT48LC32M8A2_75
  186. bool
  187. depends on (BFIN537_STAMP || PNAV10)
  188. default y
  189. config MEM_MT48LC8M32B2B5_7
  190. bool
  191. depends on (BFIN561_BLUETECHNIX_CM)
  192. default y
  193. config MEM_MT48LC32M16A2TG_75
  194. bool
  195. depends on (BFIN527_EZKIT || BFIN532_IP0X)
  196. default y
  197. source "arch/blackfin/mach-bf527/Kconfig"
  198. source "arch/blackfin/mach-bf533/Kconfig"
  199. source "arch/blackfin/mach-bf561/Kconfig"
  200. source "arch/blackfin/mach-bf537/Kconfig"
  201. source "arch/blackfin/mach-bf548/Kconfig"
  202. menu "Board customizations"
  203. config CMDLINE_BOOL
  204. bool "Default bootloader kernel arguments"
  205. config CMDLINE
  206. string "Initial kernel command string"
  207. depends on CMDLINE_BOOL
  208. default "console=ttyBF0,57600"
  209. help
  210. If you don't have a boot loader capable of passing a command line string
  211. to the kernel, you may specify one here. As a minimum, you should specify
  212. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  213. comment "Clock/PLL Setup"
  214. config CLKIN_HZ
  215. int "Crystal Frequency in Hz"
  216. default "11059200" if BFIN533_STAMP
  217. default "27000000" if BFIN533_EZKIT
  218. default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
  219. default "30000000" if BFIN561_EZKIT
  220. default "24576000" if PNAV10
  221. default "10000000" if BFIN532_IP0X
  222. help
  223. The frequency of CLKIN crystal oscillator on the board in Hz.
  224. config BFIN_KERNEL_CLOCK
  225. bool "Re-program Clocks while Kernel boots?"
  226. default n
  227. help
  228. This option decides if kernel clocks are re-programed from the
  229. bootloader settings. If the clocks are not set, the SDRAM settings
  230. are also not changed, and the Bootloader does 100% of the hardware
  231. configuration.
  232. config MEM_SIZE
  233. int "SDRAM Memory Size in MBytes"
  234. depends on BFIN_KERNEL_CLOCK
  235. default 64
  236. config MEM_ADD_WIDTH
  237. int "Memory Address Width"
  238. depends on BFIN_KERNEL_CLOCK
  239. depends on (!BF54x)
  240. default 9 if BFIN533_EZKIT
  241. default 9 if BFIN561_EZKIT
  242. default 9 if H8606_HVSISTEMAS
  243. default 10 if BFIN527_EZKIT
  244. default 10 if BFIN537_STAMP
  245. default 11 if BFIN533_STAMP
  246. default 10 if PNAV10
  247. default 10 if BFIN532_IP0X
  248. config PLL_BYPASS
  249. bool "Bypass PLL"
  250. depends on BFIN_KERNEL_CLOCK
  251. default n
  252. config CLKIN_HALF
  253. bool "Half Clock In"
  254. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  255. default n
  256. help
  257. If this is set the clock will be divided by 2, before it goes to the PLL.
  258. config VCO_MULT
  259. int "VCO Multiplier"
  260. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  261. range 1 64
  262. default "22" if BFIN533_EZKIT
  263. default "45" if BFIN533_STAMP
  264. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
  265. default "22" if BFIN533_BLUETECHNIX_CM
  266. default "20" if BFIN537_BLUETECHNIX_CM
  267. default "20" if BFIN561_BLUETECHNIX_CM
  268. default "20" if BFIN561_EZKIT
  269. default "16" if H8606_HVSISTEMAS
  270. help
  271. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  272. PLL Frequency = (Crystal Frequency) * (this setting)
  273. choice
  274. prompt "Core Clock Divider"
  275. depends on BFIN_KERNEL_CLOCK
  276. default CCLK_DIV_1
  277. help
  278. This sets the frequency of the core. It can be 1, 2, 4 or 8
  279. Core Frequency = (PLL frequency) / (this setting)
  280. config CCLK_DIV_1
  281. bool "1"
  282. config CCLK_DIV_2
  283. bool "2"
  284. config CCLK_DIV_4
  285. bool "4"
  286. config CCLK_DIV_8
  287. bool "8"
  288. endchoice
  289. config SCLK_DIV
  290. int "System Clock Divider"
  291. depends on BFIN_KERNEL_CLOCK
  292. range 1 15
  293. default 5 if BFIN533_EZKIT
  294. default 5 if BFIN533_STAMP
  295. default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
  296. default 5 if BFIN533_BLUETECHNIX_CM
  297. default 4 if BFIN537_BLUETECHNIX_CM
  298. default 4 if BFIN561_BLUETECHNIX_CM
  299. default 5 if BFIN561_EZKIT
  300. default 3 if H8606_HVSISTEMAS
  301. help
  302. This sets the frequency of the system clock (including SDRAM or DDR).
  303. This can be between 1 and 15
  304. System Clock = (PLL frequency) / (this setting)
  305. config MAX_MEM_SIZE
  306. int "Max SDRAM Memory Size in MBytes"
  307. depends on !BFIN_KERNEL_CLOCK && !MPU
  308. default 512
  309. help
  310. This is the max memory size that the kernel will create CPLB
  311. tables for. Your system will not be able to handle any more.
  312. #
  313. # Max & Min Speeds for various Chips
  314. #
  315. config MAX_VCO_HZ
  316. int
  317. default 600000000 if BF522
  318. default 400000000 if BF523
  319. default 400000000 if BF524
  320. default 600000000 if BF525
  321. default 400000000 if BF526
  322. default 600000000 if BF527
  323. default 400000000 if BF531
  324. default 400000000 if BF532
  325. default 750000000 if BF533
  326. default 500000000 if BF534
  327. default 400000000 if BF536
  328. default 600000000 if BF537
  329. default 533333333 if BF538
  330. default 533333333 if BF539
  331. default 600000000 if BF542
  332. default 533333333 if BF544
  333. default 600000000 if BF547
  334. default 600000000 if BF548
  335. default 533333333 if BF549
  336. default 600000000 if BF561
  337. config MIN_VCO_HZ
  338. int
  339. default 50000000
  340. config MAX_SCLK_HZ
  341. int
  342. default 133333333
  343. config MIN_SCLK_HZ
  344. int
  345. default 27000000
  346. comment "Kernel Timer/Scheduler"
  347. source kernel/Kconfig.hz
  348. config GENERIC_TIME
  349. bool "Generic time"
  350. default y
  351. config GENERIC_CLOCKEVENTS
  352. bool "Generic clock events"
  353. depends on GENERIC_TIME
  354. default y
  355. config CYCLES_CLOCKSOURCE
  356. bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
  357. depends on EXPERIMENTAL
  358. depends on GENERIC_CLOCKEVENTS
  359. depends on !BFIN_SCRATCH_REG_CYCLES
  360. default n
  361. help
  362. If you say Y here, you will enable support for using the 'cycles'
  363. registers as a clock source. Doing so means you will be unable to
  364. safely write to the 'cycles' register during runtime. You will
  365. still be able to read it (such as for performance monitoring), but
  366. writing the registers will most likely crash the kernel.
  367. source kernel/time/Kconfig
  368. comment "Memory Setup"
  369. choice
  370. prompt "DDR SDRAM Chip Type"
  371. depends on (BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
  372. default MEM_MT46V32M16_5B
  373. config MEM_MT46V32M16_6T
  374. bool "MT46V32M16_6T"
  375. config MEM_MT46V32M16_5B
  376. bool "MT46V32M16_5B"
  377. endchoice
  378. config ENET_FLASH_PIN
  379. int "PF port/pin used for flash and ethernet sharing"
  380. depends on (BFIN533_STAMP)
  381. default 0
  382. help
  383. PF port/pin used for flash and ethernet sharing to allow other PF
  384. pins to be used on other platforms without having to touch common
  385. code.
  386. For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
  387. config BOOT_LOAD
  388. hex "Kernel load address for booting"
  389. default "0x1000"
  390. range 0x1000 0x20000000
  391. help
  392. This option allows you to set the load address of the kernel.
  393. This can be useful if you are on a board which has a small amount
  394. of memory or you wish to reserve some memory at the beginning of
  395. the address space.
  396. Note that you need to keep this value above 4k (0x1000) as this
  397. memory region is used to capture NULL pointer references as well
  398. as some core kernel functions.
  399. choice
  400. prompt "Blackfin Exception Scratch Register"
  401. default BFIN_SCRATCH_REG_RETN
  402. help
  403. Select the resource to reserve for the Exception handler:
  404. - RETN: Non-Maskable Interrupt (NMI)
  405. - RETE: Exception Return (JTAG/ICE)
  406. - CYCLES: Performance counter
  407. If you are unsure, please select "RETN".
  408. config BFIN_SCRATCH_REG_RETN
  409. bool "RETN"
  410. help
  411. Use the RETN register in the Blackfin exception handler
  412. as a stack scratch register. This means you cannot
  413. safely use NMI on the Blackfin while running Linux, but
  414. you can debug the system with a JTAG ICE and use the
  415. CYCLES performance registers.
  416. If you are unsure, please select "RETN".
  417. config BFIN_SCRATCH_REG_RETE
  418. bool "RETE"
  419. help
  420. Use the RETE register in the Blackfin exception handler
  421. as a stack scratch register. This means you cannot
  422. safely use a JTAG ICE while debugging a Blackfin board,
  423. but you can safely use the CYCLES performance registers
  424. and the NMI.
  425. If you are unsure, please select "RETN".
  426. config BFIN_SCRATCH_REG_CYCLES
  427. bool "CYCLES"
  428. help
  429. Use the CYCLES register in the Blackfin exception handler
  430. as a stack scratch register. This means you cannot
  431. safely use the CYCLES performance registers on a Blackfin
  432. board at anytime, but you can debug the system with a JTAG
  433. ICE and use the NMI.
  434. If you are unsure, please select "RETN".
  435. endchoice
  436. endmenu
  437. menu "Blackfin Kernel Optimizations"
  438. comment "Memory Optimizations"
  439. config I_ENTRY_L1
  440. bool "Locate interrupt entry code in L1 Memory"
  441. default y
  442. help
  443. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  444. into L1 instruction memory. (less latency)
  445. config EXCPT_IRQ_SYSC_L1
  446. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  447. default y
  448. help
  449. If enabled, the entire ASM lowlevel exception and interrupt entry code
  450. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  451. (less latency)
  452. config DO_IRQ_L1
  453. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  454. default y
  455. help
  456. If enabled, the frequently called do_irq dispatcher function is linked
  457. into L1 instruction memory. (less latency)
  458. config CORE_TIMER_IRQ_L1
  459. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  460. default y
  461. help
  462. If enabled, the frequently called timer_interrupt() function is linked
  463. into L1 instruction memory. (less latency)
  464. config IDLE_L1
  465. bool "Locate frequently idle function in L1 Memory"
  466. default y
  467. help
  468. If enabled, the frequently called idle function is linked
  469. into L1 instruction memory. (less latency)
  470. config SCHEDULE_L1
  471. bool "Locate kernel schedule function in L1 Memory"
  472. default y
  473. help
  474. If enabled, the frequently called kernel schedule is linked
  475. into L1 instruction memory. (less latency)
  476. config ARITHMETIC_OPS_L1
  477. bool "Locate kernel owned arithmetic functions in L1 Memory"
  478. default y
  479. help
  480. If enabled, arithmetic functions are linked
  481. into L1 instruction memory. (less latency)
  482. config ACCESS_OK_L1
  483. bool "Locate access_ok function in L1 Memory"
  484. default y
  485. help
  486. If enabled, the access_ok function is linked
  487. into L1 instruction memory. (less latency)
  488. config MEMSET_L1
  489. bool "Locate memset function in L1 Memory"
  490. default y
  491. help
  492. If enabled, the memset function is linked
  493. into L1 instruction memory. (less latency)
  494. config MEMCPY_L1
  495. bool "Locate memcpy function in L1 Memory"
  496. default y
  497. help
  498. If enabled, the memcpy function is linked
  499. into L1 instruction memory. (less latency)
  500. config SYS_BFIN_SPINLOCK_L1
  501. bool "Locate sys_bfin_spinlock function in L1 Memory"
  502. default y
  503. help
  504. If enabled, sys_bfin_spinlock function is linked
  505. into L1 instruction memory. (less latency)
  506. config IP_CHECKSUM_L1
  507. bool "Locate IP Checksum function in L1 Memory"
  508. default n
  509. help
  510. If enabled, the IP Checksum function is linked
  511. into L1 instruction memory. (less latency)
  512. config CACHELINE_ALIGNED_L1
  513. bool "Locate cacheline_aligned data to L1 Data Memory"
  514. default y if !BF54x
  515. default n if BF54x
  516. depends on !BF531
  517. help
  518. If enabled, cacheline_anligned data is linked
  519. into L1 data memory. (less latency)
  520. config SYSCALL_TAB_L1
  521. bool "Locate Syscall Table L1 Data Memory"
  522. default n
  523. depends on !BF531
  524. help
  525. If enabled, the Syscall LUT is linked
  526. into L1 data memory. (less latency)
  527. config CPLB_SWITCH_TAB_L1
  528. bool "Locate CPLB Switch Tables L1 Data Memory"
  529. default n
  530. depends on !BF531
  531. help
  532. If enabled, the CPLB Switch Tables are linked
  533. into L1 data memory. (less latency)
  534. endmenu
  535. choice
  536. prompt "Kernel executes from"
  537. help
  538. Choose the memory type that the kernel will be running in.
  539. config RAMKERNEL
  540. bool "RAM"
  541. help
  542. The kernel will be resident in RAM when running.
  543. config ROMKERNEL
  544. bool "ROM"
  545. help
  546. The kernel will be resident in FLASH/ROM when running.
  547. endchoice
  548. source "mm/Kconfig"
  549. config BFIN_GPTIMERS
  550. tristate "Enable Blackfin General Purpose Timers API"
  551. default n
  552. help
  553. Enable support for the General Purpose Timers API. If you
  554. are unsure, say N.
  555. To compile this driver as a module, choose M here: the module
  556. will be called gptimers.ko.
  557. config BFIN_DMA_5XX
  558. bool "Enable DMA Support"
  559. depends on (BF52x || BF53x || BF561 || BF54x)
  560. default y
  561. help
  562. DMA driver for BF5xx.
  563. choice
  564. prompt "Uncached SDRAM region"
  565. default DMA_UNCACHED_1M
  566. depends on BFIN_DMA_5XX
  567. config DMA_UNCACHED_2M
  568. bool "Enable 2M DMA region"
  569. config DMA_UNCACHED_1M
  570. bool "Enable 1M DMA region"
  571. config DMA_UNCACHED_NONE
  572. bool "Disable DMA region"
  573. endchoice
  574. comment "Cache Support"
  575. config BFIN_ICACHE
  576. bool "Enable ICACHE"
  577. config BFIN_DCACHE
  578. bool "Enable DCACHE"
  579. config BFIN_DCACHE_BANKA
  580. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  581. depends on BFIN_DCACHE && !BF531
  582. default n
  583. config BFIN_ICACHE_LOCK
  584. bool "Enable Instruction Cache Locking"
  585. choice
  586. prompt "Policy"
  587. depends on BFIN_DCACHE
  588. default BFIN_WB
  589. config BFIN_WB
  590. bool "Write back"
  591. help
  592. Write Back Policy:
  593. Cached data will be written back to SDRAM only when needed.
  594. This can give a nice increase in performance, but beware of
  595. broken drivers that do not properly invalidate/flush their
  596. cache.
  597. Write Through Policy:
  598. Cached data will always be written back to SDRAM when the
  599. cache is updated. This is a completely safe setting, but
  600. performance is worse than Write Back.
  601. If you are unsure of the options and you want to be safe,
  602. then go with Write Through.
  603. config BFIN_WT
  604. bool "Write through"
  605. help
  606. Write Back Policy:
  607. Cached data will be written back to SDRAM only when needed.
  608. This can give a nice increase in performance, but beware of
  609. broken drivers that do not properly invalidate/flush their
  610. cache.
  611. Write Through Policy:
  612. Cached data will always be written back to SDRAM when the
  613. cache is updated. This is a completely safe setting, but
  614. performance is worse than Write Back.
  615. If you are unsure of the options and you want to be safe,
  616. then go with Write Through.
  617. endchoice
  618. config L1_MAX_PIECE
  619. int "Set the max L1 SRAM pieces"
  620. default 16
  621. help
  622. Set the max memory pieces for the L1 SRAM allocation algorithm.
  623. Min value is 16. Max value is 1024.
  624. config MPU
  625. bool "Enable the memory protection unit (EXPERIMENTAL)"
  626. default n
  627. help
  628. Use the processor's MPU to protect applications from accessing
  629. memory they do not own. This comes at a performance penalty
  630. and is recommended only for debugging.
  631. comment "Asynchonous Memory Configuration"
  632. menu "EBIU_AMGCTL Global Control"
  633. config C_AMCKEN
  634. bool "Enable CLKOUT"
  635. default y
  636. config C_CDPRIO
  637. bool "DMA has priority over core for ext. accesses"
  638. default n
  639. config C_B0PEN
  640. depends on BF561
  641. bool "Bank 0 16 bit packing enable"
  642. default y
  643. config C_B1PEN
  644. depends on BF561
  645. bool "Bank 1 16 bit packing enable"
  646. default y
  647. config C_B2PEN
  648. depends on BF561
  649. bool "Bank 2 16 bit packing enable"
  650. default y
  651. config C_B3PEN
  652. depends on BF561
  653. bool "Bank 3 16 bit packing enable"
  654. default n
  655. choice
  656. prompt"Enable Asynchonous Memory Banks"
  657. default C_AMBEN_ALL
  658. config C_AMBEN
  659. bool "Disable All Banks"
  660. config C_AMBEN_B0
  661. bool "Enable Bank 0"
  662. config C_AMBEN_B0_B1
  663. bool "Enable Bank 0 & 1"
  664. config C_AMBEN_B0_B1_B2
  665. bool "Enable Bank 0 & 1 & 2"
  666. config C_AMBEN_ALL
  667. bool "Enable All Banks"
  668. endchoice
  669. endmenu
  670. menu "EBIU_AMBCTL Control"
  671. config BANK_0
  672. hex "Bank 0"
  673. default 0x7BB0
  674. config BANK_1
  675. hex "Bank 1"
  676. default 0x7BB0
  677. config BANK_2
  678. hex "Bank 2"
  679. default 0x7BB0
  680. config BANK_3
  681. hex "Bank 3"
  682. default 0x99B3
  683. endmenu
  684. config EBIU_MBSCTLVAL
  685. hex "EBIU Bank Select Control Register"
  686. depends on BF54x
  687. default 0
  688. config EBIU_MODEVAL
  689. hex "Flash Memory Mode Control Register"
  690. depends on BF54x
  691. default 1
  692. config EBIU_FCTLVAL
  693. hex "Flash Memory Bank Control Register"
  694. depends on BF54x
  695. default 6
  696. endmenu
  697. #############################################################################
  698. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  699. config PCI
  700. bool "PCI support"
  701. help
  702. Support for PCI bus.
  703. source "drivers/pci/Kconfig"
  704. config HOTPLUG
  705. bool "Support for hot-pluggable device"
  706. help
  707. Say Y here if you want to plug devices into your computer while
  708. the system is running, and be able to use them quickly. In many
  709. cases, the devices can likewise be unplugged at any time too.
  710. One well known example of this is PCMCIA- or PC-cards, credit-card
  711. size devices such as network cards, modems or hard drives which are
  712. plugged into slots found on all modern laptop computers. Another
  713. example, used on modern desktops as well as laptops, is USB.
  714. Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
  715. software (at <http://linux-hotplug.sourceforge.net/>) and install it.
  716. Then your kernel will automatically call out to a user mode "policy
  717. agent" (/sbin/hotplug) to load modules and set up software needed
  718. to use devices as you hotplug them.
  719. source "drivers/pcmcia/Kconfig"
  720. source "drivers/pci/hotplug/Kconfig"
  721. endmenu
  722. menu "Executable file formats"
  723. source "fs/Kconfig.binfmt"
  724. endmenu
  725. menu "Power management options"
  726. source "kernel/power/Kconfig"
  727. config ARCH_SUSPEND_POSSIBLE
  728. def_bool y
  729. depends on !SMP
  730. choice
  731. prompt "Default Power Saving Mode"
  732. depends on PM
  733. default PM_BFIN_SLEEP_DEEPER
  734. config PM_BFIN_SLEEP_DEEPER
  735. bool "Sleep Deeper"
  736. help
  737. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  738. power dissipation by disabling the clock to the processor core (CCLK).
  739. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  740. to 0.85 V to provide the greatest power savings, while preserving the
  741. processor state.
  742. The PLL and system clock (SCLK) continue to operate at a very low
  743. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  744. the SDRAM is put into Self Refresh Mode. Typically an external event
  745. such as GPIO interrupt or RTC activity wakes up the processor.
  746. Various Peripherals such as UART, SPORT, PPI may not function as
  747. normal during Sleep Deeper, due to the reduced SCLK frequency.
  748. When in the sleep mode, system DMA access to L1 memory is not supported.
  749. config PM_BFIN_SLEEP
  750. bool "Sleep"
  751. help
  752. Sleep Mode (High Power Savings) - The sleep mode reduces power
  753. dissipation by disabling the clock to the processor core (CCLK).
  754. The PLL and system clock (SCLK), however, continue to operate in
  755. this mode. Typically an external event or RTC activity will wake
  756. up the processor. When in the sleep mode,
  757. system DMA access to L1 memory is not supported.
  758. endchoice
  759. config PM_WAKEUP_BY_GPIO
  760. bool "Cause Wakeup Event by GPIO"
  761. config PM_WAKEUP_GPIO_NUMBER
  762. int "Wakeup GPIO number"
  763. range 0 47
  764. depends on PM_WAKEUP_BY_GPIO
  765. default 2 if BFIN537_STAMP
  766. choice
  767. prompt "GPIO Polarity"
  768. depends on PM_WAKEUP_BY_GPIO
  769. default PM_WAKEUP_GPIO_POLAR_H
  770. config PM_WAKEUP_GPIO_POLAR_H
  771. bool "Active High"
  772. config PM_WAKEUP_GPIO_POLAR_L
  773. bool "Active Low"
  774. config PM_WAKEUP_GPIO_POLAR_EDGE_F
  775. bool "Falling EDGE"
  776. config PM_WAKEUP_GPIO_POLAR_EDGE_R
  777. bool "Rising EDGE"
  778. config PM_WAKEUP_GPIO_POLAR_EDGE_B
  779. bool "Both EDGE"
  780. endchoice
  781. endmenu
  782. if (BF537 || BF533 || BF54x)
  783. menu "CPU Frequency scaling"
  784. source "drivers/cpufreq/Kconfig"
  785. config CPU_FREQ
  786. bool
  787. default n
  788. help
  789. If you want to enable this option, you should select the
  790. DPMC driver from Character Devices.
  791. endmenu
  792. endif
  793. source "net/Kconfig"
  794. source "drivers/Kconfig"
  795. source "fs/Kconfig"
  796. source "arch/blackfin/Kconfig.debug"
  797. source "security/Kconfig"
  798. source "crypto/Kconfig"
  799. source "lib/Kconfig"