devs.c 39 KB

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  1. /* linux/arch/arm/plat-samsung/devs.c
  2. *
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Base SAMSUNG platform device definitions
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/types.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/list.h>
  16. #include <linux/timer.h>
  17. #include <linux/init.h>
  18. #include <linux/serial_core.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/io.h>
  21. #include <linux/slab.h>
  22. #include <linux/string.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/fb.h>
  25. #include <linux/gfp.h>
  26. #include <linux/mtd/mtd.h>
  27. #include <linux/mtd/onenand.h>
  28. #include <linux/mtd/partitions.h>
  29. #include <linux/mmc/host.h>
  30. #include <linux/ioport.h>
  31. #include <linux/platform_data/s3c-hsudc.h>
  32. #include <linux/platform_data/s3c-hsotg.h>
  33. #include <media/s5p_hdmi.h>
  34. #include <asm/irq.h>
  35. #include <asm/mach/arch.h>
  36. #include <asm/mach/map.h>
  37. #include <asm/mach/irq.h>
  38. #include <mach/hardware.h>
  39. #include <mach/dma.h>
  40. #include <mach/irqs.h>
  41. #include <mach/map.h>
  42. #include <plat/cpu.h>
  43. #include <plat/devs.h>
  44. #include <plat/adc.h>
  45. #include <linux/platform_data/ata-samsung_cf.h>
  46. #include <linux/platform_data/usb-ehci-s5p.h>
  47. #include <plat/fb.h>
  48. #include <plat/fb-s3c2410.h>
  49. #include <plat/hdmi.h>
  50. #include <linux/platform_data/hwmon-s3c.h>
  51. #include <linux/platform_data/i2c-s3c2410.h>
  52. #include <plat/keypad.h>
  53. #include <linux/platform_data/mmc-s3cmci.h>
  54. #include <linux/platform_data/mtd-nand-s3c2410.h>
  55. #include <plat/sdhci.h>
  56. #include <linux/platform_data/touchscreen-s3c2410.h>
  57. #include <linux/platform_data/usb-s3c2410_udc.h>
  58. #include <linux/platform_data/usb-ohci-s3c2410.h>
  59. #include <plat/usb-phy.h>
  60. #include <plat/regs-iic.h>
  61. #include <plat/regs-serial.h>
  62. #include <plat/regs-spi.h>
  63. #include <linux/platform_data/spi-s3c64xx.h>
  64. static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
  65. /* AC97 */
  66. #ifdef CONFIG_CPU_S3C2440
  67. static struct resource s3c_ac97_resource[] = {
  68. [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
  69. [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
  70. [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"),
  71. [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"),
  72. [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"),
  73. };
  74. struct platform_device s3c_device_ac97 = {
  75. .name = "samsung-ac97",
  76. .id = -1,
  77. .num_resources = ARRAY_SIZE(s3c_ac97_resource),
  78. .resource = s3c_ac97_resource,
  79. .dev = {
  80. .dma_mask = &samsung_device_dma_mask,
  81. .coherent_dma_mask = DMA_BIT_MASK(32),
  82. }
  83. };
  84. #endif /* CONFIG_CPU_S3C2440 */
  85. /* ADC */
  86. #ifdef CONFIG_PLAT_S3C24XX
  87. static struct resource s3c_adc_resource[] = {
  88. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  89. [1] = DEFINE_RES_IRQ(IRQ_TC),
  90. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  91. };
  92. struct platform_device s3c_device_adc = {
  93. .name = "s3c24xx-adc",
  94. .id = -1,
  95. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  96. .resource = s3c_adc_resource,
  97. };
  98. #endif /* CONFIG_PLAT_S3C24XX */
  99. #if defined(CONFIG_SAMSUNG_DEV_ADC)
  100. static struct resource s3c_adc_resource[] = {
  101. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  102. [1] = DEFINE_RES_IRQ(IRQ_TC),
  103. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  104. };
  105. struct platform_device s3c_device_adc = {
  106. .name = "samsung-adc",
  107. .id = -1,
  108. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  109. .resource = s3c_adc_resource,
  110. };
  111. #endif /* CONFIG_SAMSUNG_DEV_ADC */
  112. /* Camif Controller */
  113. #ifdef CONFIG_CPU_S3C2440
  114. static struct resource s3c_camif_resource[] = {
  115. [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
  116. [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C),
  117. [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P),
  118. };
  119. struct platform_device s3c_device_camif = {
  120. .name = "s3c2440-camif",
  121. .id = -1,
  122. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  123. .resource = s3c_camif_resource,
  124. .dev = {
  125. .dma_mask = &samsung_device_dma_mask,
  126. .coherent_dma_mask = DMA_BIT_MASK(32),
  127. }
  128. };
  129. #endif /* CONFIG_CPU_S3C2440 */
  130. /* ASOC DMA */
  131. struct platform_device samsung_asoc_idma = {
  132. .name = "samsung-idma",
  133. .id = -1,
  134. .dev = {
  135. .dma_mask = &samsung_device_dma_mask,
  136. .coherent_dma_mask = DMA_BIT_MASK(32),
  137. }
  138. };
  139. /* FB */
  140. #ifdef CONFIG_S3C_DEV_FB
  141. static struct resource s3c_fb_resource[] = {
  142. [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K),
  143. [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC),
  144. [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO),
  145. [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM),
  146. };
  147. struct platform_device s3c_device_fb = {
  148. .name = "s3c-fb",
  149. .id = -1,
  150. .num_resources = ARRAY_SIZE(s3c_fb_resource),
  151. .resource = s3c_fb_resource,
  152. .dev = {
  153. .dma_mask = &samsung_device_dma_mask,
  154. .coherent_dma_mask = DMA_BIT_MASK(32),
  155. },
  156. };
  157. void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
  158. {
  159. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  160. &s3c_device_fb);
  161. }
  162. #endif /* CONFIG_S3C_DEV_FB */
  163. /* FIMC */
  164. #ifdef CONFIG_S5P_DEV_FIMC0
  165. static struct resource s5p_fimc0_resource[] = {
  166. [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
  167. [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
  168. };
  169. struct platform_device s5p_device_fimc0 = {
  170. .name = "s5p-fimc",
  171. .id = 0,
  172. .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
  173. .resource = s5p_fimc0_resource,
  174. .dev = {
  175. .dma_mask = &samsung_device_dma_mask,
  176. .coherent_dma_mask = DMA_BIT_MASK(32),
  177. },
  178. };
  179. struct platform_device s5p_device_fimc_md = {
  180. .name = "s5p-fimc-md",
  181. .id = -1,
  182. };
  183. #endif /* CONFIG_S5P_DEV_FIMC0 */
  184. #ifdef CONFIG_S5P_DEV_FIMC1
  185. static struct resource s5p_fimc1_resource[] = {
  186. [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
  187. [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
  188. };
  189. struct platform_device s5p_device_fimc1 = {
  190. .name = "s5p-fimc",
  191. .id = 1,
  192. .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
  193. .resource = s5p_fimc1_resource,
  194. .dev = {
  195. .dma_mask = &samsung_device_dma_mask,
  196. .coherent_dma_mask = DMA_BIT_MASK(32),
  197. },
  198. };
  199. #endif /* CONFIG_S5P_DEV_FIMC1 */
  200. #ifdef CONFIG_S5P_DEV_FIMC2
  201. static struct resource s5p_fimc2_resource[] = {
  202. [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
  203. [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
  204. };
  205. struct platform_device s5p_device_fimc2 = {
  206. .name = "s5p-fimc",
  207. .id = 2,
  208. .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
  209. .resource = s5p_fimc2_resource,
  210. .dev = {
  211. .dma_mask = &samsung_device_dma_mask,
  212. .coherent_dma_mask = DMA_BIT_MASK(32),
  213. },
  214. };
  215. #endif /* CONFIG_S5P_DEV_FIMC2 */
  216. #ifdef CONFIG_S5P_DEV_FIMC3
  217. static struct resource s5p_fimc3_resource[] = {
  218. [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
  219. [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
  220. };
  221. struct platform_device s5p_device_fimc3 = {
  222. .name = "s5p-fimc",
  223. .id = 3,
  224. .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
  225. .resource = s5p_fimc3_resource,
  226. .dev = {
  227. .dma_mask = &samsung_device_dma_mask,
  228. .coherent_dma_mask = DMA_BIT_MASK(32),
  229. },
  230. };
  231. #endif /* CONFIG_S5P_DEV_FIMC3 */
  232. /* G2D */
  233. #ifdef CONFIG_S5P_DEV_G2D
  234. static struct resource s5p_g2d_resource[] = {
  235. [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
  236. [1] = DEFINE_RES_IRQ(IRQ_2D),
  237. };
  238. struct platform_device s5p_device_g2d = {
  239. .name = "s5p-g2d",
  240. .id = 0,
  241. .num_resources = ARRAY_SIZE(s5p_g2d_resource),
  242. .resource = s5p_g2d_resource,
  243. .dev = {
  244. .dma_mask = &samsung_device_dma_mask,
  245. .coherent_dma_mask = DMA_BIT_MASK(32),
  246. },
  247. };
  248. #endif /* CONFIG_S5P_DEV_G2D */
  249. #ifdef CONFIG_S5P_DEV_JPEG
  250. static struct resource s5p_jpeg_resource[] = {
  251. [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
  252. [1] = DEFINE_RES_IRQ(IRQ_JPEG),
  253. };
  254. struct platform_device s5p_device_jpeg = {
  255. .name = "s5p-jpeg",
  256. .id = 0,
  257. .num_resources = ARRAY_SIZE(s5p_jpeg_resource),
  258. .resource = s5p_jpeg_resource,
  259. .dev = {
  260. .dma_mask = &samsung_device_dma_mask,
  261. .coherent_dma_mask = DMA_BIT_MASK(32),
  262. },
  263. };
  264. #endif /* CONFIG_S5P_DEV_JPEG */
  265. /* FIMD0 */
  266. #ifdef CONFIG_S5P_DEV_FIMD0
  267. static struct resource s5p_fimd0_resource[] = {
  268. [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
  269. [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
  270. [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
  271. [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
  272. };
  273. struct platform_device s5p_device_fimd0 = {
  274. .name = "s5p-fb",
  275. .id = 0,
  276. .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
  277. .resource = s5p_fimd0_resource,
  278. .dev = {
  279. .dma_mask = &samsung_device_dma_mask,
  280. .coherent_dma_mask = DMA_BIT_MASK(32),
  281. },
  282. };
  283. void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
  284. {
  285. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  286. &s5p_device_fimd0);
  287. }
  288. #endif /* CONFIG_S5P_DEV_FIMD0 */
  289. /* HWMON */
  290. #ifdef CONFIG_S3C_DEV_HWMON
  291. struct platform_device s3c_device_hwmon = {
  292. .name = "s3c-hwmon",
  293. .id = -1,
  294. .dev.parent = &s3c_device_adc.dev,
  295. };
  296. void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
  297. {
  298. s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
  299. &s3c_device_hwmon);
  300. }
  301. #endif /* CONFIG_S3C_DEV_HWMON */
  302. /* HSMMC */
  303. #ifdef CONFIG_S3C_DEV_HSMMC
  304. static struct resource s3c_hsmmc_resource[] = {
  305. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
  306. [1] = DEFINE_RES_IRQ(IRQ_HSMMC0),
  307. };
  308. struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
  309. .max_width = 4,
  310. .host_caps = (MMC_CAP_4_BIT_DATA |
  311. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  312. };
  313. struct platform_device s3c_device_hsmmc0 = {
  314. .name = "s3c-sdhci",
  315. .id = 0,
  316. .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
  317. .resource = s3c_hsmmc_resource,
  318. .dev = {
  319. .dma_mask = &samsung_device_dma_mask,
  320. .coherent_dma_mask = DMA_BIT_MASK(32),
  321. .platform_data = &s3c_hsmmc0_def_platdata,
  322. },
  323. };
  324. void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
  325. {
  326. s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
  327. }
  328. #endif /* CONFIG_S3C_DEV_HSMMC */
  329. #ifdef CONFIG_S3C_DEV_HSMMC1
  330. static struct resource s3c_hsmmc1_resource[] = {
  331. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
  332. [1] = DEFINE_RES_IRQ(IRQ_HSMMC1),
  333. };
  334. struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
  335. .max_width = 4,
  336. .host_caps = (MMC_CAP_4_BIT_DATA |
  337. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  338. };
  339. struct platform_device s3c_device_hsmmc1 = {
  340. .name = "s3c-sdhci",
  341. .id = 1,
  342. .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
  343. .resource = s3c_hsmmc1_resource,
  344. .dev = {
  345. .dma_mask = &samsung_device_dma_mask,
  346. .coherent_dma_mask = DMA_BIT_MASK(32),
  347. .platform_data = &s3c_hsmmc1_def_platdata,
  348. },
  349. };
  350. void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
  351. {
  352. s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
  353. }
  354. #endif /* CONFIG_S3C_DEV_HSMMC1 */
  355. /* HSMMC2 */
  356. #ifdef CONFIG_S3C_DEV_HSMMC2
  357. static struct resource s3c_hsmmc2_resource[] = {
  358. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
  359. [1] = DEFINE_RES_IRQ(IRQ_HSMMC2),
  360. };
  361. struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
  362. .max_width = 4,
  363. .host_caps = (MMC_CAP_4_BIT_DATA |
  364. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  365. };
  366. struct platform_device s3c_device_hsmmc2 = {
  367. .name = "s3c-sdhci",
  368. .id = 2,
  369. .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
  370. .resource = s3c_hsmmc2_resource,
  371. .dev = {
  372. .dma_mask = &samsung_device_dma_mask,
  373. .coherent_dma_mask = DMA_BIT_MASK(32),
  374. .platform_data = &s3c_hsmmc2_def_platdata,
  375. },
  376. };
  377. void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
  378. {
  379. s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
  380. }
  381. #endif /* CONFIG_S3C_DEV_HSMMC2 */
  382. #ifdef CONFIG_S3C_DEV_HSMMC3
  383. static struct resource s3c_hsmmc3_resource[] = {
  384. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
  385. [1] = DEFINE_RES_IRQ(IRQ_HSMMC3),
  386. };
  387. struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
  388. .max_width = 4,
  389. .host_caps = (MMC_CAP_4_BIT_DATA |
  390. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  391. };
  392. struct platform_device s3c_device_hsmmc3 = {
  393. .name = "s3c-sdhci",
  394. .id = 3,
  395. .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
  396. .resource = s3c_hsmmc3_resource,
  397. .dev = {
  398. .dma_mask = &samsung_device_dma_mask,
  399. .coherent_dma_mask = DMA_BIT_MASK(32),
  400. .platform_data = &s3c_hsmmc3_def_platdata,
  401. },
  402. };
  403. void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
  404. {
  405. s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
  406. }
  407. #endif /* CONFIG_S3C_DEV_HSMMC3 */
  408. /* I2C */
  409. static struct resource s3c_i2c0_resource[] = {
  410. [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
  411. [1] = DEFINE_RES_IRQ(IRQ_IIC),
  412. };
  413. struct platform_device s3c_device_i2c0 = {
  414. .name = "s3c2410-i2c",
  415. #ifdef CONFIG_S3C_DEV_I2C1
  416. .id = 0,
  417. #else
  418. .id = -1,
  419. #endif
  420. .num_resources = ARRAY_SIZE(s3c_i2c0_resource),
  421. .resource = s3c_i2c0_resource,
  422. };
  423. struct s3c2410_platform_i2c default_i2c_data __initdata = {
  424. .flags = 0,
  425. .slave_addr = 0x10,
  426. .frequency = 100*1000,
  427. .sda_delay = 100,
  428. };
  429. void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
  430. {
  431. struct s3c2410_platform_i2c *npd;
  432. if (!pd) {
  433. pd = &default_i2c_data;
  434. pd->bus_num = 0;
  435. }
  436. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  437. &s3c_device_i2c0);
  438. if (!npd->cfg_gpio)
  439. npd->cfg_gpio = s3c_i2c0_cfg_gpio;
  440. }
  441. #ifdef CONFIG_S3C_DEV_I2C1
  442. static struct resource s3c_i2c1_resource[] = {
  443. [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
  444. [1] = DEFINE_RES_IRQ(IRQ_IIC1),
  445. };
  446. struct platform_device s3c_device_i2c1 = {
  447. .name = "s3c2410-i2c",
  448. .id = 1,
  449. .num_resources = ARRAY_SIZE(s3c_i2c1_resource),
  450. .resource = s3c_i2c1_resource,
  451. };
  452. void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
  453. {
  454. struct s3c2410_platform_i2c *npd;
  455. if (!pd) {
  456. pd = &default_i2c_data;
  457. pd->bus_num = 1;
  458. }
  459. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  460. &s3c_device_i2c1);
  461. if (!npd->cfg_gpio)
  462. npd->cfg_gpio = s3c_i2c1_cfg_gpio;
  463. }
  464. #endif /* CONFIG_S3C_DEV_I2C1 */
  465. #ifdef CONFIG_S3C_DEV_I2C2
  466. static struct resource s3c_i2c2_resource[] = {
  467. [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K),
  468. [1] = DEFINE_RES_IRQ(IRQ_IIC2),
  469. };
  470. struct platform_device s3c_device_i2c2 = {
  471. .name = "s3c2410-i2c",
  472. .id = 2,
  473. .num_resources = ARRAY_SIZE(s3c_i2c2_resource),
  474. .resource = s3c_i2c2_resource,
  475. };
  476. void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
  477. {
  478. struct s3c2410_platform_i2c *npd;
  479. if (!pd) {
  480. pd = &default_i2c_data;
  481. pd->bus_num = 2;
  482. }
  483. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  484. &s3c_device_i2c2);
  485. if (!npd->cfg_gpio)
  486. npd->cfg_gpio = s3c_i2c2_cfg_gpio;
  487. }
  488. #endif /* CONFIG_S3C_DEV_I2C2 */
  489. #ifdef CONFIG_S3C_DEV_I2C3
  490. static struct resource s3c_i2c3_resource[] = {
  491. [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K),
  492. [1] = DEFINE_RES_IRQ(IRQ_IIC3),
  493. };
  494. struct platform_device s3c_device_i2c3 = {
  495. .name = "s3c2440-i2c",
  496. .id = 3,
  497. .num_resources = ARRAY_SIZE(s3c_i2c3_resource),
  498. .resource = s3c_i2c3_resource,
  499. };
  500. void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
  501. {
  502. struct s3c2410_platform_i2c *npd;
  503. if (!pd) {
  504. pd = &default_i2c_data;
  505. pd->bus_num = 3;
  506. }
  507. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  508. &s3c_device_i2c3);
  509. if (!npd->cfg_gpio)
  510. npd->cfg_gpio = s3c_i2c3_cfg_gpio;
  511. }
  512. #endif /*CONFIG_S3C_DEV_I2C3 */
  513. #ifdef CONFIG_S3C_DEV_I2C4
  514. static struct resource s3c_i2c4_resource[] = {
  515. [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K),
  516. [1] = DEFINE_RES_IRQ(IRQ_IIC4),
  517. };
  518. struct platform_device s3c_device_i2c4 = {
  519. .name = "s3c2440-i2c",
  520. .id = 4,
  521. .num_resources = ARRAY_SIZE(s3c_i2c4_resource),
  522. .resource = s3c_i2c4_resource,
  523. };
  524. void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
  525. {
  526. struct s3c2410_platform_i2c *npd;
  527. if (!pd) {
  528. pd = &default_i2c_data;
  529. pd->bus_num = 4;
  530. }
  531. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  532. &s3c_device_i2c4);
  533. if (!npd->cfg_gpio)
  534. npd->cfg_gpio = s3c_i2c4_cfg_gpio;
  535. }
  536. #endif /*CONFIG_S3C_DEV_I2C4 */
  537. #ifdef CONFIG_S3C_DEV_I2C5
  538. static struct resource s3c_i2c5_resource[] = {
  539. [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K),
  540. [1] = DEFINE_RES_IRQ(IRQ_IIC5),
  541. };
  542. struct platform_device s3c_device_i2c5 = {
  543. .name = "s3c2440-i2c",
  544. .id = 5,
  545. .num_resources = ARRAY_SIZE(s3c_i2c5_resource),
  546. .resource = s3c_i2c5_resource,
  547. };
  548. void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
  549. {
  550. struct s3c2410_platform_i2c *npd;
  551. if (!pd) {
  552. pd = &default_i2c_data;
  553. pd->bus_num = 5;
  554. }
  555. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  556. &s3c_device_i2c5);
  557. if (!npd->cfg_gpio)
  558. npd->cfg_gpio = s3c_i2c5_cfg_gpio;
  559. }
  560. #endif /*CONFIG_S3C_DEV_I2C5 */
  561. #ifdef CONFIG_S3C_DEV_I2C6
  562. static struct resource s3c_i2c6_resource[] = {
  563. [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K),
  564. [1] = DEFINE_RES_IRQ(IRQ_IIC6),
  565. };
  566. struct platform_device s3c_device_i2c6 = {
  567. .name = "s3c2440-i2c",
  568. .id = 6,
  569. .num_resources = ARRAY_SIZE(s3c_i2c6_resource),
  570. .resource = s3c_i2c6_resource,
  571. };
  572. void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
  573. {
  574. struct s3c2410_platform_i2c *npd;
  575. if (!pd) {
  576. pd = &default_i2c_data;
  577. pd->bus_num = 6;
  578. }
  579. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  580. &s3c_device_i2c6);
  581. if (!npd->cfg_gpio)
  582. npd->cfg_gpio = s3c_i2c6_cfg_gpio;
  583. }
  584. #endif /* CONFIG_S3C_DEV_I2C6 */
  585. #ifdef CONFIG_S3C_DEV_I2C7
  586. static struct resource s3c_i2c7_resource[] = {
  587. [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K),
  588. [1] = DEFINE_RES_IRQ(IRQ_IIC7),
  589. };
  590. struct platform_device s3c_device_i2c7 = {
  591. .name = "s3c2440-i2c",
  592. .id = 7,
  593. .num_resources = ARRAY_SIZE(s3c_i2c7_resource),
  594. .resource = s3c_i2c7_resource,
  595. };
  596. void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
  597. {
  598. struct s3c2410_platform_i2c *npd;
  599. if (!pd) {
  600. pd = &default_i2c_data;
  601. pd->bus_num = 7;
  602. }
  603. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  604. &s3c_device_i2c7);
  605. if (!npd->cfg_gpio)
  606. npd->cfg_gpio = s3c_i2c7_cfg_gpio;
  607. }
  608. #endif /* CONFIG_S3C_DEV_I2C7 */
  609. /* I2C HDMIPHY */
  610. #ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
  611. static struct resource s5p_i2c_resource[] = {
  612. [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
  613. [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
  614. };
  615. struct platform_device s5p_device_i2c_hdmiphy = {
  616. .name = "s3c2440-hdmiphy-i2c",
  617. .id = -1,
  618. .num_resources = ARRAY_SIZE(s5p_i2c_resource),
  619. .resource = s5p_i2c_resource,
  620. };
  621. void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
  622. {
  623. struct s3c2410_platform_i2c *npd;
  624. if (!pd) {
  625. pd = &default_i2c_data;
  626. if (soc_is_exynos4210() ||
  627. soc_is_exynos4212() || soc_is_exynos4412())
  628. pd->bus_num = 8;
  629. else if (soc_is_s5pv210())
  630. pd->bus_num = 3;
  631. else
  632. pd->bus_num = 0;
  633. }
  634. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  635. &s5p_device_i2c_hdmiphy);
  636. }
  637. static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
  638. void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
  639. struct i2c_board_info *mhl_info, int mhl_bus)
  640. {
  641. struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
  642. if (soc_is_exynos4210() ||
  643. soc_is_exynos4212() || soc_is_exynos4412())
  644. pd->hdmiphy_bus = 8;
  645. else if (soc_is_s5pv210())
  646. pd->hdmiphy_bus = 3;
  647. else
  648. pd->hdmiphy_bus = 0;
  649. pd->hdmiphy_info = hdmiphy_info;
  650. pd->mhl_info = mhl_info;
  651. pd->mhl_bus = mhl_bus;
  652. s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
  653. &s5p_device_hdmi);
  654. }
  655. #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
  656. /* I2S */
  657. #ifdef CONFIG_PLAT_S3C24XX
  658. static struct resource s3c_iis_resource[] = {
  659. [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
  660. };
  661. struct platform_device s3c_device_iis = {
  662. .name = "s3c24xx-iis",
  663. .id = -1,
  664. .num_resources = ARRAY_SIZE(s3c_iis_resource),
  665. .resource = s3c_iis_resource,
  666. .dev = {
  667. .dma_mask = &samsung_device_dma_mask,
  668. .coherent_dma_mask = DMA_BIT_MASK(32),
  669. }
  670. };
  671. #endif /* CONFIG_PLAT_S3C24XX */
  672. /* IDE CFCON */
  673. #ifdef CONFIG_SAMSUNG_DEV_IDE
  674. static struct resource s3c_cfcon_resource[] = {
  675. [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K),
  676. [1] = DEFINE_RES_IRQ(IRQ_CFCON),
  677. };
  678. struct platform_device s3c_device_cfcon = {
  679. .id = 0,
  680. .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
  681. .resource = s3c_cfcon_resource,
  682. };
  683. void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
  684. {
  685. s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
  686. &s3c_device_cfcon);
  687. }
  688. #endif /* CONFIG_SAMSUNG_DEV_IDE */
  689. /* KEYPAD */
  690. #ifdef CONFIG_SAMSUNG_DEV_KEYPAD
  691. static struct resource samsung_keypad_resources[] = {
  692. [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32),
  693. [1] = DEFINE_RES_IRQ(IRQ_KEYPAD),
  694. };
  695. struct platform_device samsung_device_keypad = {
  696. .name = "samsung-keypad",
  697. .id = -1,
  698. .num_resources = ARRAY_SIZE(samsung_keypad_resources),
  699. .resource = samsung_keypad_resources,
  700. };
  701. void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
  702. {
  703. struct samsung_keypad_platdata *npd;
  704. npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata),
  705. &samsung_device_keypad);
  706. if (!npd->cfg_gpio)
  707. npd->cfg_gpio = samsung_keypad_cfg_gpio;
  708. }
  709. #endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
  710. /* LCD Controller */
  711. #ifdef CONFIG_PLAT_S3C24XX
  712. static struct resource s3c_lcd_resource[] = {
  713. [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD),
  714. [1] = DEFINE_RES_IRQ(IRQ_LCD),
  715. };
  716. struct platform_device s3c_device_lcd = {
  717. .name = "s3c2410-lcd",
  718. .id = -1,
  719. .num_resources = ARRAY_SIZE(s3c_lcd_resource),
  720. .resource = s3c_lcd_resource,
  721. .dev = {
  722. .dma_mask = &samsung_device_dma_mask,
  723. .coherent_dma_mask = DMA_BIT_MASK(32),
  724. }
  725. };
  726. void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
  727. {
  728. struct s3c2410fb_mach_info *npd;
  729. npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
  730. if (npd) {
  731. npd->displays = kmemdup(pd->displays,
  732. sizeof(struct s3c2410fb_display) * npd->num_displays,
  733. GFP_KERNEL);
  734. if (!npd->displays)
  735. printk(KERN_ERR "no memory for LCD display data\n");
  736. } else {
  737. printk(KERN_ERR "no memory for LCD platform data\n");
  738. }
  739. }
  740. #endif /* CONFIG_PLAT_S3C24XX */
  741. /* MFC */
  742. #ifdef CONFIG_S5P_DEV_MFC
  743. static struct resource s5p_mfc_resource[] = {
  744. [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
  745. [1] = DEFINE_RES_IRQ(IRQ_MFC),
  746. };
  747. struct platform_device s5p_device_mfc = {
  748. .name = "s5p-mfc",
  749. .id = -1,
  750. .num_resources = ARRAY_SIZE(s5p_mfc_resource),
  751. .resource = s5p_mfc_resource,
  752. };
  753. /*
  754. * MFC hardware has 2 memory interfaces which are modelled as two separate
  755. * platform devices to let dma-mapping distinguish between them.
  756. *
  757. * MFC parent device (s5p_device_mfc) must be registered before memory
  758. * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
  759. */
  760. struct platform_device s5p_device_mfc_l = {
  761. .name = "s5p-mfc-l",
  762. .id = -1,
  763. .dev = {
  764. .parent = &s5p_device_mfc.dev,
  765. .dma_mask = &samsung_device_dma_mask,
  766. .coherent_dma_mask = DMA_BIT_MASK(32),
  767. },
  768. };
  769. struct platform_device s5p_device_mfc_r = {
  770. .name = "s5p-mfc-r",
  771. .id = -1,
  772. .dev = {
  773. .parent = &s5p_device_mfc.dev,
  774. .dma_mask = &samsung_device_dma_mask,
  775. .coherent_dma_mask = DMA_BIT_MASK(32),
  776. },
  777. };
  778. #endif /* CONFIG_S5P_DEV_MFC */
  779. /* MIPI CSIS */
  780. #ifdef CONFIG_S5P_DEV_CSIS0
  781. static struct resource s5p_mipi_csis0_resource[] = {
  782. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
  783. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
  784. };
  785. struct platform_device s5p_device_mipi_csis0 = {
  786. .name = "s5p-mipi-csis",
  787. .id = 0,
  788. .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
  789. .resource = s5p_mipi_csis0_resource,
  790. };
  791. #endif /* CONFIG_S5P_DEV_CSIS0 */
  792. #ifdef CONFIG_S5P_DEV_CSIS1
  793. static struct resource s5p_mipi_csis1_resource[] = {
  794. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
  795. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
  796. };
  797. struct platform_device s5p_device_mipi_csis1 = {
  798. .name = "s5p-mipi-csis",
  799. .id = 1,
  800. .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
  801. .resource = s5p_mipi_csis1_resource,
  802. };
  803. #endif
  804. /* NAND */
  805. #ifdef CONFIG_S3C_DEV_NAND
  806. static struct resource s3c_nand_resource[] = {
  807. [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M),
  808. };
  809. struct platform_device s3c_device_nand = {
  810. .name = "s3c2410-nand",
  811. .id = -1,
  812. .num_resources = ARRAY_SIZE(s3c_nand_resource),
  813. .resource = s3c_nand_resource,
  814. };
  815. /*
  816. * s3c_nand_copy_set() - copy nand set data
  817. * @set: The new structure, directly copied from the old.
  818. *
  819. * Copy all the fields from the NAND set field from what is probably __initdata
  820. * to new kernel memory. The code returns 0 if the copy happened correctly or
  821. * an error code for the calling function to display.
  822. *
  823. * Note, we currently do not try and look to see if we've already copied the
  824. * data in a previous set.
  825. */
  826. static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
  827. {
  828. void *ptr;
  829. int size;
  830. size = sizeof(struct mtd_partition) * set->nr_partitions;
  831. if (size) {
  832. ptr = kmemdup(set->partitions, size, GFP_KERNEL);
  833. set->partitions = ptr;
  834. if (!ptr)
  835. return -ENOMEM;
  836. }
  837. if (set->nr_map && set->nr_chips) {
  838. size = sizeof(int) * set->nr_chips;
  839. ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
  840. set->nr_map = ptr;
  841. if (!ptr)
  842. return -ENOMEM;
  843. }
  844. if (set->ecc_layout) {
  845. ptr = kmemdup(set->ecc_layout,
  846. sizeof(struct nand_ecclayout), GFP_KERNEL);
  847. set->ecc_layout = ptr;
  848. if (!ptr)
  849. return -ENOMEM;
  850. }
  851. return 0;
  852. }
  853. void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
  854. {
  855. struct s3c2410_platform_nand *npd;
  856. int size;
  857. int ret;
  858. /* note, if we get a failure in allocation, we simply drop out of the
  859. * function. If there is so little memory available at initialisation
  860. * time then there is little chance the system is going to run.
  861. */
  862. npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
  863. &s3c_device_nand);
  864. if (!npd)
  865. return;
  866. /* now see if we need to copy any of the nand set data */
  867. size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
  868. if (size) {
  869. struct s3c2410_nand_set *from = npd->sets;
  870. struct s3c2410_nand_set *to;
  871. int i;
  872. to = kmemdup(from, size, GFP_KERNEL);
  873. npd->sets = to; /* set, even if we failed */
  874. if (!to) {
  875. printk(KERN_ERR "%s: no memory for sets\n", __func__);
  876. return;
  877. }
  878. for (i = 0; i < npd->nr_sets; i++) {
  879. ret = s3c_nand_copy_set(to);
  880. if (ret) {
  881. printk(KERN_ERR "%s: failed to copy set %d\n",
  882. __func__, i);
  883. return;
  884. }
  885. to++;
  886. }
  887. }
  888. }
  889. #endif /* CONFIG_S3C_DEV_NAND */
  890. /* ONENAND */
  891. #ifdef CONFIG_S3C_DEV_ONENAND
  892. static struct resource s3c_onenand_resources[] = {
  893. [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K),
  894. [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF),
  895. [2] = DEFINE_RES_IRQ(IRQ_ONENAND),
  896. };
  897. struct platform_device s3c_device_onenand = {
  898. .name = "samsung-onenand",
  899. .id = 0,
  900. .num_resources = ARRAY_SIZE(s3c_onenand_resources),
  901. .resource = s3c_onenand_resources,
  902. };
  903. #endif /* CONFIG_S3C_DEV_ONENAND */
  904. #ifdef CONFIG_S3C64XX_DEV_ONENAND1
  905. static struct resource s3c64xx_onenand1_resources[] = {
  906. [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K),
  907. [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
  908. [2] = DEFINE_RES_IRQ(IRQ_ONENAND1),
  909. };
  910. struct platform_device s3c64xx_device_onenand1 = {
  911. .name = "samsung-onenand",
  912. .id = 1,
  913. .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
  914. .resource = s3c64xx_onenand1_resources,
  915. };
  916. void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
  917. {
  918. s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
  919. &s3c64xx_device_onenand1);
  920. }
  921. #endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
  922. #ifdef CONFIG_S5P_DEV_ONENAND
  923. static struct resource s5p_onenand_resources[] = {
  924. [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
  925. [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
  926. [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
  927. };
  928. struct platform_device s5p_device_onenand = {
  929. .name = "s5pc110-onenand",
  930. .id = -1,
  931. .num_resources = ARRAY_SIZE(s5p_onenand_resources),
  932. .resource = s5p_onenand_resources,
  933. };
  934. #endif /* CONFIG_S5P_DEV_ONENAND */
  935. /* PMU */
  936. #ifdef CONFIG_PLAT_S5P
  937. static struct resource s5p_pmu_resource[] = {
  938. DEFINE_RES_IRQ(IRQ_PMU)
  939. };
  940. static struct platform_device s5p_device_pmu = {
  941. .name = "arm-pmu",
  942. .id = -1,
  943. .num_resources = ARRAY_SIZE(s5p_pmu_resource),
  944. .resource = s5p_pmu_resource,
  945. };
  946. static int __init s5p_pmu_init(void)
  947. {
  948. platform_device_register(&s5p_device_pmu);
  949. return 0;
  950. }
  951. arch_initcall(s5p_pmu_init);
  952. #endif /* CONFIG_PLAT_S5P */
  953. /* PWM Timer */
  954. #ifdef CONFIG_SAMSUNG_DEV_PWM
  955. #define TIMER_RESOURCE_SIZE (1)
  956. #define TIMER_RESOURCE(_tmr, _irq) \
  957. (struct resource [TIMER_RESOURCE_SIZE]) { \
  958. [0] = { \
  959. .start = _irq, \
  960. .end = _irq, \
  961. .flags = IORESOURCE_IRQ \
  962. } \
  963. }
  964. #define DEFINE_S3C_TIMER(_tmr_no, _irq) \
  965. .name = "s3c24xx-pwm", \
  966. .id = _tmr_no, \
  967. .num_resources = TIMER_RESOURCE_SIZE, \
  968. .resource = TIMER_RESOURCE(_tmr_no, _irq), \
  969. /*
  970. * since we already have an static mapping for the timer,
  971. * we do not bother setting any IO resource for the base.
  972. */
  973. struct platform_device s3c_device_timer[] = {
  974. [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
  975. [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
  976. [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
  977. [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
  978. [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
  979. };
  980. #endif /* CONFIG_SAMSUNG_DEV_PWM */
  981. /* RTC */
  982. #ifdef CONFIG_PLAT_S3C24XX
  983. static struct resource s3c_rtc_resource[] = {
  984. [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
  985. [1] = DEFINE_RES_IRQ(IRQ_RTC),
  986. [2] = DEFINE_RES_IRQ(IRQ_TICK),
  987. };
  988. struct platform_device s3c_device_rtc = {
  989. .name = "s3c2410-rtc",
  990. .id = -1,
  991. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  992. .resource = s3c_rtc_resource,
  993. };
  994. #endif /* CONFIG_PLAT_S3C24XX */
  995. #ifdef CONFIG_S3C_DEV_RTC
  996. static struct resource s3c_rtc_resource[] = {
  997. [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
  998. [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM),
  999. [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC),
  1000. };
  1001. struct platform_device s3c_device_rtc = {
  1002. .name = "s3c64xx-rtc",
  1003. .id = -1,
  1004. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  1005. .resource = s3c_rtc_resource,
  1006. };
  1007. #endif /* CONFIG_S3C_DEV_RTC */
  1008. /* SDI */
  1009. #ifdef CONFIG_PLAT_S3C24XX
  1010. static struct resource s3c_sdi_resource[] = {
  1011. [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
  1012. [1] = DEFINE_RES_IRQ(IRQ_SDI),
  1013. };
  1014. struct platform_device s3c_device_sdi = {
  1015. .name = "s3c2410-sdi",
  1016. .id = -1,
  1017. .num_resources = ARRAY_SIZE(s3c_sdi_resource),
  1018. .resource = s3c_sdi_resource,
  1019. };
  1020. void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
  1021. {
  1022. s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
  1023. &s3c_device_sdi);
  1024. }
  1025. #endif /* CONFIG_PLAT_S3C24XX */
  1026. /* SPI */
  1027. #ifdef CONFIG_PLAT_S3C24XX
  1028. static struct resource s3c_spi0_resource[] = {
  1029. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32),
  1030. [1] = DEFINE_RES_IRQ(IRQ_SPI0),
  1031. };
  1032. struct platform_device s3c_device_spi0 = {
  1033. .name = "s3c2410-spi",
  1034. .id = 0,
  1035. .num_resources = ARRAY_SIZE(s3c_spi0_resource),
  1036. .resource = s3c_spi0_resource,
  1037. .dev = {
  1038. .dma_mask = &samsung_device_dma_mask,
  1039. .coherent_dma_mask = DMA_BIT_MASK(32),
  1040. }
  1041. };
  1042. static struct resource s3c_spi1_resource[] = {
  1043. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32),
  1044. [1] = DEFINE_RES_IRQ(IRQ_SPI1),
  1045. };
  1046. struct platform_device s3c_device_spi1 = {
  1047. .name = "s3c2410-spi",
  1048. .id = 1,
  1049. .num_resources = ARRAY_SIZE(s3c_spi1_resource),
  1050. .resource = s3c_spi1_resource,
  1051. .dev = {
  1052. .dma_mask = &samsung_device_dma_mask,
  1053. .coherent_dma_mask = DMA_BIT_MASK(32),
  1054. }
  1055. };
  1056. #endif /* CONFIG_PLAT_S3C24XX */
  1057. /* Touchscreen */
  1058. #ifdef CONFIG_PLAT_S3C24XX
  1059. static struct resource s3c_ts_resource[] = {
  1060. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  1061. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1062. };
  1063. struct platform_device s3c_device_ts = {
  1064. .name = "s3c2410-ts",
  1065. .id = -1,
  1066. .dev.parent = &s3c_device_adc.dev,
  1067. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1068. .resource = s3c_ts_resource,
  1069. };
  1070. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
  1071. {
  1072. s3c_set_platdata(hard_s3c2410ts_info,
  1073. sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
  1074. }
  1075. #endif /* CONFIG_PLAT_S3C24XX */
  1076. #ifdef CONFIG_SAMSUNG_DEV_TS
  1077. static struct resource s3c_ts_resource[] = {
  1078. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  1079. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1080. };
  1081. static struct s3c2410_ts_mach_info default_ts_data __initdata = {
  1082. .delay = 10000,
  1083. .presc = 49,
  1084. .oversampling_shift = 2,
  1085. };
  1086. struct platform_device s3c_device_ts = {
  1087. .name = "s3c64xx-ts",
  1088. .id = -1,
  1089. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1090. .resource = s3c_ts_resource,
  1091. };
  1092. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
  1093. {
  1094. if (!pd)
  1095. pd = &default_ts_data;
  1096. s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
  1097. &s3c_device_ts);
  1098. }
  1099. #endif /* CONFIG_SAMSUNG_DEV_TS */
  1100. /* TV */
  1101. #ifdef CONFIG_S5P_DEV_TV
  1102. static struct resource s5p_hdmi_resources[] = {
  1103. [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
  1104. [1] = DEFINE_RES_IRQ(IRQ_HDMI),
  1105. };
  1106. struct platform_device s5p_device_hdmi = {
  1107. .name = "s5p-hdmi",
  1108. .id = -1,
  1109. .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
  1110. .resource = s5p_hdmi_resources,
  1111. };
  1112. static struct resource s5p_sdo_resources[] = {
  1113. [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
  1114. [1] = DEFINE_RES_IRQ(IRQ_SDO),
  1115. };
  1116. struct platform_device s5p_device_sdo = {
  1117. .name = "s5p-sdo",
  1118. .id = -1,
  1119. .num_resources = ARRAY_SIZE(s5p_sdo_resources),
  1120. .resource = s5p_sdo_resources,
  1121. };
  1122. static struct resource s5p_mixer_resources[] = {
  1123. [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
  1124. [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
  1125. [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
  1126. };
  1127. struct platform_device s5p_device_mixer = {
  1128. .name = "s5p-mixer",
  1129. .id = -1,
  1130. .num_resources = ARRAY_SIZE(s5p_mixer_resources),
  1131. .resource = s5p_mixer_resources,
  1132. .dev = {
  1133. .dma_mask = &samsung_device_dma_mask,
  1134. .coherent_dma_mask = DMA_BIT_MASK(32),
  1135. }
  1136. };
  1137. #endif /* CONFIG_S5P_DEV_TV */
  1138. /* USB */
  1139. #ifdef CONFIG_S3C_DEV_USB_HOST
  1140. static struct resource s3c_usb_resource[] = {
  1141. [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
  1142. [1] = DEFINE_RES_IRQ(IRQ_USBH),
  1143. };
  1144. struct platform_device s3c_device_ohci = {
  1145. .name = "s3c2410-ohci",
  1146. .id = -1,
  1147. .num_resources = ARRAY_SIZE(s3c_usb_resource),
  1148. .resource = s3c_usb_resource,
  1149. .dev = {
  1150. .dma_mask = &samsung_device_dma_mask,
  1151. .coherent_dma_mask = DMA_BIT_MASK(32),
  1152. }
  1153. };
  1154. /*
  1155. * s3c_ohci_set_platdata - initialise OHCI device platform data
  1156. * @info: The platform data.
  1157. *
  1158. * This call copies the @info passed in and sets the device .platform_data
  1159. * field to that copy. The @info is copied so that the original can be marked
  1160. * __initdata.
  1161. */
  1162. void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
  1163. {
  1164. s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
  1165. &s3c_device_ohci);
  1166. }
  1167. #endif /* CONFIG_S3C_DEV_USB_HOST */
  1168. /* USB Device (Gadget) */
  1169. #ifdef CONFIG_PLAT_S3C24XX
  1170. static struct resource s3c_usbgadget_resource[] = {
  1171. [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV),
  1172. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1173. };
  1174. struct platform_device s3c_device_usbgadget = {
  1175. .name = "s3c2410-usbgadget",
  1176. .id = -1,
  1177. .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
  1178. .resource = s3c_usbgadget_resource,
  1179. };
  1180. void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
  1181. {
  1182. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
  1183. }
  1184. #endif /* CONFIG_PLAT_S3C24XX */
  1185. /* USB EHCI Host Controller */
  1186. #ifdef CONFIG_S5P_DEV_USB_EHCI
  1187. static struct resource s5p_ehci_resource[] = {
  1188. [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256),
  1189. [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
  1190. };
  1191. struct platform_device s5p_device_ehci = {
  1192. .name = "s5p-ehci",
  1193. .id = -1,
  1194. .num_resources = ARRAY_SIZE(s5p_ehci_resource),
  1195. .resource = s5p_ehci_resource,
  1196. .dev = {
  1197. .dma_mask = &samsung_device_dma_mask,
  1198. .coherent_dma_mask = DMA_BIT_MASK(32),
  1199. }
  1200. };
  1201. void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
  1202. {
  1203. struct s5p_ehci_platdata *npd;
  1204. npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
  1205. &s5p_device_ehci);
  1206. if (!npd->phy_init)
  1207. npd->phy_init = s5p_usb_phy_init;
  1208. if (!npd->phy_exit)
  1209. npd->phy_exit = s5p_usb_phy_exit;
  1210. }
  1211. #endif /* CONFIG_S5P_DEV_USB_EHCI */
  1212. /* USB HSOTG */
  1213. #ifdef CONFIG_S3C_DEV_USB_HSOTG
  1214. static struct resource s3c_usb_hsotg_resources[] = {
  1215. [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_128K),
  1216. [1] = DEFINE_RES_IRQ(IRQ_OTG),
  1217. };
  1218. struct platform_device s3c_device_usb_hsotg = {
  1219. .name = "s3c-hsotg",
  1220. .id = -1,
  1221. .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
  1222. .resource = s3c_usb_hsotg_resources,
  1223. .dev = {
  1224. .dma_mask = &samsung_device_dma_mask,
  1225. .coherent_dma_mask = DMA_BIT_MASK(32),
  1226. },
  1227. };
  1228. void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
  1229. {
  1230. struct s3c_hsotg_plat *npd;
  1231. npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat),
  1232. &s3c_device_usb_hsotg);
  1233. if (!npd->phy_init)
  1234. npd->phy_init = s5p_usb_phy_init;
  1235. if (!npd->phy_exit)
  1236. npd->phy_exit = s5p_usb_phy_exit;
  1237. }
  1238. #endif /* CONFIG_S3C_DEV_USB_HSOTG */
  1239. /* USB High Spped 2.0 Device (Gadget) */
  1240. #ifdef CONFIG_PLAT_S3C24XX
  1241. static struct resource s3c_hsudc_resource[] = {
  1242. [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC),
  1243. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1244. };
  1245. struct platform_device s3c_device_usb_hsudc = {
  1246. .name = "s3c-hsudc",
  1247. .id = -1,
  1248. .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
  1249. .resource = s3c_hsudc_resource,
  1250. .dev = {
  1251. .dma_mask = &samsung_device_dma_mask,
  1252. .coherent_dma_mask = DMA_BIT_MASK(32),
  1253. },
  1254. };
  1255. void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
  1256. {
  1257. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
  1258. }
  1259. #endif /* CONFIG_PLAT_S3C24XX */
  1260. /* WDT */
  1261. #ifdef CONFIG_S3C_DEV_WDT
  1262. static struct resource s3c_wdt_resource[] = {
  1263. [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K),
  1264. [1] = DEFINE_RES_IRQ(IRQ_WDT),
  1265. };
  1266. struct platform_device s3c_device_wdt = {
  1267. .name = "s3c2410-wdt",
  1268. .id = -1,
  1269. .num_resources = ARRAY_SIZE(s3c_wdt_resource),
  1270. .resource = s3c_wdt_resource,
  1271. };
  1272. #endif /* CONFIG_S3C_DEV_WDT */
  1273. #ifdef CONFIG_S3C64XX_DEV_SPI0
  1274. static struct resource s3c64xx_spi0_resource[] = {
  1275. [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
  1276. [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
  1277. [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
  1278. [3] = DEFINE_RES_IRQ(IRQ_SPI0),
  1279. };
  1280. struct platform_device s3c64xx_device_spi0 = {
  1281. .name = "s3c6410-spi",
  1282. .id = 0,
  1283. .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
  1284. .resource = s3c64xx_spi0_resource,
  1285. .dev = {
  1286. .dma_mask = &samsung_device_dma_mask,
  1287. .coherent_dma_mask = DMA_BIT_MASK(32),
  1288. },
  1289. };
  1290. void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1291. int num_cs)
  1292. {
  1293. struct s3c64xx_spi_info pd;
  1294. /* Reject invalid configuration */
  1295. if (!num_cs || src_clk_nr < 0) {
  1296. pr_err("%s: Invalid SPI configuration\n", __func__);
  1297. return;
  1298. }
  1299. pd.num_cs = num_cs;
  1300. pd.src_clk_nr = src_clk_nr;
  1301. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
  1302. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
  1303. }
  1304. #endif /* CONFIG_S3C64XX_DEV_SPI0 */
  1305. #ifdef CONFIG_S3C64XX_DEV_SPI1
  1306. static struct resource s3c64xx_spi1_resource[] = {
  1307. [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
  1308. [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
  1309. [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
  1310. [3] = DEFINE_RES_IRQ(IRQ_SPI1),
  1311. };
  1312. struct platform_device s3c64xx_device_spi1 = {
  1313. .name = "s3c6410-spi",
  1314. .id = 1,
  1315. .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
  1316. .resource = s3c64xx_spi1_resource,
  1317. .dev = {
  1318. .dma_mask = &samsung_device_dma_mask,
  1319. .coherent_dma_mask = DMA_BIT_MASK(32),
  1320. },
  1321. };
  1322. void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1323. int num_cs)
  1324. {
  1325. struct s3c64xx_spi_info pd;
  1326. /* Reject invalid configuration */
  1327. if (!num_cs || src_clk_nr < 0) {
  1328. pr_err("%s: Invalid SPI configuration\n", __func__);
  1329. return;
  1330. }
  1331. pd.num_cs = num_cs;
  1332. pd.src_clk_nr = src_clk_nr;
  1333. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
  1334. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
  1335. }
  1336. #endif /* CONFIG_S3C64XX_DEV_SPI1 */
  1337. #ifdef CONFIG_S3C64XX_DEV_SPI2
  1338. static struct resource s3c64xx_spi2_resource[] = {
  1339. [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
  1340. [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
  1341. [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
  1342. [3] = DEFINE_RES_IRQ(IRQ_SPI2),
  1343. };
  1344. struct platform_device s3c64xx_device_spi2 = {
  1345. .name = "s3c6410-spi",
  1346. .id = 2,
  1347. .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
  1348. .resource = s3c64xx_spi2_resource,
  1349. .dev = {
  1350. .dma_mask = &samsung_device_dma_mask,
  1351. .coherent_dma_mask = DMA_BIT_MASK(32),
  1352. },
  1353. };
  1354. void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1355. int num_cs)
  1356. {
  1357. struct s3c64xx_spi_info pd;
  1358. /* Reject invalid configuration */
  1359. if (!num_cs || src_clk_nr < 0) {
  1360. pr_err("%s: Invalid SPI configuration\n", __func__);
  1361. return;
  1362. }
  1363. pd.num_cs = num_cs;
  1364. pd.src_clk_nr = src_clk_nr;
  1365. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
  1366. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
  1367. }
  1368. #endif /* CONFIG_S3C64XX_DEV_SPI2 */