Kconfig 64 KB

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  1. config ARM
  2. bool
  3. default y
  4. select HAVE_AOUT
  5. select HAVE_DMA_API_DEBUG
  6. select HAVE_IDE if PCI || ISA || PCMCIA
  7. select HAVE_MEMBLOCK
  8. select RTC_LIB
  9. select SYS_SUPPORTS_APM_EMULATION
  10. select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
  11. select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  12. select HAVE_ARCH_KGDB
  13. select HAVE_KPROBES if !XIP_KERNEL
  14. select HAVE_KRETPROBES if (HAVE_KPROBES)
  15. select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  16. select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  17. select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  18. select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  19. select HAVE_GENERIC_DMA_COHERENT
  20. select HAVE_KERNEL_GZIP
  21. select HAVE_KERNEL_LZO
  22. select HAVE_KERNEL_LZMA
  23. select HAVE_IRQ_WORK
  24. select HAVE_PERF_EVENTS
  25. select PERF_USE_VMALLOC
  26. select HAVE_REGS_AND_STACK_ACCESS_API
  27. select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  28. select HAVE_C_RECORDMCOUNT
  29. select HAVE_GENERIC_HARDIRQS
  30. select HAVE_SPARSE_IRQ
  31. select GENERIC_IRQ_SHOW
  32. select CPU_PM if (SUSPEND || CPU_IDLE)
  33. help
  34. The ARM series is a line of low-power-consumption RISC chip designs
  35. licensed by ARM Ltd and targeted at embedded applications and
  36. handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
  37. manufactured, but legacy ARM-based PC hardware remains popular in
  38. Europe. There is an ARM Linux project with a web page at
  39. <http://www.arm.linux.org.uk/>.
  40. config ARM_HAS_SG_CHAIN
  41. bool
  42. config HAVE_PWM
  43. bool
  44. config MIGHT_HAVE_PCI
  45. bool
  46. config SYS_SUPPORTS_APM_EMULATION
  47. bool
  48. config HAVE_SCHED_CLOCK
  49. bool
  50. config GENERIC_GPIO
  51. bool
  52. config ARCH_USES_GETTIMEOFFSET
  53. bool
  54. default n
  55. config GENERIC_CLOCKEVENTS
  56. bool
  57. config GENERIC_CLOCKEVENTS_BROADCAST
  58. bool
  59. depends on GENERIC_CLOCKEVENTS
  60. default y if SMP
  61. config KTIME_SCALAR
  62. bool
  63. default y
  64. config HAVE_TCM
  65. bool
  66. select GENERIC_ALLOCATOR
  67. config HAVE_PROC_CPU
  68. bool
  69. config NO_IOPORT
  70. bool
  71. config EISA
  72. bool
  73. ---help---
  74. The Extended Industry Standard Architecture (EISA) bus was
  75. developed as an open alternative to the IBM MicroChannel bus.
  76. The EISA bus provided some of the features of the IBM MicroChannel
  77. bus while maintaining backward compatibility with cards made for
  78. the older ISA bus. The EISA bus saw limited use between 1988 and
  79. 1995 when it was made obsolete by the PCI bus.
  80. Say Y here if you are building a kernel for an EISA-based machine.
  81. Otherwise, say N.
  82. config SBUS
  83. bool
  84. config MCA
  85. bool
  86. help
  87. MicroChannel Architecture is found in some IBM PS/2 machines and
  88. laptops. It is a bus system similar to PCI or ISA. See
  89. <file:Documentation/mca.txt> (and especially the web page given
  90. there) before attempting to build an MCA bus kernel.
  91. config STACKTRACE_SUPPORT
  92. bool
  93. default y
  94. config HAVE_LATENCYTOP_SUPPORT
  95. bool
  96. depends on !SMP
  97. default y
  98. config LOCKDEP_SUPPORT
  99. bool
  100. default y
  101. config TRACE_IRQFLAGS_SUPPORT
  102. bool
  103. default y
  104. config HARDIRQS_SW_RESEND
  105. bool
  106. default y
  107. config GENERIC_IRQ_PROBE
  108. bool
  109. default y
  110. config GENERIC_LOCKBREAK
  111. bool
  112. default y
  113. depends on SMP && PREEMPT
  114. config RWSEM_GENERIC_SPINLOCK
  115. bool
  116. default y
  117. config RWSEM_XCHGADD_ALGORITHM
  118. bool
  119. config ARCH_HAS_ILOG2_U32
  120. bool
  121. config ARCH_HAS_ILOG2_U64
  122. bool
  123. config ARCH_HAS_CPUFREQ
  124. bool
  125. help
  126. Internal node to signify that the ARCH has CPUFREQ support
  127. and that the relevant menu configurations are displayed for
  128. it.
  129. config ARCH_HAS_CPU_IDLE_WAIT
  130. def_bool y
  131. config GENERIC_HWEIGHT
  132. bool
  133. default y
  134. config GENERIC_CALIBRATE_DELAY
  135. bool
  136. default y
  137. config ARCH_MAY_HAVE_PC_FDC
  138. bool
  139. config ZONE_DMA
  140. bool
  141. config NEED_DMA_MAP_STATE
  142. def_bool y
  143. config GENERIC_ISA_DMA
  144. bool
  145. config FIQ
  146. bool
  147. config ARCH_MTD_XIP
  148. bool
  149. config VECTORS_BASE
  150. hex
  151. default 0xffff0000 if MMU || CPU_HIGH_VECTOR
  152. default DRAM_BASE if REMAP_VECTORS_TO_RAM
  153. default 0x00000000
  154. help
  155. The base address of exception vectors.
  156. config ARM_PATCH_PHYS_VIRT
  157. bool "Patch physical to virtual translations at runtime" if EMBEDDED
  158. default y
  159. depends on !XIP_KERNEL && MMU
  160. depends on !ARCH_REALVIEW || !SPARSEMEM
  161. help
  162. Patch phys-to-virt and virt-to-phys translation functions at
  163. boot and module load time according to the position of the
  164. kernel in system memory.
  165. This can only be used with non-XIP MMU kernels where the base
  166. of physical memory is at a 16MB boundary.
  167. Only disable this option if you know that you do not require
  168. this feature (eg, building a kernel for a single machine) and
  169. you need to shrink the kernel to the minimal size.
  170. config NEED_MACH_MEMORY_H
  171. bool
  172. help
  173. Select this when mach/memory.h is required to provide special
  174. definitions for this platform. The need for mach/memory.h should
  175. be avoided when possible.
  176. config PHYS_OFFSET
  177. hex "Physical address of main memory" if MMU
  178. depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
  179. default DRAM_BASE if !MMU
  180. help
  181. Please provide the physical address corresponding to the
  182. location of main memory in your system.
  183. config GENERIC_BUG
  184. def_bool y
  185. depends on BUG
  186. source "init/Kconfig"
  187. source "kernel/Kconfig.freezer"
  188. menu "System Type"
  189. config MMU
  190. bool "MMU-based Paged Memory Management Support"
  191. default y
  192. help
  193. Select if you want MMU-based virtualised addressing space
  194. support by paged memory management. If unsure, say 'Y'.
  195. #
  196. # The "ARM system type" choice list is ordered alphabetically by option
  197. # text. Please add new entries in the option alphabetic order.
  198. #
  199. choice
  200. prompt "ARM system type"
  201. default ARCH_VERSATILE
  202. config ARCH_INTEGRATOR
  203. bool "ARM Ltd. Integrator family"
  204. select ARM_AMBA
  205. select ARCH_HAS_CPUFREQ
  206. select CLKDEV_LOOKUP
  207. select HAVE_MACH_CLKDEV
  208. select HAVE_TCM
  209. select ICST
  210. select GENERIC_CLOCKEVENTS
  211. select PLAT_VERSATILE
  212. select PLAT_VERSATILE_FPGA_IRQ
  213. select NEED_MACH_MEMORY_H
  214. help
  215. Support for ARM's Integrator platform.
  216. config ARCH_REALVIEW
  217. bool "ARM Ltd. RealView family"
  218. select ARM_AMBA
  219. select CLKDEV_LOOKUP
  220. select HAVE_MACH_CLKDEV
  221. select ICST
  222. select GENERIC_CLOCKEVENTS
  223. select ARCH_WANT_OPTIONAL_GPIOLIB
  224. select PLAT_VERSATILE
  225. select PLAT_VERSATILE_CLCD
  226. select ARM_TIMER_SP804
  227. select GPIO_PL061 if GPIOLIB
  228. select NEED_MACH_MEMORY_H
  229. help
  230. This enables support for ARM Ltd RealView boards.
  231. config ARCH_VERSATILE
  232. bool "ARM Ltd. Versatile family"
  233. select ARM_AMBA
  234. select ARM_VIC
  235. select CLKDEV_LOOKUP
  236. select HAVE_MACH_CLKDEV
  237. select ICST
  238. select GENERIC_CLOCKEVENTS
  239. select ARCH_WANT_OPTIONAL_GPIOLIB
  240. select PLAT_VERSATILE
  241. select PLAT_VERSATILE_CLCD
  242. select PLAT_VERSATILE_FPGA_IRQ
  243. select ARM_TIMER_SP804
  244. help
  245. This enables support for ARM Ltd Versatile board.
  246. config ARCH_VEXPRESS
  247. bool "ARM Ltd. Versatile Express family"
  248. select ARCH_WANT_OPTIONAL_GPIOLIB
  249. select ARM_AMBA
  250. select ARM_TIMER_SP804
  251. select CLKDEV_LOOKUP
  252. select HAVE_MACH_CLKDEV
  253. select GENERIC_CLOCKEVENTS
  254. select HAVE_CLK
  255. select HAVE_PATA_PLATFORM
  256. select ICST
  257. select PLAT_VERSATILE
  258. select PLAT_VERSATILE_CLCD
  259. help
  260. This enables support for the ARM Ltd Versatile Express boards.
  261. config ARCH_AT91
  262. bool "Atmel AT91"
  263. select ARCH_REQUIRE_GPIOLIB
  264. select HAVE_CLK
  265. select CLKDEV_LOOKUP
  266. help
  267. This enables support for systems based on the Atmel AT91RM9200,
  268. AT91SAM9 and AT91CAP9 processors.
  269. config ARCH_BCMRING
  270. bool "Broadcom BCMRING"
  271. depends on MMU
  272. select CPU_V6
  273. select ARM_AMBA
  274. select ARM_TIMER_SP804
  275. select CLKDEV_LOOKUP
  276. select GENERIC_CLOCKEVENTS
  277. select ARCH_WANT_OPTIONAL_GPIOLIB
  278. help
  279. Support for Broadcom's BCMRing platform.
  280. config ARCH_HIGHBANK
  281. bool "Calxeda Highbank-based"
  282. select ARCH_WANT_OPTIONAL_GPIOLIB
  283. select ARM_AMBA
  284. select ARM_GIC
  285. select ARM_TIMER_SP804
  286. select CACHE_L2X0
  287. select CLKDEV_LOOKUP
  288. select CPU_V7
  289. select GENERIC_CLOCKEVENTS
  290. select HAVE_ARM_SCU
  291. select HAVE_SMP
  292. select USE_OF
  293. help
  294. Support for the Calxeda Highbank SoC based boards.
  295. config ARCH_CLPS711X
  296. bool "Cirrus Logic CLPS711x/EP721x-based"
  297. select CPU_ARM720T
  298. select ARCH_USES_GETTIMEOFFSET
  299. select NEED_MACH_MEMORY_H
  300. help
  301. Support for Cirrus Logic 711x/721x based boards.
  302. config ARCH_CNS3XXX
  303. bool "Cavium Networks CNS3XXX family"
  304. select CPU_V6K
  305. select GENERIC_CLOCKEVENTS
  306. select ARM_GIC
  307. select MIGHT_HAVE_CACHE_L2X0
  308. select MIGHT_HAVE_PCI
  309. select PCI_DOMAINS if PCI
  310. help
  311. Support for Cavium Networks CNS3XXX platform.
  312. config ARCH_GEMINI
  313. bool "Cortina Systems Gemini"
  314. select CPU_FA526
  315. select ARCH_REQUIRE_GPIOLIB
  316. select ARCH_USES_GETTIMEOFFSET
  317. help
  318. Support for the Cortina Systems Gemini family SoCs
  319. config ARCH_PRIMA2
  320. bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
  321. select CPU_V7
  322. select NO_IOPORT
  323. select GENERIC_CLOCKEVENTS
  324. select CLKDEV_LOOKUP
  325. select GENERIC_IRQ_CHIP
  326. select MIGHT_HAVE_CACHE_L2X0
  327. select USE_OF
  328. select ZONE_DMA
  329. help
  330. Support for CSR SiRFSoC ARM Cortex A9 Platform
  331. config ARCH_EBSA110
  332. bool "EBSA-110"
  333. select CPU_SA110
  334. select ISA
  335. select NO_IOPORT
  336. select ARCH_USES_GETTIMEOFFSET
  337. select NEED_MACH_MEMORY_H
  338. help
  339. This is an evaluation board for the StrongARM processor available
  340. from Digital. It has limited hardware on-board, including an
  341. Ethernet interface, two PCMCIA sockets, two serial ports and a
  342. parallel port.
  343. config ARCH_EP93XX
  344. bool "EP93xx-based"
  345. select CPU_ARM920T
  346. select ARM_AMBA
  347. select ARM_VIC
  348. select CLKDEV_LOOKUP
  349. select ARCH_REQUIRE_GPIOLIB
  350. select ARCH_HAS_HOLES_MEMORYMODEL
  351. select ARCH_USES_GETTIMEOFFSET
  352. select NEED_MACH_MEMORY_H
  353. help
  354. This enables support for the Cirrus EP93xx series of CPUs.
  355. config ARCH_FOOTBRIDGE
  356. bool "FootBridge"
  357. select CPU_SA110
  358. select FOOTBRIDGE
  359. select GENERIC_CLOCKEVENTS
  360. select HAVE_IDE
  361. select NEED_MACH_MEMORY_H
  362. help
  363. Support for systems based on the DC21285 companion chip
  364. ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
  365. config ARCH_MXC
  366. bool "Freescale MXC/iMX-based"
  367. select GENERIC_CLOCKEVENTS
  368. select ARCH_REQUIRE_GPIOLIB
  369. select CLKDEV_LOOKUP
  370. select CLKSRC_MMIO
  371. select GENERIC_IRQ_CHIP
  372. select HAVE_SCHED_CLOCK
  373. select MULTI_IRQ_HANDLER
  374. help
  375. Support for Freescale MXC/iMX-based family of processors
  376. config ARCH_MXS
  377. bool "Freescale MXS-based"
  378. select GENERIC_CLOCKEVENTS
  379. select ARCH_REQUIRE_GPIOLIB
  380. select CLKDEV_LOOKUP
  381. select CLKSRC_MMIO
  382. help
  383. Support for Freescale MXS-based family of processors
  384. config ARCH_NETX
  385. bool "Hilscher NetX based"
  386. select CLKSRC_MMIO
  387. select CPU_ARM926T
  388. select ARM_VIC
  389. select GENERIC_CLOCKEVENTS
  390. help
  391. This enables support for systems based on the Hilscher NetX Soc
  392. config ARCH_H720X
  393. bool "Hynix HMS720x-based"
  394. select CPU_ARM720T
  395. select ISA_DMA_API
  396. select ARCH_USES_GETTIMEOFFSET
  397. help
  398. This enables support for systems based on the Hynix HMS720x
  399. config ARCH_IOP13XX
  400. bool "IOP13xx-based"
  401. depends on MMU
  402. select CPU_XSC3
  403. select PLAT_IOP
  404. select PCI
  405. select ARCH_SUPPORTS_MSI
  406. select VMSPLIT_1G
  407. select NEED_MACH_MEMORY_H
  408. help
  409. Support for Intel's IOP13XX (XScale) family of processors.
  410. config ARCH_IOP32X
  411. bool "IOP32x-based"
  412. depends on MMU
  413. select CPU_XSCALE
  414. select PLAT_IOP
  415. select PCI
  416. select ARCH_REQUIRE_GPIOLIB
  417. help
  418. Support for Intel's 80219 and IOP32X (XScale) family of
  419. processors.
  420. config ARCH_IOP33X
  421. bool "IOP33x-based"
  422. depends on MMU
  423. select CPU_XSCALE
  424. select PLAT_IOP
  425. select PCI
  426. select ARCH_REQUIRE_GPIOLIB
  427. help
  428. Support for Intel's IOP33X (XScale) family of processors.
  429. config ARCH_IXP23XX
  430. bool "IXP23XX-based"
  431. depends on MMU
  432. select CPU_XSC3
  433. select PCI
  434. select ARCH_USES_GETTIMEOFFSET
  435. select NEED_MACH_MEMORY_H
  436. help
  437. Support for Intel's IXP23xx (XScale) family of processors.
  438. config ARCH_IXP2000
  439. bool "IXP2400/2800-based"
  440. depends on MMU
  441. select CPU_XSCALE
  442. select PCI
  443. select ARCH_USES_GETTIMEOFFSET
  444. select NEED_MACH_MEMORY_H
  445. help
  446. Support for Intel's IXP2400/2800 (XScale) family of processors.
  447. config ARCH_IXP4XX
  448. bool "IXP4xx-based"
  449. depends on MMU
  450. select CLKSRC_MMIO
  451. select CPU_XSCALE
  452. select GENERIC_GPIO
  453. select GENERIC_CLOCKEVENTS
  454. select HAVE_SCHED_CLOCK
  455. select MIGHT_HAVE_PCI
  456. select DMABOUNCE if PCI
  457. help
  458. Support for Intel's IXP4XX (XScale) family of processors.
  459. config ARCH_DOVE
  460. bool "Marvell Dove"
  461. select CPU_V7
  462. select PCI
  463. select ARCH_REQUIRE_GPIOLIB
  464. select GENERIC_CLOCKEVENTS
  465. select PLAT_ORION
  466. help
  467. Support for the Marvell Dove SoC 88AP510
  468. config ARCH_KIRKWOOD
  469. bool "Marvell Kirkwood"
  470. select CPU_FEROCEON
  471. select PCI
  472. select ARCH_REQUIRE_GPIOLIB
  473. select GENERIC_CLOCKEVENTS
  474. select PLAT_ORION
  475. help
  476. Support for the following Marvell Kirkwood series SoCs:
  477. 88F6180, 88F6192 and 88F6281.
  478. config ARCH_LPC32XX
  479. bool "NXP LPC32XX"
  480. select CLKSRC_MMIO
  481. select CPU_ARM926T
  482. select ARCH_REQUIRE_GPIOLIB
  483. select HAVE_IDE
  484. select ARM_AMBA
  485. select USB_ARCH_HAS_OHCI
  486. select CLKDEV_LOOKUP
  487. select GENERIC_CLOCKEVENTS
  488. help
  489. Support for the NXP LPC32XX family of processors
  490. config ARCH_MV78XX0
  491. bool "Marvell MV78xx0"
  492. select CPU_FEROCEON
  493. select PCI
  494. select ARCH_REQUIRE_GPIOLIB
  495. select GENERIC_CLOCKEVENTS
  496. select PLAT_ORION
  497. help
  498. Support for the following Marvell MV78xx0 series SoCs:
  499. MV781x0, MV782x0.
  500. config ARCH_ORION5X
  501. bool "Marvell Orion"
  502. depends on MMU
  503. select CPU_FEROCEON
  504. select PCI
  505. select ARCH_REQUIRE_GPIOLIB
  506. select GENERIC_CLOCKEVENTS
  507. select PLAT_ORION
  508. help
  509. Support for the following Marvell Orion 5x series SoCs:
  510. Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
  511. Orion-2 (5281), Orion-1-90 (6183).
  512. config ARCH_MMP
  513. bool "Marvell PXA168/910/MMP2"
  514. depends on MMU
  515. select ARCH_REQUIRE_GPIOLIB
  516. select CLKDEV_LOOKUP
  517. select GENERIC_CLOCKEVENTS
  518. select HAVE_SCHED_CLOCK
  519. select TICK_ONESHOT
  520. select PLAT_PXA
  521. select SPARSE_IRQ
  522. select GENERIC_ALLOCATOR
  523. help
  524. Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
  525. config ARCH_KS8695
  526. bool "Micrel/Kendin KS8695"
  527. select CPU_ARM922T
  528. select ARCH_REQUIRE_GPIOLIB
  529. select ARCH_USES_GETTIMEOFFSET
  530. select NEED_MACH_MEMORY_H
  531. help
  532. Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
  533. System-on-Chip devices.
  534. config ARCH_W90X900
  535. bool "Nuvoton W90X900 CPU"
  536. select CPU_ARM926T
  537. select ARCH_REQUIRE_GPIOLIB
  538. select CLKDEV_LOOKUP
  539. select CLKSRC_MMIO
  540. select GENERIC_CLOCKEVENTS
  541. help
  542. Support for Nuvoton (Winbond logic dept.) ARM9 processor,
  543. At present, the w90x900 has been renamed nuc900, regarding
  544. the ARM series product line, you can login the following
  545. link address to know more.
  546. <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
  547. ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
  548. config ARCH_TEGRA
  549. bool "NVIDIA Tegra"
  550. select CLKDEV_LOOKUP
  551. select CLKSRC_MMIO
  552. select GENERIC_CLOCKEVENTS
  553. select GENERIC_GPIO
  554. select HAVE_CLK
  555. select HAVE_SCHED_CLOCK
  556. select HAVE_SMP
  557. select MIGHT_HAVE_CACHE_L2X0
  558. select ARCH_HAS_CPUFREQ
  559. help
  560. This enables support for NVIDIA Tegra based systems (Tegra APX,
  561. Tegra 6xx and Tegra 2 series).
  562. config ARCH_PICOXCELL
  563. bool "Picochip picoXcell"
  564. select ARCH_REQUIRE_GPIOLIB
  565. select ARM_PATCH_PHYS_VIRT
  566. select ARM_VIC
  567. select CPU_V6K
  568. select DW_APB_TIMER
  569. select GENERIC_CLOCKEVENTS
  570. select GENERIC_GPIO
  571. select HAVE_SCHED_CLOCK
  572. select HAVE_TCM
  573. select NO_IOPORT
  574. select SPARSE_IRQ
  575. select USE_OF
  576. help
  577. This enables support for systems based on the Picochip picoXcell
  578. family of Femtocell devices. The picoxcell support requires device tree
  579. for all boards.
  580. config ARCH_PNX4008
  581. bool "Philips Nexperia PNX4008 Mobile"
  582. select CPU_ARM926T
  583. select CLKDEV_LOOKUP
  584. select ARCH_USES_GETTIMEOFFSET
  585. help
  586. This enables support for Philips PNX4008 mobile platform.
  587. config ARCH_PXA
  588. bool "PXA2xx/PXA3xx-based"
  589. depends on MMU
  590. select ARCH_MTD_XIP
  591. select ARCH_HAS_CPUFREQ
  592. select CLKDEV_LOOKUP
  593. select CLKSRC_MMIO
  594. select ARCH_REQUIRE_GPIOLIB
  595. select GENERIC_CLOCKEVENTS
  596. select HAVE_SCHED_CLOCK
  597. select TICK_ONESHOT
  598. select PLAT_PXA
  599. select SPARSE_IRQ
  600. select AUTO_ZRELADDR
  601. select MULTI_IRQ_HANDLER
  602. select ARM_CPU_SUSPEND if PM
  603. select HAVE_IDE
  604. help
  605. Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
  606. config ARCH_MSM
  607. bool "Qualcomm MSM"
  608. select HAVE_CLK
  609. select GENERIC_CLOCKEVENTS
  610. select ARCH_REQUIRE_GPIOLIB
  611. select CLKDEV_LOOKUP
  612. help
  613. Support for Qualcomm MSM/QSD based systems. This runs on the
  614. apps processor of the MSM/QSD and depends on a shared memory
  615. interface to the modem processor which runs the baseband
  616. stack and controls some vital subsystems
  617. (clock and power control, etc).
  618. config ARCH_SHMOBILE
  619. bool "Renesas SH-Mobile / R-Mobile"
  620. select HAVE_CLK
  621. select CLKDEV_LOOKUP
  622. select HAVE_MACH_CLKDEV
  623. select HAVE_SMP
  624. select GENERIC_CLOCKEVENTS
  625. select MIGHT_HAVE_CACHE_L2X0
  626. select NO_IOPORT
  627. select SPARSE_IRQ
  628. select MULTI_IRQ_HANDLER
  629. select PM_GENERIC_DOMAINS if PM
  630. select NEED_MACH_MEMORY_H
  631. help
  632. Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
  633. config ARCH_RPC
  634. bool "RiscPC"
  635. select ARCH_ACORN
  636. select FIQ
  637. select TIMER_ACORN
  638. select ARCH_MAY_HAVE_PC_FDC
  639. select HAVE_PATA_PLATFORM
  640. select ISA_DMA_API
  641. select NO_IOPORT
  642. select ARCH_SPARSEMEM_ENABLE
  643. select ARCH_USES_GETTIMEOFFSET
  644. select HAVE_IDE
  645. select NEED_MACH_MEMORY_H
  646. help
  647. On the Acorn Risc-PC, Linux can support the internal IDE disk and
  648. CD-ROM interface, serial and parallel port, and the floppy drive.
  649. config ARCH_SA1100
  650. bool "SA1100-based"
  651. select CLKSRC_MMIO
  652. select CPU_SA1100
  653. select ISA
  654. select ARCH_SPARSEMEM_ENABLE
  655. select ARCH_MTD_XIP
  656. select ARCH_HAS_CPUFREQ
  657. select CPU_FREQ
  658. select GENERIC_CLOCKEVENTS
  659. select HAVE_CLK
  660. select HAVE_SCHED_CLOCK
  661. select TICK_ONESHOT
  662. select ARCH_REQUIRE_GPIOLIB
  663. select HAVE_IDE
  664. select NEED_MACH_MEMORY_H
  665. help
  666. Support for StrongARM 11x0 based boards.
  667. config ARCH_S3C2410
  668. bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
  669. select GENERIC_GPIO
  670. select ARCH_HAS_CPUFREQ
  671. select HAVE_CLK
  672. select CLKDEV_LOOKUP
  673. select ARCH_USES_GETTIMEOFFSET
  674. select HAVE_S3C2410_I2C if I2C
  675. help
  676. Samsung S3C2410X CPU based systems, such as the Simtec Electronics
  677. BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
  678. the Samsung SMDK2410 development board (and derivatives).
  679. Note, the S3C2416 and the S3C2450 are so close that they even share
  680. the same SoC ID code. This means that there is no separate machine
  681. directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
  682. config ARCH_S3C64XX
  683. bool "Samsung S3C64XX"
  684. select PLAT_SAMSUNG
  685. select CPU_V6
  686. select ARM_VIC
  687. select HAVE_CLK
  688. select HAVE_TCM
  689. select CLKDEV_LOOKUP
  690. select NO_IOPORT
  691. select ARCH_USES_GETTIMEOFFSET
  692. select ARCH_HAS_CPUFREQ
  693. select ARCH_REQUIRE_GPIOLIB
  694. select SAMSUNG_CLKSRC
  695. select SAMSUNG_IRQ_VIC_TIMER
  696. select S3C_GPIO_TRACK
  697. select S3C_DEV_NAND
  698. select USB_ARCH_HAS_OHCI
  699. select SAMSUNG_GPIOLIB_4BIT
  700. select HAVE_S3C2410_I2C if I2C
  701. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  702. help
  703. Samsung S3C64XX series based systems
  704. config ARCH_S5P64X0
  705. bool "Samsung S5P6440 S5P6450"
  706. select CPU_V6
  707. select GENERIC_GPIO
  708. select HAVE_CLK
  709. select CLKDEV_LOOKUP
  710. select CLKSRC_MMIO
  711. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  712. select GENERIC_CLOCKEVENTS
  713. select HAVE_SCHED_CLOCK
  714. select HAVE_S3C2410_I2C if I2C
  715. select HAVE_S3C_RTC if RTC_CLASS
  716. help
  717. Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
  718. SMDK6450.
  719. config ARCH_S5PC100
  720. bool "Samsung S5PC100"
  721. select GENERIC_GPIO
  722. select HAVE_CLK
  723. select CLKDEV_LOOKUP
  724. select CPU_V7
  725. select ARM_L1_CACHE_SHIFT_6
  726. select ARCH_USES_GETTIMEOFFSET
  727. select HAVE_S3C2410_I2C if I2C
  728. select HAVE_S3C_RTC if RTC_CLASS
  729. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  730. help
  731. Samsung S5PC100 series based systems
  732. config ARCH_S5PV210
  733. bool "Samsung S5PV210/S5PC110"
  734. select CPU_V7
  735. select ARCH_SPARSEMEM_ENABLE
  736. select ARCH_HAS_HOLES_MEMORYMODEL
  737. select GENERIC_GPIO
  738. select HAVE_CLK
  739. select CLKDEV_LOOKUP
  740. select CLKSRC_MMIO
  741. select ARM_L1_CACHE_SHIFT_6
  742. select ARCH_HAS_CPUFREQ
  743. select GENERIC_CLOCKEVENTS
  744. select HAVE_SCHED_CLOCK
  745. select HAVE_S3C2410_I2C if I2C
  746. select HAVE_S3C_RTC if RTC_CLASS
  747. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  748. select NEED_MACH_MEMORY_H
  749. help
  750. Samsung S5PV210/S5PC110 series based systems
  751. config ARCH_EXYNOS
  752. bool "SAMSUNG EXYNOS"
  753. select CPU_V7
  754. select ARCH_SPARSEMEM_ENABLE
  755. select ARCH_HAS_HOLES_MEMORYMODEL
  756. select GENERIC_GPIO
  757. select HAVE_CLK
  758. select CLKDEV_LOOKUP
  759. select ARCH_HAS_CPUFREQ
  760. select GENERIC_CLOCKEVENTS
  761. select HAVE_S3C_RTC if RTC_CLASS
  762. select HAVE_S3C2410_I2C if I2C
  763. select HAVE_S3C2410_WATCHDOG if WATCHDOG
  764. select NEED_MACH_MEMORY_H
  765. help
  766. Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
  767. config ARCH_SHARK
  768. bool "Shark"
  769. select CPU_SA110
  770. select ISA
  771. select ISA_DMA
  772. select ZONE_DMA
  773. select PCI
  774. select ARCH_USES_GETTIMEOFFSET
  775. select NEED_MACH_MEMORY_H
  776. help
  777. Support for the StrongARM based Digital DNARD machine, also known
  778. as "Shark" (<http://www.shark-linux.de/shark.html>).
  779. config ARCH_U300
  780. bool "ST-Ericsson U300 Series"
  781. depends on MMU
  782. select CLKSRC_MMIO
  783. select CPU_ARM926T
  784. select HAVE_SCHED_CLOCK
  785. select HAVE_TCM
  786. select ARM_AMBA
  787. select ARM_PATCH_PHYS_VIRT
  788. select ARM_VIC
  789. select GENERIC_CLOCKEVENTS
  790. select CLKDEV_LOOKUP
  791. select HAVE_MACH_CLKDEV
  792. select GENERIC_GPIO
  793. select ARCH_REQUIRE_GPIOLIB
  794. help
  795. Support for ST-Ericsson U300 series mobile platforms.
  796. config ARCH_U8500
  797. bool "ST-Ericsson U8500 Series"
  798. select CPU_V7
  799. select ARM_AMBA
  800. select GENERIC_CLOCKEVENTS
  801. select CLKDEV_LOOKUP
  802. select ARCH_REQUIRE_GPIOLIB
  803. select ARCH_HAS_CPUFREQ
  804. select HAVE_SMP
  805. select MIGHT_HAVE_CACHE_L2X0
  806. help
  807. Support for ST-Ericsson's Ux500 architecture
  808. config ARCH_NOMADIK
  809. bool "STMicroelectronics Nomadik"
  810. select ARM_AMBA
  811. select ARM_VIC
  812. select CPU_ARM926T
  813. select CLKDEV_LOOKUP
  814. select GENERIC_CLOCKEVENTS
  815. select MIGHT_HAVE_CACHE_L2X0
  816. select ARCH_REQUIRE_GPIOLIB
  817. help
  818. Support for the Nomadik platform by ST-Ericsson
  819. config ARCH_DAVINCI
  820. bool "TI DaVinci"
  821. select GENERIC_CLOCKEVENTS
  822. select ARCH_REQUIRE_GPIOLIB
  823. select ZONE_DMA
  824. select HAVE_IDE
  825. select CLKDEV_LOOKUP
  826. select GENERIC_ALLOCATOR
  827. select GENERIC_IRQ_CHIP
  828. select ARCH_HAS_HOLES_MEMORYMODEL
  829. help
  830. Support for TI's DaVinci platform.
  831. config ARCH_OMAP
  832. bool "TI OMAP"
  833. select HAVE_CLK
  834. select ARCH_REQUIRE_GPIOLIB
  835. select ARCH_HAS_CPUFREQ
  836. select CLKSRC_MMIO
  837. select GENERIC_CLOCKEVENTS
  838. select HAVE_SCHED_CLOCK
  839. select ARCH_HAS_HOLES_MEMORYMODEL
  840. help
  841. Support for TI's OMAP platform (OMAP1/2/3/4).
  842. config PLAT_SPEAR
  843. bool "ST SPEAr"
  844. select ARM_AMBA
  845. select ARCH_REQUIRE_GPIOLIB
  846. select CLKDEV_LOOKUP
  847. select CLKSRC_MMIO
  848. select GENERIC_CLOCKEVENTS
  849. select HAVE_CLK
  850. help
  851. Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
  852. config ARCH_VT8500
  853. bool "VIA/WonderMedia 85xx"
  854. select CPU_ARM926T
  855. select GENERIC_GPIO
  856. select ARCH_HAS_CPUFREQ
  857. select GENERIC_CLOCKEVENTS
  858. select ARCH_REQUIRE_GPIOLIB
  859. select HAVE_PWM
  860. help
  861. Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
  862. config ARCH_ZYNQ
  863. bool "Xilinx Zynq ARM Cortex A9 Platform"
  864. select CPU_V7
  865. select GENERIC_CLOCKEVENTS
  866. select CLKDEV_LOOKUP
  867. select ARM_GIC
  868. select ARM_AMBA
  869. select ICST
  870. select MIGHT_HAVE_CACHE_L2X0
  871. select USE_OF
  872. help
  873. Support for Xilinx Zynq ARM Cortex A9 Platform
  874. endchoice
  875. #
  876. # This is sorted alphabetically by mach-* pathname. However, plat-*
  877. # Kconfigs may be included either alphabetically (according to the
  878. # plat- suffix) or along side the corresponding mach-* source.
  879. #
  880. source "arch/arm/mach-at91/Kconfig"
  881. source "arch/arm/mach-bcmring/Kconfig"
  882. source "arch/arm/mach-clps711x/Kconfig"
  883. source "arch/arm/mach-cns3xxx/Kconfig"
  884. source "arch/arm/mach-davinci/Kconfig"
  885. source "arch/arm/mach-dove/Kconfig"
  886. source "arch/arm/mach-ep93xx/Kconfig"
  887. source "arch/arm/mach-footbridge/Kconfig"
  888. source "arch/arm/mach-gemini/Kconfig"
  889. source "arch/arm/mach-h720x/Kconfig"
  890. source "arch/arm/mach-integrator/Kconfig"
  891. source "arch/arm/mach-iop32x/Kconfig"
  892. source "arch/arm/mach-iop33x/Kconfig"
  893. source "arch/arm/mach-iop13xx/Kconfig"
  894. source "arch/arm/mach-ixp4xx/Kconfig"
  895. source "arch/arm/mach-ixp2000/Kconfig"
  896. source "arch/arm/mach-ixp23xx/Kconfig"
  897. source "arch/arm/mach-kirkwood/Kconfig"
  898. source "arch/arm/mach-ks8695/Kconfig"
  899. source "arch/arm/mach-lpc32xx/Kconfig"
  900. source "arch/arm/mach-msm/Kconfig"
  901. source "arch/arm/mach-mv78xx0/Kconfig"
  902. source "arch/arm/plat-mxc/Kconfig"
  903. source "arch/arm/mach-mxs/Kconfig"
  904. source "arch/arm/mach-netx/Kconfig"
  905. source "arch/arm/mach-nomadik/Kconfig"
  906. source "arch/arm/plat-nomadik/Kconfig"
  907. source "arch/arm/plat-omap/Kconfig"
  908. source "arch/arm/mach-omap1/Kconfig"
  909. source "arch/arm/mach-omap2/Kconfig"
  910. source "arch/arm/mach-orion5x/Kconfig"
  911. source "arch/arm/mach-pxa/Kconfig"
  912. source "arch/arm/plat-pxa/Kconfig"
  913. source "arch/arm/mach-mmp/Kconfig"
  914. source "arch/arm/mach-realview/Kconfig"
  915. source "arch/arm/mach-sa1100/Kconfig"
  916. source "arch/arm/plat-samsung/Kconfig"
  917. source "arch/arm/plat-s3c24xx/Kconfig"
  918. source "arch/arm/plat-s5p/Kconfig"
  919. source "arch/arm/plat-spear/Kconfig"
  920. if ARCH_S3C2410
  921. source "arch/arm/mach-s3c2410/Kconfig"
  922. source "arch/arm/mach-s3c2412/Kconfig"
  923. source "arch/arm/mach-s3c2416/Kconfig"
  924. source "arch/arm/mach-s3c2440/Kconfig"
  925. source "arch/arm/mach-s3c2443/Kconfig"
  926. endif
  927. if ARCH_S3C64XX
  928. source "arch/arm/mach-s3c64xx/Kconfig"
  929. endif
  930. source "arch/arm/mach-s5p64x0/Kconfig"
  931. source "arch/arm/mach-s5pc100/Kconfig"
  932. source "arch/arm/mach-s5pv210/Kconfig"
  933. source "arch/arm/mach-exynos/Kconfig"
  934. source "arch/arm/mach-shmobile/Kconfig"
  935. source "arch/arm/mach-tegra/Kconfig"
  936. source "arch/arm/mach-u300/Kconfig"
  937. source "arch/arm/mach-ux500/Kconfig"
  938. source "arch/arm/mach-versatile/Kconfig"
  939. source "arch/arm/mach-vexpress/Kconfig"
  940. source "arch/arm/plat-versatile/Kconfig"
  941. source "arch/arm/mach-vt8500/Kconfig"
  942. source "arch/arm/mach-w90x900/Kconfig"
  943. # Definitions to make life easier
  944. config ARCH_ACORN
  945. bool
  946. config PLAT_IOP
  947. bool
  948. select GENERIC_CLOCKEVENTS
  949. select HAVE_SCHED_CLOCK
  950. config PLAT_ORION
  951. bool
  952. select CLKSRC_MMIO
  953. select GENERIC_IRQ_CHIP
  954. select HAVE_SCHED_CLOCK
  955. config PLAT_PXA
  956. bool
  957. config PLAT_VERSATILE
  958. bool
  959. config ARM_TIMER_SP804
  960. bool
  961. select CLKSRC_MMIO
  962. source arch/arm/mm/Kconfig
  963. config ARM_NR_BANKS
  964. int
  965. default 16 if ARCH_EP93XX
  966. default 8
  967. config IWMMXT
  968. bool "Enable iWMMXt support"
  969. depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
  970. default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
  971. help
  972. Enable support for iWMMXt context switching at run time if
  973. running on a CPU that supports it.
  974. # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
  975. config XSCALE_PMU
  976. bool
  977. depends on CPU_XSCALE && !XSCALE_PMU_TIMER
  978. default y
  979. config CPU_HAS_PMU
  980. depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
  981. (!ARCH_OMAP3 || OMAP3_EMU)
  982. default y
  983. bool
  984. config MULTI_IRQ_HANDLER
  985. bool
  986. help
  987. Allow each machine to specify it's own IRQ handler at run time.
  988. if !MMU
  989. source "arch/arm/Kconfig-nommu"
  990. endif
  991. config ARM_ERRATA_411920
  992. bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
  993. depends on CPU_V6 || CPU_V6K
  994. help
  995. Invalidation of the Instruction Cache operation can
  996. fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
  997. It does not affect the MPCore. This option enables the ARM Ltd.
  998. recommended workaround.
  999. config ARM_ERRATA_430973
  1000. bool "ARM errata: Stale prediction on replaced interworking branch"
  1001. depends on CPU_V7
  1002. help
  1003. This option enables the workaround for the 430973 Cortex-A8
  1004. (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
  1005. interworking branch is replaced with another code sequence at the
  1006. same virtual address, whether due to self-modifying code or virtual
  1007. to physical address re-mapping, Cortex-A8 does not recover from the
  1008. stale interworking branch prediction. This results in Cortex-A8
  1009. executing the new code sequence in the incorrect ARM or Thumb state.
  1010. The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
  1011. and also flushes the branch target cache at every context switch.
  1012. Note that setting specific bits in the ACTLR register may not be
  1013. available in non-secure mode.
  1014. config ARM_ERRATA_458693
  1015. bool "ARM errata: Processor deadlock when a false hazard is created"
  1016. depends on CPU_V7
  1017. help
  1018. This option enables the workaround for the 458693 Cortex-A8 (r2p0)
  1019. erratum. For very specific sequences of memory operations, it is
  1020. possible for a hazard condition intended for a cache line to instead
  1021. be incorrectly associated with a different cache line. This false
  1022. hazard might then cause a processor deadlock. The workaround enables
  1023. the L1 caching of the NEON accesses and disables the PLD instruction
  1024. in the ACTLR register. Note that setting specific bits in the ACTLR
  1025. register may not be available in non-secure mode.
  1026. config ARM_ERRATA_460075
  1027. bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
  1028. depends on CPU_V7
  1029. help
  1030. This option enables the workaround for the 460075 Cortex-A8 (r2p0)
  1031. erratum. Any asynchronous access to the L2 cache may encounter a
  1032. situation in which recent store transactions to the L2 cache are lost
  1033. and overwritten with stale memory contents from external memory. The
  1034. workaround disables the write-allocate mode for the L2 cache via the
  1035. ACTLR register. Note that setting specific bits in the ACTLR register
  1036. may not be available in non-secure mode.
  1037. config ARM_ERRATA_742230
  1038. bool "ARM errata: DMB operation may be faulty"
  1039. depends on CPU_V7 && SMP
  1040. help
  1041. This option enables the workaround for the 742230 Cortex-A9
  1042. (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
  1043. between two write operations may not ensure the correct visibility
  1044. ordering of the two writes. This workaround sets a specific bit in
  1045. the diagnostic register of the Cortex-A9 which causes the DMB
  1046. instruction to behave as a DSB, ensuring the correct behaviour of
  1047. the two writes.
  1048. config ARM_ERRATA_742231
  1049. bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
  1050. depends on CPU_V7 && SMP
  1051. help
  1052. This option enables the workaround for the 742231 Cortex-A9
  1053. (r2p0..r2p2) erratum. Under certain conditions, specific to the
  1054. Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
  1055. accessing some data located in the same cache line, may get corrupted
  1056. data due to bad handling of the address hazard when the line gets
  1057. replaced from one of the CPUs at the same time as another CPU is
  1058. accessing it. This workaround sets specific bits in the diagnostic
  1059. register of the Cortex-A9 which reduces the linefill issuing
  1060. capabilities of the processor.
  1061. config PL310_ERRATA_588369
  1062. bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
  1063. depends on CACHE_L2X0
  1064. help
  1065. The PL310 L2 cache controller implements three types of Clean &
  1066. Invalidate maintenance operations: by Physical Address
  1067. (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
  1068. They are architecturally defined to behave as the execution of a
  1069. clean operation followed immediately by an invalidate operation,
  1070. both performing to the same memory location. This functionality
  1071. is not correctly implemented in PL310 as clean lines are not
  1072. invalidated as a result of these operations.
  1073. config ARM_ERRATA_720789
  1074. bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
  1075. depends on CPU_V7
  1076. help
  1077. This option enables the workaround for the 720789 Cortex-A9 (prior to
  1078. r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
  1079. broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
  1080. As a consequence of this erratum, some TLB entries which should be
  1081. invalidated are not, resulting in an incoherency in the system page
  1082. tables. The workaround changes the TLB flushing routines to invalidate
  1083. entries regardless of the ASID.
  1084. config PL310_ERRATA_727915
  1085. bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
  1086. depends on CACHE_L2X0
  1087. help
  1088. PL310 implements the Clean & Invalidate by Way L2 cache maintenance
  1089. operation (offset 0x7FC). This operation runs in background so that
  1090. PL310 can handle normal accesses while it is in progress. Under very
  1091. rare circumstances, due to this erratum, write data can be lost when
  1092. PL310 treats a cacheable write transaction during a Clean &
  1093. Invalidate by Way operation.
  1094. config ARM_ERRATA_743622
  1095. bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
  1096. depends on CPU_V7
  1097. help
  1098. This option enables the workaround for the 743622 Cortex-A9
  1099. (r2p0..r2p2) erratum. Under very rare conditions, a faulty
  1100. optimisation in the Cortex-A9 Store Buffer may lead to data
  1101. corruption. This workaround sets a specific bit in the diagnostic
  1102. register of the Cortex-A9 which disables the Store Buffer
  1103. optimisation, preventing the defect from occurring. This has no
  1104. visible impact on the overall performance or power consumption of the
  1105. processor.
  1106. config ARM_ERRATA_751472
  1107. bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
  1108. depends on CPU_V7
  1109. help
  1110. This option enables the workaround for the 751472 Cortex-A9 (prior
  1111. to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
  1112. completion of a following broadcasted operation if the second
  1113. operation is received by a CPU before the ICIALLUIS has completed,
  1114. potentially leading to corrupted entries in the cache or TLB.
  1115. config PL310_ERRATA_753970
  1116. bool "PL310 errata: cache sync operation may be faulty"
  1117. depends on CACHE_PL310
  1118. help
  1119. This option enables the workaround for the 753970 PL310 (r3p0) erratum.
  1120. Under some condition the effect of cache sync operation on
  1121. the store buffer still remains when the operation completes.
  1122. This means that the store buffer is always asked to drain and
  1123. this prevents it from merging any further writes. The workaround
  1124. is to replace the normal offset of cache sync operation (0x730)
  1125. by another offset targeting an unmapped PL310 register 0x740.
  1126. This has the same effect as the cache sync operation: store buffer
  1127. drain and waiting for all buffers empty.
  1128. config ARM_ERRATA_754322
  1129. bool "ARM errata: possible faulty MMU translations following an ASID switch"
  1130. depends on CPU_V7
  1131. help
  1132. This option enables the workaround for the 754322 Cortex-A9 (r2p*,
  1133. r3p*) erratum. A speculative memory access may cause a page table walk
  1134. which starts prior to an ASID switch but completes afterwards. This
  1135. can populate the micro-TLB with a stale entry which may be hit with
  1136. the new ASID. This workaround places two dsb instructions in the mm
  1137. switching code so that no page table walks can cross the ASID switch.
  1138. config ARM_ERRATA_754327
  1139. bool "ARM errata: no automatic Store Buffer drain"
  1140. depends on CPU_V7 && SMP
  1141. help
  1142. This option enables the workaround for the 754327 Cortex-A9 (prior to
  1143. r2p0) erratum. The Store Buffer does not have any automatic draining
  1144. mechanism and therefore a livelock may occur if an external agent
  1145. continuously polls a memory location waiting to observe an update.
  1146. This workaround defines cpu_relax() as smp_mb(), preventing correctly
  1147. written polling loops from denying visibility of updates to memory.
  1148. config ARM_ERRATA_364296
  1149. bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
  1150. depends on CPU_V6 && !SMP
  1151. help
  1152. This options enables the workaround for the 364296 ARM1136
  1153. r0p2 erratum (possible cache data corruption with
  1154. hit-under-miss enabled). It sets the undocumented bit 31 in
  1155. the auxiliary control register and the FI bit in the control
  1156. register, thus disabling hit-under-miss without putting the
  1157. processor into full low interrupt latency mode. ARM11MPCore
  1158. is not affected.
  1159. config ARM_ERRATA_764369
  1160. bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
  1161. depends on CPU_V7 && SMP
  1162. help
  1163. This option enables the workaround for erratum 764369
  1164. affecting Cortex-A9 MPCore with two or more processors (all
  1165. current revisions). Under certain timing circumstances, a data
  1166. cache line maintenance operation by MVA targeting an Inner
  1167. Shareable memory region may fail to proceed up to either the
  1168. Point of Coherency or to the Point of Unification of the
  1169. system. This workaround adds a DSB instruction before the
  1170. relevant cache maintenance functions and sets a specific bit
  1171. in the diagnostic control register of the SCU.
  1172. config PL310_ERRATA_769419
  1173. bool "PL310 errata: no automatic Store Buffer drain"
  1174. depends on CACHE_L2X0
  1175. help
  1176. On revisions of the PL310 prior to r3p2, the Store Buffer does
  1177. not automatically drain. This can cause normal, non-cacheable
  1178. writes to be retained when the memory system is idle, leading
  1179. to suboptimal I/O performance for drivers using coherent DMA.
  1180. This option adds a write barrier to the cpu_idle loop so that,
  1181. on systems with an outer cache, the store buffer is drained
  1182. explicitly.
  1183. endmenu
  1184. source "arch/arm/common/Kconfig"
  1185. menu "Bus support"
  1186. config ARM_AMBA
  1187. bool
  1188. config ISA
  1189. bool
  1190. help
  1191. Find out whether you have ISA slots on your motherboard. ISA is the
  1192. name of a bus system, i.e. the way the CPU talks to the other stuff
  1193. inside your box. Other bus systems are PCI, EISA, MicroChannel
  1194. (MCA) or VESA. ISA is an older system, now being displaced by PCI;
  1195. newer boards don't support it. If you have ISA, say Y, otherwise N.
  1196. # Select ISA DMA controller support
  1197. config ISA_DMA
  1198. bool
  1199. select ISA_DMA_API
  1200. # Select ISA DMA interface
  1201. config ISA_DMA_API
  1202. bool
  1203. config PCI
  1204. bool "PCI support" if MIGHT_HAVE_PCI
  1205. help
  1206. Find out whether you have a PCI motherboard. PCI is the name of a
  1207. bus system, i.e. the way the CPU talks to the other stuff inside
  1208. your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
  1209. VESA. If you have PCI, say Y, otherwise N.
  1210. config PCI_DOMAINS
  1211. bool
  1212. depends on PCI
  1213. config PCI_NANOENGINE
  1214. bool "BSE nanoEngine PCI support"
  1215. depends on SA1100_NANOENGINE
  1216. help
  1217. Enable PCI on the BSE nanoEngine board.
  1218. config PCI_SYSCALL
  1219. def_bool PCI
  1220. # Select the host bridge type
  1221. config PCI_HOST_VIA82C505
  1222. bool
  1223. depends on PCI && ARCH_SHARK
  1224. default y
  1225. config PCI_HOST_ITE8152
  1226. bool
  1227. depends on PCI && MACH_ARMCORE
  1228. default y
  1229. select DMABOUNCE
  1230. source "drivers/pci/Kconfig"
  1231. source "drivers/pcmcia/Kconfig"
  1232. endmenu
  1233. menu "Kernel Features"
  1234. source "kernel/time/Kconfig"
  1235. config HAVE_SMP
  1236. bool
  1237. help
  1238. This option should be selected by machines which have an SMP-
  1239. capable CPU.
  1240. The only effect of this option is to make the SMP-related
  1241. options available to the user for configuration.
  1242. config SMP
  1243. bool "Symmetric Multi-Processing"
  1244. depends on CPU_V6K || CPU_V7
  1245. depends on GENERIC_CLOCKEVENTS
  1246. depends on HAVE_SMP
  1247. depends on MMU
  1248. select USE_GENERIC_SMP_HELPERS
  1249. select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
  1250. help
  1251. This enables support for systems with more than one CPU. If you have
  1252. a system with only one CPU, like most personal computers, say N. If
  1253. you have a system with more than one CPU, say Y.
  1254. If you say N here, the kernel will run on single and multiprocessor
  1255. machines, but will use only one CPU of a multiprocessor machine. If
  1256. you say Y here, the kernel will run on many, but not all, single
  1257. processor machines. On a single processor machine, the kernel will
  1258. run faster if you say N here.
  1259. See also <file:Documentation/x86/i386/IO-APIC.txt>,
  1260. <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
  1261. <http://tldp.org/HOWTO/SMP-HOWTO.html>.
  1262. If you don't know what to do here, say N.
  1263. config SMP_ON_UP
  1264. bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
  1265. depends on EXPERIMENTAL
  1266. depends on SMP && !XIP_KERNEL
  1267. default y
  1268. help
  1269. SMP kernels contain instructions which fail on non-SMP processors.
  1270. Enabling this option allows the kernel to modify itself to make
  1271. these instructions safe. Disabling it allows about 1K of space
  1272. savings.
  1273. If you don't know what to do here, say Y.
  1274. config ARM_CPU_TOPOLOGY
  1275. bool "Support cpu topology definition"
  1276. depends on SMP && CPU_V7
  1277. default y
  1278. help
  1279. Support ARM cpu topology definition. The MPIDR register defines
  1280. affinity between processors which is then used to describe the cpu
  1281. topology of an ARM System.
  1282. config SCHED_MC
  1283. bool "Multi-core scheduler support"
  1284. depends on ARM_CPU_TOPOLOGY
  1285. help
  1286. Multi-core scheduler support improves the CPU scheduler's decision
  1287. making when dealing with multi-core CPU chips at a cost of slightly
  1288. increased overhead in some places. If unsure say N here.
  1289. config SCHED_SMT
  1290. bool "SMT scheduler support"
  1291. depends on ARM_CPU_TOPOLOGY
  1292. help
  1293. Improves the CPU scheduler's decision making when dealing with
  1294. MultiThreading at a cost of slightly increased overhead in some
  1295. places. If unsure say N here.
  1296. config HAVE_ARM_SCU
  1297. bool
  1298. help
  1299. This option enables support for the ARM system coherency unit
  1300. config HAVE_ARM_TWD
  1301. bool
  1302. depends on SMP
  1303. select TICK_ONESHOT
  1304. help
  1305. This options enables support for the ARM timer and watchdog unit
  1306. choice
  1307. prompt "Memory split"
  1308. default VMSPLIT_3G
  1309. help
  1310. Select the desired split between kernel and user memory.
  1311. If you are not absolutely sure what you are doing, leave this
  1312. option alone!
  1313. config VMSPLIT_3G
  1314. bool "3G/1G user/kernel split"
  1315. config VMSPLIT_2G
  1316. bool "2G/2G user/kernel split"
  1317. config VMSPLIT_1G
  1318. bool "1G/3G user/kernel split"
  1319. endchoice
  1320. config PAGE_OFFSET
  1321. hex
  1322. default 0x40000000 if VMSPLIT_1G
  1323. default 0x80000000 if VMSPLIT_2G
  1324. default 0xC0000000
  1325. config NR_CPUS
  1326. int "Maximum number of CPUs (2-32)"
  1327. range 2 32
  1328. depends on SMP
  1329. default "4"
  1330. config HOTPLUG_CPU
  1331. bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
  1332. depends on SMP && HOTPLUG && EXPERIMENTAL
  1333. help
  1334. Say Y here to experiment with turning CPUs off and on. CPUs
  1335. can be controlled through /sys/devices/system/cpu.
  1336. config LOCAL_TIMERS
  1337. bool "Use local timer interrupts"
  1338. depends on SMP
  1339. default y
  1340. select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
  1341. help
  1342. Enable support for local timers on SMP platforms, rather then the
  1343. legacy IPI broadcast method. Local timers allows the system
  1344. accounting to be spread across the timer interval, preventing a
  1345. "thundering herd" at every timer tick.
  1346. config ARCH_NR_GPIO
  1347. int
  1348. default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
  1349. default 350 if ARCH_U8500
  1350. default 0
  1351. help
  1352. Maximum number of GPIOs in the system.
  1353. If unsure, leave the default value.
  1354. source kernel/Kconfig.preempt
  1355. config HZ
  1356. int
  1357. default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
  1358. ARCH_S5PV210 || ARCH_EXYNOS4
  1359. default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
  1360. default AT91_TIMER_HZ if ARCH_AT91
  1361. default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
  1362. default 100
  1363. config THUMB2_KERNEL
  1364. bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
  1365. depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
  1366. select AEABI
  1367. select ARM_ASM_UNIFIED
  1368. select ARM_UNWIND
  1369. help
  1370. By enabling this option, the kernel will be compiled in
  1371. Thumb-2 mode. A compiler/assembler that understand the unified
  1372. ARM-Thumb syntax is needed.
  1373. If unsure, say N.
  1374. config THUMB2_AVOID_R_ARM_THM_JUMP11
  1375. bool "Work around buggy Thumb-2 short branch relocations in gas"
  1376. depends on THUMB2_KERNEL && MODULES
  1377. default y
  1378. help
  1379. Various binutils versions can resolve Thumb-2 branches to
  1380. locally-defined, preemptible global symbols as short-range "b.n"
  1381. branch instructions.
  1382. This is a problem, because there's no guarantee the final
  1383. destination of the symbol, or any candidate locations for a
  1384. trampoline, are within range of the branch. For this reason, the
  1385. kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
  1386. relocation in modules at all, and it makes little sense to add
  1387. support.
  1388. The symptom is that the kernel fails with an "unsupported
  1389. relocation" error when loading some modules.
  1390. Until fixed tools are available, passing
  1391. -fno-optimize-sibling-calls to gcc should prevent gcc generating
  1392. code which hits this problem, at the cost of a bit of extra runtime
  1393. stack usage in some cases.
  1394. The problem is described in more detail at:
  1395. https://bugs.launchpad.net/binutils-linaro/+bug/725126
  1396. Only Thumb-2 kernels are affected.
  1397. Unless you are sure your tools don't have this problem, say Y.
  1398. config ARM_ASM_UNIFIED
  1399. bool
  1400. config AEABI
  1401. bool "Use the ARM EABI to compile the kernel"
  1402. help
  1403. This option allows for the kernel to be compiled using the latest
  1404. ARM ABI (aka EABI). This is only useful if you are using a user
  1405. space environment that is also compiled with EABI.
  1406. Since there are major incompatibilities between the legacy ABI and
  1407. EABI, especially with regard to structure member alignment, this
  1408. option also changes the kernel syscall calling convention to
  1409. disambiguate both ABIs and allow for backward compatibility support
  1410. (selected with CONFIG_OABI_COMPAT).
  1411. To use this you need GCC version 4.0.0 or later.
  1412. config OABI_COMPAT
  1413. bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
  1414. depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
  1415. default y
  1416. help
  1417. This option preserves the old syscall interface along with the
  1418. new (ARM EABI) one. It also provides a compatibility layer to
  1419. intercept syscalls that have structure arguments which layout
  1420. in memory differs between the legacy ABI and the new ARM EABI
  1421. (only for non "thumb" binaries). This option adds a tiny
  1422. overhead to all syscalls and produces a slightly larger kernel.
  1423. If you know you'll be using only pure EABI user space then you
  1424. can say N here. If this option is not selected and you attempt
  1425. to execute a legacy ABI binary then the result will be
  1426. UNPREDICTABLE (in fact it can be predicted that it won't work
  1427. at all). If in doubt say Y.
  1428. config ARCH_HAS_HOLES_MEMORYMODEL
  1429. bool
  1430. config ARCH_SPARSEMEM_ENABLE
  1431. bool
  1432. config ARCH_SPARSEMEM_DEFAULT
  1433. def_bool ARCH_SPARSEMEM_ENABLE
  1434. config ARCH_SELECT_MEMORY_MODEL
  1435. def_bool ARCH_SPARSEMEM_ENABLE
  1436. config HAVE_ARCH_PFN_VALID
  1437. def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
  1438. config HIGHMEM
  1439. bool "High Memory Support"
  1440. depends on MMU
  1441. help
  1442. The address space of ARM processors is only 4 Gigabytes large
  1443. and it has to accommodate user address space, kernel address
  1444. space as well as some memory mapped IO. That means that, if you
  1445. have a large amount of physical memory and/or IO, not all of the
  1446. memory can be "permanently mapped" by the kernel. The physical
  1447. memory that is not permanently mapped is called "high memory".
  1448. Depending on the selected kernel/user memory split, minimum
  1449. vmalloc space and actual amount of RAM, you may not need this
  1450. option which should result in a slightly faster kernel.
  1451. If unsure, say n.
  1452. config HIGHPTE
  1453. bool "Allocate 2nd-level pagetables from highmem"
  1454. depends on HIGHMEM
  1455. config HW_PERF_EVENTS
  1456. bool "Enable hardware performance counter support for perf events"
  1457. depends on PERF_EVENTS && CPU_HAS_PMU
  1458. default y
  1459. help
  1460. Enable hardware performance counter support for perf events. If
  1461. disabled, perf events will use software events only.
  1462. source "mm/Kconfig"
  1463. config FORCE_MAX_ZONEORDER
  1464. int "Maximum zone order" if ARCH_SHMOBILE
  1465. range 11 64 if ARCH_SHMOBILE
  1466. default "9" if SA1111
  1467. default "11"
  1468. help
  1469. The kernel memory allocator divides physically contiguous memory
  1470. blocks into "zones", where each zone is a power of two number of
  1471. pages. This option selects the largest power of two that the kernel
  1472. keeps in the memory allocator. If you need to allocate very large
  1473. blocks of physically contiguous memory, then you may need to
  1474. increase this value.
  1475. This config option is actually maximum order plus one. For example,
  1476. a value of 11 means that the largest free memory block is 2^10 pages.
  1477. config LEDS
  1478. bool "Timer and CPU usage LEDs"
  1479. depends on ARCH_CDB89712 || ARCH_EBSA110 || \
  1480. ARCH_EBSA285 || ARCH_INTEGRATOR || \
  1481. ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
  1482. ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
  1483. ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
  1484. ARCH_AT91 || ARCH_DAVINCI || \
  1485. ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
  1486. help
  1487. If you say Y here, the LEDs on your machine will be used
  1488. to provide useful information about your current system status.
  1489. If you are compiling a kernel for a NetWinder or EBSA-285, you will
  1490. be able to select which LEDs are active using the options below. If
  1491. you are compiling a kernel for the EBSA-110 or the LART however, the
  1492. red LED will simply flash regularly to indicate that the system is
  1493. still functional. It is safe to say Y here if you have a CATS
  1494. system, but the driver will do nothing.
  1495. config LEDS_TIMER
  1496. bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
  1497. OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
  1498. || MACH_OMAP_PERSEUS2
  1499. depends on LEDS
  1500. depends on !GENERIC_CLOCKEVENTS
  1501. default y if ARCH_EBSA110
  1502. help
  1503. If you say Y here, one of the system LEDs (the green one on the
  1504. NetWinder, the amber one on the EBSA285, or the red one on the LART)
  1505. will flash regularly to indicate that the system is still
  1506. operational. This is mainly useful to kernel hackers who are
  1507. debugging unstable kernels.
  1508. The LART uses the same LED for both Timer LED and CPU usage LED
  1509. functions. You may choose to use both, but the Timer LED function
  1510. will overrule the CPU usage LED.
  1511. config LEDS_CPU
  1512. bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
  1513. !ARCH_OMAP) \
  1514. || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
  1515. || MACH_OMAP_PERSEUS2
  1516. depends on LEDS
  1517. help
  1518. If you say Y here, the red LED will be used to give a good real
  1519. time indication of CPU usage, by lighting whenever the idle task
  1520. is not currently executing.
  1521. The LART uses the same LED for both Timer LED and CPU usage LED
  1522. functions. You may choose to use both, but the Timer LED function
  1523. will overrule the CPU usage LED.
  1524. config ALIGNMENT_TRAP
  1525. bool
  1526. depends on CPU_CP15_MMU
  1527. default y if !ARCH_EBSA110
  1528. select HAVE_PROC_CPU if PROC_FS
  1529. help
  1530. ARM processors cannot fetch/store information which is not
  1531. naturally aligned on the bus, i.e., a 4 byte fetch must start at an
  1532. address divisible by 4. On 32-bit ARM processors, these non-aligned
  1533. fetch/store instructions will be emulated in software if you say
  1534. here, which has a severe performance impact. This is necessary for
  1535. correct operation of some network protocols. With an IP-only
  1536. configuration it is safe to say N, otherwise say Y.
  1537. config UACCESS_WITH_MEMCPY
  1538. bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
  1539. depends on MMU && EXPERIMENTAL
  1540. default y if CPU_FEROCEON
  1541. help
  1542. Implement faster copy_to_user and clear_user methods for CPU
  1543. cores where a 8-word STM instruction give significantly higher
  1544. memory write throughput than a sequence of individual 32bit stores.
  1545. A possible side effect is a slight increase in scheduling latency
  1546. between threads sharing the same address space if they invoke
  1547. such copy operations with large buffers.
  1548. However, if the CPU data cache is using a write-allocate mode,
  1549. this option is unlikely to provide any performance gain.
  1550. config SECCOMP
  1551. bool
  1552. prompt "Enable seccomp to safely compute untrusted bytecode"
  1553. ---help---
  1554. This kernel feature is useful for number crunching applications
  1555. that may need to compute untrusted bytecode during their
  1556. execution. By using pipes or other transports made available to
  1557. the process as file descriptors supporting the read/write
  1558. syscalls, it's possible to isolate those applications in
  1559. their own address space using seccomp. Once seccomp is
  1560. enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
  1561. and the task is only allowed to execute a few safe syscalls
  1562. defined by each seccomp mode.
  1563. config CC_STACKPROTECTOR
  1564. bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
  1565. depends on EXPERIMENTAL
  1566. help
  1567. This option turns on the -fstack-protector GCC feature. This
  1568. feature puts, at the beginning of functions, a canary value on
  1569. the stack just before the return address, and validates
  1570. the value just before actually returning. Stack based buffer
  1571. overflows (that need to overwrite this return address) now also
  1572. overwrite the canary, which gets detected and the attack is then
  1573. neutralized via a kernel panic.
  1574. This feature requires gcc version 4.2 or above.
  1575. config DEPRECATED_PARAM_STRUCT
  1576. bool "Provide old way to pass kernel parameters"
  1577. help
  1578. This was deprecated in 2001 and announced to live on for 5 years.
  1579. Some old boot loaders still use this way.
  1580. endmenu
  1581. menu "Boot options"
  1582. config USE_OF
  1583. bool "Flattened Device Tree support"
  1584. select OF
  1585. select OF_EARLY_FLATTREE
  1586. select IRQ_DOMAIN
  1587. help
  1588. Include support for flattened device tree machine descriptions.
  1589. # Compressed boot loader in ROM. Yes, we really want to ask about
  1590. # TEXT and BSS so we preserve their values in the config files.
  1591. config ZBOOT_ROM_TEXT
  1592. hex "Compressed ROM boot loader base address"
  1593. default "0"
  1594. help
  1595. The physical address at which the ROM-able zImage is to be
  1596. placed in the target. Platforms which normally make use of
  1597. ROM-able zImage formats normally set this to a suitable
  1598. value in their defconfig file.
  1599. If ZBOOT_ROM is not enabled, this has no effect.
  1600. config ZBOOT_ROM_BSS
  1601. hex "Compressed ROM boot loader BSS address"
  1602. default "0"
  1603. help
  1604. The base address of an area of read/write memory in the target
  1605. for the ROM-able zImage which must be available while the
  1606. decompressor is running. It must be large enough to hold the
  1607. entire decompressed kernel plus an additional 128 KiB.
  1608. Platforms which normally make use of ROM-able zImage formats
  1609. normally set this to a suitable value in their defconfig file.
  1610. If ZBOOT_ROM is not enabled, this has no effect.
  1611. config ZBOOT_ROM
  1612. bool "Compressed boot loader in ROM/flash"
  1613. depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
  1614. help
  1615. Say Y here if you intend to execute your compressed kernel image
  1616. (zImage) directly from ROM or flash. If unsure, say N.
  1617. choice
  1618. prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
  1619. depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
  1620. default ZBOOT_ROM_NONE
  1621. help
  1622. Include experimental SD/MMC loading code in the ROM-able zImage.
  1623. With this enabled it is possible to write the the ROM-able zImage
  1624. kernel image to an MMC or SD card and boot the kernel straight
  1625. from the reset vector. At reset the processor Mask ROM will load
  1626. the first part of the the ROM-able zImage which in turn loads the
  1627. rest the kernel image to RAM.
  1628. config ZBOOT_ROM_NONE
  1629. bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
  1630. help
  1631. Do not load image from SD or MMC
  1632. config ZBOOT_ROM_MMCIF
  1633. bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
  1634. help
  1635. Load image from MMCIF hardware block.
  1636. config ZBOOT_ROM_SH_MOBILE_SDHI
  1637. bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
  1638. help
  1639. Load image from SDHI hardware block
  1640. endchoice
  1641. config ARM_APPENDED_DTB
  1642. bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
  1643. depends on OF && !ZBOOT_ROM && EXPERIMENTAL
  1644. help
  1645. With this option, the boot code will look for a device tree binary
  1646. (DTB) appended to zImage
  1647. (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
  1648. This is meant as a backward compatibility convenience for those
  1649. systems with a bootloader that can't be upgraded to accommodate
  1650. the documented boot protocol using a device tree.
  1651. Beware that there is very little in terms of protection against
  1652. this option being confused by leftover garbage in memory that might
  1653. look like a DTB header after a reboot if no actual DTB is appended
  1654. to zImage. Do not leave this option active in a production kernel
  1655. if you don't intend to always append a DTB. Proper passing of the
  1656. location into r2 of a bootloader provided DTB is always preferable
  1657. to this option.
  1658. config ARM_ATAG_DTB_COMPAT
  1659. bool "Supplement the appended DTB with traditional ATAG information"
  1660. depends on ARM_APPENDED_DTB
  1661. help
  1662. Some old bootloaders can't be updated to a DTB capable one, yet
  1663. they provide ATAGs with memory configuration, the ramdisk address,
  1664. the kernel cmdline string, etc. Such information is dynamically
  1665. provided by the bootloader and can't always be stored in a static
  1666. DTB. To allow a device tree enabled kernel to be used with such
  1667. bootloaders, this option allows zImage to extract the information
  1668. from the ATAG list and store it at run time into the appended DTB.
  1669. config CMDLINE
  1670. string "Default kernel command string"
  1671. default ""
  1672. help
  1673. On some architectures (EBSA110 and CATS), there is currently no way
  1674. for the boot loader to pass arguments to the kernel. For these
  1675. architectures, you should supply some command-line options at build
  1676. time by entering them here. As a minimum, you should specify the
  1677. memory size and the root device (e.g., mem=64M root=/dev/nfs).
  1678. choice
  1679. prompt "Kernel command line type" if CMDLINE != ""
  1680. default CMDLINE_FROM_BOOTLOADER
  1681. config CMDLINE_FROM_BOOTLOADER
  1682. bool "Use bootloader kernel arguments if available"
  1683. help
  1684. Uses the command-line options passed by the boot loader. If
  1685. the boot loader doesn't provide any, the default kernel command
  1686. string provided in CMDLINE will be used.
  1687. config CMDLINE_EXTEND
  1688. bool "Extend bootloader kernel arguments"
  1689. help
  1690. The command-line arguments provided by the boot loader will be
  1691. appended to the default kernel command string.
  1692. config CMDLINE_FORCE
  1693. bool "Always use the default kernel command string"
  1694. help
  1695. Always use the default kernel command string, even if the boot
  1696. loader passes other arguments to the kernel.
  1697. This is useful if you cannot or don't want to change the
  1698. command-line options your boot loader passes to the kernel.
  1699. endchoice
  1700. config XIP_KERNEL
  1701. bool "Kernel Execute-In-Place from ROM"
  1702. depends on !ZBOOT_ROM && !ARM_LPAE
  1703. help
  1704. Execute-In-Place allows the kernel to run from non-volatile storage
  1705. directly addressable by the CPU, such as NOR flash. This saves RAM
  1706. space since the text section of the kernel is not loaded from flash
  1707. to RAM. Read-write sections, such as the data section and stack,
  1708. are still copied to RAM. The XIP kernel is not compressed since
  1709. it has to run directly from flash, so it will take more space to
  1710. store it. The flash address used to link the kernel object files,
  1711. and for storing it, is configuration dependent. Therefore, if you
  1712. say Y here, you must know the proper physical address where to
  1713. store the kernel image depending on your own flash memory usage.
  1714. Also note that the make target becomes "make xipImage" rather than
  1715. "make zImage" or "make Image". The final kernel binary to put in
  1716. ROM memory will be arch/arm/boot/xipImage.
  1717. If unsure, say N.
  1718. config XIP_PHYS_ADDR
  1719. hex "XIP Kernel Physical Location"
  1720. depends on XIP_KERNEL
  1721. default "0x00080000"
  1722. help
  1723. This is the physical address in your flash memory the kernel will
  1724. be linked for and stored to. This address is dependent on your
  1725. own flash usage.
  1726. config KEXEC
  1727. bool "Kexec system call (EXPERIMENTAL)"
  1728. depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
  1729. help
  1730. kexec is a system call that implements the ability to shutdown your
  1731. current kernel, and to start another kernel. It is like a reboot
  1732. but it is independent of the system firmware. And like a reboot
  1733. you can start any kernel with it, not just Linux.
  1734. It is an ongoing process to be certain the hardware in a machine
  1735. is properly shutdown, so do not be surprised if this code does not
  1736. initially work for you. It may help to enable device hotplugging
  1737. support.
  1738. config ATAGS_PROC
  1739. bool "Export atags in procfs"
  1740. depends on KEXEC
  1741. default y
  1742. help
  1743. Should the atags used to boot the kernel be exported in an "atags"
  1744. file in procfs. Useful with kexec.
  1745. config CRASH_DUMP
  1746. bool "Build kdump crash kernel (EXPERIMENTAL)"
  1747. depends on EXPERIMENTAL
  1748. help
  1749. Generate crash dump after being started by kexec. This should
  1750. be normally only set in special crash dump kernels which are
  1751. loaded in the main kernel with kexec-tools into a specially
  1752. reserved region and then later executed after a crash by
  1753. kdump/kexec. The crash dump kernel must be compiled to a
  1754. memory address not used by the main kernel
  1755. For more details see Documentation/kdump/kdump.txt
  1756. config AUTO_ZRELADDR
  1757. bool "Auto calculation of the decompressed kernel image address"
  1758. depends on !ZBOOT_ROM && !ARCH_U300
  1759. help
  1760. ZRELADDR is the physical address where the decompressed kernel
  1761. image will be placed. If AUTO_ZRELADDR is selected, the address
  1762. will be determined at run-time by masking the current IP with
  1763. 0xf8000000. This assumes the zImage being placed in the first 128MB
  1764. from start of memory.
  1765. endmenu
  1766. menu "CPU Power Management"
  1767. if ARCH_HAS_CPUFREQ
  1768. source "drivers/cpufreq/Kconfig"
  1769. config CPU_FREQ_IMX
  1770. tristate "CPUfreq driver for i.MX CPUs"
  1771. depends on ARCH_MXC && CPU_FREQ
  1772. help
  1773. This enables the CPUfreq driver for i.MX CPUs.
  1774. config CPU_FREQ_SA1100
  1775. bool
  1776. config CPU_FREQ_SA1110
  1777. bool
  1778. config CPU_FREQ_INTEGRATOR
  1779. tristate "CPUfreq driver for ARM Integrator CPUs"
  1780. depends on ARCH_INTEGRATOR && CPU_FREQ
  1781. default y
  1782. help
  1783. This enables the CPUfreq driver for ARM Integrator CPUs.
  1784. For details, take a look at <file:Documentation/cpu-freq>.
  1785. If in doubt, say Y.
  1786. config CPU_FREQ_PXA
  1787. bool
  1788. depends on CPU_FREQ && ARCH_PXA && PXA25x
  1789. default y
  1790. select CPU_FREQ_TABLE
  1791. select CPU_FREQ_DEFAULT_GOV_USERSPACE
  1792. config CPU_FREQ_S3C
  1793. bool
  1794. help
  1795. Internal configuration node for common cpufreq on Samsung SoC
  1796. config CPU_FREQ_S3C24XX
  1797. bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
  1798. depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
  1799. select CPU_FREQ_S3C
  1800. help
  1801. This enables the CPUfreq driver for the Samsung S3C24XX family
  1802. of CPUs.
  1803. For details, take a look at <file:Documentation/cpu-freq>.
  1804. If in doubt, say N.
  1805. config CPU_FREQ_S3C24XX_PLL
  1806. bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
  1807. depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
  1808. help
  1809. Compile in support for changing the PLL frequency from the
  1810. S3C24XX series CPUfreq driver. The PLL takes time to settle
  1811. after a frequency change, so by default it is not enabled.
  1812. This also means that the PLL tables for the selected CPU(s) will
  1813. be built which may increase the size of the kernel image.
  1814. config CPU_FREQ_S3C24XX_DEBUG
  1815. bool "Debug CPUfreq Samsung driver core"
  1816. depends on CPU_FREQ_S3C24XX
  1817. help
  1818. Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
  1819. config CPU_FREQ_S3C24XX_IODEBUG
  1820. bool "Debug CPUfreq Samsung driver IO timing"
  1821. depends on CPU_FREQ_S3C24XX
  1822. help
  1823. Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
  1824. config CPU_FREQ_S3C24XX_DEBUGFS
  1825. bool "Export debugfs for CPUFreq"
  1826. depends on CPU_FREQ_S3C24XX && DEBUG_FS
  1827. help
  1828. Export status information via debugfs.
  1829. endif
  1830. source "drivers/cpuidle/Kconfig"
  1831. endmenu
  1832. menu "Floating point emulation"
  1833. comment "At least one emulation must be selected"
  1834. config FPE_NWFPE
  1835. bool "NWFPE math emulation"
  1836. depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
  1837. ---help---
  1838. Say Y to include the NWFPE floating point emulator in the kernel.
  1839. This is necessary to run most binaries. Linux does not currently
  1840. support floating point hardware so you need to say Y here even if
  1841. your machine has an FPA or floating point co-processor podule.
  1842. You may say N here if you are going to load the Acorn FPEmulator
  1843. early in the bootup.
  1844. config FPE_NWFPE_XP
  1845. bool "Support extended precision"
  1846. depends on FPE_NWFPE
  1847. help
  1848. Say Y to include 80-bit support in the kernel floating-point
  1849. emulator. Otherwise, only 32 and 64-bit support is compiled in.
  1850. Note that gcc does not generate 80-bit operations by default,
  1851. so in most cases this option only enlarges the size of the
  1852. floating point emulator without any good reason.
  1853. You almost surely want to say N here.
  1854. config FPE_FASTFPE
  1855. bool "FastFPE math emulation (EXPERIMENTAL)"
  1856. depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
  1857. ---help---
  1858. Say Y here to include the FAST floating point emulator in the kernel.
  1859. This is an experimental much faster emulator which now also has full
  1860. precision for the mantissa. It does not support any exceptions.
  1861. It is very simple, and approximately 3-6 times faster than NWFPE.
  1862. It should be sufficient for most programs. It may be not suitable
  1863. for scientific calculations, but you have to check this for yourself.
  1864. If you do not feel you need a faster FP emulation you should better
  1865. choose NWFPE.
  1866. config VFP
  1867. bool "VFP-format floating point maths"
  1868. depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
  1869. help
  1870. Say Y to include VFP support code in the kernel. This is needed
  1871. if your hardware includes a VFP unit.
  1872. Please see <file:Documentation/arm/VFP/release-notes.txt> for
  1873. release notes and additional status information.
  1874. Say N if your target does not have VFP hardware.
  1875. config VFPv3
  1876. bool
  1877. depends on VFP
  1878. default y if CPU_V7
  1879. config NEON
  1880. bool "Advanced SIMD (NEON) Extension support"
  1881. depends on VFPv3 && CPU_V7
  1882. help
  1883. Say Y to include support code for NEON, the ARMv7 Advanced SIMD
  1884. Extension.
  1885. endmenu
  1886. menu "Userspace binary formats"
  1887. source "fs/Kconfig.binfmt"
  1888. config ARTHUR
  1889. tristate "RISC OS personality"
  1890. depends on !AEABI
  1891. help
  1892. Say Y here to include the kernel code necessary if you want to run
  1893. Acorn RISC OS/Arthur binaries under Linux. This code is still very
  1894. experimental; if this sounds frightening, say N and sleep in peace.
  1895. You can also say M here to compile this support as a module (which
  1896. will be called arthur).
  1897. endmenu
  1898. menu "Power management options"
  1899. source "kernel/power/Kconfig"
  1900. config ARCH_SUSPEND_POSSIBLE
  1901. depends on !ARCH_S5PC100
  1902. depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
  1903. CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
  1904. def_bool y
  1905. config ARM_CPU_SUSPEND
  1906. def_bool PM_SLEEP
  1907. endmenu
  1908. source "net/Kconfig"
  1909. source "drivers/Kconfig"
  1910. source "fs/Kconfig"
  1911. source "arch/arm/Kconfig.debug"
  1912. source "security/Kconfig"
  1913. source "crypto/Kconfig"
  1914. source "lib/Kconfig"