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mach-ep93xx
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ep93xx-regs.h

ep93xx-regs.h 5.0 KB
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  1. /*
    2. 

  2.  * arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
    3. 

  3.  */
    4. 

  4. 

  5. #ifndef __ASM_ARCH_EP93XX_REGS_H
    6. 

  6. #define __ASM_ARCH_EP93XX_REGS_H
    7. 

  7. 

  8. /*
    9. 

  9.  * EP93xx linux memory map:
    10. 

  10.  *
    11. 

  11.  * virt		phys		size
    12. 

  12.  * fe800000			5M		per-platform mappings
    13. 

  13.  * fed00000	80800000	2M		APB
    14. 

  14.  * fef00000	80000000	1M		AHB
    15. 

  15.  */
    16. 

  16. 

  17. #define EP93XX_AHB_PHYS_BASE		0x80000000
    18. 

  18. #define EP93XX_AHB_VIRT_BASE		0xfef00000
    19. 

  19. #define EP93XX_AHB_SIZE			0x00100000
    20. 

  20. 

  21. #define EP93XX_AHB_PHYS(x)		(EP93XX_AHB_PHYS_BASE + (x))
    22. 

  22. #define EP93XX_AHB_IOMEM(x)		IOMEM(EP93XX_AHB_VIRT_BASE + (x))
    23. 

  23. 

  24. #define EP93XX_APB_PHYS_BASE		0x80800000
    25. 

  25. #define EP93XX_APB_VIRT_BASE		0xfed00000
    26. 

  26. #define EP93XX_APB_SIZE			0x00200000
    27. 

  27. 

  28. #define EP93XX_APB_PHYS(x)		(EP93XX_APB_PHYS_BASE + (x))
    29. 

  29. #define EP93XX_APB_IOMEM(x)		IOMEM(EP93XX_APB_VIRT_BASE + (x))
    30. 

  30. 

  31. /* APB UARTs */
    32. 

  32. #define EP93XX_UART1_PHYS_BASE		EP93XX_APB_PHYS(0x000c0000)
    33. 

  33. #define EP93XX_UART1_BASE		EP93XX_APB_IOMEM(0x000c0000)
    34. 

  34. 

  35. #define EP93XX_UART2_PHYS_BASE		EP93XX_APB_PHYS(0x000d0000)
    36. 

  36. #define EP93XX_UART2_BASE		EP93XX_APB_IOMEM(0x000d0000)
    37. 

  37. 

  38. #define EP93XX_UART3_PHYS_BASE		EP93XX_APB_PHYS(0x000e0000)
    39. 

  39. #define EP93XX_UART3_BASE		EP93XX_APB_IOMEM(0x000e0000)
    40. 

  40. 

  41. #define EP93XX_SYSCON_BASE		EP93XX_APB_IOMEM(0x00130000)
    42. 

  42. #define EP93XX_SYSCON_REG(x)		(EP93XX_SYSCON_BASE + (x))
    43. 

  43. #define EP93XX_SYSCON_POWER_STATE	EP93XX_SYSCON_REG(0x00)
    44. 

  44. #define EP93XX_SYSCON_PWRCNT		EP93XX_SYSCON_REG(0x04)
    45. 

  45. #define EP93XX_SYSCON_PWRCNT_FIR_EN	(1<<31)
    46. 

  46. #define EP93XX_SYSCON_PWRCNT_UARTBAUD	(1<<29)
    47. 

  47. #define EP93XX_SYSCON_PWRCNT_USH_EN	(1<<28)
    48. 

  48. #define EP93XX_SYSCON_PWRCNT_DMA_M2M1	(1<<27)
    49. 

  49. #define EP93XX_SYSCON_PWRCNT_DMA_M2M0	(1<<26)
    50. 

  50. #define EP93XX_SYSCON_PWRCNT_DMA_M2P8	(1<<25)
    51. 

  51. #define EP93XX_SYSCON_PWRCNT_DMA_M2P9	(1<<24)
    52. 

  52. #define EP93XX_SYSCON_PWRCNT_DMA_M2P6	(1<<23)
    53. 

  53. #define EP93XX_SYSCON_PWRCNT_DMA_M2P7	(1<<22)
    54. 

  54. #define EP93XX_SYSCON_PWRCNT_DMA_M2P4	(1<<21)
    55. 

  55. #define EP93XX_SYSCON_PWRCNT_DMA_M2P5	(1<<20)
    56. 

  56. #define EP93XX_SYSCON_PWRCNT_DMA_M2P2	(1<<19)
    57. 

  57. #define EP93XX_SYSCON_PWRCNT_DMA_M2P3	(1<<18)
    58. 

  58. #define EP93XX_SYSCON_PWRCNT_DMA_M2P0	(1<<17)
    59. 

  59. #define EP93XX_SYSCON_PWRCNT_DMA_M2P1	(1<<16)
    60. 

  60. #define EP93XX_SYSCON_HALT		EP93XX_SYSCON_REG(0x08)
    61. 

  61. #define EP93XX_SYSCON_STANDBY		EP93XX_SYSCON_REG(0x0c)
    62. 

  62. #define EP93XX_SYSCON_CLKSET1		EP93XX_SYSCON_REG(0x20)
    63. 

  63. #define EP93XX_SYSCON_CLKSET1_NBYP1	(1<<23)
    64. 

  64. #define EP93XX_SYSCON_CLKSET2		EP93XX_SYSCON_REG(0x24)
    65. 

  65. #define EP93XX_SYSCON_CLKSET2_NBYP2	(1<<19)
    66. 

  66. #define EP93XX_SYSCON_CLKSET2_PLL2_EN	(1<<18)
    67. 

  67. #define EP93XX_SYSCON_DEVCFG		EP93XX_SYSCON_REG(0x80)
    68. 

  68. #define EP93XX_SYSCON_DEVCFG_SWRST	(1<<31)
    69. 

  69. #define EP93XX_SYSCON_DEVCFG_D1ONG	(1<<30)
    70. 

  70. #define EP93XX_SYSCON_DEVCFG_D0ONG	(1<<29)
    71. 

  71. #define EP93XX_SYSCON_DEVCFG_IONU2	(1<<28)
    72. 

  72. #define EP93XX_SYSCON_DEVCFG_GONK	(1<<27)
    73. 

  73. #define EP93XX_SYSCON_DEVCFG_TONG	(1<<26)
    74. 

  74. #define EP93XX_SYSCON_DEVCFG_MONG	(1<<25)
    75. 

  75. #define EP93XX_SYSCON_DEVCFG_U3EN	(1<<24)
    76. 

  76. #define EP93XX_SYSCON_DEVCFG_CPENA	(1<<23)
    77. 

  77. #define EP93XX_SYSCON_DEVCFG_A2ONG	(1<<22)
    78. 

  78. #define EP93XX_SYSCON_DEVCFG_A1ONG	(1<<21)
    79. 

  79. #define EP93XX_SYSCON_DEVCFG_U2EN	(1<<20)
    80. 

  80. #define EP93XX_SYSCON_DEVCFG_EXVC	(1<<19)
    81. 

  81. #define EP93XX_SYSCON_DEVCFG_U1EN	(1<<18)
    82. 

  82. #define EP93XX_SYSCON_DEVCFG_TIN	(1<<17)
    83. 

  83. #define EP93XX_SYSCON_DEVCFG_HC3IN	(1<<15)
    84. 

  84. #define EP93XX_SYSCON_DEVCFG_HC3EN	(1<<14)
    85. 

  85. #define EP93XX_SYSCON_DEVCFG_HC1IN	(1<<13)
    86. 

  86. #define EP93XX_SYSCON_DEVCFG_HC1EN	(1<<12)
    87. 

  87. #define EP93XX_SYSCON_DEVCFG_HONIDE	(1<<11)
    88. 

  88. #define EP93XX_SYSCON_DEVCFG_GONIDE	(1<<10)
    89. 

  89. #define EP93XX_SYSCON_DEVCFG_PONG	(1<<9)
    90. 

  90. #define EP93XX_SYSCON_DEVCFG_EONIDE	(1<<8)
    91. 

  91. #define EP93XX_SYSCON_DEVCFG_I2SONSSP	(1<<7)
    92. 

  92. #define EP93XX_SYSCON_DEVCFG_I2SONAC97	(1<<6)
    93. 

  93. #define EP93XX_SYSCON_DEVCFG_RASONP3	(1<<4)
    94. 

  94. #define EP93XX_SYSCON_DEVCFG_RAS	(1<<3)
    95. 

  95. #define EP93XX_SYSCON_DEVCFG_ADCPD	(1<<2)
    96. 

  96. #define EP93XX_SYSCON_DEVCFG_KEYS	(1<<1)
    97. 

  97. #define EP93XX_SYSCON_DEVCFG_SHENA	(1<<0)
    98. 

  98. #define EP93XX_SYSCON_VIDCLKDIV		EP93XX_SYSCON_REG(0x84)
    99. 

  99. #define EP93XX_SYSCON_CLKDIV_ENABLE	(1<<15)
    100. 

  100. #define EP93XX_SYSCON_CLKDIV_ESEL	(1<<14)
    101. 

  101. #define EP93XX_SYSCON_CLKDIV_PSEL	(1<<13)
    102. 

  102. #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT	8
    103. 

  103. #define EP93XX_SYSCON_I2SCLKDIV		EP93XX_SYSCON_REG(0x8c)
    104. 

  104. #define EP93XX_SYSCON_I2SCLKDIV_SENA	(1<<31)
    105. 

  105. #define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)
    106. 

  106. #define EP93XX_SYSCON_I2SCLKDIV_SPOL	(1<<19)
    107. 

  107. #define EP93XX_I2SCLKDIV_SDIV		(1 << 16)
    108. 

  108. #define EP93XX_I2SCLKDIV_LRDIV32	(0 << 17)
    109. 

  109. #define EP93XX_I2SCLKDIV_LRDIV64	(1 << 17)
    110. 

  110. #define EP93XX_I2SCLKDIV_LRDIV128 	(2 << 17)
    111. 

  111. #define EP93XX_I2SCLKDIV_LRDIV_MASK 	(3 << 17)
    112. 

  112. #define EP93XX_SYSCON_KEYTCHCLKDIV	EP93XX_SYSCON_REG(0x90)
    113. 

  113. #define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN	(1<<31)
    114. 

  114. #define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV	(1<<16)
    115. 

  115. #define EP93XX_SYSCON_KEYTCHCLKDIV_KEN	(1<<15)
    116. 

  116. #define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV	(1<<0)
    117. 

  117. #define EP93XX_SYSCON_SYSCFG		EP93XX_SYSCON_REG(0x9c)
    118. 

  118. #define EP93XX_SYSCON_SYSCFG_REV_MASK	(0xf0000000)
    119. 

  119. #define EP93XX_SYSCON_SYSCFG_REV_SHIFT	(28)
    120. 

  120. #define EP93XX_SYSCON_SYSCFG_SBOOT	(1<<8)
    121. 

  121. #define EP93XX_SYSCON_SYSCFG_LCSN7	(1<<7)
    122. 

  122. #define EP93XX_SYSCON_SYSCFG_LCSN6	(1<<6)
    123. 

  123. #define EP93XX_SYSCON_SYSCFG_LASDO	(1<<5)
    124. 

  124. #define EP93XX_SYSCON_SYSCFG_LEEDA	(1<<4)
    125. 

  125. #define EP93XX_SYSCON_SYSCFG_LEECLK	(1<<3)
    126. 

  126. #define EP93XX_SYSCON_SYSCFG_LCSN2	(1<<1)
    127. 

  127. #define EP93XX_SYSCON_SYSCFG_LCSN1	(1<<0)
    128. 

  128. #define EP93XX_SYSCON_SWLOCK		EP93XX_SYSCON_REG(0xc0)
    129. 

  129. 

  130. #endif
    131.