fimc-lite.c 44 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714
  1. /*
  2. * Samsung EXYNOS FIMC-LITE (camera host interface) driver
  3. *
  4. * Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd.
  5. * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
  12. #include <linux/bug.h>
  13. #include <linux/clk.h>
  14. #include <linux/device.h>
  15. #include <linux/errno.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/kernel.h>
  18. #include <linux/list.h>
  19. #include <linux/module.h>
  20. #include <linux/of.h>
  21. #include <linux/types.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/pm_runtime.h>
  24. #include <linux/slab.h>
  25. #include <linux/videodev2.h>
  26. #include <media/v4l2-device.h>
  27. #include <media/v4l2-ioctl.h>
  28. #include <media/v4l2-mem2mem.h>
  29. #include <media/videobuf2-core.h>
  30. #include <media/videobuf2-dma-contig.h>
  31. #include <media/s5p_fimc.h>
  32. #include "common.h"
  33. #include "fimc-core.h"
  34. #include "fimc-lite.h"
  35. #include "fimc-lite-reg.h"
  36. static int debug;
  37. module_param(debug, int, 0644);
  38. static const struct fimc_fmt fimc_lite_formats[] = {
  39. {
  40. .name = "YUV 4:2:2 packed, YCbYCr",
  41. .fourcc = V4L2_PIX_FMT_YUYV,
  42. .depth = { 16 },
  43. .color = FIMC_FMT_YCBYCR422,
  44. .memplanes = 1,
  45. .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
  46. .flags = FMT_FLAGS_YUV,
  47. }, {
  48. .name = "YUV 4:2:2 packed, CbYCrY",
  49. .fourcc = V4L2_PIX_FMT_UYVY,
  50. .depth = { 16 },
  51. .color = FIMC_FMT_CBYCRY422,
  52. .memplanes = 1,
  53. .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
  54. .flags = FMT_FLAGS_YUV,
  55. }, {
  56. .name = "YUV 4:2:2 packed, CrYCbY",
  57. .fourcc = V4L2_PIX_FMT_VYUY,
  58. .depth = { 16 },
  59. .color = FIMC_FMT_CRYCBY422,
  60. .memplanes = 1,
  61. .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
  62. .flags = FMT_FLAGS_YUV,
  63. }, {
  64. .name = "YUV 4:2:2 packed, YCrYCb",
  65. .fourcc = V4L2_PIX_FMT_YVYU,
  66. .depth = { 16 },
  67. .color = FIMC_FMT_YCRYCB422,
  68. .memplanes = 1,
  69. .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
  70. .flags = FMT_FLAGS_YUV,
  71. }, {
  72. .name = "RAW8 (GRBG)",
  73. .fourcc = V4L2_PIX_FMT_SGRBG8,
  74. .depth = { 8 },
  75. .color = FIMC_FMT_RAW8,
  76. .memplanes = 1,
  77. .mbus_code = V4L2_MBUS_FMT_SGRBG8_1X8,
  78. .flags = FMT_FLAGS_RAW_BAYER,
  79. }, {
  80. .name = "RAW10 (GRBG)",
  81. .fourcc = V4L2_PIX_FMT_SGRBG10,
  82. .depth = { 10 },
  83. .color = FIMC_FMT_RAW10,
  84. .memplanes = 1,
  85. .mbus_code = V4L2_MBUS_FMT_SGRBG10_1X10,
  86. .flags = FMT_FLAGS_RAW_BAYER,
  87. }, {
  88. .name = "RAW12 (GRBG)",
  89. .fourcc = V4L2_PIX_FMT_SGRBG12,
  90. .depth = { 12 },
  91. .color = FIMC_FMT_RAW12,
  92. .memplanes = 1,
  93. .mbus_code = V4L2_MBUS_FMT_SGRBG12_1X12,
  94. .flags = FMT_FLAGS_RAW_BAYER,
  95. },
  96. };
  97. /**
  98. * fimc_lite_find_format - lookup fimc color format by fourcc or media bus code
  99. * @pixelformat: fourcc to match, ignored if null
  100. * @mbus_code: media bus code to match, ignored if null
  101. * @mask: the color format flags to match
  102. * @index: index to the fimc_lite_formats array, ignored if negative
  103. */
  104. static const struct fimc_fmt *fimc_lite_find_format(const u32 *pixelformat,
  105. const u32 *mbus_code, unsigned int mask, int index)
  106. {
  107. const struct fimc_fmt *fmt, *def_fmt = NULL;
  108. unsigned int i;
  109. int id = 0;
  110. if (index >= (int)ARRAY_SIZE(fimc_lite_formats))
  111. return NULL;
  112. for (i = 0; i < ARRAY_SIZE(fimc_lite_formats); ++i) {
  113. fmt = &fimc_lite_formats[i];
  114. if (mask && !(fmt->flags & mask))
  115. continue;
  116. if (pixelformat && fmt->fourcc == *pixelformat)
  117. return fmt;
  118. if (mbus_code && fmt->mbus_code == *mbus_code)
  119. return fmt;
  120. if (index == id)
  121. def_fmt = fmt;
  122. id++;
  123. }
  124. return def_fmt;
  125. }
  126. static int fimc_lite_hw_init(struct fimc_lite *fimc, bool isp_output)
  127. {
  128. struct fimc_source_info *si;
  129. unsigned long flags;
  130. if (fimc->sensor == NULL)
  131. return -ENXIO;
  132. if (fimc->inp_frame.fmt == NULL || fimc->out_frame.fmt == NULL)
  133. return -EINVAL;
  134. /* Get sensor configuration data from the sensor subdev */
  135. si = v4l2_get_subdev_hostdata(fimc->sensor);
  136. if (!si)
  137. return -EINVAL;
  138. spin_lock_irqsave(&fimc->slock, flags);
  139. flite_hw_set_camera_bus(fimc, si);
  140. flite_hw_set_source_format(fimc, &fimc->inp_frame);
  141. flite_hw_set_window_offset(fimc, &fimc->inp_frame);
  142. flite_hw_set_dma_buf_mask(fimc, 0);
  143. flite_hw_set_output_dma(fimc, &fimc->out_frame, !isp_output);
  144. flite_hw_set_interrupt_mask(fimc);
  145. flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
  146. if (debug > 0)
  147. flite_hw_dump_regs(fimc, __func__);
  148. spin_unlock_irqrestore(&fimc->slock, flags);
  149. return 0;
  150. }
  151. /*
  152. * Reinitialize the driver so it is ready to start the streaming again.
  153. * Set fimc->state to indicate stream off and the hardware shut down state.
  154. * If not suspending (@suspend is false), return any buffers to videobuf2.
  155. * Otherwise put any owned buffers onto the pending buffers queue, so they
  156. * can be re-spun when the device is being resumed. Also perform FIMC
  157. * software reset and disable streaming on the whole pipeline if required.
  158. */
  159. static int fimc_lite_reinit(struct fimc_lite *fimc, bool suspend)
  160. {
  161. struct flite_buffer *buf;
  162. unsigned long flags;
  163. bool streaming;
  164. spin_lock_irqsave(&fimc->slock, flags);
  165. streaming = fimc->state & (1 << ST_SENSOR_STREAM);
  166. fimc->state &= ~(1 << ST_FLITE_RUN | 1 << ST_FLITE_OFF |
  167. 1 << ST_FLITE_STREAM | 1 << ST_SENSOR_STREAM);
  168. if (suspend)
  169. fimc->state |= (1 << ST_FLITE_SUSPENDED);
  170. else
  171. fimc->state &= ~(1 << ST_FLITE_PENDING |
  172. 1 << ST_FLITE_SUSPENDED);
  173. /* Release unused buffers */
  174. while (!suspend && !list_empty(&fimc->pending_buf_q)) {
  175. buf = fimc_lite_pending_queue_pop(fimc);
  176. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  177. }
  178. /* If suspending put unused buffers onto pending queue */
  179. while (!list_empty(&fimc->active_buf_q)) {
  180. buf = fimc_lite_active_queue_pop(fimc);
  181. if (suspend)
  182. fimc_lite_pending_queue_add(fimc, buf);
  183. else
  184. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  185. }
  186. spin_unlock_irqrestore(&fimc->slock, flags);
  187. flite_hw_reset(fimc);
  188. if (!streaming)
  189. return 0;
  190. return fimc_pipeline_call(&fimc->ve, set_stream, 0);
  191. }
  192. static int fimc_lite_stop_capture(struct fimc_lite *fimc, bool suspend)
  193. {
  194. unsigned long flags;
  195. if (!fimc_lite_active(fimc))
  196. return 0;
  197. spin_lock_irqsave(&fimc->slock, flags);
  198. set_bit(ST_FLITE_OFF, &fimc->state);
  199. flite_hw_capture_stop(fimc);
  200. spin_unlock_irqrestore(&fimc->slock, flags);
  201. wait_event_timeout(fimc->irq_queue,
  202. !test_bit(ST_FLITE_OFF, &fimc->state),
  203. (2*HZ/10)); /* 200 ms */
  204. return fimc_lite_reinit(fimc, suspend);
  205. }
  206. /* Must be called with fimc.slock spinlock held. */
  207. static void fimc_lite_config_update(struct fimc_lite *fimc)
  208. {
  209. flite_hw_set_window_offset(fimc, &fimc->inp_frame);
  210. flite_hw_set_dma_window(fimc, &fimc->out_frame);
  211. flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
  212. clear_bit(ST_FLITE_CONFIG, &fimc->state);
  213. }
  214. static irqreturn_t flite_irq_handler(int irq, void *priv)
  215. {
  216. struct fimc_lite *fimc = priv;
  217. struct flite_buffer *vbuf;
  218. unsigned long flags;
  219. struct timeval *tv;
  220. struct timespec ts;
  221. u32 intsrc;
  222. spin_lock_irqsave(&fimc->slock, flags);
  223. intsrc = flite_hw_get_interrupt_source(fimc);
  224. flite_hw_clear_pending_irq(fimc);
  225. if (test_and_clear_bit(ST_FLITE_OFF, &fimc->state)) {
  226. wake_up(&fimc->irq_queue);
  227. goto done;
  228. }
  229. if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW) {
  230. clear_bit(ST_FLITE_RUN, &fimc->state);
  231. fimc->events.data_overflow++;
  232. }
  233. if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND) {
  234. flite_hw_clear_last_capture_end(fimc);
  235. clear_bit(ST_FLITE_STREAM, &fimc->state);
  236. wake_up(&fimc->irq_queue);
  237. }
  238. if (atomic_read(&fimc->out_path) != FIMC_IO_DMA)
  239. goto done;
  240. if ((intsrc & FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART) &&
  241. test_bit(ST_FLITE_RUN, &fimc->state) &&
  242. !list_empty(&fimc->pending_buf_q)) {
  243. vbuf = fimc_lite_pending_queue_pop(fimc);
  244. flite_hw_set_dma_buffer(fimc, vbuf);
  245. fimc_lite_active_queue_add(fimc, vbuf);
  246. }
  247. if ((intsrc & FLITE_REG_CISTATUS_IRQ_SRC_FRMEND) &&
  248. test_bit(ST_FLITE_RUN, &fimc->state) &&
  249. !list_empty(&fimc->active_buf_q)) {
  250. vbuf = fimc_lite_active_queue_pop(fimc);
  251. ktime_get_ts(&ts);
  252. tv = &vbuf->vb.v4l2_buf.timestamp;
  253. tv->tv_sec = ts.tv_sec;
  254. tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
  255. vbuf->vb.v4l2_buf.sequence = fimc->frame_count++;
  256. flite_hw_mask_dma_buffer(fimc, vbuf->index);
  257. vb2_buffer_done(&vbuf->vb, VB2_BUF_STATE_DONE);
  258. }
  259. if (test_bit(ST_FLITE_CONFIG, &fimc->state))
  260. fimc_lite_config_update(fimc);
  261. if (list_empty(&fimc->pending_buf_q)) {
  262. flite_hw_capture_stop(fimc);
  263. clear_bit(ST_FLITE_STREAM, &fimc->state);
  264. }
  265. done:
  266. set_bit(ST_FLITE_RUN, &fimc->state);
  267. spin_unlock_irqrestore(&fimc->slock, flags);
  268. return IRQ_HANDLED;
  269. }
  270. static int start_streaming(struct vb2_queue *q, unsigned int count)
  271. {
  272. struct fimc_lite *fimc = q->drv_priv;
  273. unsigned long flags;
  274. int ret;
  275. spin_lock_irqsave(&fimc->slock, flags);
  276. fimc->buf_index = 0;
  277. fimc->frame_count = 0;
  278. spin_unlock_irqrestore(&fimc->slock, flags);
  279. ret = fimc_lite_hw_init(fimc, false);
  280. if (ret) {
  281. fimc_lite_reinit(fimc, false);
  282. return ret;
  283. }
  284. set_bit(ST_FLITE_PENDING, &fimc->state);
  285. if (!list_empty(&fimc->active_buf_q) &&
  286. !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
  287. flite_hw_capture_start(fimc);
  288. if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
  289. fimc_pipeline_call(&fimc->ve, set_stream, 1);
  290. }
  291. if (debug > 0)
  292. flite_hw_dump_regs(fimc, __func__);
  293. return 0;
  294. }
  295. static int stop_streaming(struct vb2_queue *q)
  296. {
  297. struct fimc_lite *fimc = q->drv_priv;
  298. if (!fimc_lite_active(fimc))
  299. return -EINVAL;
  300. return fimc_lite_stop_capture(fimc, false);
  301. }
  302. static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *pfmt,
  303. unsigned int *num_buffers, unsigned int *num_planes,
  304. unsigned int sizes[], void *allocators[])
  305. {
  306. const struct v4l2_pix_format_mplane *pixm = NULL;
  307. struct fimc_lite *fimc = vq->drv_priv;
  308. struct flite_frame *frame = &fimc->out_frame;
  309. const struct fimc_fmt *fmt = frame->fmt;
  310. unsigned long wh;
  311. int i;
  312. if (pfmt) {
  313. pixm = &pfmt->fmt.pix_mp;
  314. fmt = fimc_lite_find_format(&pixm->pixelformat, NULL, 0, -1);
  315. wh = pixm->width * pixm->height;
  316. } else {
  317. wh = frame->f_width * frame->f_height;
  318. }
  319. if (fmt == NULL)
  320. return -EINVAL;
  321. *num_planes = fmt->memplanes;
  322. for (i = 0; i < fmt->memplanes; i++) {
  323. unsigned int size = (wh * fmt->depth[i]) / 8;
  324. if (pixm)
  325. sizes[i] = max(size, pixm->plane_fmt[i].sizeimage);
  326. else
  327. sizes[i] = size;
  328. allocators[i] = fimc->alloc_ctx;
  329. }
  330. return 0;
  331. }
  332. static int buffer_prepare(struct vb2_buffer *vb)
  333. {
  334. struct vb2_queue *vq = vb->vb2_queue;
  335. struct fimc_lite *fimc = vq->drv_priv;
  336. int i;
  337. if (fimc->out_frame.fmt == NULL)
  338. return -EINVAL;
  339. for (i = 0; i < fimc->out_frame.fmt->memplanes; i++) {
  340. unsigned long size = fimc->payload[i];
  341. if (vb2_plane_size(vb, i) < size) {
  342. v4l2_err(&fimc->ve.vdev,
  343. "User buffer too small (%ld < %ld)\n",
  344. vb2_plane_size(vb, i), size);
  345. return -EINVAL;
  346. }
  347. vb2_set_plane_payload(vb, i, size);
  348. }
  349. return 0;
  350. }
  351. static void buffer_queue(struct vb2_buffer *vb)
  352. {
  353. struct flite_buffer *buf
  354. = container_of(vb, struct flite_buffer, vb);
  355. struct fimc_lite *fimc = vb2_get_drv_priv(vb->vb2_queue);
  356. unsigned long flags;
  357. spin_lock_irqsave(&fimc->slock, flags);
  358. buf->paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
  359. buf->index = fimc->buf_index++;
  360. if (fimc->buf_index >= fimc->reqbufs_count)
  361. fimc->buf_index = 0;
  362. if (!test_bit(ST_FLITE_SUSPENDED, &fimc->state) &&
  363. !test_bit(ST_FLITE_STREAM, &fimc->state) &&
  364. list_empty(&fimc->active_buf_q)) {
  365. flite_hw_set_dma_buffer(fimc, buf);
  366. fimc_lite_active_queue_add(fimc, buf);
  367. } else {
  368. fimc_lite_pending_queue_add(fimc, buf);
  369. }
  370. if (vb2_is_streaming(&fimc->vb_queue) &&
  371. !list_empty(&fimc->pending_buf_q) &&
  372. !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
  373. flite_hw_capture_start(fimc);
  374. spin_unlock_irqrestore(&fimc->slock, flags);
  375. if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
  376. fimc_pipeline_call(&fimc->ve, set_stream, 1);
  377. return;
  378. }
  379. spin_unlock_irqrestore(&fimc->slock, flags);
  380. }
  381. static const struct vb2_ops fimc_lite_qops = {
  382. .queue_setup = queue_setup,
  383. .buf_prepare = buffer_prepare,
  384. .buf_queue = buffer_queue,
  385. .wait_prepare = vb2_ops_wait_prepare,
  386. .wait_finish = vb2_ops_wait_finish,
  387. .start_streaming = start_streaming,
  388. .stop_streaming = stop_streaming,
  389. };
  390. static void fimc_lite_clear_event_counters(struct fimc_lite *fimc)
  391. {
  392. unsigned long flags;
  393. spin_lock_irqsave(&fimc->slock, flags);
  394. memset(&fimc->events, 0, sizeof(fimc->events));
  395. spin_unlock_irqrestore(&fimc->slock, flags);
  396. }
  397. static int fimc_lite_open(struct file *file)
  398. {
  399. struct fimc_lite *fimc = video_drvdata(file);
  400. struct media_entity *me = &fimc->ve.vdev.entity;
  401. int ret;
  402. mutex_lock(&fimc->lock);
  403. if (atomic_read(&fimc->out_path) != FIMC_IO_DMA) {
  404. ret = -EBUSY;
  405. goto unlock;
  406. }
  407. set_bit(ST_FLITE_IN_USE, &fimc->state);
  408. ret = pm_runtime_get_sync(&fimc->pdev->dev);
  409. if (ret < 0)
  410. goto unlock;
  411. ret = v4l2_fh_open(file);
  412. if (ret < 0)
  413. goto err_pm;
  414. if (!v4l2_fh_is_singular_file(file) ||
  415. atomic_read(&fimc->out_path) != FIMC_IO_DMA)
  416. goto unlock;
  417. mutex_lock(&me->parent->graph_mutex);
  418. ret = fimc_pipeline_call(&fimc->ve, open, me, true);
  419. /* Mark video pipeline ending at this video node as in use. */
  420. if (ret == 0)
  421. me->use_count++;
  422. mutex_unlock(&me->parent->graph_mutex);
  423. if (!ret) {
  424. fimc_lite_clear_event_counters(fimc);
  425. goto unlock;
  426. }
  427. v4l2_fh_release(file);
  428. err_pm:
  429. pm_runtime_put_sync(&fimc->pdev->dev);
  430. clear_bit(ST_FLITE_IN_USE, &fimc->state);
  431. unlock:
  432. mutex_unlock(&fimc->lock);
  433. return ret;
  434. }
  435. static int fimc_lite_release(struct file *file)
  436. {
  437. struct fimc_lite *fimc = video_drvdata(file);
  438. struct media_entity *entity = &fimc->ve.vdev.entity;
  439. mutex_lock(&fimc->lock);
  440. if (v4l2_fh_is_singular_file(file) &&
  441. atomic_read(&fimc->out_path) == FIMC_IO_DMA) {
  442. if (fimc->streaming) {
  443. media_entity_pipeline_stop(entity);
  444. fimc->streaming = false;
  445. }
  446. fimc_lite_stop_capture(fimc, false);
  447. fimc_pipeline_call(&fimc->ve, close);
  448. clear_bit(ST_FLITE_IN_USE, &fimc->state);
  449. mutex_lock(&entity->parent->graph_mutex);
  450. entity->use_count--;
  451. mutex_unlock(&entity->parent->graph_mutex);
  452. }
  453. vb2_fop_release(file);
  454. pm_runtime_put(&fimc->pdev->dev);
  455. clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
  456. mutex_unlock(&fimc->lock);
  457. return 0;
  458. }
  459. static const struct v4l2_file_operations fimc_lite_fops = {
  460. .owner = THIS_MODULE,
  461. .open = fimc_lite_open,
  462. .release = fimc_lite_release,
  463. .poll = vb2_fop_poll,
  464. .unlocked_ioctl = video_ioctl2,
  465. .mmap = vb2_fop_mmap,
  466. };
  467. /*
  468. * Format and crop negotiation helpers
  469. */
  470. static const struct fimc_fmt *fimc_lite_subdev_try_fmt(struct fimc_lite *fimc,
  471. struct v4l2_subdev_fh *fh,
  472. struct v4l2_subdev_format *format)
  473. {
  474. struct flite_drvdata *dd = fimc->dd;
  475. struct v4l2_mbus_framefmt *mf = &format->format;
  476. const struct fimc_fmt *fmt = NULL;
  477. if (format->pad == FLITE_SD_PAD_SINK) {
  478. v4l_bound_align_image(&mf->width, 8, dd->max_width,
  479. ffs(dd->out_width_align) - 1,
  480. &mf->height, 0, dd->max_height, 0, 0);
  481. fmt = fimc_lite_find_format(NULL, &mf->code, 0, 0);
  482. if (WARN_ON(!fmt))
  483. return NULL;
  484. mf->code = fmt->mbus_code;
  485. } else {
  486. struct flite_frame *sink = &fimc->inp_frame;
  487. struct v4l2_mbus_framefmt *sink_fmt;
  488. struct v4l2_rect *rect;
  489. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  490. sink_fmt = v4l2_subdev_get_try_format(fh,
  491. FLITE_SD_PAD_SINK);
  492. mf->code = sink_fmt->code;
  493. rect = v4l2_subdev_get_try_crop(fh,
  494. FLITE_SD_PAD_SINK);
  495. } else {
  496. mf->code = sink->fmt->mbus_code;
  497. rect = &sink->rect;
  498. }
  499. /* Allow changing format only on sink pad */
  500. mf->width = rect->width;
  501. mf->height = rect->height;
  502. }
  503. mf->field = V4L2_FIELD_NONE;
  504. v4l2_dbg(1, debug, &fimc->subdev, "code: %#x (%d), %dx%d\n",
  505. mf->code, mf->colorspace, mf->width, mf->height);
  506. return fmt;
  507. }
  508. static void fimc_lite_try_crop(struct fimc_lite *fimc, struct v4l2_rect *r)
  509. {
  510. struct flite_frame *frame = &fimc->inp_frame;
  511. v4l_bound_align_image(&r->width, 0, frame->f_width, 0,
  512. &r->height, 0, frame->f_height, 0, 0);
  513. /* Adjust left/top if cropping rectangle got out of bounds */
  514. r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
  515. r->left = round_down(r->left, fimc->dd->win_hor_offs_align);
  516. r->top = clamp_t(u32, r->top, 0, frame->f_height - r->height);
  517. v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, sink fmt: %dx%d\n",
  518. r->left, r->top, r->width, r->height,
  519. frame->f_width, frame->f_height);
  520. }
  521. static void fimc_lite_try_compose(struct fimc_lite *fimc, struct v4l2_rect *r)
  522. {
  523. struct flite_frame *frame = &fimc->out_frame;
  524. struct v4l2_rect *crop_rect = &fimc->inp_frame.rect;
  525. /* Scaling is not supported so we enforce compose rectangle size
  526. same as size of the sink crop rectangle. */
  527. r->width = crop_rect->width;
  528. r->height = crop_rect->height;
  529. /* Adjust left/top if the composing rectangle got out of bounds */
  530. r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
  531. r->left = round_down(r->left, fimc->dd->out_hor_offs_align);
  532. r->top = clamp_t(u32, r->top, 0, fimc->out_frame.f_height - r->height);
  533. v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, source fmt: %dx%d\n",
  534. r->left, r->top, r->width, r->height,
  535. frame->f_width, frame->f_height);
  536. }
  537. /*
  538. * Video node ioctl operations
  539. */
  540. static int fimc_lite_querycap(struct file *file, void *priv,
  541. struct v4l2_capability *cap)
  542. {
  543. struct fimc_lite *fimc = video_drvdata(file);
  544. strlcpy(cap->driver, FIMC_LITE_DRV_NAME, sizeof(cap->driver));
  545. strlcpy(cap->card, FIMC_LITE_DRV_NAME, sizeof(cap->card));
  546. snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
  547. dev_name(&fimc->pdev->dev));
  548. cap->device_caps = V4L2_CAP_STREAMING;
  549. cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
  550. return 0;
  551. }
  552. static int fimc_lite_enum_fmt_mplane(struct file *file, void *priv,
  553. struct v4l2_fmtdesc *f)
  554. {
  555. const struct fimc_fmt *fmt;
  556. if (f->index >= ARRAY_SIZE(fimc_lite_formats))
  557. return -EINVAL;
  558. fmt = &fimc_lite_formats[f->index];
  559. strlcpy(f->description, fmt->name, sizeof(f->description));
  560. f->pixelformat = fmt->fourcc;
  561. return 0;
  562. }
  563. static int fimc_lite_g_fmt_mplane(struct file *file, void *fh,
  564. struct v4l2_format *f)
  565. {
  566. struct fimc_lite *fimc = video_drvdata(file);
  567. struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
  568. struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[0];
  569. struct flite_frame *frame = &fimc->out_frame;
  570. const struct fimc_fmt *fmt = frame->fmt;
  571. plane_fmt->bytesperline = (frame->f_width * fmt->depth[0]) / 8;
  572. plane_fmt->sizeimage = plane_fmt->bytesperline * frame->f_height;
  573. pixm->num_planes = fmt->memplanes;
  574. pixm->pixelformat = fmt->fourcc;
  575. pixm->width = frame->f_width;
  576. pixm->height = frame->f_height;
  577. pixm->field = V4L2_FIELD_NONE;
  578. pixm->colorspace = V4L2_COLORSPACE_JPEG;
  579. return 0;
  580. }
  581. static int fimc_lite_try_fmt(struct fimc_lite *fimc,
  582. struct v4l2_pix_format_mplane *pixm,
  583. const struct fimc_fmt **ffmt)
  584. {
  585. u32 bpl = pixm->plane_fmt[0].bytesperline;
  586. struct flite_drvdata *dd = fimc->dd;
  587. const struct fimc_fmt *inp_fmt = fimc->inp_frame.fmt;
  588. const struct fimc_fmt *fmt;
  589. if (WARN_ON(inp_fmt == NULL))
  590. return -EINVAL;
  591. /*
  592. * We allow some flexibility only for YUV formats. In case of raw
  593. * raw Bayer the FIMC-LITE's output format must match its camera
  594. * interface input format.
  595. */
  596. if (inp_fmt->flags & FMT_FLAGS_YUV)
  597. fmt = fimc_lite_find_format(&pixm->pixelformat, NULL,
  598. inp_fmt->flags, 0);
  599. else
  600. fmt = inp_fmt;
  601. if (WARN_ON(fmt == NULL))
  602. return -EINVAL;
  603. if (ffmt)
  604. *ffmt = fmt;
  605. v4l_bound_align_image(&pixm->width, 8, dd->max_width,
  606. ffs(dd->out_width_align) - 1,
  607. &pixm->height, 0, dd->max_height, 0, 0);
  608. if ((bpl == 0 || ((bpl * 8) / fmt->depth[0]) < pixm->width))
  609. pixm->plane_fmt[0].bytesperline = (pixm->width *
  610. fmt->depth[0]) / 8;
  611. if (pixm->plane_fmt[0].sizeimage == 0)
  612. pixm->plane_fmt[0].sizeimage = (pixm->width * pixm->height *
  613. fmt->depth[0]) / 8;
  614. pixm->num_planes = fmt->memplanes;
  615. pixm->pixelformat = fmt->fourcc;
  616. pixm->colorspace = V4L2_COLORSPACE_JPEG;
  617. pixm->field = V4L2_FIELD_NONE;
  618. return 0;
  619. }
  620. static int fimc_lite_try_fmt_mplane(struct file *file, void *fh,
  621. struct v4l2_format *f)
  622. {
  623. struct fimc_lite *fimc = video_drvdata(file);
  624. return fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, NULL);
  625. }
  626. static int fimc_lite_s_fmt_mplane(struct file *file, void *priv,
  627. struct v4l2_format *f)
  628. {
  629. struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
  630. struct fimc_lite *fimc = video_drvdata(file);
  631. struct flite_frame *frame = &fimc->out_frame;
  632. const struct fimc_fmt *fmt = NULL;
  633. int ret;
  634. if (vb2_is_busy(&fimc->vb_queue))
  635. return -EBUSY;
  636. ret = fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, &fmt);
  637. if (ret < 0)
  638. return ret;
  639. frame->fmt = fmt;
  640. fimc->payload[0] = max((pixm->width * pixm->height * fmt->depth[0]) / 8,
  641. pixm->plane_fmt[0].sizeimage);
  642. frame->f_width = pixm->width;
  643. frame->f_height = pixm->height;
  644. return 0;
  645. }
  646. static int fimc_pipeline_validate(struct fimc_lite *fimc)
  647. {
  648. struct v4l2_subdev *sd = &fimc->subdev;
  649. struct v4l2_subdev_format sink_fmt, src_fmt;
  650. struct media_pad *pad;
  651. int ret;
  652. while (1) {
  653. /* Retrieve format at the sink pad */
  654. pad = &sd->entity.pads[0];
  655. if (!(pad->flags & MEDIA_PAD_FL_SINK))
  656. break;
  657. /* Don't call FIMC subdev operation to avoid nested locking */
  658. if (sd == &fimc->subdev) {
  659. struct flite_frame *ff = &fimc->out_frame;
  660. sink_fmt.format.width = ff->f_width;
  661. sink_fmt.format.height = ff->f_height;
  662. sink_fmt.format.code = fimc->inp_frame.fmt->mbus_code;
  663. } else {
  664. sink_fmt.pad = pad->index;
  665. sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  666. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL,
  667. &sink_fmt);
  668. if (ret < 0 && ret != -ENOIOCTLCMD)
  669. return -EPIPE;
  670. }
  671. /* Retrieve format at the source pad */
  672. pad = media_entity_remote_pad(pad);
  673. if (pad == NULL ||
  674. media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
  675. break;
  676. sd = media_entity_to_v4l2_subdev(pad->entity);
  677. src_fmt.pad = pad->index;
  678. src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  679. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt);
  680. if (ret < 0 && ret != -ENOIOCTLCMD)
  681. return -EPIPE;
  682. if (src_fmt.format.width != sink_fmt.format.width ||
  683. src_fmt.format.height != sink_fmt.format.height ||
  684. src_fmt.format.code != sink_fmt.format.code)
  685. return -EPIPE;
  686. }
  687. return 0;
  688. }
  689. static int fimc_lite_streamon(struct file *file, void *priv,
  690. enum v4l2_buf_type type)
  691. {
  692. struct fimc_lite *fimc = video_drvdata(file);
  693. struct media_entity *entity = &fimc->ve.vdev.entity;
  694. int ret;
  695. if (fimc_lite_active(fimc))
  696. return -EBUSY;
  697. ret = media_entity_pipeline_start(entity, &fimc->ve.pipe->mp);
  698. if (ret < 0)
  699. return ret;
  700. ret = fimc_pipeline_validate(fimc);
  701. if (ret < 0)
  702. goto err_p_stop;
  703. fimc->sensor = fimc_find_remote_sensor(&fimc->subdev.entity);
  704. ret = vb2_ioctl_streamon(file, priv, type);
  705. if (!ret) {
  706. fimc->streaming = true;
  707. return ret;
  708. }
  709. err_p_stop:
  710. media_entity_pipeline_stop(entity);
  711. return 0;
  712. }
  713. static int fimc_lite_streamoff(struct file *file, void *priv,
  714. enum v4l2_buf_type type)
  715. {
  716. struct fimc_lite *fimc = video_drvdata(file);
  717. int ret;
  718. ret = vb2_ioctl_streamoff(file, priv, type);
  719. if (ret < 0)
  720. return ret;
  721. media_entity_pipeline_stop(&fimc->ve.vdev.entity);
  722. fimc->streaming = false;
  723. return 0;
  724. }
  725. static int fimc_lite_reqbufs(struct file *file, void *priv,
  726. struct v4l2_requestbuffers *reqbufs)
  727. {
  728. struct fimc_lite *fimc = video_drvdata(file);
  729. int ret;
  730. reqbufs->count = max_t(u32, FLITE_REQ_BUFS_MIN, reqbufs->count);
  731. ret = vb2_ioctl_reqbufs(file, priv, reqbufs);
  732. if (!ret)
  733. fimc->reqbufs_count = reqbufs->count;
  734. return ret;
  735. }
  736. /* Return 1 if rectangle a is enclosed in rectangle b, or 0 otherwise. */
  737. static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b)
  738. {
  739. if (a->left < b->left || a->top < b->top)
  740. return 0;
  741. if (a->left + a->width > b->left + b->width)
  742. return 0;
  743. if (a->top + a->height > b->top + b->height)
  744. return 0;
  745. return 1;
  746. }
  747. static int fimc_lite_g_selection(struct file *file, void *fh,
  748. struct v4l2_selection *sel)
  749. {
  750. struct fimc_lite *fimc = video_drvdata(file);
  751. struct flite_frame *f = &fimc->out_frame;
  752. if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
  753. return -EINVAL;
  754. switch (sel->target) {
  755. case V4L2_SEL_TGT_COMPOSE_BOUNDS:
  756. case V4L2_SEL_TGT_COMPOSE_DEFAULT:
  757. sel->r.left = 0;
  758. sel->r.top = 0;
  759. sel->r.width = f->f_width;
  760. sel->r.height = f->f_height;
  761. return 0;
  762. case V4L2_SEL_TGT_COMPOSE:
  763. sel->r = f->rect;
  764. return 0;
  765. }
  766. return -EINVAL;
  767. }
  768. static int fimc_lite_s_selection(struct file *file, void *fh,
  769. struct v4l2_selection *sel)
  770. {
  771. struct fimc_lite *fimc = video_drvdata(file);
  772. struct flite_frame *f = &fimc->out_frame;
  773. struct v4l2_rect rect = sel->r;
  774. unsigned long flags;
  775. if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ||
  776. sel->target != V4L2_SEL_TGT_COMPOSE)
  777. return -EINVAL;
  778. fimc_lite_try_compose(fimc, &rect);
  779. if ((sel->flags & V4L2_SEL_FLAG_LE) &&
  780. !enclosed_rectangle(&rect, &sel->r))
  781. return -ERANGE;
  782. if ((sel->flags & V4L2_SEL_FLAG_GE) &&
  783. !enclosed_rectangle(&sel->r, &rect))
  784. return -ERANGE;
  785. sel->r = rect;
  786. spin_lock_irqsave(&fimc->slock, flags);
  787. f->rect = rect;
  788. set_bit(ST_FLITE_CONFIG, &fimc->state);
  789. spin_unlock_irqrestore(&fimc->slock, flags);
  790. return 0;
  791. }
  792. static const struct v4l2_ioctl_ops fimc_lite_ioctl_ops = {
  793. .vidioc_querycap = fimc_lite_querycap,
  794. .vidioc_enum_fmt_vid_cap_mplane = fimc_lite_enum_fmt_mplane,
  795. .vidioc_try_fmt_vid_cap_mplane = fimc_lite_try_fmt_mplane,
  796. .vidioc_s_fmt_vid_cap_mplane = fimc_lite_s_fmt_mplane,
  797. .vidioc_g_fmt_vid_cap_mplane = fimc_lite_g_fmt_mplane,
  798. .vidioc_g_selection = fimc_lite_g_selection,
  799. .vidioc_s_selection = fimc_lite_s_selection,
  800. .vidioc_reqbufs = fimc_lite_reqbufs,
  801. .vidioc_querybuf = vb2_ioctl_querybuf,
  802. .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
  803. .vidioc_create_bufs = vb2_ioctl_create_bufs,
  804. .vidioc_qbuf = vb2_ioctl_qbuf,
  805. .vidioc_dqbuf = vb2_ioctl_dqbuf,
  806. .vidioc_streamon = fimc_lite_streamon,
  807. .vidioc_streamoff = fimc_lite_streamoff,
  808. };
  809. /* Capture subdev media entity operations */
  810. static int fimc_lite_link_setup(struct media_entity *entity,
  811. const struct media_pad *local,
  812. const struct media_pad *remote, u32 flags)
  813. {
  814. struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
  815. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  816. unsigned int remote_ent_type = media_entity_type(remote->entity);
  817. int ret = 0;
  818. if (WARN_ON(fimc == NULL))
  819. return 0;
  820. v4l2_dbg(1, debug, sd, "%s: %s --> %s, flags: 0x%x. source_id: 0x%x\n",
  821. __func__, remote->entity->name, local->entity->name,
  822. flags, fimc->source_subdev_grp_id);
  823. switch (local->index) {
  824. case FLITE_SD_PAD_SINK:
  825. if (remote_ent_type != MEDIA_ENT_T_V4L2_SUBDEV) {
  826. ret = -EINVAL;
  827. break;
  828. }
  829. if (flags & MEDIA_LNK_FL_ENABLED) {
  830. if (fimc->source_subdev_grp_id == 0)
  831. fimc->source_subdev_grp_id = sd->grp_id;
  832. else
  833. ret = -EBUSY;
  834. } else {
  835. fimc->source_subdev_grp_id = 0;
  836. fimc->sensor = NULL;
  837. }
  838. break;
  839. case FLITE_SD_PAD_SOURCE_DMA:
  840. if (!(flags & MEDIA_LNK_FL_ENABLED))
  841. atomic_set(&fimc->out_path, FIMC_IO_NONE);
  842. else if (remote_ent_type == MEDIA_ENT_T_DEVNODE)
  843. atomic_set(&fimc->out_path, FIMC_IO_DMA);
  844. else
  845. ret = -EINVAL;
  846. break;
  847. case FLITE_SD_PAD_SOURCE_ISP:
  848. if (!(flags & MEDIA_LNK_FL_ENABLED))
  849. atomic_set(&fimc->out_path, FIMC_IO_NONE);
  850. else if (remote_ent_type == MEDIA_ENT_T_V4L2_SUBDEV)
  851. atomic_set(&fimc->out_path, FIMC_IO_ISP);
  852. else
  853. ret = -EINVAL;
  854. break;
  855. default:
  856. v4l2_err(sd, "Invalid pad index\n");
  857. ret = -EINVAL;
  858. }
  859. mb();
  860. return ret;
  861. }
  862. static const struct media_entity_operations fimc_lite_subdev_media_ops = {
  863. .link_setup = fimc_lite_link_setup,
  864. };
  865. static int fimc_lite_subdev_enum_mbus_code(struct v4l2_subdev *sd,
  866. struct v4l2_subdev_fh *fh,
  867. struct v4l2_subdev_mbus_code_enum *code)
  868. {
  869. const struct fimc_fmt *fmt;
  870. fmt = fimc_lite_find_format(NULL, NULL, 0, code->index);
  871. if (!fmt)
  872. return -EINVAL;
  873. code->code = fmt->mbus_code;
  874. return 0;
  875. }
  876. static struct v4l2_mbus_framefmt *__fimc_lite_subdev_get_try_fmt(
  877. struct v4l2_subdev_fh *fh, unsigned int pad)
  878. {
  879. if (pad != FLITE_SD_PAD_SINK)
  880. pad = FLITE_SD_PAD_SOURCE_DMA;
  881. return v4l2_subdev_get_try_format(fh, pad);
  882. }
  883. static int fimc_lite_subdev_get_fmt(struct v4l2_subdev *sd,
  884. struct v4l2_subdev_fh *fh,
  885. struct v4l2_subdev_format *fmt)
  886. {
  887. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  888. struct v4l2_mbus_framefmt *mf = &fmt->format;
  889. struct flite_frame *f = &fimc->inp_frame;
  890. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  891. mf = __fimc_lite_subdev_get_try_fmt(fh, fmt->pad);
  892. fmt->format = *mf;
  893. return 0;
  894. }
  895. mf->colorspace = V4L2_COLORSPACE_JPEG;
  896. mutex_lock(&fimc->lock);
  897. mf->code = f->fmt->mbus_code;
  898. if (fmt->pad == FLITE_SD_PAD_SINK) {
  899. /* full camera input frame size */
  900. mf->width = f->f_width;
  901. mf->height = f->f_height;
  902. } else {
  903. /* crop size */
  904. mf->width = f->rect.width;
  905. mf->height = f->rect.height;
  906. }
  907. mutex_unlock(&fimc->lock);
  908. return 0;
  909. }
  910. static int fimc_lite_subdev_set_fmt(struct v4l2_subdev *sd,
  911. struct v4l2_subdev_fh *fh,
  912. struct v4l2_subdev_format *fmt)
  913. {
  914. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  915. struct v4l2_mbus_framefmt *mf = &fmt->format;
  916. struct flite_frame *sink = &fimc->inp_frame;
  917. struct flite_frame *source = &fimc->out_frame;
  918. const struct fimc_fmt *ffmt;
  919. v4l2_dbg(1, debug, sd, "pad%d: code: 0x%x, %dx%d\n",
  920. fmt->pad, mf->code, mf->width, mf->height);
  921. mf->colorspace = V4L2_COLORSPACE_JPEG;
  922. mutex_lock(&fimc->lock);
  923. if ((atomic_read(&fimc->out_path) == FIMC_IO_ISP &&
  924. sd->entity.stream_count > 0) ||
  925. (atomic_read(&fimc->out_path) == FIMC_IO_DMA &&
  926. vb2_is_busy(&fimc->vb_queue))) {
  927. mutex_unlock(&fimc->lock);
  928. return -EBUSY;
  929. }
  930. ffmt = fimc_lite_subdev_try_fmt(fimc, fh, fmt);
  931. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  932. struct v4l2_mbus_framefmt *src_fmt;
  933. mf = __fimc_lite_subdev_get_try_fmt(fh, fmt->pad);
  934. *mf = fmt->format;
  935. if (fmt->pad == FLITE_SD_PAD_SINK) {
  936. unsigned int pad = FLITE_SD_PAD_SOURCE_DMA;
  937. src_fmt = __fimc_lite_subdev_get_try_fmt(fh, pad);
  938. *src_fmt = *mf;
  939. }
  940. mutex_unlock(&fimc->lock);
  941. return 0;
  942. }
  943. if (fmt->pad == FLITE_SD_PAD_SINK) {
  944. sink->f_width = mf->width;
  945. sink->f_height = mf->height;
  946. sink->fmt = ffmt;
  947. /* Set sink crop rectangle */
  948. sink->rect.width = mf->width;
  949. sink->rect.height = mf->height;
  950. sink->rect.left = 0;
  951. sink->rect.top = 0;
  952. /* Reset source format and crop rectangle */
  953. source->rect = sink->rect;
  954. source->f_width = mf->width;
  955. source->f_height = mf->height;
  956. }
  957. mutex_unlock(&fimc->lock);
  958. return 0;
  959. }
  960. static int fimc_lite_subdev_get_selection(struct v4l2_subdev *sd,
  961. struct v4l2_subdev_fh *fh,
  962. struct v4l2_subdev_selection *sel)
  963. {
  964. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  965. struct flite_frame *f = &fimc->inp_frame;
  966. if ((sel->target != V4L2_SEL_TGT_CROP &&
  967. sel->target != V4L2_SEL_TGT_CROP_BOUNDS) ||
  968. sel->pad != FLITE_SD_PAD_SINK)
  969. return -EINVAL;
  970. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  971. sel->r = *v4l2_subdev_get_try_crop(fh, sel->pad);
  972. return 0;
  973. }
  974. mutex_lock(&fimc->lock);
  975. if (sel->target == V4L2_SEL_TGT_CROP) {
  976. sel->r = f->rect;
  977. } else {
  978. sel->r.left = 0;
  979. sel->r.top = 0;
  980. sel->r.width = f->f_width;
  981. sel->r.height = f->f_height;
  982. }
  983. mutex_unlock(&fimc->lock);
  984. v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d\n",
  985. __func__, f->rect.left, f->rect.top, f->rect.width,
  986. f->rect.height, f->f_width, f->f_height);
  987. return 0;
  988. }
  989. static int fimc_lite_subdev_set_selection(struct v4l2_subdev *sd,
  990. struct v4l2_subdev_fh *fh,
  991. struct v4l2_subdev_selection *sel)
  992. {
  993. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  994. struct flite_frame *f = &fimc->inp_frame;
  995. int ret = 0;
  996. if (sel->target != V4L2_SEL_TGT_CROP || sel->pad != FLITE_SD_PAD_SINK)
  997. return -EINVAL;
  998. mutex_lock(&fimc->lock);
  999. fimc_lite_try_crop(fimc, &sel->r);
  1000. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  1001. *v4l2_subdev_get_try_crop(fh, sel->pad) = sel->r;
  1002. } else {
  1003. unsigned long flags;
  1004. spin_lock_irqsave(&fimc->slock, flags);
  1005. f->rect = sel->r;
  1006. /* Same crop rectangle on the source pad */
  1007. fimc->out_frame.rect = sel->r;
  1008. set_bit(ST_FLITE_CONFIG, &fimc->state);
  1009. spin_unlock_irqrestore(&fimc->slock, flags);
  1010. }
  1011. mutex_unlock(&fimc->lock);
  1012. v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d\n",
  1013. __func__, f->rect.left, f->rect.top, f->rect.width,
  1014. f->rect.height, f->f_width, f->f_height);
  1015. return ret;
  1016. }
  1017. static int fimc_lite_subdev_s_stream(struct v4l2_subdev *sd, int on)
  1018. {
  1019. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1020. unsigned long flags;
  1021. int ret;
  1022. /*
  1023. * Find sensor subdev linked to FIMC-LITE directly or through
  1024. * MIPI-CSIS. This is required for configuration where FIMC-LITE
  1025. * is used as a subdev only and feeds data internally to FIMC-IS.
  1026. * The pipeline links are protected through entity.stream_count
  1027. * so there is no need to take the media graph mutex here.
  1028. */
  1029. fimc->sensor = fimc_find_remote_sensor(&sd->entity);
  1030. if (atomic_read(&fimc->out_path) != FIMC_IO_ISP)
  1031. return -ENOIOCTLCMD;
  1032. mutex_lock(&fimc->lock);
  1033. if (on) {
  1034. flite_hw_reset(fimc);
  1035. ret = fimc_lite_hw_init(fimc, true);
  1036. if (!ret) {
  1037. spin_lock_irqsave(&fimc->slock, flags);
  1038. flite_hw_capture_start(fimc);
  1039. spin_unlock_irqrestore(&fimc->slock, flags);
  1040. }
  1041. } else {
  1042. set_bit(ST_FLITE_OFF, &fimc->state);
  1043. spin_lock_irqsave(&fimc->slock, flags);
  1044. flite_hw_capture_stop(fimc);
  1045. spin_unlock_irqrestore(&fimc->slock, flags);
  1046. ret = wait_event_timeout(fimc->irq_queue,
  1047. !test_bit(ST_FLITE_OFF, &fimc->state),
  1048. msecs_to_jiffies(200));
  1049. if (ret == 0)
  1050. v4l2_err(sd, "s_stream(0) timeout\n");
  1051. clear_bit(ST_FLITE_RUN, &fimc->state);
  1052. }
  1053. mutex_unlock(&fimc->lock);
  1054. return ret;
  1055. }
  1056. static int fimc_lite_log_status(struct v4l2_subdev *sd)
  1057. {
  1058. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1059. flite_hw_dump_regs(fimc, __func__);
  1060. return 0;
  1061. }
  1062. static int fimc_lite_subdev_registered(struct v4l2_subdev *sd)
  1063. {
  1064. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1065. struct vb2_queue *q = &fimc->vb_queue;
  1066. struct video_device *vfd = &fimc->ve.vdev;
  1067. int ret;
  1068. memset(vfd, 0, sizeof(*vfd));
  1069. atomic_set(&fimc->out_path, FIMC_IO_DMA);
  1070. snprintf(vfd->name, sizeof(vfd->name), "fimc-lite.%d.capture",
  1071. fimc->index);
  1072. vfd->fops = &fimc_lite_fops;
  1073. vfd->ioctl_ops = &fimc_lite_ioctl_ops;
  1074. vfd->v4l2_dev = sd->v4l2_dev;
  1075. vfd->minor = -1;
  1076. vfd->release = video_device_release_empty;
  1077. vfd->queue = q;
  1078. fimc->reqbufs_count = 0;
  1079. INIT_LIST_HEAD(&fimc->pending_buf_q);
  1080. INIT_LIST_HEAD(&fimc->active_buf_q);
  1081. memset(q, 0, sizeof(*q));
  1082. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
  1083. q->io_modes = VB2_MMAP | VB2_USERPTR;
  1084. q->ops = &fimc_lite_qops;
  1085. q->mem_ops = &vb2_dma_contig_memops;
  1086. q->buf_struct_size = sizeof(struct flite_buffer);
  1087. q->drv_priv = fimc;
  1088. q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  1089. q->lock = &fimc->lock;
  1090. ret = vb2_queue_init(q);
  1091. if (ret < 0)
  1092. return ret;
  1093. fimc->vd_pad.flags = MEDIA_PAD_FL_SINK;
  1094. ret = media_entity_init(&vfd->entity, 1, &fimc->vd_pad, 0);
  1095. if (ret < 0)
  1096. return ret;
  1097. video_set_drvdata(vfd, fimc);
  1098. fimc->ve.pipe = v4l2_get_subdev_hostdata(sd);
  1099. ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
  1100. if (ret < 0) {
  1101. media_entity_cleanup(&vfd->entity);
  1102. fimc->ve.pipe = NULL;
  1103. return ret;
  1104. }
  1105. v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
  1106. vfd->name, video_device_node_name(vfd));
  1107. return 0;
  1108. }
  1109. static void fimc_lite_subdev_unregistered(struct v4l2_subdev *sd)
  1110. {
  1111. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1112. if (fimc == NULL)
  1113. return;
  1114. mutex_lock(&fimc->lock);
  1115. if (video_is_registered(&fimc->ve.vdev)) {
  1116. video_unregister_device(&fimc->ve.vdev);
  1117. media_entity_cleanup(&fimc->ve.vdev.entity);
  1118. fimc->ve.pipe = NULL;
  1119. }
  1120. mutex_unlock(&fimc->lock);
  1121. }
  1122. static const struct v4l2_subdev_internal_ops fimc_lite_subdev_internal_ops = {
  1123. .registered = fimc_lite_subdev_registered,
  1124. .unregistered = fimc_lite_subdev_unregistered,
  1125. };
  1126. static const struct v4l2_subdev_pad_ops fimc_lite_subdev_pad_ops = {
  1127. .enum_mbus_code = fimc_lite_subdev_enum_mbus_code,
  1128. .get_selection = fimc_lite_subdev_get_selection,
  1129. .set_selection = fimc_lite_subdev_set_selection,
  1130. .get_fmt = fimc_lite_subdev_get_fmt,
  1131. .set_fmt = fimc_lite_subdev_set_fmt,
  1132. };
  1133. static const struct v4l2_subdev_video_ops fimc_lite_subdev_video_ops = {
  1134. .s_stream = fimc_lite_subdev_s_stream,
  1135. };
  1136. static const struct v4l2_subdev_core_ops fimc_lite_core_ops = {
  1137. .log_status = fimc_lite_log_status,
  1138. };
  1139. static struct v4l2_subdev_ops fimc_lite_subdev_ops = {
  1140. .core = &fimc_lite_core_ops,
  1141. .video = &fimc_lite_subdev_video_ops,
  1142. .pad = &fimc_lite_subdev_pad_ops,
  1143. };
  1144. static int fimc_lite_s_ctrl(struct v4l2_ctrl *ctrl)
  1145. {
  1146. struct fimc_lite *fimc = container_of(ctrl->handler, struct fimc_lite,
  1147. ctrl_handler);
  1148. set_bit(ST_FLITE_CONFIG, &fimc->state);
  1149. return 0;
  1150. }
  1151. static const struct v4l2_ctrl_ops fimc_lite_ctrl_ops = {
  1152. .s_ctrl = fimc_lite_s_ctrl,
  1153. };
  1154. static const struct v4l2_ctrl_config fimc_lite_ctrl = {
  1155. .ops = &fimc_lite_ctrl_ops,
  1156. .id = V4L2_CTRL_CLASS_USER | 0x1001,
  1157. .type = V4L2_CTRL_TYPE_BOOLEAN,
  1158. .name = "Test Pattern 640x480",
  1159. .step = 1,
  1160. };
  1161. static void fimc_lite_set_default_config(struct fimc_lite *fimc)
  1162. {
  1163. struct flite_frame *sink = &fimc->inp_frame;
  1164. struct flite_frame *source = &fimc->out_frame;
  1165. sink->fmt = &fimc_lite_formats[0];
  1166. sink->f_width = FLITE_DEFAULT_WIDTH;
  1167. sink->f_height = FLITE_DEFAULT_HEIGHT;
  1168. sink->rect.width = FLITE_DEFAULT_WIDTH;
  1169. sink->rect.height = FLITE_DEFAULT_HEIGHT;
  1170. sink->rect.left = 0;
  1171. sink->rect.top = 0;
  1172. *source = *sink;
  1173. }
  1174. static int fimc_lite_create_capture_subdev(struct fimc_lite *fimc)
  1175. {
  1176. struct v4l2_ctrl_handler *handler = &fimc->ctrl_handler;
  1177. struct v4l2_subdev *sd = &fimc->subdev;
  1178. int ret;
  1179. v4l2_subdev_init(sd, &fimc_lite_subdev_ops);
  1180. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  1181. snprintf(sd->name, sizeof(sd->name), "FIMC-LITE.%d", fimc->index);
  1182. fimc->subdev_pads[FLITE_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
  1183. fimc->subdev_pads[FLITE_SD_PAD_SOURCE_DMA].flags = MEDIA_PAD_FL_SOURCE;
  1184. fimc->subdev_pads[FLITE_SD_PAD_SOURCE_ISP].flags = MEDIA_PAD_FL_SOURCE;
  1185. ret = media_entity_init(&sd->entity, FLITE_SD_PADS_NUM,
  1186. fimc->subdev_pads, 0);
  1187. if (ret)
  1188. return ret;
  1189. v4l2_ctrl_handler_init(handler, 1);
  1190. fimc->test_pattern = v4l2_ctrl_new_custom(handler, &fimc_lite_ctrl,
  1191. NULL);
  1192. if (handler->error) {
  1193. media_entity_cleanup(&sd->entity);
  1194. return handler->error;
  1195. }
  1196. sd->ctrl_handler = handler;
  1197. sd->internal_ops = &fimc_lite_subdev_internal_ops;
  1198. sd->entity.ops = &fimc_lite_subdev_media_ops;
  1199. sd->owner = THIS_MODULE;
  1200. v4l2_set_subdevdata(sd, fimc);
  1201. return 0;
  1202. }
  1203. static void fimc_lite_unregister_capture_subdev(struct fimc_lite *fimc)
  1204. {
  1205. struct v4l2_subdev *sd = &fimc->subdev;
  1206. v4l2_device_unregister_subdev(sd);
  1207. media_entity_cleanup(&sd->entity);
  1208. v4l2_ctrl_handler_free(&fimc->ctrl_handler);
  1209. v4l2_set_subdevdata(sd, NULL);
  1210. }
  1211. static void fimc_lite_clk_put(struct fimc_lite *fimc)
  1212. {
  1213. if (IS_ERR(fimc->clock))
  1214. return;
  1215. clk_unprepare(fimc->clock);
  1216. clk_put(fimc->clock);
  1217. fimc->clock = ERR_PTR(-EINVAL);
  1218. }
  1219. static int fimc_lite_clk_get(struct fimc_lite *fimc)
  1220. {
  1221. int ret;
  1222. fimc->clock = clk_get(&fimc->pdev->dev, FLITE_CLK_NAME);
  1223. if (IS_ERR(fimc->clock))
  1224. return PTR_ERR(fimc->clock);
  1225. ret = clk_prepare(fimc->clock);
  1226. if (ret < 0) {
  1227. clk_put(fimc->clock);
  1228. fimc->clock = ERR_PTR(-EINVAL);
  1229. }
  1230. return ret;
  1231. }
  1232. static const struct of_device_id flite_of_match[];
  1233. static int fimc_lite_probe(struct platform_device *pdev)
  1234. {
  1235. struct flite_drvdata *drv_data = NULL;
  1236. struct device *dev = &pdev->dev;
  1237. const struct of_device_id *of_id;
  1238. struct fimc_lite *fimc;
  1239. struct resource *res;
  1240. int ret;
  1241. fimc = devm_kzalloc(dev, sizeof(*fimc), GFP_KERNEL);
  1242. if (!fimc)
  1243. return -ENOMEM;
  1244. if (dev->of_node) {
  1245. of_id = of_match_node(flite_of_match, dev->of_node);
  1246. if (of_id)
  1247. drv_data = (struct flite_drvdata *)of_id->data;
  1248. fimc->index = of_alias_get_id(dev->of_node, "fimc-lite");
  1249. }
  1250. if (!drv_data || fimc->index >= drv_data->num_instances ||
  1251. fimc->index < 0) {
  1252. dev_err(dev, "Wrong %s node alias\n",
  1253. dev->of_node->full_name);
  1254. return -EINVAL;
  1255. }
  1256. fimc->dd = drv_data;
  1257. fimc->pdev = pdev;
  1258. init_waitqueue_head(&fimc->irq_queue);
  1259. spin_lock_init(&fimc->slock);
  1260. mutex_init(&fimc->lock);
  1261. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1262. fimc->regs = devm_ioremap_resource(dev, res);
  1263. if (IS_ERR(fimc->regs))
  1264. return PTR_ERR(fimc->regs);
  1265. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1266. if (res == NULL) {
  1267. dev_err(dev, "Failed to get IRQ resource\n");
  1268. return -ENXIO;
  1269. }
  1270. ret = fimc_lite_clk_get(fimc);
  1271. if (ret)
  1272. return ret;
  1273. ret = devm_request_irq(dev, res->start, flite_irq_handler,
  1274. 0, dev_name(dev), fimc);
  1275. if (ret) {
  1276. dev_err(dev, "Failed to install irq (%d)\n", ret);
  1277. goto err_clk;
  1278. }
  1279. /* The video node will be created within the subdev's registered() op */
  1280. ret = fimc_lite_create_capture_subdev(fimc);
  1281. if (ret)
  1282. goto err_clk;
  1283. platform_set_drvdata(pdev, fimc);
  1284. pm_runtime_enable(dev);
  1285. ret = pm_runtime_get_sync(dev);
  1286. if (ret < 0)
  1287. goto err_sd;
  1288. fimc->alloc_ctx = vb2_dma_contig_init_ctx(dev);
  1289. if (IS_ERR(fimc->alloc_ctx)) {
  1290. ret = PTR_ERR(fimc->alloc_ctx);
  1291. goto err_pm;
  1292. }
  1293. pm_runtime_put(dev);
  1294. fimc_lite_set_default_config(fimc);
  1295. dev_dbg(dev, "FIMC-LITE.%d registered successfully\n",
  1296. fimc->index);
  1297. return 0;
  1298. err_pm:
  1299. pm_runtime_put(dev);
  1300. err_sd:
  1301. fimc_lite_unregister_capture_subdev(fimc);
  1302. err_clk:
  1303. fimc_lite_clk_put(fimc);
  1304. return ret;
  1305. }
  1306. static int fimc_lite_runtime_resume(struct device *dev)
  1307. {
  1308. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1309. clk_enable(fimc->clock);
  1310. return 0;
  1311. }
  1312. static int fimc_lite_runtime_suspend(struct device *dev)
  1313. {
  1314. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1315. clk_disable(fimc->clock);
  1316. return 0;
  1317. }
  1318. #ifdef CONFIG_PM_SLEEP
  1319. static int fimc_lite_resume(struct device *dev)
  1320. {
  1321. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1322. struct flite_buffer *buf;
  1323. unsigned long flags;
  1324. int i;
  1325. spin_lock_irqsave(&fimc->slock, flags);
  1326. if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
  1327. !test_bit(ST_FLITE_IN_USE, &fimc->state)) {
  1328. spin_unlock_irqrestore(&fimc->slock, flags);
  1329. return 0;
  1330. }
  1331. flite_hw_reset(fimc);
  1332. spin_unlock_irqrestore(&fimc->slock, flags);
  1333. if (!test_and_clear_bit(ST_FLITE_SUSPENDED, &fimc->state))
  1334. return 0;
  1335. INIT_LIST_HEAD(&fimc->active_buf_q);
  1336. fimc_pipeline_call(&fimc->ve, open,
  1337. &fimc->ve.vdev.entity, false);
  1338. fimc_lite_hw_init(fimc, atomic_read(&fimc->out_path) == FIMC_IO_ISP);
  1339. clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
  1340. for (i = 0; i < fimc->reqbufs_count; i++) {
  1341. if (list_empty(&fimc->pending_buf_q))
  1342. break;
  1343. buf = fimc_lite_pending_queue_pop(fimc);
  1344. buffer_queue(&buf->vb);
  1345. }
  1346. return 0;
  1347. }
  1348. static int fimc_lite_suspend(struct device *dev)
  1349. {
  1350. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1351. bool suspend = test_bit(ST_FLITE_IN_USE, &fimc->state);
  1352. int ret;
  1353. if (test_and_set_bit(ST_LPM, &fimc->state))
  1354. return 0;
  1355. ret = fimc_lite_stop_capture(fimc, suspend);
  1356. if (ret < 0 || !fimc_lite_active(fimc))
  1357. return ret;
  1358. return fimc_pipeline_call(&fimc->ve, close);
  1359. }
  1360. #endif /* CONFIG_PM_SLEEP */
  1361. static int fimc_lite_remove(struct platform_device *pdev)
  1362. {
  1363. struct fimc_lite *fimc = platform_get_drvdata(pdev);
  1364. struct device *dev = &pdev->dev;
  1365. pm_runtime_disable(dev);
  1366. pm_runtime_set_suspended(dev);
  1367. fimc_lite_unregister_capture_subdev(fimc);
  1368. vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
  1369. fimc_lite_clk_put(fimc);
  1370. dev_info(dev, "Driver unloaded\n");
  1371. return 0;
  1372. }
  1373. static const struct dev_pm_ops fimc_lite_pm_ops = {
  1374. SET_SYSTEM_SLEEP_PM_OPS(fimc_lite_suspend, fimc_lite_resume)
  1375. SET_RUNTIME_PM_OPS(fimc_lite_runtime_suspend, fimc_lite_runtime_resume,
  1376. NULL)
  1377. };
  1378. /* EXYNOS4212, EXYNOS4412 */
  1379. static struct flite_drvdata fimc_lite_drvdata_exynos4 = {
  1380. .max_width = 8192,
  1381. .max_height = 8192,
  1382. .out_width_align = 8,
  1383. .win_hor_offs_align = 2,
  1384. .out_hor_offs_align = 8,
  1385. .max_dma_bufs = 1,
  1386. .num_instances = 2,
  1387. };
  1388. /* EXYNOS5250 */
  1389. static struct flite_drvdata fimc_lite_drvdata_exynos5 = {
  1390. .max_width = 8192,
  1391. .max_height = 8192,
  1392. .out_width_align = 8,
  1393. .win_hor_offs_align = 2,
  1394. .out_hor_offs_align = 8,
  1395. .max_dma_bufs = 32,
  1396. .num_instances = 3,
  1397. };
  1398. static const struct of_device_id flite_of_match[] = {
  1399. {
  1400. .compatible = "samsung,exynos4212-fimc-lite",
  1401. .data = &fimc_lite_drvdata_exynos4,
  1402. },
  1403. {
  1404. .compatible = "samsung,exynos5250-fimc-lite",
  1405. .data = &fimc_lite_drvdata_exynos5,
  1406. },
  1407. { /* sentinel */ },
  1408. };
  1409. MODULE_DEVICE_TABLE(of, flite_of_match);
  1410. static struct platform_driver fimc_lite_driver = {
  1411. .probe = fimc_lite_probe,
  1412. .remove = fimc_lite_remove,
  1413. .driver = {
  1414. .of_match_table = flite_of_match,
  1415. .name = FIMC_LITE_DRV_NAME,
  1416. .owner = THIS_MODULE,
  1417. .pm = &fimc_lite_pm_ops,
  1418. }
  1419. };
  1420. module_platform_driver(fimc_lite_driver);
  1421. MODULE_LICENSE("GPL");
  1422. MODULE_ALIAS("platform:" FIMC_LITE_DRV_NAME);