qla_init.c 146 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_gbl.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <linux/vmalloc.h>
  12. #include "qla_devtbl.h"
  13. #ifdef CONFIG_SPARC
  14. #include <asm/prom.h>
  15. #endif
  16. /*
  17. * QLogic ISP2x00 Hardware Support Function Prototypes.
  18. */
  19. static int qla2x00_isp_firmware(scsi_qla_host_t *);
  20. static int qla2x00_setup_chip(scsi_qla_host_t *);
  21. static int qla2x00_init_rings(scsi_qla_host_t *);
  22. static int qla2x00_fw_ready(scsi_qla_host_t *);
  23. static int qla2x00_configure_hba(scsi_qla_host_t *);
  24. static int qla2x00_configure_loop(scsi_qla_host_t *);
  25. static int qla2x00_configure_local_loop(scsi_qla_host_t *);
  26. static int qla2x00_configure_fabric(scsi_qla_host_t *);
  27. static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
  28. static int qla2x00_device_resync(scsi_qla_host_t *);
  29. static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
  30. uint16_t *);
  31. static int qla2x00_restart_isp(scsi_qla_host_t *);
  32. static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
  33. static int qla84xx_init_chip(scsi_qla_host_t *);
  34. static int qla25xx_init_queues(struct qla_hw_data *);
  35. /* SRB Extensions ---------------------------------------------------------- */
  36. static void
  37. qla2x00_ctx_sp_timeout(unsigned long __data)
  38. {
  39. srb_t *sp = (srb_t *)__data;
  40. struct srb_ctx *ctx;
  41. struct srb_iocb *iocb;
  42. fc_port_t *fcport = sp->fcport;
  43. struct qla_hw_data *ha = fcport->vha->hw;
  44. struct req_que *req;
  45. unsigned long flags;
  46. spin_lock_irqsave(&ha->hardware_lock, flags);
  47. req = ha->req_q_map[0];
  48. req->outstanding_cmds[sp->handle] = NULL;
  49. ctx = sp->ctx;
  50. iocb = ctx->u.iocb_cmd;
  51. iocb->timeout(sp);
  52. iocb->free(sp);
  53. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  54. }
  55. static void
  56. qla2x00_ctx_sp_free(srb_t *sp)
  57. {
  58. struct srb_ctx *ctx = sp->ctx;
  59. struct srb_iocb *iocb = ctx->u.iocb_cmd;
  60. struct scsi_qla_host *vha = sp->fcport->vha;
  61. del_timer(&iocb->timer);
  62. kfree(iocb);
  63. kfree(ctx);
  64. mempool_free(sp, sp->fcport->vha->hw->srb_mempool);
  65. QLA_VHA_MARK_NOT_BUSY(vha);
  66. }
  67. inline srb_t *
  68. qla2x00_get_ctx_sp(scsi_qla_host_t *vha, fc_port_t *fcport, size_t size,
  69. unsigned long tmo)
  70. {
  71. srb_t *sp = NULL;
  72. struct qla_hw_data *ha = vha->hw;
  73. struct srb_ctx *ctx;
  74. struct srb_iocb *iocb;
  75. uint8_t bail;
  76. QLA_VHA_MARK_BUSY(vha, bail);
  77. if (bail)
  78. return NULL;
  79. sp = mempool_alloc(ha->srb_mempool, GFP_KERNEL);
  80. if (!sp)
  81. goto done;
  82. ctx = kzalloc(size, GFP_KERNEL);
  83. if (!ctx) {
  84. mempool_free(sp, ha->srb_mempool);
  85. sp = NULL;
  86. goto done;
  87. }
  88. iocb = kzalloc(sizeof(struct srb_iocb), GFP_KERNEL);
  89. if (!iocb) {
  90. mempool_free(sp, ha->srb_mempool);
  91. sp = NULL;
  92. kfree(ctx);
  93. goto done;
  94. }
  95. memset(sp, 0, sizeof(*sp));
  96. sp->fcport = fcport;
  97. sp->ctx = ctx;
  98. ctx->u.iocb_cmd = iocb;
  99. iocb->free = qla2x00_ctx_sp_free;
  100. init_timer(&iocb->timer);
  101. if (!tmo)
  102. goto done;
  103. iocb->timer.expires = jiffies + tmo * HZ;
  104. iocb->timer.data = (unsigned long)sp;
  105. iocb->timer.function = qla2x00_ctx_sp_timeout;
  106. add_timer(&iocb->timer);
  107. done:
  108. if (!sp)
  109. QLA_VHA_MARK_NOT_BUSY(vha);
  110. return sp;
  111. }
  112. /* Asynchronous Login/Logout Routines -------------------------------------- */
  113. static inline unsigned long
  114. qla2x00_get_async_timeout(struct scsi_qla_host *vha)
  115. {
  116. unsigned long tmo;
  117. struct qla_hw_data *ha = vha->hw;
  118. /* Firmware should use switch negotiated r_a_tov for timeout. */
  119. tmo = ha->r_a_tov / 10 * 2;
  120. if (!IS_FWI2_CAPABLE(ha)) {
  121. /*
  122. * Except for earlier ISPs where the timeout is seeded from the
  123. * initialization control block.
  124. */
  125. tmo = ha->login_timeout;
  126. }
  127. return tmo;
  128. }
  129. static void
  130. qla2x00_async_iocb_timeout(srb_t *sp)
  131. {
  132. fc_port_t *fcport = sp->fcport;
  133. struct srb_ctx *ctx = sp->ctx;
  134. ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
  135. "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
  136. ctx->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
  137. fcport->d_id.b.al_pa);
  138. fcport->flags &= ~FCF_ASYNC_SENT;
  139. if (ctx->type == SRB_LOGIN_CMD) {
  140. struct srb_iocb *lio = ctx->u.iocb_cmd;
  141. qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
  142. /* Retry as needed. */
  143. lio->u.logio.data[0] = MBS_COMMAND_ERROR;
  144. lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  145. QLA_LOGIO_LOGIN_RETRIED : 0;
  146. qla2x00_post_async_login_done_work(fcport->vha, fcport,
  147. lio->u.logio.data);
  148. }
  149. }
  150. static void
  151. qla2x00_async_login_ctx_done(srb_t *sp)
  152. {
  153. struct srb_ctx *ctx = sp->ctx;
  154. struct srb_iocb *lio = ctx->u.iocb_cmd;
  155. qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
  156. lio->u.logio.data);
  157. lio->free(sp);
  158. }
  159. int
  160. qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
  161. uint16_t *data)
  162. {
  163. srb_t *sp;
  164. struct srb_ctx *ctx;
  165. struct srb_iocb *lio;
  166. int rval;
  167. rval = QLA_FUNCTION_FAILED;
  168. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  169. qla2x00_get_async_timeout(vha) + 2);
  170. if (!sp)
  171. goto done;
  172. ctx = sp->ctx;
  173. ctx->type = SRB_LOGIN_CMD;
  174. ctx->name = "login";
  175. lio = ctx->u.iocb_cmd;
  176. lio->timeout = qla2x00_async_iocb_timeout;
  177. lio->done = qla2x00_async_login_ctx_done;
  178. lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
  179. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  180. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  181. rval = qla2x00_start_sp(sp);
  182. if (rval != QLA_SUCCESS)
  183. goto done_free_sp;
  184. ql_dbg(ql_dbg_disc, vha, 0x2072,
  185. "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
  186. "retries=%d.\n", sp->handle, fcport->loop_id,
  187. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  188. fcport->login_retry);
  189. return rval;
  190. done_free_sp:
  191. lio->free(sp);
  192. done:
  193. return rval;
  194. }
  195. static void
  196. qla2x00_async_logout_ctx_done(srb_t *sp)
  197. {
  198. struct srb_ctx *ctx = sp->ctx;
  199. struct srb_iocb *lio = ctx->u.iocb_cmd;
  200. qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
  201. lio->u.logio.data);
  202. lio->free(sp);
  203. }
  204. int
  205. qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
  206. {
  207. srb_t *sp;
  208. struct srb_ctx *ctx;
  209. struct srb_iocb *lio;
  210. int rval;
  211. rval = QLA_FUNCTION_FAILED;
  212. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  213. qla2x00_get_async_timeout(vha) + 2);
  214. if (!sp)
  215. goto done;
  216. ctx = sp->ctx;
  217. ctx->type = SRB_LOGOUT_CMD;
  218. ctx->name = "logout";
  219. lio = ctx->u.iocb_cmd;
  220. lio->timeout = qla2x00_async_iocb_timeout;
  221. lio->done = qla2x00_async_logout_ctx_done;
  222. rval = qla2x00_start_sp(sp);
  223. if (rval != QLA_SUCCESS)
  224. goto done_free_sp;
  225. ql_dbg(ql_dbg_disc, vha, 0x2070,
  226. "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
  227. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  228. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  229. return rval;
  230. done_free_sp:
  231. lio->free(sp);
  232. done:
  233. return rval;
  234. }
  235. static void
  236. qla2x00_async_adisc_ctx_done(srb_t *sp)
  237. {
  238. struct srb_ctx *ctx = sp->ctx;
  239. struct srb_iocb *lio = ctx->u.iocb_cmd;
  240. qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
  241. lio->u.logio.data);
  242. lio->free(sp);
  243. }
  244. int
  245. qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
  246. uint16_t *data)
  247. {
  248. srb_t *sp;
  249. struct srb_ctx *ctx;
  250. struct srb_iocb *lio;
  251. int rval;
  252. rval = QLA_FUNCTION_FAILED;
  253. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  254. qla2x00_get_async_timeout(vha) + 2);
  255. if (!sp)
  256. goto done;
  257. ctx = sp->ctx;
  258. ctx->type = SRB_ADISC_CMD;
  259. ctx->name = "adisc";
  260. lio = ctx->u.iocb_cmd;
  261. lio->timeout = qla2x00_async_iocb_timeout;
  262. lio->done = qla2x00_async_adisc_ctx_done;
  263. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  264. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  265. rval = qla2x00_start_sp(sp);
  266. if (rval != QLA_SUCCESS)
  267. goto done_free_sp;
  268. ql_dbg(ql_dbg_disc, vha, 0x206f,
  269. "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
  270. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  271. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  272. return rval;
  273. done_free_sp:
  274. lio->free(sp);
  275. done:
  276. return rval;
  277. }
  278. static void
  279. qla2x00_async_tm_cmd_ctx_done(srb_t *sp)
  280. {
  281. struct srb_ctx *ctx = sp->ctx;
  282. struct srb_iocb *iocb = (struct srb_iocb *)ctx->u.iocb_cmd;
  283. qla2x00_async_tm_cmd_done(sp->fcport->vha, sp->fcport, iocb);
  284. iocb->free(sp);
  285. }
  286. int
  287. qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
  288. uint32_t tag)
  289. {
  290. struct scsi_qla_host *vha = fcport->vha;
  291. srb_t *sp;
  292. struct srb_ctx *ctx;
  293. struct srb_iocb *tcf;
  294. int rval;
  295. rval = QLA_FUNCTION_FAILED;
  296. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  297. qla2x00_get_async_timeout(vha) + 2);
  298. if (!sp)
  299. goto done;
  300. ctx = sp->ctx;
  301. ctx->type = SRB_TM_CMD;
  302. ctx->name = "tmf";
  303. tcf = ctx->u.iocb_cmd;
  304. tcf->u.tmf.flags = flags;
  305. tcf->u.tmf.lun = lun;
  306. tcf->u.tmf.data = tag;
  307. tcf->timeout = qla2x00_async_iocb_timeout;
  308. tcf->done = qla2x00_async_tm_cmd_ctx_done;
  309. rval = qla2x00_start_sp(sp);
  310. if (rval != QLA_SUCCESS)
  311. goto done_free_sp;
  312. ql_dbg(ql_dbg_taskm, vha, 0x802f,
  313. "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
  314. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  315. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  316. return rval;
  317. done_free_sp:
  318. tcf->free(sp);
  319. done:
  320. return rval;
  321. }
  322. void
  323. qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  324. uint16_t *data)
  325. {
  326. int rval;
  327. switch (data[0]) {
  328. case MBS_COMMAND_COMPLETE:
  329. /*
  330. * Driver must validate login state - If PRLI not complete,
  331. * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
  332. * requests.
  333. */
  334. rval = qla2x00_get_port_database(vha, fcport, 0);
  335. if (rval != QLA_SUCCESS) {
  336. qla2x00_post_async_logout_work(vha, fcport, NULL);
  337. qla2x00_post_async_login_work(vha, fcport, NULL);
  338. break;
  339. }
  340. if (fcport->flags & FCF_FCP2_DEVICE) {
  341. qla2x00_post_async_adisc_work(vha, fcport, data);
  342. break;
  343. }
  344. qla2x00_update_fcport(vha, fcport);
  345. break;
  346. case MBS_COMMAND_ERROR:
  347. fcport->flags &= ~FCF_ASYNC_SENT;
  348. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  349. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  350. else
  351. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  352. break;
  353. case MBS_PORT_ID_USED:
  354. fcport->loop_id = data[1];
  355. qla2x00_post_async_logout_work(vha, fcport, NULL);
  356. qla2x00_post_async_login_work(vha, fcport, NULL);
  357. break;
  358. case MBS_LOOP_ID_USED:
  359. fcport->loop_id++;
  360. rval = qla2x00_find_new_loop_id(vha, fcport);
  361. if (rval != QLA_SUCCESS) {
  362. fcport->flags &= ~FCF_ASYNC_SENT;
  363. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  364. break;
  365. }
  366. qla2x00_post_async_login_work(vha, fcport, NULL);
  367. break;
  368. }
  369. return;
  370. }
  371. void
  372. qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  373. uint16_t *data)
  374. {
  375. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  376. return;
  377. }
  378. void
  379. qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  380. uint16_t *data)
  381. {
  382. if (data[0] == MBS_COMMAND_COMPLETE) {
  383. qla2x00_update_fcport(vha, fcport);
  384. return;
  385. }
  386. /* Retry login. */
  387. fcport->flags &= ~FCF_ASYNC_SENT;
  388. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  389. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  390. else
  391. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  392. return;
  393. }
  394. void
  395. qla2x00_async_tm_cmd_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  396. struct srb_iocb *iocb)
  397. {
  398. int rval;
  399. uint32_t flags;
  400. uint16_t lun;
  401. flags = iocb->u.tmf.flags;
  402. lun = (uint16_t)iocb->u.tmf.lun;
  403. /* Issue Marker IOCB */
  404. rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
  405. vha->hw->rsp_q_map[0], fcport->loop_id, lun,
  406. flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
  407. if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
  408. ql_dbg(ql_dbg_taskm, vha, 0x8030,
  409. "TM IOCB failed (%x).\n", rval);
  410. }
  411. return;
  412. }
  413. /****************************************************************************/
  414. /* QLogic ISP2x00 Hardware Support Functions. */
  415. /****************************************************************************/
  416. /*
  417. * qla2x00_initialize_adapter
  418. * Initialize board.
  419. *
  420. * Input:
  421. * ha = adapter block pointer.
  422. *
  423. * Returns:
  424. * 0 = success
  425. */
  426. int
  427. qla2x00_initialize_adapter(scsi_qla_host_t *vha)
  428. {
  429. int rval;
  430. struct qla_hw_data *ha = vha->hw;
  431. struct req_que *req = ha->req_q_map[0];
  432. /* Clear adapter flags. */
  433. vha->flags.online = 0;
  434. ha->flags.chip_reset_done = 0;
  435. vha->flags.reset_active = 0;
  436. ha->flags.pci_channel_io_perm_failure = 0;
  437. ha->flags.eeh_busy = 0;
  438. ha->flags.thermal_supported = 1;
  439. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  440. atomic_set(&vha->loop_state, LOOP_DOWN);
  441. vha->device_flags = DFLG_NO_CABLE;
  442. vha->dpc_flags = 0;
  443. vha->flags.management_server_logged_in = 0;
  444. vha->marker_needed = 0;
  445. ha->isp_abort_cnt = 0;
  446. ha->beacon_blink_led = 0;
  447. set_bit(0, ha->req_qid_map);
  448. set_bit(0, ha->rsp_qid_map);
  449. ql_dbg(ql_dbg_init, vha, 0x0040,
  450. "Configuring PCI space...\n");
  451. rval = ha->isp_ops->pci_config(vha);
  452. if (rval) {
  453. ql_log(ql_log_warn, vha, 0x0044,
  454. "Unable to configure PCI space.\n");
  455. return (rval);
  456. }
  457. ha->isp_ops->reset_chip(vha);
  458. rval = qla2xxx_get_flash_info(vha);
  459. if (rval) {
  460. ql_log(ql_log_fatal, vha, 0x004f,
  461. "Unable to validate FLASH data.\n");
  462. return (rval);
  463. }
  464. ha->isp_ops->get_flash_version(vha, req->ring);
  465. ql_dbg(ql_dbg_init, vha, 0x0061,
  466. "Configure NVRAM parameters...\n");
  467. ha->isp_ops->nvram_config(vha);
  468. if (ha->flags.disable_serdes) {
  469. /* Mask HBA via NVRAM settings? */
  470. ql_log(ql_log_info, vha, 0x0077,
  471. "Masking HBA WWPN "
  472. "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
  473. vha->port_name[0], vha->port_name[1],
  474. vha->port_name[2], vha->port_name[3],
  475. vha->port_name[4], vha->port_name[5],
  476. vha->port_name[6], vha->port_name[7]);
  477. return QLA_FUNCTION_FAILED;
  478. }
  479. ql_dbg(ql_dbg_init, vha, 0x0078,
  480. "Verifying loaded RISC code...\n");
  481. if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
  482. rval = ha->isp_ops->chip_diag(vha);
  483. if (rval)
  484. return (rval);
  485. rval = qla2x00_setup_chip(vha);
  486. if (rval)
  487. return (rval);
  488. }
  489. if (IS_QLA84XX(ha)) {
  490. ha->cs84xx = qla84xx_get_chip(vha);
  491. if (!ha->cs84xx) {
  492. ql_log(ql_log_warn, vha, 0x00d0,
  493. "Unable to configure ISP84XX.\n");
  494. return QLA_FUNCTION_FAILED;
  495. }
  496. }
  497. rval = qla2x00_init_rings(vha);
  498. ha->flags.chip_reset_done = 1;
  499. if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
  500. /* Issue verify 84xx FW IOCB to complete 84xx initialization */
  501. rval = qla84xx_init_chip(vha);
  502. if (rval != QLA_SUCCESS) {
  503. ql_log(ql_log_warn, vha, 0x00d4,
  504. "Unable to initialize ISP84XX.\n");
  505. qla84xx_put_chip(vha);
  506. }
  507. }
  508. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
  509. qla24xx_read_fcp_prio_cfg(vha);
  510. return (rval);
  511. }
  512. /**
  513. * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
  514. * @ha: HA context
  515. *
  516. * Returns 0 on success.
  517. */
  518. int
  519. qla2100_pci_config(scsi_qla_host_t *vha)
  520. {
  521. uint16_t w;
  522. unsigned long flags;
  523. struct qla_hw_data *ha = vha->hw;
  524. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  525. pci_set_master(ha->pdev);
  526. pci_try_set_mwi(ha->pdev);
  527. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  528. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  529. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  530. pci_disable_rom(ha->pdev);
  531. /* Get PCI bus information. */
  532. spin_lock_irqsave(&ha->hardware_lock, flags);
  533. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  534. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  535. return QLA_SUCCESS;
  536. }
  537. /**
  538. * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
  539. * @ha: HA context
  540. *
  541. * Returns 0 on success.
  542. */
  543. int
  544. qla2300_pci_config(scsi_qla_host_t *vha)
  545. {
  546. uint16_t w;
  547. unsigned long flags = 0;
  548. uint32_t cnt;
  549. struct qla_hw_data *ha = vha->hw;
  550. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  551. pci_set_master(ha->pdev);
  552. pci_try_set_mwi(ha->pdev);
  553. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  554. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  555. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  556. w &= ~PCI_COMMAND_INTX_DISABLE;
  557. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  558. /*
  559. * If this is a 2300 card and not 2312, reset the
  560. * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
  561. * the 2310 also reports itself as a 2300 so we need to get the
  562. * fb revision level -- a 6 indicates it really is a 2300 and
  563. * not a 2310.
  564. */
  565. if (IS_QLA2300(ha)) {
  566. spin_lock_irqsave(&ha->hardware_lock, flags);
  567. /* Pause RISC. */
  568. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  569. for (cnt = 0; cnt < 30000; cnt++) {
  570. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
  571. break;
  572. udelay(10);
  573. }
  574. /* Select FPM registers. */
  575. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  576. RD_REG_WORD(&reg->ctrl_status);
  577. /* Get the fb rev level */
  578. ha->fb_rev = RD_FB_CMD_REG(ha, reg);
  579. if (ha->fb_rev == FPM_2300)
  580. pci_clear_mwi(ha->pdev);
  581. /* Deselect FPM registers. */
  582. WRT_REG_WORD(&reg->ctrl_status, 0x0);
  583. RD_REG_WORD(&reg->ctrl_status);
  584. /* Release RISC module. */
  585. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  586. for (cnt = 0; cnt < 30000; cnt++) {
  587. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
  588. break;
  589. udelay(10);
  590. }
  591. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  592. }
  593. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  594. pci_disable_rom(ha->pdev);
  595. /* Get PCI bus information. */
  596. spin_lock_irqsave(&ha->hardware_lock, flags);
  597. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  598. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  599. return QLA_SUCCESS;
  600. }
  601. /**
  602. * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
  603. * @ha: HA context
  604. *
  605. * Returns 0 on success.
  606. */
  607. int
  608. qla24xx_pci_config(scsi_qla_host_t *vha)
  609. {
  610. uint16_t w;
  611. unsigned long flags = 0;
  612. struct qla_hw_data *ha = vha->hw;
  613. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  614. pci_set_master(ha->pdev);
  615. pci_try_set_mwi(ha->pdev);
  616. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  617. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  618. w &= ~PCI_COMMAND_INTX_DISABLE;
  619. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  620. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  621. /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
  622. if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
  623. pcix_set_mmrbc(ha->pdev, 2048);
  624. /* PCIe -- adjust Maximum Read Request Size (2048). */
  625. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  626. pcie_set_readrq(ha->pdev, 2048);
  627. pci_disable_rom(ha->pdev);
  628. ha->chip_revision = ha->pdev->revision;
  629. /* Get PCI bus information. */
  630. spin_lock_irqsave(&ha->hardware_lock, flags);
  631. ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
  632. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  633. return QLA_SUCCESS;
  634. }
  635. /**
  636. * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
  637. * @ha: HA context
  638. *
  639. * Returns 0 on success.
  640. */
  641. int
  642. qla25xx_pci_config(scsi_qla_host_t *vha)
  643. {
  644. uint16_t w;
  645. struct qla_hw_data *ha = vha->hw;
  646. pci_set_master(ha->pdev);
  647. pci_try_set_mwi(ha->pdev);
  648. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  649. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  650. w &= ~PCI_COMMAND_INTX_DISABLE;
  651. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  652. /* PCIe -- adjust Maximum Read Request Size (2048). */
  653. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  654. pcie_set_readrq(ha->pdev, 2048);
  655. pci_disable_rom(ha->pdev);
  656. ha->chip_revision = ha->pdev->revision;
  657. return QLA_SUCCESS;
  658. }
  659. /**
  660. * qla2x00_isp_firmware() - Choose firmware image.
  661. * @ha: HA context
  662. *
  663. * Returns 0 on success.
  664. */
  665. static int
  666. qla2x00_isp_firmware(scsi_qla_host_t *vha)
  667. {
  668. int rval;
  669. uint16_t loop_id, topo, sw_cap;
  670. uint8_t domain, area, al_pa;
  671. struct qla_hw_data *ha = vha->hw;
  672. /* Assume loading risc code */
  673. rval = QLA_FUNCTION_FAILED;
  674. if (ha->flags.disable_risc_code_load) {
  675. ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
  676. /* Verify checksum of loaded RISC code. */
  677. rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
  678. if (rval == QLA_SUCCESS) {
  679. /* And, verify we are not in ROM code. */
  680. rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
  681. &area, &domain, &topo, &sw_cap);
  682. }
  683. }
  684. if (rval)
  685. ql_dbg(ql_dbg_init, vha, 0x007a,
  686. "**** Load RISC code ****.\n");
  687. return (rval);
  688. }
  689. /**
  690. * qla2x00_reset_chip() - Reset ISP chip.
  691. * @ha: HA context
  692. *
  693. * Returns 0 on success.
  694. */
  695. void
  696. qla2x00_reset_chip(scsi_qla_host_t *vha)
  697. {
  698. unsigned long flags = 0;
  699. struct qla_hw_data *ha = vha->hw;
  700. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  701. uint32_t cnt;
  702. uint16_t cmd;
  703. if (unlikely(pci_channel_offline(ha->pdev)))
  704. return;
  705. ha->isp_ops->disable_intrs(ha);
  706. spin_lock_irqsave(&ha->hardware_lock, flags);
  707. /* Turn off master enable */
  708. cmd = 0;
  709. pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
  710. cmd &= ~PCI_COMMAND_MASTER;
  711. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  712. if (!IS_QLA2100(ha)) {
  713. /* Pause RISC. */
  714. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  715. if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
  716. for (cnt = 0; cnt < 30000; cnt++) {
  717. if ((RD_REG_WORD(&reg->hccr) &
  718. HCCR_RISC_PAUSE) != 0)
  719. break;
  720. udelay(100);
  721. }
  722. } else {
  723. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  724. udelay(10);
  725. }
  726. /* Select FPM registers. */
  727. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  728. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  729. /* FPM Soft Reset. */
  730. WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
  731. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  732. /* Toggle Fpm Reset. */
  733. if (!IS_QLA2200(ha)) {
  734. WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
  735. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  736. }
  737. /* Select frame buffer registers. */
  738. WRT_REG_WORD(&reg->ctrl_status, 0x10);
  739. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  740. /* Reset frame buffer FIFOs. */
  741. if (IS_QLA2200(ha)) {
  742. WRT_FB_CMD_REG(ha, reg, 0xa000);
  743. RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
  744. } else {
  745. WRT_FB_CMD_REG(ha, reg, 0x00fc);
  746. /* Read back fb_cmd until zero or 3 seconds max */
  747. for (cnt = 0; cnt < 3000; cnt++) {
  748. if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
  749. break;
  750. udelay(100);
  751. }
  752. }
  753. /* Select RISC module registers. */
  754. WRT_REG_WORD(&reg->ctrl_status, 0);
  755. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  756. /* Reset RISC processor. */
  757. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  758. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  759. /* Release RISC processor. */
  760. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  761. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  762. }
  763. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  764. WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
  765. /* Reset ISP chip. */
  766. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  767. /* Wait for RISC to recover from reset. */
  768. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  769. /*
  770. * It is necessary to for a delay here since the card doesn't
  771. * respond to PCI reads during a reset. On some architectures
  772. * this will result in an MCA.
  773. */
  774. udelay(20);
  775. for (cnt = 30000; cnt; cnt--) {
  776. if ((RD_REG_WORD(&reg->ctrl_status) &
  777. CSR_ISP_SOFT_RESET) == 0)
  778. break;
  779. udelay(100);
  780. }
  781. } else
  782. udelay(10);
  783. /* Reset RISC processor. */
  784. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  785. WRT_REG_WORD(&reg->semaphore, 0);
  786. /* Release RISC processor. */
  787. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  788. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  789. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  790. for (cnt = 0; cnt < 30000; cnt++) {
  791. if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
  792. break;
  793. udelay(100);
  794. }
  795. } else
  796. udelay(100);
  797. /* Turn on master enable */
  798. cmd |= PCI_COMMAND_MASTER;
  799. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  800. /* Disable RISC pause on FPM parity error. */
  801. if (!IS_QLA2100(ha)) {
  802. WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
  803. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  804. }
  805. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  806. }
  807. /**
  808. * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
  809. *
  810. * Returns 0 on success.
  811. */
  812. int
  813. qla81xx_reset_mpi(scsi_qla_host_t *vha)
  814. {
  815. uint16_t mb[4] = {0x1010, 0, 1, 0};
  816. return qla81xx_write_mpi_register(vha, mb);
  817. }
  818. /**
  819. * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
  820. * @ha: HA context
  821. *
  822. * Returns 0 on success.
  823. */
  824. static inline void
  825. qla24xx_reset_risc(scsi_qla_host_t *vha)
  826. {
  827. unsigned long flags = 0;
  828. struct qla_hw_data *ha = vha->hw;
  829. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  830. uint32_t cnt, d2;
  831. uint16_t wd;
  832. static int abts_cnt; /* ISP abort retry counts */
  833. spin_lock_irqsave(&ha->hardware_lock, flags);
  834. /* Reset RISC. */
  835. WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  836. for (cnt = 0; cnt < 30000; cnt++) {
  837. if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
  838. break;
  839. udelay(10);
  840. }
  841. WRT_REG_DWORD(&reg->ctrl_status,
  842. CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  843. pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
  844. udelay(100);
  845. /* Wait for firmware to complete NVRAM accesses. */
  846. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  847. for (cnt = 10000 ; cnt && d2; cnt--) {
  848. udelay(5);
  849. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  850. barrier();
  851. }
  852. /* Wait for soft-reset to complete. */
  853. d2 = RD_REG_DWORD(&reg->ctrl_status);
  854. for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
  855. udelay(5);
  856. d2 = RD_REG_DWORD(&reg->ctrl_status);
  857. barrier();
  858. }
  859. /* If required, do an MPI FW reset now */
  860. if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
  861. if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
  862. if (++abts_cnt < 5) {
  863. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  864. set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
  865. } else {
  866. /*
  867. * We exhausted the ISP abort retries. We have to
  868. * set the board offline.
  869. */
  870. abts_cnt = 0;
  871. vha->flags.online = 0;
  872. }
  873. }
  874. }
  875. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  876. RD_REG_DWORD(&reg->hccr);
  877. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  878. RD_REG_DWORD(&reg->hccr);
  879. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
  880. RD_REG_DWORD(&reg->hccr);
  881. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  882. for (cnt = 6000000 ; cnt && d2; cnt--) {
  883. udelay(5);
  884. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  885. barrier();
  886. }
  887. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  888. if (IS_NOPOLLING_TYPE(ha))
  889. ha->isp_ops->enable_intrs(ha);
  890. }
  891. /**
  892. * qla24xx_reset_chip() - Reset ISP24xx chip.
  893. * @ha: HA context
  894. *
  895. * Returns 0 on success.
  896. */
  897. void
  898. qla24xx_reset_chip(scsi_qla_host_t *vha)
  899. {
  900. struct qla_hw_data *ha = vha->hw;
  901. if (pci_channel_offline(ha->pdev) &&
  902. ha->flags.pci_channel_io_perm_failure) {
  903. return;
  904. }
  905. ha->isp_ops->disable_intrs(ha);
  906. /* Perform RISC reset. */
  907. qla24xx_reset_risc(vha);
  908. }
  909. /**
  910. * qla2x00_chip_diag() - Test chip for proper operation.
  911. * @ha: HA context
  912. *
  913. * Returns 0 on success.
  914. */
  915. int
  916. qla2x00_chip_diag(scsi_qla_host_t *vha)
  917. {
  918. int rval;
  919. struct qla_hw_data *ha = vha->hw;
  920. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  921. unsigned long flags = 0;
  922. uint16_t data;
  923. uint32_t cnt;
  924. uint16_t mb[5];
  925. struct req_que *req = ha->req_q_map[0];
  926. /* Assume a failed state */
  927. rval = QLA_FUNCTION_FAILED;
  928. ql_dbg(ql_dbg_init, vha, 0x007b,
  929. "Testing device at %lx.\n", (u_long)&reg->flash_address);
  930. spin_lock_irqsave(&ha->hardware_lock, flags);
  931. /* Reset ISP chip. */
  932. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  933. /*
  934. * We need to have a delay here since the card will not respond while
  935. * in reset causing an MCA on some architectures.
  936. */
  937. udelay(20);
  938. data = qla2x00_debounce_register(&reg->ctrl_status);
  939. for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
  940. udelay(5);
  941. data = RD_REG_WORD(&reg->ctrl_status);
  942. barrier();
  943. }
  944. if (!cnt)
  945. goto chip_diag_failed;
  946. ql_dbg(ql_dbg_init, vha, 0x007c,
  947. "Reset register cleared by chip reset.\n");
  948. /* Reset RISC processor. */
  949. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  950. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  951. /* Workaround for QLA2312 PCI parity error */
  952. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  953. data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
  954. for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
  955. udelay(5);
  956. data = RD_MAILBOX_REG(ha, reg, 0);
  957. barrier();
  958. }
  959. } else
  960. udelay(10);
  961. if (!cnt)
  962. goto chip_diag_failed;
  963. /* Check product ID of chip */
  964. ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
  965. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  966. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  967. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  968. mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
  969. if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
  970. mb[3] != PROD_ID_3) {
  971. ql_log(ql_log_warn, vha, 0x0062,
  972. "Wrong product ID = 0x%x,0x%x,0x%x.\n",
  973. mb[1], mb[2], mb[3]);
  974. goto chip_diag_failed;
  975. }
  976. ha->product_id[0] = mb[1];
  977. ha->product_id[1] = mb[2];
  978. ha->product_id[2] = mb[3];
  979. ha->product_id[3] = mb[4];
  980. /* Adjust fw RISC transfer size */
  981. if (req->length > 1024)
  982. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
  983. else
  984. ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
  985. req->length;
  986. if (IS_QLA2200(ha) &&
  987. RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
  988. /* Limit firmware transfer size with a 2200A */
  989. ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
  990. ha->device_type |= DT_ISP2200A;
  991. ha->fw_transfer_size = 128;
  992. }
  993. /* Wrap Incoming Mailboxes Test. */
  994. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  995. ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
  996. rval = qla2x00_mbx_reg_test(vha);
  997. if (rval)
  998. ql_log(ql_log_warn, vha, 0x0080,
  999. "Failed mailbox send register test.\n");
  1000. else
  1001. /* Flag a successful rval */
  1002. rval = QLA_SUCCESS;
  1003. spin_lock_irqsave(&ha->hardware_lock, flags);
  1004. chip_diag_failed:
  1005. if (rval)
  1006. ql_log(ql_log_info, vha, 0x0081,
  1007. "Chip diagnostics **** FAILED ****.\n");
  1008. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1009. return (rval);
  1010. }
  1011. /**
  1012. * qla24xx_chip_diag() - Test ISP24xx for proper operation.
  1013. * @ha: HA context
  1014. *
  1015. * Returns 0 on success.
  1016. */
  1017. int
  1018. qla24xx_chip_diag(scsi_qla_host_t *vha)
  1019. {
  1020. int rval;
  1021. struct qla_hw_data *ha = vha->hw;
  1022. struct req_que *req = ha->req_q_map[0];
  1023. if (IS_QLA82XX(ha))
  1024. return QLA_SUCCESS;
  1025. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  1026. rval = qla2x00_mbx_reg_test(vha);
  1027. if (rval) {
  1028. ql_log(ql_log_warn, vha, 0x0082,
  1029. "Failed mailbox send register test.\n");
  1030. } else {
  1031. /* Flag a successful rval */
  1032. rval = QLA_SUCCESS;
  1033. }
  1034. return rval;
  1035. }
  1036. void
  1037. qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
  1038. {
  1039. int rval;
  1040. uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
  1041. eft_size, fce_size, mq_size;
  1042. dma_addr_t tc_dma;
  1043. void *tc;
  1044. struct qla_hw_data *ha = vha->hw;
  1045. struct req_que *req = ha->req_q_map[0];
  1046. struct rsp_que *rsp = ha->rsp_q_map[0];
  1047. if (ha->fw_dump) {
  1048. ql_dbg(ql_dbg_init, vha, 0x00bd,
  1049. "Firmware dump already allocated.\n");
  1050. return;
  1051. }
  1052. ha->fw_dumped = 0;
  1053. fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
  1054. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  1055. fixed_size = sizeof(struct qla2100_fw_dump);
  1056. } else if (IS_QLA23XX(ha)) {
  1057. fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
  1058. mem_size = (ha->fw_memory_size - 0x11000 + 1) *
  1059. sizeof(uint16_t);
  1060. } else if (IS_FWI2_CAPABLE(ha)) {
  1061. if (IS_QLA81XX(ha))
  1062. fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
  1063. else if (IS_QLA25XX(ha))
  1064. fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
  1065. else
  1066. fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
  1067. mem_size = (ha->fw_memory_size - 0x100000 + 1) *
  1068. sizeof(uint32_t);
  1069. if (ha->mqenable)
  1070. mq_size = sizeof(struct qla2xxx_mq_chain);
  1071. /* Allocate memory for Fibre Channel Event Buffer. */
  1072. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))
  1073. goto try_eft;
  1074. tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
  1075. GFP_KERNEL);
  1076. if (!tc) {
  1077. ql_log(ql_log_warn, vha, 0x00be,
  1078. "Unable to allocate (%d KB) for FCE.\n",
  1079. FCE_SIZE / 1024);
  1080. goto try_eft;
  1081. }
  1082. memset(tc, 0, FCE_SIZE);
  1083. rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
  1084. ha->fce_mb, &ha->fce_bufs);
  1085. if (rval) {
  1086. ql_log(ql_log_warn, vha, 0x00bf,
  1087. "Unable to initialize FCE (%d).\n", rval);
  1088. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
  1089. tc_dma);
  1090. ha->flags.fce_enabled = 0;
  1091. goto try_eft;
  1092. }
  1093. ql_dbg(ql_dbg_init, vha, 0x00c0,
  1094. "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
  1095. fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
  1096. ha->flags.fce_enabled = 1;
  1097. ha->fce_dma = tc_dma;
  1098. ha->fce = tc;
  1099. try_eft:
  1100. /* Allocate memory for Extended Trace Buffer. */
  1101. tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
  1102. GFP_KERNEL);
  1103. if (!tc) {
  1104. ql_log(ql_log_warn, vha, 0x00c1,
  1105. "Unable to allocate (%d KB) for EFT.\n",
  1106. EFT_SIZE / 1024);
  1107. goto cont_alloc;
  1108. }
  1109. memset(tc, 0, EFT_SIZE);
  1110. rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
  1111. if (rval) {
  1112. ql_log(ql_log_warn, vha, 0x00c2,
  1113. "Unable to initialize EFT (%d).\n", rval);
  1114. dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
  1115. tc_dma);
  1116. goto cont_alloc;
  1117. }
  1118. ql_dbg(ql_dbg_init, vha, 0x00c3,
  1119. "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
  1120. eft_size = EFT_SIZE;
  1121. ha->eft_dma = tc_dma;
  1122. ha->eft = tc;
  1123. }
  1124. cont_alloc:
  1125. req_q_size = req->length * sizeof(request_t);
  1126. rsp_q_size = rsp->length * sizeof(response_t);
  1127. dump_size = offsetof(struct qla2xxx_fw_dump, isp);
  1128. dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
  1129. ha->chain_offset = dump_size;
  1130. dump_size += mq_size + fce_size;
  1131. ha->fw_dump = vmalloc(dump_size);
  1132. if (!ha->fw_dump) {
  1133. ql_log(ql_log_warn, vha, 0x00c4,
  1134. "Unable to allocate (%d KB) for firmware dump.\n",
  1135. dump_size / 1024);
  1136. if (ha->fce) {
  1137. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  1138. ha->fce_dma);
  1139. ha->fce = NULL;
  1140. ha->fce_dma = 0;
  1141. }
  1142. if (ha->eft) {
  1143. dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
  1144. ha->eft_dma);
  1145. ha->eft = NULL;
  1146. ha->eft_dma = 0;
  1147. }
  1148. return;
  1149. }
  1150. ql_dbg(ql_dbg_init, vha, 0x00c5,
  1151. "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
  1152. ha->fw_dump_len = dump_size;
  1153. ha->fw_dump->signature[0] = 'Q';
  1154. ha->fw_dump->signature[1] = 'L';
  1155. ha->fw_dump->signature[2] = 'G';
  1156. ha->fw_dump->signature[3] = 'C';
  1157. ha->fw_dump->version = __constant_htonl(1);
  1158. ha->fw_dump->fixed_size = htonl(fixed_size);
  1159. ha->fw_dump->mem_size = htonl(mem_size);
  1160. ha->fw_dump->req_q_size = htonl(req_q_size);
  1161. ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
  1162. ha->fw_dump->eft_size = htonl(eft_size);
  1163. ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
  1164. ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
  1165. ha->fw_dump->header_size =
  1166. htonl(offsetof(struct qla2xxx_fw_dump, isp));
  1167. }
  1168. static int
  1169. qla81xx_mpi_sync(scsi_qla_host_t *vha)
  1170. {
  1171. #define MPS_MASK 0xe0
  1172. int rval;
  1173. uint16_t dc;
  1174. uint32_t dw;
  1175. if (!IS_QLA81XX(vha->hw))
  1176. return QLA_SUCCESS;
  1177. rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
  1178. if (rval != QLA_SUCCESS) {
  1179. ql_log(ql_log_warn, vha, 0x0105,
  1180. "Unable to acquire semaphore.\n");
  1181. goto done;
  1182. }
  1183. pci_read_config_word(vha->hw->pdev, 0x54, &dc);
  1184. rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
  1185. if (rval != QLA_SUCCESS) {
  1186. ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
  1187. goto done_release;
  1188. }
  1189. dc &= MPS_MASK;
  1190. if (dc == (dw & MPS_MASK))
  1191. goto done_release;
  1192. dw &= ~MPS_MASK;
  1193. dw |= dc;
  1194. rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
  1195. if (rval != QLA_SUCCESS) {
  1196. ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
  1197. }
  1198. done_release:
  1199. rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
  1200. if (rval != QLA_SUCCESS) {
  1201. ql_log(ql_log_warn, vha, 0x006d,
  1202. "Unable to release semaphore.\n");
  1203. }
  1204. done:
  1205. return rval;
  1206. }
  1207. /**
  1208. * qla2x00_setup_chip() - Load and start RISC firmware.
  1209. * @ha: HA context
  1210. *
  1211. * Returns 0 on success.
  1212. */
  1213. static int
  1214. qla2x00_setup_chip(scsi_qla_host_t *vha)
  1215. {
  1216. int rval;
  1217. uint32_t srisc_address = 0;
  1218. struct qla_hw_data *ha = vha->hw;
  1219. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1220. unsigned long flags;
  1221. uint16_t fw_major_version;
  1222. if (IS_QLA82XX(ha)) {
  1223. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1224. if (rval == QLA_SUCCESS) {
  1225. qla2x00_stop_firmware(vha);
  1226. goto enable_82xx_npiv;
  1227. } else
  1228. goto failed;
  1229. }
  1230. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1231. /* Disable SRAM, Instruction RAM and GP RAM parity. */
  1232. spin_lock_irqsave(&ha->hardware_lock, flags);
  1233. WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
  1234. RD_REG_WORD(&reg->hccr);
  1235. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1236. }
  1237. qla81xx_mpi_sync(vha);
  1238. /* Load firmware sequences */
  1239. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1240. if (rval == QLA_SUCCESS) {
  1241. ql_dbg(ql_dbg_init, vha, 0x00c9,
  1242. "Verifying Checksum of loaded RISC code.\n");
  1243. rval = qla2x00_verify_checksum(vha, srisc_address);
  1244. if (rval == QLA_SUCCESS) {
  1245. /* Start firmware execution. */
  1246. ql_dbg(ql_dbg_init, vha, 0x00ca,
  1247. "Starting firmware.\n");
  1248. rval = qla2x00_execute_fw(vha, srisc_address);
  1249. /* Retrieve firmware information. */
  1250. if (rval == QLA_SUCCESS) {
  1251. enable_82xx_npiv:
  1252. fw_major_version = ha->fw_major_version;
  1253. if (IS_QLA82XX(ha))
  1254. qla82xx_check_md_needed(vha);
  1255. else {
  1256. rval = qla2x00_get_fw_version(vha,
  1257. &ha->fw_major_version,
  1258. &ha->fw_minor_version,
  1259. &ha->fw_subminor_version,
  1260. &ha->fw_attributes,
  1261. &ha->fw_memory_size,
  1262. ha->mpi_version,
  1263. &ha->mpi_capabilities,
  1264. ha->phy_version);
  1265. }
  1266. if (rval != QLA_SUCCESS)
  1267. goto failed;
  1268. ha->flags.npiv_supported = 0;
  1269. if (IS_QLA2XXX_MIDTYPE(ha) &&
  1270. (ha->fw_attributes & BIT_2)) {
  1271. ha->flags.npiv_supported = 1;
  1272. if ((!ha->max_npiv_vports) ||
  1273. ((ha->max_npiv_vports + 1) %
  1274. MIN_MULTI_ID_FABRIC))
  1275. ha->max_npiv_vports =
  1276. MIN_MULTI_ID_FABRIC - 1;
  1277. }
  1278. qla2x00_get_resource_cnts(vha, NULL,
  1279. &ha->fw_xcb_count, NULL, NULL,
  1280. &ha->max_npiv_vports, NULL);
  1281. if (!fw_major_version && ql2xallocfwdump
  1282. && !IS_QLA82XX(ha))
  1283. qla2x00_alloc_fw_dump(vha);
  1284. }
  1285. } else {
  1286. ql_log(ql_log_fatal, vha, 0x00cd,
  1287. "ISP Firmware failed checksum.\n");
  1288. goto failed;
  1289. }
  1290. }
  1291. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1292. /* Enable proper parity. */
  1293. spin_lock_irqsave(&ha->hardware_lock, flags);
  1294. if (IS_QLA2300(ha))
  1295. /* SRAM parity */
  1296. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
  1297. else
  1298. /* SRAM, Instruction RAM and GP RAM parity */
  1299. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
  1300. RD_REG_WORD(&reg->hccr);
  1301. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1302. }
  1303. if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
  1304. uint32_t size;
  1305. rval = qla81xx_fac_get_sector_size(vha, &size);
  1306. if (rval == QLA_SUCCESS) {
  1307. ha->flags.fac_supported = 1;
  1308. ha->fdt_block_size = size << 2;
  1309. } else {
  1310. ql_log(ql_log_warn, vha, 0x00ce,
  1311. "Unsupported FAC firmware (%d.%02d.%02d).\n",
  1312. ha->fw_major_version, ha->fw_minor_version,
  1313. ha->fw_subminor_version);
  1314. }
  1315. }
  1316. failed:
  1317. if (rval) {
  1318. ql_log(ql_log_fatal, vha, 0x00cf,
  1319. "Setup chip ****FAILED****.\n");
  1320. }
  1321. return (rval);
  1322. }
  1323. /**
  1324. * qla2x00_init_response_q_entries() - Initializes response queue entries.
  1325. * @ha: HA context
  1326. *
  1327. * Beginning of request ring has initialization control block already built
  1328. * by nvram config routine.
  1329. *
  1330. * Returns 0 on success.
  1331. */
  1332. void
  1333. qla2x00_init_response_q_entries(struct rsp_que *rsp)
  1334. {
  1335. uint16_t cnt;
  1336. response_t *pkt;
  1337. rsp->ring_ptr = rsp->ring;
  1338. rsp->ring_index = 0;
  1339. rsp->status_srb = NULL;
  1340. pkt = rsp->ring_ptr;
  1341. for (cnt = 0; cnt < rsp->length; cnt++) {
  1342. pkt->signature = RESPONSE_PROCESSED;
  1343. pkt++;
  1344. }
  1345. }
  1346. /**
  1347. * qla2x00_update_fw_options() - Read and process firmware options.
  1348. * @ha: HA context
  1349. *
  1350. * Returns 0 on success.
  1351. */
  1352. void
  1353. qla2x00_update_fw_options(scsi_qla_host_t *vha)
  1354. {
  1355. uint16_t swing, emphasis, tx_sens, rx_sens;
  1356. struct qla_hw_data *ha = vha->hw;
  1357. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  1358. qla2x00_get_fw_options(vha, ha->fw_options);
  1359. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  1360. return;
  1361. /* Serial Link options. */
  1362. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
  1363. "Serial link options.\n");
  1364. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
  1365. (uint8_t *)&ha->fw_seriallink_options,
  1366. sizeof(ha->fw_seriallink_options));
  1367. ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
  1368. if (ha->fw_seriallink_options[3] & BIT_2) {
  1369. ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
  1370. /* 1G settings */
  1371. swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
  1372. emphasis = (ha->fw_seriallink_options[2] &
  1373. (BIT_4 | BIT_3)) >> 3;
  1374. tx_sens = ha->fw_seriallink_options[0] &
  1375. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1376. rx_sens = (ha->fw_seriallink_options[0] &
  1377. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1378. ha->fw_options[10] = (emphasis << 14) | (swing << 8);
  1379. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1380. if (rx_sens == 0x0)
  1381. rx_sens = 0x3;
  1382. ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
  1383. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1384. ha->fw_options[10] |= BIT_5 |
  1385. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1386. (tx_sens & (BIT_1 | BIT_0));
  1387. /* 2G settings */
  1388. swing = (ha->fw_seriallink_options[2] &
  1389. (BIT_7 | BIT_6 | BIT_5)) >> 5;
  1390. emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
  1391. tx_sens = ha->fw_seriallink_options[1] &
  1392. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1393. rx_sens = (ha->fw_seriallink_options[1] &
  1394. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1395. ha->fw_options[11] = (emphasis << 14) | (swing << 8);
  1396. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1397. if (rx_sens == 0x0)
  1398. rx_sens = 0x3;
  1399. ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
  1400. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1401. ha->fw_options[11] |= BIT_5 |
  1402. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1403. (tx_sens & (BIT_1 | BIT_0));
  1404. }
  1405. /* FCP2 options. */
  1406. /* Return command IOCBs without waiting for an ABTS to complete. */
  1407. ha->fw_options[3] |= BIT_13;
  1408. /* LED scheme. */
  1409. if (ha->flags.enable_led_scheme)
  1410. ha->fw_options[2] |= BIT_12;
  1411. /* Detect ISP6312. */
  1412. if (IS_QLA6312(ha))
  1413. ha->fw_options[2] |= BIT_13;
  1414. /* Update firmware options. */
  1415. qla2x00_set_fw_options(vha, ha->fw_options);
  1416. }
  1417. void
  1418. qla24xx_update_fw_options(scsi_qla_host_t *vha)
  1419. {
  1420. int rval;
  1421. struct qla_hw_data *ha = vha->hw;
  1422. if (IS_QLA82XX(ha))
  1423. return;
  1424. /* Update Serial Link options. */
  1425. if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
  1426. return;
  1427. rval = qla2x00_set_serdes_params(vha,
  1428. le16_to_cpu(ha->fw_seriallink_options24[1]),
  1429. le16_to_cpu(ha->fw_seriallink_options24[2]),
  1430. le16_to_cpu(ha->fw_seriallink_options24[3]));
  1431. if (rval != QLA_SUCCESS) {
  1432. ql_log(ql_log_warn, vha, 0x0104,
  1433. "Unable to update Serial Link options (%x).\n", rval);
  1434. }
  1435. }
  1436. void
  1437. qla2x00_config_rings(struct scsi_qla_host *vha)
  1438. {
  1439. struct qla_hw_data *ha = vha->hw;
  1440. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1441. struct req_que *req = ha->req_q_map[0];
  1442. struct rsp_que *rsp = ha->rsp_q_map[0];
  1443. /* Setup ring parameters in initialization control block. */
  1444. ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
  1445. ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
  1446. ha->init_cb->request_q_length = cpu_to_le16(req->length);
  1447. ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
  1448. ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1449. ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1450. ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1451. ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1452. WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
  1453. WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
  1454. WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
  1455. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
  1456. RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
  1457. }
  1458. void
  1459. qla24xx_config_rings(struct scsi_qla_host *vha)
  1460. {
  1461. struct qla_hw_data *ha = vha->hw;
  1462. device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
  1463. struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
  1464. struct qla_msix_entry *msix;
  1465. struct init_cb_24xx *icb;
  1466. uint16_t rid = 0;
  1467. struct req_que *req = ha->req_q_map[0];
  1468. struct rsp_que *rsp = ha->rsp_q_map[0];
  1469. /* Setup ring parameters in initialization control block. */
  1470. icb = (struct init_cb_24xx *)ha->init_cb;
  1471. icb->request_q_outpointer = __constant_cpu_to_le16(0);
  1472. icb->response_q_inpointer = __constant_cpu_to_le16(0);
  1473. icb->request_q_length = cpu_to_le16(req->length);
  1474. icb->response_q_length = cpu_to_le16(rsp->length);
  1475. icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1476. icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1477. icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1478. icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1479. if (ha->mqenable) {
  1480. icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
  1481. icb->rid = __constant_cpu_to_le16(rid);
  1482. if (ha->flags.msix_enabled) {
  1483. msix = &ha->msix_entries[1];
  1484. ql_dbg(ql_dbg_init, vha, 0x00fd,
  1485. "Registering vector 0x%x for base que.\n",
  1486. msix->entry);
  1487. icb->msix = cpu_to_le16(msix->entry);
  1488. }
  1489. /* Use alternate PCI bus number */
  1490. if (MSB(rid))
  1491. icb->firmware_options_2 |=
  1492. __constant_cpu_to_le32(BIT_19);
  1493. /* Use alternate PCI devfn */
  1494. if (LSB(rid))
  1495. icb->firmware_options_2 |=
  1496. __constant_cpu_to_le32(BIT_18);
  1497. /* Use Disable MSIX Handshake mode for capable adapters */
  1498. if (IS_MSIX_NACK_CAPABLE(ha)) {
  1499. icb->firmware_options_2 &=
  1500. __constant_cpu_to_le32(~BIT_22);
  1501. ha->flags.disable_msix_handshake = 1;
  1502. ql_dbg(ql_dbg_init, vha, 0x00fe,
  1503. "MSIX Handshake Disable Mode turned on.\n");
  1504. } else {
  1505. icb->firmware_options_2 |=
  1506. __constant_cpu_to_le32(BIT_22);
  1507. }
  1508. icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
  1509. WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
  1510. WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
  1511. WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
  1512. WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
  1513. } else {
  1514. WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
  1515. WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
  1516. WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
  1517. WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
  1518. }
  1519. /* PCI posting */
  1520. RD_REG_DWORD(&ioreg->hccr);
  1521. }
  1522. /**
  1523. * qla2x00_init_rings() - Initializes firmware.
  1524. * @ha: HA context
  1525. *
  1526. * Beginning of request ring has initialization control block already built
  1527. * by nvram config routine.
  1528. *
  1529. * Returns 0 on success.
  1530. */
  1531. static int
  1532. qla2x00_init_rings(scsi_qla_host_t *vha)
  1533. {
  1534. int rval;
  1535. unsigned long flags = 0;
  1536. int cnt, que;
  1537. struct qla_hw_data *ha = vha->hw;
  1538. struct req_que *req;
  1539. struct rsp_que *rsp;
  1540. struct scsi_qla_host *vp;
  1541. struct mid_init_cb_24xx *mid_init_cb =
  1542. (struct mid_init_cb_24xx *) ha->init_cb;
  1543. spin_lock_irqsave(&ha->hardware_lock, flags);
  1544. /* Clear outstanding commands array. */
  1545. for (que = 0; que < ha->max_req_queues; que++) {
  1546. req = ha->req_q_map[que];
  1547. if (!req)
  1548. continue;
  1549. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++)
  1550. req->outstanding_cmds[cnt] = NULL;
  1551. req->current_outstanding_cmd = 1;
  1552. /* Initialize firmware. */
  1553. req->ring_ptr = req->ring;
  1554. req->ring_index = 0;
  1555. req->cnt = req->length;
  1556. }
  1557. for (que = 0; que < ha->max_rsp_queues; que++) {
  1558. rsp = ha->rsp_q_map[que];
  1559. if (!rsp)
  1560. continue;
  1561. /* Initialize response queue entries */
  1562. qla2x00_init_response_q_entries(rsp);
  1563. }
  1564. spin_lock(&ha->vport_slock);
  1565. /* Clear RSCN queue. */
  1566. list_for_each_entry(vp, &ha->vp_list, list) {
  1567. vp->rscn_in_ptr = 0;
  1568. vp->rscn_out_ptr = 0;
  1569. }
  1570. spin_unlock(&ha->vport_slock);
  1571. ha->isp_ops->config_rings(vha);
  1572. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1573. /* Update any ISP specific firmware options before initialization. */
  1574. ha->isp_ops->update_fw_options(vha);
  1575. ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
  1576. if (ha->flags.npiv_supported) {
  1577. if (ha->operating_mode == LOOP)
  1578. ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
  1579. mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
  1580. }
  1581. if (IS_FWI2_CAPABLE(ha)) {
  1582. mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
  1583. mid_init_cb->init_cb.execution_throttle =
  1584. cpu_to_le16(ha->fw_xcb_count);
  1585. }
  1586. rval = qla2x00_init_firmware(vha, ha->init_cb_size);
  1587. if (rval) {
  1588. ql_log(ql_log_fatal, vha, 0x00d2,
  1589. "Init Firmware **** FAILED ****.\n");
  1590. } else {
  1591. ql_dbg(ql_dbg_init, vha, 0x00d3,
  1592. "Init Firmware -- success.\n");
  1593. }
  1594. return (rval);
  1595. }
  1596. /**
  1597. * qla2x00_fw_ready() - Waits for firmware ready.
  1598. * @ha: HA context
  1599. *
  1600. * Returns 0 on success.
  1601. */
  1602. static int
  1603. qla2x00_fw_ready(scsi_qla_host_t *vha)
  1604. {
  1605. int rval;
  1606. unsigned long wtime, mtime, cs84xx_time;
  1607. uint16_t min_wait; /* Minimum wait time if loop is down */
  1608. uint16_t wait_time; /* Wait time if loop is coming ready */
  1609. uint16_t state[5];
  1610. struct qla_hw_data *ha = vha->hw;
  1611. rval = QLA_SUCCESS;
  1612. /* 20 seconds for loop down. */
  1613. min_wait = 20;
  1614. /*
  1615. * Firmware should take at most one RATOV to login, plus 5 seconds for
  1616. * our own processing.
  1617. */
  1618. if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
  1619. wait_time = min_wait;
  1620. }
  1621. /* Min wait time if loop down */
  1622. mtime = jiffies + (min_wait * HZ);
  1623. /* wait time before firmware ready */
  1624. wtime = jiffies + (wait_time * HZ);
  1625. /* Wait for ISP to finish LIP */
  1626. if (!vha->flags.init_done)
  1627. ql_log(ql_log_info, vha, 0x801e,
  1628. "Waiting for LIP to complete.\n");
  1629. do {
  1630. rval = qla2x00_get_firmware_state(vha, state);
  1631. if (rval == QLA_SUCCESS) {
  1632. if (state[0] < FSTATE_LOSS_OF_SYNC) {
  1633. vha->device_flags &= ~DFLG_NO_CABLE;
  1634. }
  1635. if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
  1636. ql_dbg(ql_dbg_taskm, vha, 0x801f,
  1637. "fw_state=%x 84xx=%x.\n", state[0],
  1638. state[2]);
  1639. if ((state[2] & FSTATE_LOGGED_IN) &&
  1640. (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
  1641. ql_dbg(ql_dbg_taskm, vha, 0x8028,
  1642. "Sending verify iocb.\n");
  1643. cs84xx_time = jiffies;
  1644. rval = qla84xx_init_chip(vha);
  1645. if (rval != QLA_SUCCESS) {
  1646. ql_log(ql_log_warn,
  1647. vha, 0x8007,
  1648. "Init chip failed.\n");
  1649. break;
  1650. }
  1651. /* Add time taken to initialize. */
  1652. cs84xx_time = jiffies - cs84xx_time;
  1653. wtime += cs84xx_time;
  1654. mtime += cs84xx_time;
  1655. ql_dbg(ql_dbg_taskm, vha, 0x8008,
  1656. "Increasing wait time by %ld. "
  1657. "New time %ld.\n", cs84xx_time,
  1658. wtime);
  1659. }
  1660. } else if (state[0] == FSTATE_READY) {
  1661. ql_dbg(ql_dbg_taskm, vha, 0x8037,
  1662. "F/W Ready - OK.\n");
  1663. qla2x00_get_retry_cnt(vha, &ha->retry_count,
  1664. &ha->login_timeout, &ha->r_a_tov);
  1665. rval = QLA_SUCCESS;
  1666. break;
  1667. }
  1668. rval = QLA_FUNCTION_FAILED;
  1669. if (atomic_read(&vha->loop_down_timer) &&
  1670. state[0] != FSTATE_READY) {
  1671. /* Loop down. Timeout on min_wait for states
  1672. * other than Wait for Login.
  1673. */
  1674. if (time_after_eq(jiffies, mtime)) {
  1675. ql_log(ql_log_info, vha, 0x8038,
  1676. "Cable is unplugged...\n");
  1677. vha->device_flags |= DFLG_NO_CABLE;
  1678. break;
  1679. }
  1680. }
  1681. } else {
  1682. /* Mailbox cmd failed. Timeout on min_wait. */
  1683. if (time_after_eq(jiffies, mtime) ||
  1684. ha->flags.isp82xx_fw_hung)
  1685. break;
  1686. }
  1687. if (time_after_eq(jiffies, wtime))
  1688. break;
  1689. /* Delay for a while */
  1690. msleep(500);
  1691. } while (1);
  1692. ql_dbg(ql_dbg_taskm, vha, 0x803a,
  1693. "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
  1694. state[1], state[2], state[3], state[4], jiffies);
  1695. if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
  1696. ql_log(ql_log_warn, vha, 0x803b,
  1697. "Firmware ready **** FAILED ****.\n");
  1698. }
  1699. return (rval);
  1700. }
  1701. /*
  1702. * qla2x00_configure_hba
  1703. * Setup adapter context.
  1704. *
  1705. * Input:
  1706. * ha = adapter state pointer.
  1707. *
  1708. * Returns:
  1709. * 0 = success
  1710. *
  1711. * Context:
  1712. * Kernel context.
  1713. */
  1714. static int
  1715. qla2x00_configure_hba(scsi_qla_host_t *vha)
  1716. {
  1717. int rval;
  1718. uint16_t loop_id;
  1719. uint16_t topo;
  1720. uint16_t sw_cap;
  1721. uint8_t al_pa;
  1722. uint8_t area;
  1723. uint8_t domain;
  1724. char connect_type[22];
  1725. struct qla_hw_data *ha = vha->hw;
  1726. /* Get host addresses. */
  1727. rval = qla2x00_get_adapter_id(vha,
  1728. &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
  1729. if (rval != QLA_SUCCESS) {
  1730. if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
  1731. IS_QLA8XXX_TYPE(ha) ||
  1732. (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
  1733. ql_dbg(ql_dbg_disc, vha, 0x2008,
  1734. "Loop is in a transition state.\n");
  1735. } else {
  1736. ql_log(ql_log_warn, vha, 0x2009,
  1737. "Unable to get host loop ID.\n");
  1738. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1739. }
  1740. return (rval);
  1741. }
  1742. if (topo == 4) {
  1743. ql_log(ql_log_info, vha, 0x200a,
  1744. "Cannot get topology - retrying.\n");
  1745. return (QLA_FUNCTION_FAILED);
  1746. }
  1747. vha->loop_id = loop_id;
  1748. /* initialize */
  1749. ha->min_external_loopid = SNS_FIRST_LOOP_ID;
  1750. ha->operating_mode = LOOP;
  1751. ha->switch_cap = 0;
  1752. switch (topo) {
  1753. case 0:
  1754. ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
  1755. ha->current_topology = ISP_CFG_NL;
  1756. strcpy(connect_type, "(Loop)");
  1757. break;
  1758. case 1:
  1759. ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
  1760. ha->switch_cap = sw_cap;
  1761. ha->current_topology = ISP_CFG_FL;
  1762. strcpy(connect_type, "(FL_Port)");
  1763. break;
  1764. case 2:
  1765. ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
  1766. ha->operating_mode = P2P;
  1767. ha->current_topology = ISP_CFG_N;
  1768. strcpy(connect_type, "(N_Port-to-N_Port)");
  1769. break;
  1770. case 3:
  1771. ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
  1772. ha->switch_cap = sw_cap;
  1773. ha->operating_mode = P2P;
  1774. ha->current_topology = ISP_CFG_F;
  1775. strcpy(connect_type, "(F_Port)");
  1776. break;
  1777. default:
  1778. ql_dbg(ql_dbg_disc, vha, 0x200f,
  1779. "HBA in unknown topology %x, using NL.\n", topo);
  1780. ha->current_topology = ISP_CFG_NL;
  1781. strcpy(connect_type, "(Loop)");
  1782. break;
  1783. }
  1784. /* Save Host port and loop ID. */
  1785. /* byte order - Big Endian */
  1786. vha->d_id.b.domain = domain;
  1787. vha->d_id.b.area = area;
  1788. vha->d_id.b.al_pa = al_pa;
  1789. if (!vha->flags.init_done)
  1790. ql_log(ql_log_info, vha, 0x2010,
  1791. "Topology - %s, Host Loop address 0x%x.\n",
  1792. connect_type, vha->loop_id);
  1793. if (rval) {
  1794. ql_log(ql_log_warn, vha, 0x2011,
  1795. "%s FAILED\n", __func__);
  1796. } else {
  1797. ql_dbg(ql_dbg_disc, vha, 0x2012,
  1798. "%s success\n", __func__);
  1799. }
  1800. return(rval);
  1801. }
  1802. inline void
  1803. qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
  1804. char *def)
  1805. {
  1806. char *st, *en;
  1807. uint16_t index;
  1808. struct qla_hw_data *ha = vha->hw;
  1809. int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
  1810. !IS_QLA8XXX_TYPE(ha);
  1811. if (memcmp(model, BINZERO, len) != 0) {
  1812. strncpy(ha->model_number, model, len);
  1813. st = en = ha->model_number;
  1814. en += len - 1;
  1815. while (en > st) {
  1816. if (*en != 0x20 && *en != 0x00)
  1817. break;
  1818. *en-- = '\0';
  1819. }
  1820. index = (ha->pdev->subsystem_device & 0xff);
  1821. if (use_tbl &&
  1822. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1823. index < QLA_MODEL_NAMES)
  1824. strncpy(ha->model_desc,
  1825. qla2x00_model_name[index * 2 + 1],
  1826. sizeof(ha->model_desc) - 1);
  1827. } else {
  1828. index = (ha->pdev->subsystem_device & 0xff);
  1829. if (use_tbl &&
  1830. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1831. index < QLA_MODEL_NAMES) {
  1832. strcpy(ha->model_number,
  1833. qla2x00_model_name[index * 2]);
  1834. strncpy(ha->model_desc,
  1835. qla2x00_model_name[index * 2 + 1],
  1836. sizeof(ha->model_desc) - 1);
  1837. } else {
  1838. strcpy(ha->model_number, def);
  1839. }
  1840. }
  1841. if (IS_FWI2_CAPABLE(ha))
  1842. qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
  1843. sizeof(ha->model_desc));
  1844. }
  1845. /* On sparc systems, obtain port and node WWN from firmware
  1846. * properties.
  1847. */
  1848. static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
  1849. {
  1850. #ifdef CONFIG_SPARC
  1851. struct qla_hw_data *ha = vha->hw;
  1852. struct pci_dev *pdev = ha->pdev;
  1853. struct device_node *dp = pci_device_to_OF_node(pdev);
  1854. const u8 *val;
  1855. int len;
  1856. val = of_get_property(dp, "port-wwn", &len);
  1857. if (val && len >= WWN_SIZE)
  1858. memcpy(nv->port_name, val, WWN_SIZE);
  1859. val = of_get_property(dp, "node-wwn", &len);
  1860. if (val && len >= WWN_SIZE)
  1861. memcpy(nv->node_name, val, WWN_SIZE);
  1862. #endif
  1863. }
  1864. /*
  1865. * NVRAM configuration for ISP 2xxx
  1866. *
  1867. * Input:
  1868. * ha = adapter block pointer.
  1869. *
  1870. * Output:
  1871. * initialization control block in response_ring
  1872. * host adapters parameters in host adapter block
  1873. *
  1874. * Returns:
  1875. * 0 = success.
  1876. */
  1877. int
  1878. qla2x00_nvram_config(scsi_qla_host_t *vha)
  1879. {
  1880. int rval;
  1881. uint8_t chksum = 0;
  1882. uint16_t cnt;
  1883. uint8_t *dptr1, *dptr2;
  1884. struct qla_hw_data *ha = vha->hw;
  1885. init_cb_t *icb = ha->init_cb;
  1886. nvram_t *nv = ha->nvram;
  1887. uint8_t *ptr = ha->nvram;
  1888. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1889. rval = QLA_SUCCESS;
  1890. /* Determine NVRAM starting address. */
  1891. ha->nvram_size = sizeof(nvram_t);
  1892. ha->nvram_base = 0;
  1893. if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
  1894. if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
  1895. ha->nvram_base = 0x80;
  1896. /* Get NVRAM data and calculate checksum. */
  1897. ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
  1898. for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
  1899. chksum += *ptr++;
  1900. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
  1901. "Contents of NVRAM.\n");
  1902. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
  1903. (uint8_t *)nv, ha->nvram_size);
  1904. /* Bad NVRAM data, set defaults parameters. */
  1905. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
  1906. nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
  1907. /* Reset NVRAM data. */
  1908. ql_log(ql_log_warn, vha, 0x0064,
  1909. "Inconisistent NVRAM "
  1910. "detected: checksum=0x%x id=%c version=0x%x.\n",
  1911. chksum, nv->id[0], nv->nvram_version);
  1912. ql_log(ql_log_warn, vha, 0x0065,
  1913. "Falling back to "
  1914. "functioning (yet invalid -- WWPN) defaults.\n");
  1915. /*
  1916. * Set default initialization control block.
  1917. */
  1918. memset(nv, 0, ha->nvram_size);
  1919. nv->parameter_block_version = ICB_VERSION;
  1920. if (IS_QLA23XX(ha)) {
  1921. nv->firmware_options[0] = BIT_2 | BIT_1;
  1922. nv->firmware_options[1] = BIT_7 | BIT_5;
  1923. nv->add_firmware_options[0] = BIT_5;
  1924. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1925. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1926. nv->special_options[1] = BIT_7;
  1927. } else if (IS_QLA2200(ha)) {
  1928. nv->firmware_options[0] = BIT_2 | BIT_1;
  1929. nv->firmware_options[1] = BIT_7 | BIT_5;
  1930. nv->add_firmware_options[0] = BIT_5;
  1931. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1932. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1933. } else if (IS_QLA2100(ha)) {
  1934. nv->firmware_options[0] = BIT_3 | BIT_1;
  1935. nv->firmware_options[1] = BIT_5;
  1936. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1937. }
  1938. nv->max_iocb_allocation = __constant_cpu_to_le16(256);
  1939. nv->execution_throttle = __constant_cpu_to_le16(16);
  1940. nv->retry_count = 8;
  1941. nv->retry_delay = 1;
  1942. nv->port_name[0] = 33;
  1943. nv->port_name[3] = 224;
  1944. nv->port_name[4] = 139;
  1945. qla2xxx_nvram_wwn_from_ofw(vha, nv);
  1946. nv->login_timeout = 4;
  1947. /*
  1948. * Set default host adapter parameters
  1949. */
  1950. nv->host_p[1] = BIT_2;
  1951. nv->reset_delay = 5;
  1952. nv->port_down_retry_count = 8;
  1953. nv->max_luns_per_target = __constant_cpu_to_le16(8);
  1954. nv->link_down_timeout = 60;
  1955. rval = 1;
  1956. }
  1957. #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
  1958. /*
  1959. * The SN2 does not provide BIOS emulation which means you can't change
  1960. * potentially bogus BIOS settings. Force the use of default settings
  1961. * for link rate and frame size. Hope that the rest of the settings
  1962. * are valid.
  1963. */
  1964. if (ia64_platform_is("sn2")) {
  1965. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1966. if (IS_QLA23XX(ha))
  1967. nv->special_options[1] = BIT_7;
  1968. }
  1969. #endif
  1970. /* Reset Initialization control block */
  1971. memset(icb, 0, ha->init_cb_size);
  1972. /*
  1973. * Setup driver NVRAM options.
  1974. */
  1975. nv->firmware_options[0] |= (BIT_6 | BIT_1);
  1976. nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
  1977. nv->firmware_options[1] |= (BIT_5 | BIT_0);
  1978. nv->firmware_options[1] &= ~BIT_4;
  1979. if (IS_QLA23XX(ha)) {
  1980. nv->firmware_options[0] |= BIT_2;
  1981. nv->firmware_options[0] &= ~BIT_3;
  1982. nv->firmware_options[0] &= ~BIT_6;
  1983. nv->add_firmware_options[1] |= BIT_5 | BIT_4;
  1984. if (IS_QLA2300(ha)) {
  1985. if (ha->fb_rev == FPM_2310) {
  1986. strcpy(ha->model_number, "QLA2310");
  1987. } else {
  1988. strcpy(ha->model_number, "QLA2300");
  1989. }
  1990. } else {
  1991. qla2x00_set_model_info(vha, nv->model_number,
  1992. sizeof(nv->model_number), "QLA23xx");
  1993. }
  1994. } else if (IS_QLA2200(ha)) {
  1995. nv->firmware_options[0] |= BIT_2;
  1996. /*
  1997. * 'Point-to-point preferred, else loop' is not a safe
  1998. * connection mode setting.
  1999. */
  2000. if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
  2001. (BIT_5 | BIT_4)) {
  2002. /* Force 'loop preferred, else point-to-point'. */
  2003. nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
  2004. nv->add_firmware_options[0] |= BIT_5;
  2005. }
  2006. strcpy(ha->model_number, "QLA22xx");
  2007. } else /*if (IS_QLA2100(ha))*/ {
  2008. strcpy(ha->model_number, "QLA2100");
  2009. }
  2010. /*
  2011. * Copy over NVRAM RISC parameter block to initialization control block.
  2012. */
  2013. dptr1 = (uint8_t *)icb;
  2014. dptr2 = (uint8_t *)&nv->parameter_block_version;
  2015. cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
  2016. while (cnt--)
  2017. *dptr1++ = *dptr2++;
  2018. /* Copy 2nd half. */
  2019. dptr1 = (uint8_t *)icb->add_firmware_options;
  2020. cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
  2021. while (cnt--)
  2022. *dptr1++ = *dptr2++;
  2023. /* Use alternate WWN? */
  2024. if (nv->host_p[1] & BIT_7) {
  2025. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  2026. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  2027. }
  2028. /* Prepare nodename */
  2029. if ((icb->firmware_options[1] & BIT_6) == 0) {
  2030. /*
  2031. * Firmware will apply the following mask if the nodename was
  2032. * not provided.
  2033. */
  2034. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  2035. icb->node_name[0] &= 0xF0;
  2036. }
  2037. /*
  2038. * Set host adapter parameters.
  2039. */
  2040. /*
  2041. * BIT_7 in the host-parameters section allows for modification to
  2042. * internal driver logging.
  2043. */
  2044. if (nv->host_p[0] & BIT_7)
  2045. ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
  2046. ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
  2047. /* Always load RISC code on non ISP2[12]00 chips. */
  2048. if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
  2049. ha->flags.disable_risc_code_load = 0;
  2050. ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
  2051. ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
  2052. ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
  2053. ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
  2054. ha->flags.disable_serdes = 0;
  2055. ha->operating_mode =
  2056. (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
  2057. memcpy(ha->fw_seriallink_options, nv->seriallink_options,
  2058. sizeof(ha->fw_seriallink_options));
  2059. /* save HBA serial number */
  2060. ha->serial0 = icb->port_name[5];
  2061. ha->serial1 = icb->port_name[6];
  2062. ha->serial2 = icb->port_name[7];
  2063. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  2064. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  2065. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  2066. ha->retry_count = nv->retry_count;
  2067. /* Set minimum login_timeout to 4 seconds. */
  2068. if (nv->login_timeout != ql2xlogintimeout)
  2069. nv->login_timeout = ql2xlogintimeout;
  2070. if (nv->login_timeout < 4)
  2071. nv->login_timeout = 4;
  2072. ha->login_timeout = nv->login_timeout;
  2073. icb->login_timeout = nv->login_timeout;
  2074. /* Set minimum RATOV to 100 tenths of a second. */
  2075. ha->r_a_tov = 100;
  2076. ha->loop_reset_delay = nv->reset_delay;
  2077. /* Link Down Timeout = 0:
  2078. *
  2079. * When Port Down timer expires we will start returning
  2080. * I/O's to OS with "DID_NO_CONNECT".
  2081. *
  2082. * Link Down Timeout != 0:
  2083. *
  2084. * The driver waits for the link to come up after link down
  2085. * before returning I/Os to OS with "DID_NO_CONNECT".
  2086. */
  2087. if (nv->link_down_timeout == 0) {
  2088. ha->loop_down_abort_time =
  2089. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  2090. } else {
  2091. ha->link_down_timeout = nv->link_down_timeout;
  2092. ha->loop_down_abort_time =
  2093. (LOOP_DOWN_TIME - ha->link_down_timeout);
  2094. }
  2095. /*
  2096. * Need enough time to try and get the port back.
  2097. */
  2098. ha->port_down_retry_count = nv->port_down_retry_count;
  2099. if (qlport_down_retry)
  2100. ha->port_down_retry_count = qlport_down_retry;
  2101. /* Set login_retry_count */
  2102. ha->login_retry_count = nv->retry_count;
  2103. if (ha->port_down_retry_count == nv->port_down_retry_count &&
  2104. ha->port_down_retry_count > 3)
  2105. ha->login_retry_count = ha->port_down_retry_count;
  2106. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  2107. ha->login_retry_count = ha->port_down_retry_count;
  2108. if (ql2xloginretrycount)
  2109. ha->login_retry_count = ql2xloginretrycount;
  2110. icb->lun_enables = __constant_cpu_to_le16(0);
  2111. icb->command_resource_count = 0;
  2112. icb->immediate_notify_resource_count = 0;
  2113. icb->timeout = __constant_cpu_to_le16(0);
  2114. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2115. /* Enable RIO */
  2116. icb->firmware_options[0] &= ~BIT_3;
  2117. icb->add_firmware_options[0] &=
  2118. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2119. icb->add_firmware_options[0] |= BIT_2;
  2120. icb->response_accumulation_timer = 3;
  2121. icb->interrupt_delay_timer = 5;
  2122. vha->flags.process_response_queue = 1;
  2123. } else {
  2124. /* Enable ZIO. */
  2125. if (!vha->flags.init_done) {
  2126. ha->zio_mode = icb->add_firmware_options[0] &
  2127. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2128. ha->zio_timer = icb->interrupt_delay_timer ?
  2129. icb->interrupt_delay_timer: 2;
  2130. }
  2131. icb->add_firmware_options[0] &=
  2132. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2133. vha->flags.process_response_queue = 0;
  2134. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  2135. ha->zio_mode = QLA_ZIO_MODE_6;
  2136. ql_log(ql_log_info, vha, 0x0068,
  2137. "ZIO mode %d enabled; timer delay (%d us).\n",
  2138. ha->zio_mode, ha->zio_timer * 100);
  2139. icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
  2140. icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
  2141. vha->flags.process_response_queue = 1;
  2142. }
  2143. }
  2144. if (rval) {
  2145. ql_log(ql_log_warn, vha, 0x0069,
  2146. "NVRAM configuration failed.\n");
  2147. }
  2148. return (rval);
  2149. }
  2150. static void
  2151. qla2x00_rport_del(void *data)
  2152. {
  2153. fc_port_t *fcport = data;
  2154. struct fc_rport *rport;
  2155. unsigned long flags;
  2156. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2157. rport = fcport->drport ? fcport->drport: fcport->rport;
  2158. fcport->drport = NULL;
  2159. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2160. if (rport)
  2161. fc_remote_port_delete(rport);
  2162. }
  2163. /**
  2164. * qla2x00_alloc_fcport() - Allocate a generic fcport.
  2165. * @ha: HA context
  2166. * @flags: allocation flags
  2167. *
  2168. * Returns a pointer to the allocated fcport, or NULL, if none available.
  2169. */
  2170. fc_port_t *
  2171. qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
  2172. {
  2173. fc_port_t *fcport;
  2174. fcport = kzalloc(sizeof(fc_port_t), flags);
  2175. if (!fcport)
  2176. return NULL;
  2177. /* Setup fcport template structure. */
  2178. fcport->vha = vha;
  2179. fcport->vp_idx = vha->vp_idx;
  2180. fcport->port_type = FCT_UNKNOWN;
  2181. fcport->loop_id = FC_NO_LOOP_ID;
  2182. qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
  2183. fcport->supported_classes = FC_COS_UNSPECIFIED;
  2184. return fcport;
  2185. }
  2186. /*
  2187. * qla2x00_configure_loop
  2188. * Updates Fibre Channel Device Database with what is actually on loop.
  2189. *
  2190. * Input:
  2191. * ha = adapter block pointer.
  2192. *
  2193. * Returns:
  2194. * 0 = success.
  2195. * 1 = error.
  2196. * 2 = database was full and device was not configured.
  2197. */
  2198. static int
  2199. qla2x00_configure_loop(scsi_qla_host_t *vha)
  2200. {
  2201. int rval;
  2202. unsigned long flags, save_flags;
  2203. struct qla_hw_data *ha = vha->hw;
  2204. rval = QLA_SUCCESS;
  2205. /* Get Initiator ID */
  2206. if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
  2207. rval = qla2x00_configure_hba(vha);
  2208. if (rval != QLA_SUCCESS) {
  2209. ql_dbg(ql_dbg_disc, vha, 0x2013,
  2210. "Unable to configure HBA.\n");
  2211. return (rval);
  2212. }
  2213. }
  2214. save_flags = flags = vha->dpc_flags;
  2215. ql_dbg(ql_dbg_disc, vha, 0x2014,
  2216. "Configure loop -- dpc flags = 0x%lx.\n", flags);
  2217. /*
  2218. * If we have both an RSCN and PORT UPDATE pending then handle them
  2219. * both at the same time.
  2220. */
  2221. clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2222. clear_bit(RSCN_UPDATE, &vha->dpc_flags);
  2223. qla2x00_get_data_rate(vha);
  2224. /* Determine what we need to do */
  2225. if (ha->current_topology == ISP_CFG_FL &&
  2226. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2227. vha->flags.rscn_queue_overflow = 1;
  2228. set_bit(RSCN_UPDATE, &flags);
  2229. } else if (ha->current_topology == ISP_CFG_F &&
  2230. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2231. vha->flags.rscn_queue_overflow = 1;
  2232. set_bit(RSCN_UPDATE, &flags);
  2233. clear_bit(LOCAL_LOOP_UPDATE, &flags);
  2234. } else if (ha->current_topology == ISP_CFG_N) {
  2235. clear_bit(RSCN_UPDATE, &flags);
  2236. } else if (!vha->flags.online ||
  2237. (test_bit(ABORT_ISP_ACTIVE, &flags))) {
  2238. vha->flags.rscn_queue_overflow = 1;
  2239. set_bit(RSCN_UPDATE, &flags);
  2240. set_bit(LOCAL_LOOP_UPDATE, &flags);
  2241. }
  2242. if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
  2243. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2244. ql_dbg(ql_dbg_disc, vha, 0x2015,
  2245. "Loop resync needed, failing.\n");
  2246. rval = QLA_FUNCTION_FAILED;
  2247. }
  2248. else
  2249. rval = qla2x00_configure_local_loop(vha);
  2250. }
  2251. if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
  2252. if (LOOP_TRANSITION(vha)) {
  2253. ql_dbg(ql_dbg_disc, vha, 0x201e,
  2254. "Needs RSCN update and loop transition.\n");
  2255. rval = QLA_FUNCTION_FAILED;
  2256. }
  2257. else
  2258. rval = qla2x00_configure_fabric(vha);
  2259. }
  2260. if (rval == QLA_SUCCESS) {
  2261. if (atomic_read(&vha->loop_down_timer) ||
  2262. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2263. rval = QLA_FUNCTION_FAILED;
  2264. } else {
  2265. atomic_set(&vha->loop_state, LOOP_READY);
  2266. ql_dbg(ql_dbg_disc, vha, 0x2069,
  2267. "LOOP READY.\n");
  2268. }
  2269. }
  2270. if (rval) {
  2271. ql_dbg(ql_dbg_disc, vha, 0x206a,
  2272. "%s *** FAILED ***.\n", __func__);
  2273. } else {
  2274. ql_dbg(ql_dbg_disc, vha, 0x206b,
  2275. "%s: exiting normally.\n", __func__);
  2276. }
  2277. /* Restore state if a resync event occurred during processing */
  2278. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2279. if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
  2280. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2281. if (test_bit(RSCN_UPDATE, &save_flags)) {
  2282. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  2283. if (!IS_ALOGIO_CAPABLE(ha))
  2284. vha->flags.rscn_queue_overflow = 1;
  2285. }
  2286. }
  2287. return (rval);
  2288. }
  2289. /*
  2290. * qla2x00_configure_local_loop
  2291. * Updates Fibre Channel Device Database with local loop devices.
  2292. *
  2293. * Input:
  2294. * ha = adapter block pointer.
  2295. *
  2296. * Returns:
  2297. * 0 = success.
  2298. */
  2299. static int
  2300. qla2x00_configure_local_loop(scsi_qla_host_t *vha)
  2301. {
  2302. int rval, rval2;
  2303. int found_devs;
  2304. int found;
  2305. fc_port_t *fcport, *new_fcport;
  2306. uint16_t index;
  2307. uint16_t entries;
  2308. char *id_iter;
  2309. uint16_t loop_id;
  2310. uint8_t domain, area, al_pa;
  2311. struct qla_hw_data *ha = vha->hw;
  2312. found_devs = 0;
  2313. new_fcport = NULL;
  2314. entries = MAX_FIBRE_DEVICES;
  2315. ql_dbg(ql_dbg_disc, vha, 0x2016,
  2316. "Getting FCAL position map.\n");
  2317. if (ql2xextended_error_logging & ql_dbg_disc)
  2318. qla2x00_get_fcal_position_map(vha, NULL);
  2319. /* Get list of logged in devices. */
  2320. memset(ha->gid_list, 0, GID_LIST_SIZE);
  2321. rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
  2322. &entries);
  2323. if (rval != QLA_SUCCESS)
  2324. goto cleanup_allocation;
  2325. ql_dbg(ql_dbg_disc, vha, 0x2017,
  2326. "Entries in ID list (%d).\n", entries);
  2327. ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
  2328. (uint8_t *)ha->gid_list,
  2329. entries * sizeof(struct gid_list_info));
  2330. /* Allocate temporary fcport for any new fcports discovered. */
  2331. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2332. if (new_fcport == NULL) {
  2333. ql_log(ql_log_warn, vha, 0x2018,
  2334. "Memory allocation failed for fcport.\n");
  2335. rval = QLA_MEMORY_ALLOC_FAILED;
  2336. goto cleanup_allocation;
  2337. }
  2338. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2339. /*
  2340. * Mark local devices that were present with FCF_DEVICE_LOST for now.
  2341. */
  2342. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2343. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2344. fcport->port_type != FCT_BROADCAST &&
  2345. (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2346. ql_dbg(ql_dbg_disc, vha, 0x2019,
  2347. "Marking port lost loop_id=0x%04x.\n",
  2348. fcport->loop_id);
  2349. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2350. }
  2351. }
  2352. /* Add devices to port list. */
  2353. id_iter = (char *)ha->gid_list;
  2354. for (index = 0; index < entries; index++) {
  2355. domain = ((struct gid_list_info *)id_iter)->domain;
  2356. area = ((struct gid_list_info *)id_iter)->area;
  2357. al_pa = ((struct gid_list_info *)id_iter)->al_pa;
  2358. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  2359. loop_id = (uint16_t)
  2360. ((struct gid_list_info *)id_iter)->loop_id_2100;
  2361. else
  2362. loop_id = le16_to_cpu(
  2363. ((struct gid_list_info *)id_iter)->loop_id);
  2364. id_iter += ha->gid_list_info_size;
  2365. /* Bypass reserved domain fields. */
  2366. if ((domain & 0xf0) == 0xf0)
  2367. continue;
  2368. /* Bypass if not same domain and area of adapter. */
  2369. if (area && domain &&
  2370. (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
  2371. continue;
  2372. /* Bypass invalid local loop ID. */
  2373. if (loop_id > LAST_LOCAL_LOOP_ID)
  2374. continue;
  2375. /* Fill in member data. */
  2376. new_fcport->d_id.b.domain = domain;
  2377. new_fcport->d_id.b.area = area;
  2378. new_fcport->d_id.b.al_pa = al_pa;
  2379. new_fcport->loop_id = loop_id;
  2380. new_fcport->vp_idx = vha->vp_idx;
  2381. rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
  2382. if (rval2 != QLA_SUCCESS) {
  2383. ql_dbg(ql_dbg_disc, vha, 0x201a,
  2384. "Failed to retrieve fcport information "
  2385. "-- get_port_database=%x, loop_id=0x%04x.\n",
  2386. rval2, new_fcport->loop_id);
  2387. ql_dbg(ql_dbg_disc, vha, 0x201b,
  2388. "Scheduling resync.\n");
  2389. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2390. continue;
  2391. }
  2392. /* Check for matching device in port list. */
  2393. found = 0;
  2394. fcport = NULL;
  2395. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2396. if (memcmp(new_fcport->port_name, fcport->port_name,
  2397. WWN_SIZE))
  2398. continue;
  2399. fcport->flags &= ~FCF_FABRIC_DEVICE;
  2400. fcport->loop_id = new_fcport->loop_id;
  2401. fcport->port_type = new_fcport->port_type;
  2402. fcport->d_id.b24 = new_fcport->d_id.b24;
  2403. memcpy(fcport->node_name, new_fcport->node_name,
  2404. WWN_SIZE);
  2405. found++;
  2406. break;
  2407. }
  2408. if (!found) {
  2409. /* New device, add to fcports list. */
  2410. if (vha->vp_idx) {
  2411. new_fcport->vha = vha;
  2412. new_fcport->vp_idx = vha->vp_idx;
  2413. }
  2414. list_add_tail(&new_fcport->list, &vha->vp_fcports);
  2415. /* Allocate a new replacement fcport. */
  2416. fcport = new_fcport;
  2417. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2418. if (new_fcport == NULL) {
  2419. ql_log(ql_log_warn, vha, 0x201c,
  2420. "Failed to allocate memory for fcport.\n");
  2421. rval = QLA_MEMORY_ALLOC_FAILED;
  2422. goto cleanup_allocation;
  2423. }
  2424. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2425. }
  2426. /* Base iIDMA settings on HBA port speed. */
  2427. fcport->fp_speed = ha->link_data_rate;
  2428. qla2x00_update_fcport(vha, fcport);
  2429. found_devs++;
  2430. }
  2431. cleanup_allocation:
  2432. kfree(new_fcport);
  2433. if (rval != QLA_SUCCESS) {
  2434. ql_dbg(ql_dbg_disc, vha, 0x201d,
  2435. "Configure local loop error exit: rval=%x.\n", rval);
  2436. }
  2437. return (rval);
  2438. }
  2439. static void
  2440. qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2441. {
  2442. #define LS_UNKNOWN 2
  2443. static char *link_speeds[] = { "1", "2", "?", "4", "8", "10" };
  2444. char *link_speed;
  2445. int rval;
  2446. uint16_t mb[4];
  2447. struct qla_hw_data *ha = vha->hw;
  2448. if (!IS_IIDMA_CAPABLE(ha))
  2449. return;
  2450. if (atomic_read(&fcport->state) != FCS_ONLINE)
  2451. return;
  2452. if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
  2453. fcport->fp_speed > ha->link_data_rate)
  2454. return;
  2455. rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
  2456. mb);
  2457. if (rval != QLA_SUCCESS) {
  2458. ql_dbg(ql_dbg_disc, vha, 0x2004,
  2459. "Unable to adjust iIDMA "
  2460. "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
  2461. "%04x.\n", fcport->port_name[0], fcport->port_name[1],
  2462. fcport->port_name[2], fcport->port_name[3],
  2463. fcport->port_name[4], fcport->port_name[5],
  2464. fcport->port_name[6], fcport->port_name[7], rval,
  2465. fcport->fp_speed, mb[0], mb[1]);
  2466. } else {
  2467. link_speed = link_speeds[LS_UNKNOWN];
  2468. if (fcport->fp_speed < 5)
  2469. link_speed = link_speeds[fcport->fp_speed];
  2470. else if (fcport->fp_speed == 0x13)
  2471. link_speed = link_speeds[5];
  2472. ql_dbg(ql_dbg_disc, vha, 0x2005,
  2473. "iIDMA adjusted to %s GB/s "
  2474. "on %02x%02x%02x%02x%02x%02x%02x%02x.\n", link_speed,
  2475. fcport->port_name[0], fcport->port_name[1],
  2476. fcport->port_name[2], fcport->port_name[3],
  2477. fcport->port_name[4], fcport->port_name[5],
  2478. fcport->port_name[6], fcport->port_name[7]);
  2479. }
  2480. }
  2481. static void
  2482. qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
  2483. {
  2484. struct fc_rport_identifiers rport_ids;
  2485. struct fc_rport *rport;
  2486. unsigned long flags;
  2487. qla2x00_rport_del(fcport);
  2488. rport_ids.node_name = wwn_to_u64(fcport->node_name);
  2489. rport_ids.port_name = wwn_to_u64(fcport->port_name);
  2490. rport_ids.port_id = fcport->d_id.b.domain << 16 |
  2491. fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
  2492. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2493. fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
  2494. if (!rport) {
  2495. ql_log(ql_log_warn, vha, 0x2006,
  2496. "Unable to allocate fc remote port.\n");
  2497. return;
  2498. }
  2499. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2500. *((fc_port_t **)rport->dd_data) = fcport;
  2501. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2502. rport->supported_classes = fcport->supported_classes;
  2503. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2504. if (fcport->port_type == FCT_INITIATOR)
  2505. rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
  2506. if (fcport->port_type == FCT_TARGET)
  2507. rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
  2508. fc_remote_port_rolechg(rport, rport_ids.roles);
  2509. }
  2510. /*
  2511. * qla2x00_update_fcport
  2512. * Updates device on list.
  2513. *
  2514. * Input:
  2515. * ha = adapter block pointer.
  2516. * fcport = port structure pointer.
  2517. *
  2518. * Return:
  2519. * 0 - Success
  2520. * BIT_0 - error
  2521. *
  2522. * Context:
  2523. * Kernel context.
  2524. */
  2525. void
  2526. qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2527. {
  2528. fcport->vha = vha;
  2529. fcport->login_retry = 0;
  2530. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  2531. qla2x00_iidma_fcport(vha, fcport);
  2532. qla24xx_update_fcport_fcp_prio(vha, fcport);
  2533. qla2x00_reg_remote_port(vha, fcport);
  2534. qla2x00_set_fcport_state(fcport, FCS_ONLINE);
  2535. }
  2536. /*
  2537. * qla2x00_configure_fabric
  2538. * Setup SNS devices with loop ID's.
  2539. *
  2540. * Input:
  2541. * ha = adapter block pointer.
  2542. *
  2543. * Returns:
  2544. * 0 = success.
  2545. * BIT_0 = error
  2546. */
  2547. static int
  2548. qla2x00_configure_fabric(scsi_qla_host_t *vha)
  2549. {
  2550. int rval, rval2;
  2551. fc_port_t *fcport, *fcptemp;
  2552. uint16_t next_loopid;
  2553. uint16_t mb[MAILBOX_REGISTER_COUNT];
  2554. uint16_t loop_id;
  2555. LIST_HEAD(new_fcports);
  2556. struct qla_hw_data *ha = vha->hw;
  2557. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2558. /* If FL port exists, then SNS is present */
  2559. if (IS_FWI2_CAPABLE(ha))
  2560. loop_id = NPH_F_PORT;
  2561. else
  2562. loop_id = SNS_FL_PORT;
  2563. rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
  2564. if (rval != QLA_SUCCESS) {
  2565. ql_dbg(ql_dbg_disc, vha, 0x201f,
  2566. "MBX_GET_PORT_NAME failed, No FL Port.\n");
  2567. vha->device_flags &= ~SWITCH_FOUND;
  2568. return (QLA_SUCCESS);
  2569. }
  2570. vha->device_flags |= SWITCH_FOUND;
  2571. /* Mark devices that need re-synchronization. */
  2572. rval2 = qla2x00_device_resync(vha);
  2573. if (rval2 == QLA_RSCNS_HANDLED) {
  2574. /* No point doing the scan, just continue. */
  2575. return (QLA_SUCCESS);
  2576. }
  2577. do {
  2578. /* FDMI support. */
  2579. if (ql2xfdmienable &&
  2580. test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
  2581. qla2x00_fdmi_register(vha);
  2582. /* Ensure we are logged into the SNS. */
  2583. if (IS_FWI2_CAPABLE(ha))
  2584. loop_id = NPH_SNS;
  2585. else
  2586. loop_id = SIMPLE_NAME_SERVER;
  2587. ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
  2588. 0xfc, mb, BIT_1 | BIT_0);
  2589. if (mb[0] != MBS_COMMAND_COMPLETE) {
  2590. ql_dbg(ql_dbg_disc, vha, 0x2042,
  2591. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
  2592. "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
  2593. mb[2], mb[6], mb[7]);
  2594. return (QLA_SUCCESS);
  2595. }
  2596. if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
  2597. if (qla2x00_rft_id(vha)) {
  2598. /* EMPTY */
  2599. ql_dbg(ql_dbg_disc, vha, 0x2045,
  2600. "Register FC-4 TYPE failed.\n");
  2601. }
  2602. if (qla2x00_rff_id(vha)) {
  2603. /* EMPTY */
  2604. ql_dbg(ql_dbg_disc, vha, 0x2049,
  2605. "Register FC-4 Features failed.\n");
  2606. }
  2607. if (qla2x00_rnn_id(vha)) {
  2608. /* EMPTY */
  2609. ql_dbg(ql_dbg_disc, vha, 0x204f,
  2610. "Register Node Name failed.\n");
  2611. } else if (qla2x00_rsnn_nn(vha)) {
  2612. /* EMPTY */
  2613. ql_dbg(ql_dbg_disc, vha, 0x2053,
  2614. "Register Symobilic Node Name failed.\n");
  2615. }
  2616. }
  2617. rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
  2618. if (rval != QLA_SUCCESS)
  2619. break;
  2620. /*
  2621. * Logout all previous fabric devices marked lost, except
  2622. * FCP2 devices.
  2623. */
  2624. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2625. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2626. break;
  2627. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
  2628. continue;
  2629. if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
  2630. qla2x00_mark_device_lost(vha, fcport,
  2631. ql2xplogiabsentdevice, 0);
  2632. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2633. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2634. fcport->port_type != FCT_INITIATOR &&
  2635. fcport->port_type != FCT_BROADCAST) {
  2636. ha->isp_ops->fabric_logout(vha,
  2637. fcport->loop_id,
  2638. fcport->d_id.b.domain,
  2639. fcport->d_id.b.area,
  2640. fcport->d_id.b.al_pa);
  2641. fcport->loop_id = FC_NO_LOOP_ID;
  2642. }
  2643. }
  2644. }
  2645. /* Starting free loop ID. */
  2646. next_loopid = ha->min_external_loopid;
  2647. /*
  2648. * Scan through our port list and login entries that need to be
  2649. * logged in.
  2650. */
  2651. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2652. if (atomic_read(&vha->loop_down_timer) ||
  2653. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2654. break;
  2655. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
  2656. (fcport->flags & FCF_LOGIN_NEEDED) == 0)
  2657. continue;
  2658. if (fcport->loop_id == FC_NO_LOOP_ID) {
  2659. fcport->loop_id = next_loopid;
  2660. rval = qla2x00_find_new_loop_id(
  2661. base_vha, fcport);
  2662. if (rval != QLA_SUCCESS) {
  2663. /* Ran out of IDs to use */
  2664. break;
  2665. }
  2666. }
  2667. /* Login and update database */
  2668. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2669. }
  2670. /* Exit if out of loop IDs. */
  2671. if (rval != QLA_SUCCESS) {
  2672. break;
  2673. }
  2674. /*
  2675. * Login and add the new devices to our port list.
  2676. */
  2677. list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
  2678. if (atomic_read(&vha->loop_down_timer) ||
  2679. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2680. break;
  2681. /* Find a new loop ID to use. */
  2682. fcport->loop_id = next_loopid;
  2683. rval = qla2x00_find_new_loop_id(base_vha, fcport);
  2684. if (rval != QLA_SUCCESS) {
  2685. /* Ran out of IDs to use */
  2686. break;
  2687. }
  2688. /* Login and update database */
  2689. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2690. if (vha->vp_idx) {
  2691. fcport->vha = vha;
  2692. fcport->vp_idx = vha->vp_idx;
  2693. }
  2694. list_move_tail(&fcport->list, &vha->vp_fcports);
  2695. }
  2696. } while (0);
  2697. /* Free all new device structures not processed. */
  2698. list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
  2699. list_del(&fcport->list);
  2700. kfree(fcport);
  2701. }
  2702. if (rval) {
  2703. ql_dbg(ql_dbg_disc, vha, 0x2068,
  2704. "Configure fabric error exit rval=%d.\n", rval);
  2705. }
  2706. return (rval);
  2707. }
  2708. /*
  2709. * qla2x00_find_all_fabric_devs
  2710. *
  2711. * Input:
  2712. * ha = adapter block pointer.
  2713. * dev = database device entry pointer.
  2714. *
  2715. * Returns:
  2716. * 0 = success.
  2717. *
  2718. * Context:
  2719. * Kernel context.
  2720. */
  2721. static int
  2722. qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
  2723. struct list_head *new_fcports)
  2724. {
  2725. int rval;
  2726. uint16_t loop_id;
  2727. fc_port_t *fcport, *new_fcport, *fcptemp;
  2728. int found;
  2729. sw_info_t *swl;
  2730. int swl_idx;
  2731. int first_dev, last_dev;
  2732. port_id_t wrap = {}, nxt_d_id;
  2733. struct qla_hw_data *ha = vha->hw;
  2734. struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
  2735. struct scsi_qla_host *tvp;
  2736. rval = QLA_SUCCESS;
  2737. /* Try GID_PT to get device list, else GAN. */
  2738. swl = kcalloc(MAX_FIBRE_DEVICES, sizeof(sw_info_t), GFP_KERNEL);
  2739. if (!swl) {
  2740. /*EMPTY*/
  2741. ql_dbg(ql_dbg_disc, vha, 0x2054,
  2742. "GID_PT allocations failed, fallback on GA_NXT.\n");
  2743. } else {
  2744. if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
  2745. kfree(swl);
  2746. swl = NULL;
  2747. } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
  2748. kfree(swl);
  2749. swl = NULL;
  2750. } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
  2751. kfree(swl);
  2752. swl = NULL;
  2753. } else if (ql2xiidmaenable &&
  2754. qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
  2755. qla2x00_gpsc(vha, swl);
  2756. }
  2757. /* If other queries succeeded probe for FC-4 type */
  2758. if (swl)
  2759. qla2x00_gff_id(vha, swl);
  2760. }
  2761. swl_idx = 0;
  2762. /* Allocate temporary fcport for any new fcports discovered. */
  2763. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2764. if (new_fcport == NULL) {
  2765. ql_log(ql_log_warn, vha, 0x205e,
  2766. "Failed to allocate memory for fcport.\n");
  2767. kfree(swl);
  2768. return (QLA_MEMORY_ALLOC_FAILED);
  2769. }
  2770. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2771. /* Set start port ID scan at adapter ID. */
  2772. first_dev = 1;
  2773. last_dev = 0;
  2774. /* Starting free loop ID. */
  2775. loop_id = ha->min_external_loopid;
  2776. for (; loop_id <= ha->max_loop_id; loop_id++) {
  2777. if (qla2x00_is_reserved_id(vha, loop_id))
  2778. continue;
  2779. if (ha->current_topology == ISP_CFG_FL &&
  2780. (atomic_read(&vha->loop_down_timer) ||
  2781. LOOP_TRANSITION(vha))) {
  2782. atomic_set(&vha->loop_down_timer, 0);
  2783. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2784. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2785. break;
  2786. }
  2787. if (swl != NULL) {
  2788. if (last_dev) {
  2789. wrap.b24 = new_fcport->d_id.b24;
  2790. } else {
  2791. new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
  2792. memcpy(new_fcport->node_name,
  2793. swl[swl_idx].node_name, WWN_SIZE);
  2794. memcpy(new_fcport->port_name,
  2795. swl[swl_idx].port_name, WWN_SIZE);
  2796. memcpy(new_fcport->fabric_port_name,
  2797. swl[swl_idx].fabric_port_name, WWN_SIZE);
  2798. new_fcport->fp_speed = swl[swl_idx].fp_speed;
  2799. new_fcport->fc4_type = swl[swl_idx].fc4_type;
  2800. if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
  2801. last_dev = 1;
  2802. }
  2803. swl_idx++;
  2804. }
  2805. } else {
  2806. /* Send GA_NXT to the switch */
  2807. rval = qla2x00_ga_nxt(vha, new_fcport);
  2808. if (rval != QLA_SUCCESS) {
  2809. ql_log(ql_log_warn, vha, 0x2064,
  2810. "SNS scan failed -- assuming "
  2811. "zero-entry result.\n");
  2812. list_for_each_entry_safe(fcport, fcptemp,
  2813. new_fcports, list) {
  2814. list_del(&fcport->list);
  2815. kfree(fcport);
  2816. }
  2817. rval = QLA_SUCCESS;
  2818. break;
  2819. }
  2820. }
  2821. /* If wrap on switch device list, exit. */
  2822. if (first_dev) {
  2823. wrap.b24 = new_fcport->d_id.b24;
  2824. first_dev = 0;
  2825. } else if (new_fcport->d_id.b24 == wrap.b24) {
  2826. ql_dbg(ql_dbg_disc, vha, 0x2065,
  2827. "Device wrap (%02x%02x%02x).\n",
  2828. new_fcport->d_id.b.domain,
  2829. new_fcport->d_id.b.area,
  2830. new_fcport->d_id.b.al_pa);
  2831. break;
  2832. }
  2833. /* Bypass if same physical adapter. */
  2834. if (new_fcport->d_id.b24 == base_vha->d_id.b24)
  2835. continue;
  2836. /* Bypass virtual ports of the same host. */
  2837. found = 0;
  2838. if (ha->num_vhosts) {
  2839. unsigned long flags;
  2840. spin_lock_irqsave(&ha->vport_slock, flags);
  2841. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2842. if (new_fcport->d_id.b24 == vp->d_id.b24) {
  2843. found = 1;
  2844. break;
  2845. }
  2846. }
  2847. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2848. if (found)
  2849. continue;
  2850. }
  2851. /* Bypass if same domain and area of adapter. */
  2852. if (((new_fcport->d_id.b24 & 0xffff00) ==
  2853. (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
  2854. ISP_CFG_FL)
  2855. continue;
  2856. /* Bypass reserved domain fields. */
  2857. if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
  2858. continue;
  2859. /* Bypass ports whose FCP-4 type is not FCP_SCSI */
  2860. if (ql2xgffidenable &&
  2861. (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
  2862. new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
  2863. continue;
  2864. /* Locate matching device in database. */
  2865. found = 0;
  2866. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2867. if (memcmp(new_fcport->port_name, fcport->port_name,
  2868. WWN_SIZE))
  2869. continue;
  2870. found++;
  2871. /* Update port state. */
  2872. memcpy(fcport->fabric_port_name,
  2873. new_fcport->fabric_port_name, WWN_SIZE);
  2874. fcport->fp_speed = new_fcport->fp_speed;
  2875. /*
  2876. * If address the same and state FCS_ONLINE, nothing
  2877. * changed.
  2878. */
  2879. if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
  2880. atomic_read(&fcport->state) == FCS_ONLINE) {
  2881. break;
  2882. }
  2883. /*
  2884. * If device was not a fabric device before.
  2885. */
  2886. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2887. fcport->d_id.b24 = new_fcport->d_id.b24;
  2888. fcport->loop_id = FC_NO_LOOP_ID;
  2889. fcport->flags |= (FCF_FABRIC_DEVICE |
  2890. FCF_LOGIN_NEEDED);
  2891. break;
  2892. }
  2893. /*
  2894. * Port ID changed or device was marked to be updated;
  2895. * Log it out if still logged in and mark it for
  2896. * relogin later.
  2897. */
  2898. fcport->d_id.b24 = new_fcport->d_id.b24;
  2899. fcport->flags |= FCF_LOGIN_NEEDED;
  2900. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2901. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2902. fcport->port_type != FCT_INITIATOR &&
  2903. fcport->port_type != FCT_BROADCAST) {
  2904. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  2905. fcport->d_id.b.domain, fcport->d_id.b.area,
  2906. fcport->d_id.b.al_pa);
  2907. fcport->loop_id = FC_NO_LOOP_ID;
  2908. }
  2909. break;
  2910. }
  2911. if (found)
  2912. continue;
  2913. /* If device was not in our fcports list, then add it. */
  2914. list_add_tail(&new_fcport->list, new_fcports);
  2915. /* Allocate a new replacement fcport. */
  2916. nxt_d_id.b24 = new_fcport->d_id.b24;
  2917. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2918. if (new_fcport == NULL) {
  2919. ql_log(ql_log_warn, vha, 0x2066,
  2920. "Memory allocation failed for fcport.\n");
  2921. kfree(swl);
  2922. return (QLA_MEMORY_ALLOC_FAILED);
  2923. }
  2924. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2925. new_fcport->d_id.b24 = nxt_d_id.b24;
  2926. }
  2927. kfree(swl);
  2928. kfree(new_fcport);
  2929. return (rval);
  2930. }
  2931. /*
  2932. * qla2x00_find_new_loop_id
  2933. * Scan through our port list and find a new usable loop ID.
  2934. *
  2935. * Input:
  2936. * ha: adapter state pointer.
  2937. * dev: port structure pointer.
  2938. *
  2939. * Returns:
  2940. * qla2x00 local function return status code.
  2941. *
  2942. * Context:
  2943. * Kernel context.
  2944. */
  2945. int
  2946. qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
  2947. {
  2948. int rval;
  2949. int found;
  2950. fc_port_t *fcport;
  2951. uint16_t first_loop_id;
  2952. struct qla_hw_data *ha = vha->hw;
  2953. struct scsi_qla_host *vp;
  2954. struct scsi_qla_host *tvp;
  2955. unsigned long flags = 0;
  2956. rval = QLA_SUCCESS;
  2957. /* Save starting loop ID. */
  2958. first_loop_id = dev->loop_id;
  2959. for (;;) {
  2960. /* Skip loop ID if already used by adapter. */
  2961. if (dev->loop_id == vha->loop_id)
  2962. dev->loop_id++;
  2963. /* Skip reserved loop IDs. */
  2964. while (qla2x00_is_reserved_id(vha, dev->loop_id))
  2965. dev->loop_id++;
  2966. /* Reset loop ID if passed the end. */
  2967. if (dev->loop_id > ha->max_loop_id) {
  2968. /* first loop ID. */
  2969. dev->loop_id = ha->min_external_loopid;
  2970. }
  2971. /* Check for loop ID being already in use. */
  2972. found = 0;
  2973. fcport = NULL;
  2974. spin_lock_irqsave(&ha->vport_slock, flags);
  2975. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2976. list_for_each_entry(fcport, &vp->vp_fcports, list) {
  2977. if (fcport->loop_id == dev->loop_id &&
  2978. fcport != dev) {
  2979. /* ID possibly in use */
  2980. found++;
  2981. break;
  2982. }
  2983. }
  2984. if (found)
  2985. break;
  2986. }
  2987. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2988. /* If not in use then it is free to use. */
  2989. if (!found) {
  2990. break;
  2991. }
  2992. /* ID in use. Try next value. */
  2993. dev->loop_id++;
  2994. /* If wrap around. No free ID to use. */
  2995. if (dev->loop_id == first_loop_id) {
  2996. dev->loop_id = FC_NO_LOOP_ID;
  2997. rval = QLA_FUNCTION_FAILED;
  2998. break;
  2999. }
  3000. }
  3001. return (rval);
  3002. }
  3003. /*
  3004. * qla2x00_device_resync
  3005. * Marks devices in the database that needs resynchronization.
  3006. *
  3007. * Input:
  3008. * ha = adapter block pointer.
  3009. *
  3010. * Context:
  3011. * Kernel context.
  3012. */
  3013. static int
  3014. qla2x00_device_resync(scsi_qla_host_t *vha)
  3015. {
  3016. int rval;
  3017. uint32_t mask;
  3018. fc_port_t *fcport;
  3019. uint32_t rscn_entry;
  3020. uint8_t rscn_out_iter;
  3021. uint8_t format;
  3022. port_id_t d_id = {};
  3023. rval = QLA_RSCNS_HANDLED;
  3024. while (vha->rscn_out_ptr != vha->rscn_in_ptr ||
  3025. vha->flags.rscn_queue_overflow) {
  3026. rscn_entry = vha->rscn_queue[vha->rscn_out_ptr];
  3027. format = MSB(MSW(rscn_entry));
  3028. d_id.b.domain = LSB(MSW(rscn_entry));
  3029. d_id.b.area = MSB(LSW(rscn_entry));
  3030. d_id.b.al_pa = LSB(LSW(rscn_entry));
  3031. ql_dbg(ql_dbg_disc, vha, 0x2020,
  3032. "RSCN queue entry[%d] = [%02x/%02x%02x%02x].\n",
  3033. vha->rscn_out_ptr, format, d_id.b.domain, d_id.b.area,
  3034. d_id.b.al_pa);
  3035. vha->rscn_out_ptr++;
  3036. if (vha->rscn_out_ptr == MAX_RSCN_COUNT)
  3037. vha->rscn_out_ptr = 0;
  3038. /* Skip duplicate entries. */
  3039. for (rscn_out_iter = vha->rscn_out_ptr;
  3040. !vha->flags.rscn_queue_overflow &&
  3041. rscn_out_iter != vha->rscn_in_ptr;
  3042. rscn_out_iter = (rscn_out_iter ==
  3043. (MAX_RSCN_COUNT - 1)) ? 0: rscn_out_iter + 1) {
  3044. if (rscn_entry != vha->rscn_queue[rscn_out_iter])
  3045. break;
  3046. ql_dbg(ql_dbg_disc, vha, 0x2021,
  3047. "Skipping duplicate RSCN queue entry found at "
  3048. "[%d].\n", rscn_out_iter);
  3049. vha->rscn_out_ptr = rscn_out_iter;
  3050. }
  3051. /* Queue overflow, set switch default case. */
  3052. if (vha->flags.rscn_queue_overflow) {
  3053. ql_dbg(ql_dbg_disc, vha, 0x2022,
  3054. "device_resync: rscn overflow.\n");
  3055. format = 3;
  3056. vha->flags.rscn_queue_overflow = 0;
  3057. }
  3058. switch (format) {
  3059. case 0:
  3060. mask = 0xffffff;
  3061. break;
  3062. case 1:
  3063. mask = 0xffff00;
  3064. break;
  3065. case 2:
  3066. mask = 0xff0000;
  3067. break;
  3068. default:
  3069. mask = 0x0;
  3070. d_id.b24 = 0;
  3071. vha->rscn_out_ptr = vha->rscn_in_ptr;
  3072. break;
  3073. }
  3074. rval = QLA_SUCCESS;
  3075. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3076. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
  3077. (fcport->d_id.b24 & mask) != d_id.b24 ||
  3078. fcport->port_type == FCT_BROADCAST)
  3079. continue;
  3080. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  3081. if (format != 3 ||
  3082. fcport->port_type != FCT_INITIATOR) {
  3083. qla2x00_mark_device_lost(vha, fcport,
  3084. 0, 0);
  3085. }
  3086. }
  3087. }
  3088. }
  3089. return (rval);
  3090. }
  3091. /*
  3092. * qla2x00_fabric_dev_login
  3093. * Login fabric target device and update FC port database.
  3094. *
  3095. * Input:
  3096. * ha: adapter state pointer.
  3097. * fcport: port structure list pointer.
  3098. * next_loopid: contains value of a new loop ID that can be used
  3099. * by the next login attempt.
  3100. *
  3101. * Returns:
  3102. * qla2x00 local function return status code.
  3103. *
  3104. * Context:
  3105. * Kernel context.
  3106. */
  3107. static int
  3108. qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  3109. uint16_t *next_loopid)
  3110. {
  3111. int rval;
  3112. int retry;
  3113. uint8_t opts;
  3114. struct qla_hw_data *ha = vha->hw;
  3115. rval = QLA_SUCCESS;
  3116. retry = 0;
  3117. if (IS_ALOGIO_CAPABLE(ha)) {
  3118. if (fcport->flags & FCF_ASYNC_SENT)
  3119. return rval;
  3120. fcport->flags |= FCF_ASYNC_SENT;
  3121. rval = qla2x00_post_async_login_work(vha, fcport, NULL);
  3122. if (!rval)
  3123. return rval;
  3124. }
  3125. fcport->flags &= ~FCF_ASYNC_SENT;
  3126. rval = qla2x00_fabric_login(vha, fcport, next_loopid);
  3127. if (rval == QLA_SUCCESS) {
  3128. /* Send an ADISC to FCP2 devices.*/
  3129. opts = 0;
  3130. if (fcport->flags & FCF_FCP2_DEVICE)
  3131. opts |= BIT_1;
  3132. rval = qla2x00_get_port_database(vha, fcport, opts);
  3133. if (rval != QLA_SUCCESS) {
  3134. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3135. fcport->d_id.b.domain, fcport->d_id.b.area,
  3136. fcport->d_id.b.al_pa);
  3137. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3138. } else {
  3139. qla2x00_update_fcport(vha, fcport);
  3140. }
  3141. }
  3142. return (rval);
  3143. }
  3144. /*
  3145. * qla2x00_fabric_login
  3146. * Issue fabric login command.
  3147. *
  3148. * Input:
  3149. * ha = adapter block pointer.
  3150. * device = pointer to FC device type structure.
  3151. *
  3152. * Returns:
  3153. * 0 - Login successfully
  3154. * 1 - Login failed
  3155. * 2 - Initiator device
  3156. * 3 - Fatal error
  3157. */
  3158. int
  3159. qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  3160. uint16_t *next_loopid)
  3161. {
  3162. int rval;
  3163. int retry;
  3164. uint16_t tmp_loopid;
  3165. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3166. struct qla_hw_data *ha = vha->hw;
  3167. retry = 0;
  3168. tmp_loopid = 0;
  3169. for (;;) {
  3170. ql_dbg(ql_dbg_disc, vha, 0x2000,
  3171. "Trying Fabric Login w/loop id 0x%04x for port "
  3172. "%02x%02x%02x.\n",
  3173. fcport->loop_id, fcport->d_id.b.domain,
  3174. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3175. /* Login fcport on switch. */
  3176. ha->isp_ops->fabric_login(vha, fcport->loop_id,
  3177. fcport->d_id.b.domain, fcport->d_id.b.area,
  3178. fcport->d_id.b.al_pa, mb, BIT_0);
  3179. if (mb[0] == MBS_PORT_ID_USED) {
  3180. /*
  3181. * Device has another loop ID. The firmware team
  3182. * recommends the driver perform an implicit login with
  3183. * the specified ID again. The ID we just used is save
  3184. * here so we return with an ID that can be tried by
  3185. * the next login.
  3186. */
  3187. retry++;
  3188. tmp_loopid = fcport->loop_id;
  3189. fcport->loop_id = mb[1];
  3190. ql_dbg(ql_dbg_disc, vha, 0x2001,
  3191. "Fabric Login: port in use - next loop "
  3192. "id=0x%04x, port id= %02x%02x%02x.\n",
  3193. fcport->loop_id, fcport->d_id.b.domain,
  3194. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3195. } else if (mb[0] == MBS_COMMAND_COMPLETE) {
  3196. /*
  3197. * Login succeeded.
  3198. */
  3199. if (retry) {
  3200. /* A retry occurred before. */
  3201. *next_loopid = tmp_loopid;
  3202. } else {
  3203. /*
  3204. * No retry occurred before. Just increment the
  3205. * ID value for next login.
  3206. */
  3207. *next_loopid = (fcport->loop_id + 1);
  3208. }
  3209. if (mb[1] & BIT_0) {
  3210. fcport->port_type = FCT_INITIATOR;
  3211. } else {
  3212. fcport->port_type = FCT_TARGET;
  3213. if (mb[1] & BIT_1) {
  3214. fcport->flags |= FCF_FCP2_DEVICE;
  3215. }
  3216. }
  3217. if (mb[10] & BIT_0)
  3218. fcport->supported_classes |= FC_COS_CLASS2;
  3219. if (mb[10] & BIT_1)
  3220. fcport->supported_classes |= FC_COS_CLASS3;
  3221. rval = QLA_SUCCESS;
  3222. break;
  3223. } else if (mb[0] == MBS_LOOP_ID_USED) {
  3224. /*
  3225. * Loop ID already used, try next loop ID.
  3226. */
  3227. fcport->loop_id++;
  3228. rval = qla2x00_find_new_loop_id(vha, fcport);
  3229. if (rval != QLA_SUCCESS) {
  3230. /* Ran out of loop IDs to use */
  3231. break;
  3232. }
  3233. } else if (mb[0] == MBS_COMMAND_ERROR) {
  3234. /*
  3235. * Firmware possibly timed out during login. If NO
  3236. * retries are left to do then the device is declared
  3237. * dead.
  3238. */
  3239. *next_loopid = fcport->loop_id;
  3240. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3241. fcport->d_id.b.domain, fcport->d_id.b.area,
  3242. fcport->d_id.b.al_pa);
  3243. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3244. rval = 1;
  3245. break;
  3246. } else {
  3247. /*
  3248. * unrecoverable / not handled error
  3249. */
  3250. ql_dbg(ql_dbg_disc, vha, 0x2002,
  3251. "Failed=%x port_id=%02x%02x%02x loop_id=%x "
  3252. "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
  3253. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  3254. fcport->loop_id, jiffies);
  3255. *next_loopid = fcport->loop_id;
  3256. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3257. fcport->d_id.b.domain, fcport->d_id.b.area,
  3258. fcport->d_id.b.al_pa);
  3259. fcport->loop_id = FC_NO_LOOP_ID;
  3260. fcport->login_retry = 0;
  3261. rval = 3;
  3262. break;
  3263. }
  3264. }
  3265. return (rval);
  3266. }
  3267. /*
  3268. * qla2x00_local_device_login
  3269. * Issue local device login command.
  3270. *
  3271. * Input:
  3272. * ha = adapter block pointer.
  3273. * loop_id = loop id of device to login to.
  3274. *
  3275. * Returns (Where's the #define!!!!):
  3276. * 0 - Login successfully
  3277. * 1 - Login failed
  3278. * 3 - Fatal error
  3279. */
  3280. int
  3281. qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
  3282. {
  3283. int rval;
  3284. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3285. memset(mb, 0, sizeof(mb));
  3286. rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
  3287. if (rval == QLA_SUCCESS) {
  3288. /* Interrogate mailbox registers for any errors */
  3289. if (mb[0] == MBS_COMMAND_ERROR)
  3290. rval = 1;
  3291. else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
  3292. /* device not in PCB table */
  3293. rval = 3;
  3294. }
  3295. return (rval);
  3296. }
  3297. /*
  3298. * qla2x00_loop_resync
  3299. * Resync with fibre channel devices.
  3300. *
  3301. * Input:
  3302. * ha = adapter block pointer.
  3303. *
  3304. * Returns:
  3305. * 0 = success
  3306. */
  3307. int
  3308. qla2x00_loop_resync(scsi_qla_host_t *vha)
  3309. {
  3310. int rval = QLA_SUCCESS;
  3311. uint32_t wait_time;
  3312. struct req_que *req;
  3313. struct rsp_que *rsp;
  3314. if (vha->hw->flags.cpu_affinity_enabled)
  3315. req = vha->hw->req_q_map[0];
  3316. else
  3317. req = vha->req;
  3318. rsp = req->rsp;
  3319. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3320. if (vha->flags.online) {
  3321. if (!(rval = qla2x00_fw_ready(vha))) {
  3322. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3323. wait_time = 256;
  3324. do {
  3325. /* Issue a marker after FW becomes ready. */
  3326. qla2x00_marker(vha, req, rsp, 0, 0,
  3327. MK_SYNC_ALL);
  3328. vha->marker_needed = 0;
  3329. /* Remap devices on Loop. */
  3330. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3331. qla2x00_configure_loop(vha);
  3332. wait_time--;
  3333. } while (!atomic_read(&vha->loop_down_timer) &&
  3334. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3335. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3336. &vha->dpc_flags)));
  3337. }
  3338. }
  3339. if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3340. return (QLA_FUNCTION_FAILED);
  3341. if (rval)
  3342. ql_dbg(ql_dbg_disc, vha, 0x206c,
  3343. "%s *** FAILED ***.\n", __func__);
  3344. return (rval);
  3345. }
  3346. /*
  3347. * qla2x00_perform_loop_resync
  3348. * Description: This function will set the appropriate flags and call
  3349. * qla2x00_loop_resync. If successful loop will be resynced
  3350. * Arguments : scsi_qla_host_t pointer
  3351. * returm : Success or Failure
  3352. */
  3353. int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
  3354. {
  3355. int32_t rval = 0;
  3356. if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
  3357. /*Configure the flags so that resync happens properly*/
  3358. atomic_set(&ha->loop_down_timer, 0);
  3359. if (!(ha->device_flags & DFLG_NO_CABLE)) {
  3360. atomic_set(&ha->loop_state, LOOP_UP);
  3361. set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
  3362. set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
  3363. set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
  3364. rval = qla2x00_loop_resync(ha);
  3365. } else
  3366. atomic_set(&ha->loop_state, LOOP_DEAD);
  3367. clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
  3368. }
  3369. return rval;
  3370. }
  3371. void
  3372. qla2x00_update_fcports(scsi_qla_host_t *base_vha)
  3373. {
  3374. fc_port_t *fcport;
  3375. struct scsi_qla_host *vha;
  3376. struct qla_hw_data *ha = base_vha->hw;
  3377. unsigned long flags;
  3378. spin_lock_irqsave(&ha->vport_slock, flags);
  3379. /* Go with deferred removal of rport references. */
  3380. list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
  3381. atomic_inc(&vha->vref_count);
  3382. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3383. if (fcport->drport &&
  3384. atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
  3385. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3386. qla2x00_rport_del(fcport);
  3387. spin_lock_irqsave(&ha->vport_slock, flags);
  3388. }
  3389. }
  3390. atomic_dec(&vha->vref_count);
  3391. }
  3392. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3393. }
  3394. /*
  3395. * qla82xx_quiescent_state_cleanup
  3396. * Description: This function will block the new I/Os
  3397. * Its not aborting any I/Os as context
  3398. * is not destroyed during quiescence
  3399. * Arguments: scsi_qla_host_t
  3400. * return : void
  3401. */
  3402. void
  3403. qla82xx_quiescent_state_cleanup(scsi_qla_host_t *vha)
  3404. {
  3405. struct qla_hw_data *ha = vha->hw;
  3406. struct scsi_qla_host *vp;
  3407. ql_dbg(ql_dbg_p3p, vha, 0xb002,
  3408. "Performing ISP error recovery - ha=%p.\n", ha);
  3409. atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
  3410. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3411. atomic_set(&vha->loop_state, LOOP_DOWN);
  3412. qla2x00_mark_all_devices_lost(vha, 0);
  3413. list_for_each_entry(vp, &ha->vp_list, list)
  3414. qla2x00_mark_all_devices_lost(vha, 0);
  3415. } else {
  3416. if (!atomic_read(&vha->loop_down_timer))
  3417. atomic_set(&vha->loop_down_timer,
  3418. LOOP_DOWN_TIME);
  3419. }
  3420. /* Wait for pending cmds to complete */
  3421. qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
  3422. }
  3423. void
  3424. qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
  3425. {
  3426. struct qla_hw_data *ha = vha->hw;
  3427. struct scsi_qla_host *vp;
  3428. unsigned long flags;
  3429. fc_port_t *fcport;
  3430. /* For ISP82XX, driver waits for completion of the commands.
  3431. * online flag should be set.
  3432. */
  3433. if (!IS_QLA82XX(ha))
  3434. vha->flags.online = 0;
  3435. ha->flags.chip_reset_done = 0;
  3436. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3437. ha->qla_stats.total_isp_aborts++;
  3438. ql_log(ql_log_info, vha, 0x00af,
  3439. "Performing ISP error recovery - ha=%p.\n", ha);
  3440. /* For ISP82XX, reset_chip is just disabling interrupts.
  3441. * Driver waits for the completion of the commands.
  3442. * the interrupts need to be enabled.
  3443. */
  3444. if (!IS_QLA82XX(ha))
  3445. ha->isp_ops->reset_chip(vha);
  3446. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  3447. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3448. atomic_set(&vha->loop_state, LOOP_DOWN);
  3449. qla2x00_mark_all_devices_lost(vha, 0);
  3450. spin_lock_irqsave(&ha->vport_slock, flags);
  3451. list_for_each_entry(vp, &ha->vp_list, list) {
  3452. atomic_inc(&vp->vref_count);
  3453. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3454. qla2x00_mark_all_devices_lost(vp, 0);
  3455. spin_lock_irqsave(&ha->vport_slock, flags);
  3456. atomic_dec(&vp->vref_count);
  3457. }
  3458. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3459. } else {
  3460. if (!atomic_read(&vha->loop_down_timer))
  3461. atomic_set(&vha->loop_down_timer,
  3462. LOOP_DOWN_TIME);
  3463. }
  3464. /* Clear all async request states across all VPs. */
  3465. list_for_each_entry(fcport, &vha->vp_fcports, list)
  3466. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3467. spin_lock_irqsave(&ha->vport_slock, flags);
  3468. list_for_each_entry(vp, &ha->vp_list, list) {
  3469. atomic_inc(&vp->vref_count);
  3470. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3471. list_for_each_entry(fcport, &vp->vp_fcports, list)
  3472. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3473. spin_lock_irqsave(&ha->vport_slock, flags);
  3474. atomic_dec(&vp->vref_count);
  3475. }
  3476. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3477. if (!ha->flags.eeh_busy) {
  3478. /* Make sure for ISP 82XX IO DMA is complete */
  3479. if (IS_QLA82XX(ha)) {
  3480. qla82xx_chip_reset_cleanup(vha);
  3481. ql_log(ql_log_info, vha, 0x00b4,
  3482. "Done chip reset cleanup.\n");
  3483. /* Done waiting for pending commands.
  3484. * Reset the online flag.
  3485. */
  3486. vha->flags.online = 0;
  3487. }
  3488. /* Requeue all commands in outstanding command list. */
  3489. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3490. }
  3491. }
  3492. /*
  3493. * qla2x00_abort_isp
  3494. * Resets ISP and aborts all outstanding commands.
  3495. *
  3496. * Input:
  3497. * ha = adapter block pointer.
  3498. *
  3499. * Returns:
  3500. * 0 = success
  3501. */
  3502. int
  3503. qla2x00_abort_isp(scsi_qla_host_t *vha)
  3504. {
  3505. int rval;
  3506. uint8_t status = 0;
  3507. struct qla_hw_data *ha = vha->hw;
  3508. struct scsi_qla_host *vp;
  3509. struct req_que *req = ha->req_q_map[0];
  3510. unsigned long flags;
  3511. if (vha->flags.online) {
  3512. qla2x00_abort_isp_cleanup(vha);
  3513. if (unlikely(pci_channel_offline(ha->pdev) &&
  3514. ha->flags.pci_channel_io_perm_failure)) {
  3515. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3516. status = 0;
  3517. return status;
  3518. }
  3519. ha->isp_ops->get_flash_version(vha, req->ring);
  3520. ha->isp_ops->nvram_config(vha);
  3521. if (!qla2x00_restart_isp(vha)) {
  3522. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3523. if (!atomic_read(&vha->loop_down_timer)) {
  3524. /*
  3525. * Issue marker command only when we are going
  3526. * to start the I/O .
  3527. */
  3528. vha->marker_needed = 1;
  3529. }
  3530. vha->flags.online = 1;
  3531. ha->isp_ops->enable_intrs(ha);
  3532. ha->isp_abort_cnt = 0;
  3533. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3534. if (IS_QLA81XX(ha))
  3535. qla2x00_get_fw_version(vha,
  3536. &ha->fw_major_version,
  3537. &ha->fw_minor_version,
  3538. &ha->fw_subminor_version,
  3539. &ha->fw_attributes, &ha->fw_memory_size,
  3540. ha->mpi_version, &ha->mpi_capabilities,
  3541. ha->phy_version);
  3542. if (ha->fce) {
  3543. ha->flags.fce_enabled = 1;
  3544. memset(ha->fce, 0,
  3545. fce_calc_size(ha->fce_bufs));
  3546. rval = qla2x00_enable_fce_trace(vha,
  3547. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  3548. &ha->fce_bufs);
  3549. if (rval) {
  3550. ql_log(ql_log_warn, vha, 0x8033,
  3551. "Unable to reinitialize FCE "
  3552. "(%d).\n", rval);
  3553. ha->flags.fce_enabled = 0;
  3554. }
  3555. }
  3556. if (ha->eft) {
  3557. memset(ha->eft, 0, EFT_SIZE);
  3558. rval = qla2x00_enable_eft_trace(vha,
  3559. ha->eft_dma, EFT_NUM_BUFFERS);
  3560. if (rval) {
  3561. ql_log(ql_log_warn, vha, 0x8034,
  3562. "Unable to reinitialize EFT "
  3563. "(%d).\n", rval);
  3564. }
  3565. }
  3566. } else { /* failed the ISP abort */
  3567. vha->flags.online = 1;
  3568. if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  3569. if (ha->isp_abort_cnt == 0) {
  3570. ql_log(ql_log_fatal, vha, 0x8035,
  3571. "ISP error recover failed - "
  3572. "board disabled.\n");
  3573. /*
  3574. * The next call disables the board
  3575. * completely.
  3576. */
  3577. ha->isp_ops->reset_adapter(vha);
  3578. vha->flags.online = 0;
  3579. clear_bit(ISP_ABORT_RETRY,
  3580. &vha->dpc_flags);
  3581. status = 0;
  3582. } else { /* schedule another ISP abort */
  3583. ha->isp_abort_cnt--;
  3584. ql_dbg(ql_dbg_taskm, vha, 0x8020,
  3585. "ISP abort - retry remaining %d.\n",
  3586. ha->isp_abort_cnt);
  3587. status = 1;
  3588. }
  3589. } else {
  3590. ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
  3591. ql_dbg(ql_dbg_taskm, vha, 0x8021,
  3592. "ISP error recovery - retrying (%d) "
  3593. "more times.\n", ha->isp_abort_cnt);
  3594. set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3595. status = 1;
  3596. }
  3597. }
  3598. }
  3599. if (!status) {
  3600. ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
  3601. spin_lock_irqsave(&ha->vport_slock, flags);
  3602. list_for_each_entry(vp, &ha->vp_list, list) {
  3603. if (vp->vp_idx) {
  3604. atomic_inc(&vp->vref_count);
  3605. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3606. qla2x00_vp_abort_isp(vp);
  3607. spin_lock_irqsave(&ha->vport_slock, flags);
  3608. atomic_dec(&vp->vref_count);
  3609. }
  3610. }
  3611. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3612. } else {
  3613. ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
  3614. __func__);
  3615. }
  3616. return(status);
  3617. }
  3618. /*
  3619. * qla2x00_restart_isp
  3620. * restarts the ISP after a reset
  3621. *
  3622. * Input:
  3623. * ha = adapter block pointer.
  3624. *
  3625. * Returns:
  3626. * 0 = success
  3627. */
  3628. static int
  3629. qla2x00_restart_isp(scsi_qla_host_t *vha)
  3630. {
  3631. int status = 0;
  3632. uint32_t wait_time;
  3633. struct qla_hw_data *ha = vha->hw;
  3634. struct req_que *req = ha->req_q_map[0];
  3635. struct rsp_que *rsp = ha->rsp_q_map[0];
  3636. /* If firmware needs to be loaded */
  3637. if (qla2x00_isp_firmware(vha)) {
  3638. vha->flags.online = 0;
  3639. status = ha->isp_ops->chip_diag(vha);
  3640. if (!status)
  3641. status = qla2x00_setup_chip(vha);
  3642. }
  3643. if (!status && !(status = qla2x00_init_rings(vha))) {
  3644. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3645. ha->flags.chip_reset_done = 1;
  3646. /* Initialize the queues in use */
  3647. qla25xx_init_queues(ha);
  3648. status = qla2x00_fw_ready(vha);
  3649. if (!status) {
  3650. ql_dbg(ql_dbg_taskm, vha, 0x8031,
  3651. "Start configure loop status = %d.\n", status);
  3652. /* Issue a marker after FW becomes ready. */
  3653. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  3654. vha->flags.online = 1;
  3655. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3656. wait_time = 256;
  3657. do {
  3658. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3659. qla2x00_configure_loop(vha);
  3660. wait_time--;
  3661. } while (!atomic_read(&vha->loop_down_timer) &&
  3662. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3663. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3664. &vha->dpc_flags)));
  3665. }
  3666. /* if no cable then assume it's good */
  3667. if ((vha->device_flags & DFLG_NO_CABLE))
  3668. status = 0;
  3669. ql_dbg(ql_dbg_taskm, vha, 0x8032,
  3670. "Configure loop done, status = 0x%x.\n", status);
  3671. }
  3672. return (status);
  3673. }
  3674. static int
  3675. qla25xx_init_queues(struct qla_hw_data *ha)
  3676. {
  3677. struct rsp_que *rsp = NULL;
  3678. struct req_que *req = NULL;
  3679. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  3680. int ret = -1;
  3681. int i;
  3682. for (i = 1; i < ha->max_rsp_queues; i++) {
  3683. rsp = ha->rsp_q_map[i];
  3684. if (rsp) {
  3685. rsp->options &= ~BIT_0;
  3686. ret = qla25xx_init_rsp_que(base_vha, rsp);
  3687. if (ret != QLA_SUCCESS)
  3688. ql_dbg(ql_dbg_init, base_vha, 0x00ff,
  3689. "%s Rsp que: %d init failed.\n",
  3690. __func__, rsp->id);
  3691. else
  3692. ql_dbg(ql_dbg_init, base_vha, 0x0100,
  3693. "%s Rsp que: %d inited.\n",
  3694. __func__, rsp->id);
  3695. }
  3696. }
  3697. for (i = 1; i < ha->max_req_queues; i++) {
  3698. req = ha->req_q_map[i];
  3699. if (req) {
  3700. /* Clear outstanding commands array. */
  3701. req->options &= ~BIT_0;
  3702. ret = qla25xx_init_req_que(base_vha, req);
  3703. if (ret != QLA_SUCCESS)
  3704. ql_dbg(ql_dbg_init, base_vha, 0x0101,
  3705. "%s Req que: %d init failed.\n",
  3706. __func__, req->id);
  3707. else
  3708. ql_dbg(ql_dbg_init, base_vha, 0x0102,
  3709. "%s Req que: %d inited.\n",
  3710. __func__, req->id);
  3711. }
  3712. }
  3713. return ret;
  3714. }
  3715. /*
  3716. * qla2x00_reset_adapter
  3717. * Reset adapter.
  3718. *
  3719. * Input:
  3720. * ha = adapter block pointer.
  3721. */
  3722. void
  3723. qla2x00_reset_adapter(scsi_qla_host_t *vha)
  3724. {
  3725. unsigned long flags = 0;
  3726. struct qla_hw_data *ha = vha->hw;
  3727. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3728. vha->flags.online = 0;
  3729. ha->isp_ops->disable_intrs(ha);
  3730. spin_lock_irqsave(&ha->hardware_lock, flags);
  3731. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  3732. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3733. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  3734. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3735. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3736. }
  3737. void
  3738. qla24xx_reset_adapter(scsi_qla_host_t *vha)
  3739. {
  3740. unsigned long flags = 0;
  3741. struct qla_hw_data *ha = vha->hw;
  3742. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3743. if (IS_QLA82XX(ha))
  3744. return;
  3745. vha->flags.online = 0;
  3746. ha->isp_ops->disable_intrs(ha);
  3747. spin_lock_irqsave(&ha->hardware_lock, flags);
  3748. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  3749. RD_REG_DWORD(&reg->hccr);
  3750. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  3751. RD_REG_DWORD(&reg->hccr);
  3752. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3753. if (IS_NOPOLLING_TYPE(ha))
  3754. ha->isp_ops->enable_intrs(ha);
  3755. }
  3756. /* On sparc systems, obtain port and node WWN from firmware
  3757. * properties.
  3758. */
  3759. static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
  3760. struct nvram_24xx *nv)
  3761. {
  3762. #ifdef CONFIG_SPARC
  3763. struct qla_hw_data *ha = vha->hw;
  3764. struct pci_dev *pdev = ha->pdev;
  3765. struct device_node *dp = pci_device_to_OF_node(pdev);
  3766. const u8 *val;
  3767. int len;
  3768. val = of_get_property(dp, "port-wwn", &len);
  3769. if (val && len >= WWN_SIZE)
  3770. memcpy(nv->port_name, val, WWN_SIZE);
  3771. val = of_get_property(dp, "node-wwn", &len);
  3772. if (val && len >= WWN_SIZE)
  3773. memcpy(nv->node_name, val, WWN_SIZE);
  3774. #endif
  3775. }
  3776. int
  3777. qla24xx_nvram_config(scsi_qla_host_t *vha)
  3778. {
  3779. int rval;
  3780. struct init_cb_24xx *icb;
  3781. struct nvram_24xx *nv;
  3782. uint32_t *dptr;
  3783. uint8_t *dptr1, *dptr2;
  3784. uint32_t chksum;
  3785. uint16_t cnt;
  3786. struct qla_hw_data *ha = vha->hw;
  3787. rval = QLA_SUCCESS;
  3788. icb = (struct init_cb_24xx *)ha->init_cb;
  3789. nv = ha->nvram;
  3790. /* Determine NVRAM starting address. */
  3791. if (ha->flags.port0) {
  3792. ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
  3793. ha->vpd_base = FA_NVRAM_VPD0_ADDR;
  3794. } else {
  3795. ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
  3796. ha->vpd_base = FA_NVRAM_VPD1_ADDR;
  3797. }
  3798. ha->nvram_size = sizeof(struct nvram_24xx);
  3799. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  3800. if (IS_QLA82XX(ha))
  3801. ha->vpd_size = FA_VPD_SIZE_82XX;
  3802. /* Get VPD data into cache */
  3803. ha->vpd = ha->nvram + VPD_OFFSET;
  3804. ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
  3805. ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
  3806. /* Get NVRAM data into cache and calculate checksum. */
  3807. dptr = (uint32_t *)nv;
  3808. ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
  3809. ha->nvram_size);
  3810. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  3811. chksum += le32_to_cpu(*dptr++);
  3812. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
  3813. "Contents of NVRAM\n");
  3814. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
  3815. (uint8_t *)nv, ha->nvram_size);
  3816. /* Bad NVRAM data, set defaults parameters. */
  3817. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  3818. || nv->id[3] != ' ' ||
  3819. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  3820. /* Reset NVRAM data. */
  3821. ql_log(ql_log_warn, vha, 0x006b,
  3822. "Inconisistent NVRAM detected: checksum=0x%x id=%c "
  3823. "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
  3824. ql_log(ql_log_warn, vha, 0x006c,
  3825. "Falling back to functioning (yet invalid -- WWPN) "
  3826. "defaults.\n");
  3827. /*
  3828. * Set default initialization control block.
  3829. */
  3830. memset(nv, 0, ha->nvram_size);
  3831. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  3832. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  3833. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  3834. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3835. nv->exchange_count = __constant_cpu_to_le16(0);
  3836. nv->hard_address = __constant_cpu_to_le16(124);
  3837. nv->port_name[0] = 0x21;
  3838. nv->port_name[1] = 0x00 + ha->port_no;
  3839. nv->port_name[2] = 0x00;
  3840. nv->port_name[3] = 0xe0;
  3841. nv->port_name[4] = 0x8b;
  3842. nv->port_name[5] = 0x1c;
  3843. nv->port_name[6] = 0x55;
  3844. nv->port_name[7] = 0x86;
  3845. nv->node_name[0] = 0x20;
  3846. nv->node_name[1] = 0x00;
  3847. nv->node_name[2] = 0x00;
  3848. nv->node_name[3] = 0xe0;
  3849. nv->node_name[4] = 0x8b;
  3850. nv->node_name[5] = 0x1c;
  3851. nv->node_name[6] = 0x55;
  3852. nv->node_name[7] = 0x86;
  3853. qla24xx_nvram_wwn_from_ofw(vha, nv);
  3854. nv->login_retry_count = __constant_cpu_to_le16(8);
  3855. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  3856. nv->login_timeout = __constant_cpu_to_le16(0);
  3857. nv->firmware_options_1 =
  3858. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  3859. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  3860. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  3861. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  3862. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  3863. nv->efi_parameters = __constant_cpu_to_le32(0);
  3864. nv->reset_delay = 5;
  3865. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  3866. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  3867. nv->link_down_timeout = __constant_cpu_to_le16(30);
  3868. rval = 1;
  3869. }
  3870. /* Reset Initialization control block */
  3871. memset(icb, 0, ha->init_cb_size);
  3872. /* Copy 1st segment. */
  3873. dptr1 = (uint8_t *)icb;
  3874. dptr2 = (uint8_t *)&nv->version;
  3875. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  3876. while (cnt--)
  3877. *dptr1++ = *dptr2++;
  3878. icb->login_retry_count = nv->login_retry_count;
  3879. icb->link_down_on_nos = nv->link_down_on_nos;
  3880. /* Copy 2nd segment. */
  3881. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  3882. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  3883. cnt = (uint8_t *)&icb->reserved_3 -
  3884. (uint8_t *)&icb->interrupt_delay_timer;
  3885. while (cnt--)
  3886. *dptr1++ = *dptr2++;
  3887. /*
  3888. * Setup driver NVRAM options.
  3889. */
  3890. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  3891. "QLA2462");
  3892. /* Use alternate WWN? */
  3893. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  3894. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  3895. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  3896. }
  3897. /* Prepare nodename */
  3898. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  3899. /*
  3900. * Firmware will apply the following mask if the nodename was
  3901. * not provided.
  3902. */
  3903. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  3904. icb->node_name[0] &= 0xF0;
  3905. }
  3906. /* Set host adapter parameters. */
  3907. ha->flags.disable_risc_code_load = 0;
  3908. ha->flags.enable_lip_reset = 0;
  3909. ha->flags.enable_lip_full_login =
  3910. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  3911. ha->flags.enable_target_reset =
  3912. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  3913. ha->flags.enable_led_scheme = 0;
  3914. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  3915. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  3916. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  3917. memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
  3918. sizeof(ha->fw_seriallink_options24));
  3919. /* save HBA serial number */
  3920. ha->serial0 = icb->port_name[5];
  3921. ha->serial1 = icb->port_name[6];
  3922. ha->serial2 = icb->port_name[7];
  3923. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  3924. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  3925. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3926. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  3927. /* Set minimum login_timeout to 4 seconds. */
  3928. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  3929. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  3930. if (le16_to_cpu(nv->login_timeout) < 4)
  3931. nv->login_timeout = __constant_cpu_to_le16(4);
  3932. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  3933. icb->login_timeout = nv->login_timeout;
  3934. /* Set minimum RATOV to 100 tenths of a second. */
  3935. ha->r_a_tov = 100;
  3936. ha->loop_reset_delay = nv->reset_delay;
  3937. /* Link Down Timeout = 0:
  3938. *
  3939. * When Port Down timer expires we will start returning
  3940. * I/O's to OS with "DID_NO_CONNECT".
  3941. *
  3942. * Link Down Timeout != 0:
  3943. *
  3944. * The driver waits for the link to come up after link down
  3945. * before returning I/Os to OS with "DID_NO_CONNECT".
  3946. */
  3947. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  3948. ha->loop_down_abort_time =
  3949. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  3950. } else {
  3951. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  3952. ha->loop_down_abort_time =
  3953. (LOOP_DOWN_TIME - ha->link_down_timeout);
  3954. }
  3955. /* Need enough time to try and get the port back. */
  3956. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  3957. if (qlport_down_retry)
  3958. ha->port_down_retry_count = qlport_down_retry;
  3959. /* Set login_retry_count */
  3960. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  3961. if (ha->port_down_retry_count ==
  3962. le16_to_cpu(nv->port_down_retry_count) &&
  3963. ha->port_down_retry_count > 3)
  3964. ha->login_retry_count = ha->port_down_retry_count;
  3965. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  3966. ha->login_retry_count = ha->port_down_retry_count;
  3967. if (ql2xloginretrycount)
  3968. ha->login_retry_count = ql2xloginretrycount;
  3969. /* Enable ZIO. */
  3970. if (!vha->flags.init_done) {
  3971. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  3972. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  3973. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  3974. le16_to_cpu(icb->interrupt_delay_timer): 2;
  3975. }
  3976. icb->firmware_options_2 &= __constant_cpu_to_le32(
  3977. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  3978. vha->flags.process_response_queue = 0;
  3979. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  3980. ha->zio_mode = QLA_ZIO_MODE_6;
  3981. ql_log(ql_log_info, vha, 0x006f,
  3982. "ZIO mode %d enabled; timer delay (%d us).\n",
  3983. ha->zio_mode, ha->zio_timer * 100);
  3984. icb->firmware_options_2 |= cpu_to_le32(
  3985. (uint32_t)ha->zio_mode);
  3986. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  3987. vha->flags.process_response_queue = 1;
  3988. }
  3989. if (rval) {
  3990. ql_log(ql_log_warn, vha, 0x0070,
  3991. "NVRAM configuration failed.\n");
  3992. }
  3993. return (rval);
  3994. }
  3995. static int
  3996. qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
  3997. uint32_t faddr)
  3998. {
  3999. int rval = QLA_SUCCESS;
  4000. int segments, fragment;
  4001. uint32_t *dcode, dlen;
  4002. uint32_t risc_addr;
  4003. uint32_t risc_size;
  4004. uint32_t i;
  4005. struct qla_hw_data *ha = vha->hw;
  4006. struct req_que *req = ha->req_q_map[0];
  4007. ql_dbg(ql_dbg_init, vha, 0x008b,
  4008. "FW: Loading firmware from flash (%x).\n", faddr);
  4009. rval = QLA_SUCCESS;
  4010. segments = FA_RISC_CODE_SEGMENTS;
  4011. dcode = (uint32_t *)req->ring;
  4012. *srisc_addr = 0;
  4013. /* Validate firmware image by checking version. */
  4014. qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
  4015. for (i = 0; i < 4; i++)
  4016. dcode[i] = be32_to_cpu(dcode[i]);
  4017. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  4018. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  4019. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  4020. dcode[3] == 0)) {
  4021. ql_log(ql_log_fatal, vha, 0x008c,
  4022. "Unable to verify the integrity of flash firmware "
  4023. "image.\n");
  4024. ql_log(ql_log_fatal, vha, 0x008d,
  4025. "Firmware data: %08x %08x %08x %08x.\n",
  4026. dcode[0], dcode[1], dcode[2], dcode[3]);
  4027. return QLA_FUNCTION_FAILED;
  4028. }
  4029. while (segments && rval == QLA_SUCCESS) {
  4030. /* Read segment's load information. */
  4031. qla24xx_read_flash_data(vha, dcode, faddr, 4);
  4032. risc_addr = be32_to_cpu(dcode[2]);
  4033. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  4034. risc_size = be32_to_cpu(dcode[3]);
  4035. fragment = 0;
  4036. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4037. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  4038. if (dlen > risc_size)
  4039. dlen = risc_size;
  4040. ql_dbg(ql_dbg_init, vha, 0x008e,
  4041. "Loading risc segment@ risc addr %x "
  4042. "number of dwords 0x%x offset 0x%x.\n",
  4043. risc_addr, dlen, faddr);
  4044. qla24xx_read_flash_data(vha, dcode, faddr, dlen);
  4045. for (i = 0; i < dlen; i++)
  4046. dcode[i] = swab32(dcode[i]);
  4047. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4048. dlen);
  4049. if (rval) {
  4050. ql_log(ql_log_fatal, vha, 0x008f,
  4051. "Failed to load segment %d of firmware.\n",
  4052. fragment);
  4053. break;
  4054. }
  4055. faddr += dlen;
  4056. risc_addr += dlen;
  4057. risc_size -= dlen;
  4058. fragment++;
  4059. }
  4060. /* Next segment. */
  4061. segments--;
  4062. }
  4063. return rval;
  4064. }
  4065. #define QLA_FW_URL "ftp://ftp.qlogic.com/outgoing/linux/firmware/"
  4066. int
  4067. qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4068. {
  4069. int rval;
  4070. int i, fragment;
  4071. uint16_t *wcode, *fwcode;
  4072. uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
  4073. struct fw_blob *blob;
  4074. struct qla_hw_data *ha = vha->hw;
  4075. struct req_que *req = ha->req_q_map[0];
  4076. /* Load firmware blob. */
  4077. blob = qla2x00_request_firmware(vha);
  4078. if (!blob) {
  4079. ql_log(ql_log_info, vha, 0x0083,
  4080. "Fimware image unavailable.\n");
  4081. ql_log(ql_log_info, vha, 0x0084,
  4082. "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
  4083. return QLA_FUNCTION_FAILED;
  4084. }
  4085. rval = QLA_SUCCESS;
  4086. wcode = (uint16_t *)req->ring;
  4087. *srisc_addr = 0;
  4088. fwcode = (uint16_t *)blob->fw->data;
  4089. fwclen = 0;
  4090. /* Validate firmware image by checking version. */
  4091. if (blob->fw->size < 8 * sizeof(uint16_t)) {
  4092. ql_log(ql_log_fatal, vha, 0x0085,
  4093. "Unable to verify integrity of firmware image (%Zd).\n",
  4094. blob->fw->size);
  4095. goto fail_fw_integrity;
  4096. }
  4097. for (i = 0; i < 4; i++)
  4098. wcode[i] = be16_to_cpu(fwcode[i + 4]);
  4099. if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
  4100. wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
  4101. wcode[2] == 0 && wcode[3] == 0)) {
  4102. ql_log(ql_log_fatal, vha, 0x0086,
  4103. "Unable to verify integrity of firmware image.\n");
  4104. ql_log(ql_log_fatal, vha, 0x0087,
  4105. "Firmware data: %04x %04x %04x %04x.\n",
  4106. wcode[0], wcode[1], wcode[2], wcode[3]);
  4107. goto fail_fw_integrity;
  4108. }
  4109. seg = blob->segs;
  4110. while (*seg && rval == QLA_SUCCESS) {
  4111. risc_addr = *seg;
  4112. *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
  4113. risc_size = be16_to_cpu(fwcode[3]);
  4114. /* Validate firmware image size. */
  4115. fwclen += risc_size * sizeof(uint16_t);
  4116. if (blob->fw->size < fwclen) {
  4117. ql_log(ql_log_fatal, vha, 0x0088,
  4118. "Unable to verify integrity of firmware image "
  4119. "(%Zd).\n", blob->fw->size);
  4120. goto fail_fw_integrity;
  4121. }
  4122. fragment = 0;
  4123. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4124. wlen = (uint16_t)(ha->fw_transfer_size >> 1);
  4125. if (wlen > risc_size)
  4126. wlen = risc_size;
  4127. ql_dbg(ql_dbg_init, vha, 0x0089,
  4128. "Loading risc segment@ risc addr %x number of "
  4129. "words 0x%x.\n", risc_addr, wlen);
  4130. for (i = 0; i < wlen; i++)
  4131. wcode[i] = swab16(fwcode[i]);
  4132. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4133. wlen);
  4134. if (rval) {
  4135. ql_log(ql_log_fatal, vha, 0x008a,
  4136. "Failed to load segment %d of firmware.\n",
  4137. fragment);
  4138. break;
  4139. }
  4140. fwcode += wlen;
  4141. risc_addr += wlen;
  4142. risc_size -= wlen;
  4143. fragment++;
  4144. }
  4145. /* Next segment. */
  4146. seg++;
  4147. }
  4148. return rval;
  4149. fail_fw_integrity:
  4150. return QLA_FUNCTION_FAILED;
  4151. }
  4152. static int
  4153. qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4154. {
  4155. int rval;
  4156. int segments, fragment;
  4157. uint32_t *dcode, dlen;
  4158. uint32_t risc_addr;
  4159. uint32_t risc_size;
  4160. uint32_t i;
  4161. struct fw_blob *blob;
  4162. uint32_t *fwcode, fwclen;
  4163. struct qla_hw_data *ha = vha->hw;
  4164. struct req_que *req = ha->req_q_map[0];
  4165. /* Load firmware blob. */
  4166. blob = qla2x00_request_firmware(vha);
  4167. if (!blob) {
  4168. ql_log(ql_log_warn, vha, 0x0090,
  4169. "Fimware image unavailable.\n");
  4170. ql_log(ql_log_warn, vha, 0x0091,
  4171. "Firmware images can be retrieved from: "
  4172. QLA_FW_URL ".\n");
  4173. return QLA_FUNCTION_FAILED;
  4174. }
  4175. ql_dbg(ql_dbg_init, vha, 0x0092,
  4176. "FW: Loading via request-firmware.\n");
  4177. rval = QLA_SUCCESS;
  4178. segments = FA_RISC_CODE_SEGMENTS;
  4179. dcode = (uint32_t *)req->ring;
  4180. *srisc_addr = 0;
  4181. fwcode = (uint32_t *)blob->fw->data;
  4182. fwclen = 0;
  4183. /* Validate firmware image by checking version. */
  4184. if (blob->fw->size < 8 * sizeof(uint32_t)) {
  4185. ql_log(ql_log_fatal, vha, 0x0093,
  4186. "Unable to verify integrity of firmware image (%Zd).\n",
  4187. blob->fw->size);
  4188. goto fail_fw_integrity;
  4189. }
  4190. for (i = 0; i < 4; i++)
  4191. dcode[i] = be32_to_cpu(fwcode[i + 4]);
  4192. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  4193. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  4194. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  4195. dcode[3] == 0)) {
  4196. ql_log(ql_log_fatal, vha, 0x0094,
  4197. "Unable to verify integrity of firmware image (%Zd).\n",
  4198. blob->fw->size);
  4199. ql_log(ql_log_fatal, vha, 0x0095,
  4200. "Firmware data: %08x %08x %08x %08x.\n",
  4201. dcode[0], dcode[1], dcode[2], dcode[3]);
  4202. goto fail_fw_integrity;
  4203. }
  4204. while (segments && rval == QLA_SUCCESS) {
  4205. risc_addr = be32_to_cpu(fwcode[2]);
  4206. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  4207. risc_size = be32_to_cpu(fwcode[3]);
  4208. /* Validate firmware image size. */
  4209. fwclen += risc_size * sizeof(uint32_t);
  4210. if (blob->fw->size < fwclen) {
  4211. ql_log(ql_log_fatal, vha, 0x0096,
  4212. "Unable to verify integrity of firmware image "
  4213. "(%Zd).\n", blob->fw->size);
  4214. goto fail_fw_integrity;
  4215. }
  4216. fragment = 0;
  4217. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4218. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  4219. if (dlen > risc_size)
  4220. dlen = risc_size;
  4221. ql_dbg(ql_dbg_init, vha, 0x0097,
  4222. "Loading risc segment@ risc addr %x "
  4223. "number of dwords 0x%x.\n", risc_addr, dlen);
  4224. for (i = 0; i < dlen; i++)
  4225. dcode[i] = swab32(fwcode[i]);
  4226. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4227. dlen);
  4228. if (rval) {
  4229. ql_log(ql_log_fatal, vha, 0x0098,
  4230. "Failed to load segment %d of firmware.\n",
  4231. fragment);
  4232. break;
  4233. }
  4234. fwcode += dlen;
  4235. risc_addr += dlen;
  4236. risc_size -= dlen;
  4237. fragment++;
  4238. }
  4239. /* Next segment. */
  4240. segments--;
  4241. }
  4242. return rval;
  4243. fail_fw_integrity:
  4244. return QLA_FUNCTION_FAILED;
  4245. }
  4246. int
  4247. qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4248. {
  4249. int rval;
  4250. if (ql2xfwloadbin == 1)
  4251. return qla81xx_load_risc(vha, srisc_addr);
  4252. /*
  4253. * FW Load priority:
  4254. * 1) Firmware via request-firmware interface (.bin file).
  4255. * 2) Firmware residing in flash.
  4256. */
  4257. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4258. if (rval == QLA_SUCCESS)
  4259. return rval;
  4260. return qla24xx_load_risc_flash(vha, srisc_addr,
  4261. vha->hw->flt_region_fw);
  4262. }
  4263. int
  4264. qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4265. {
  4266. int rval;
  4267. struct qla_hw_data *ha = vha->hw;
  4268. if (ql2xfwloadbin == 2)
  4269. goto try_blob_fw;
  4270. /*
  4271. * FW Load priority:
  4272. * 1) Firmware residing in flash.
  4273. * 2) Firmware via request-firmware interface (.bin file).
  4274. * 3) Golden-Firmware residing in flash -- limited operation.
  4275. */
  4276. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
  4277. if (rval == QLA_SUCCESS)
  4278. return rval;
  4279. try_blob_fw:
  4280. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4281. if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
  4282. return rval;
  4283. ql_log(ql_log_info, vha, 0x0099,
  4284. "Attempting to fallback to golden firmware.\n");
  4285. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
  4286. if (rval != QLA_SUCCESS)
  4287. return rval;
  4288. ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
  4289. ha->flags.running_gold_fw = 1;
  4290. return rval;
  4291. }
  4292. void
  4293. qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
  4294. {
  4295. int ret, retries;
  4296. struct qla_hw_data *ha = vha->hw;
  4297. if (ha->flags.pci_channel_io_perm_failure)
  4298. return;
  4299. if (!IS_FWI2_CAPABLE(ha))
  4300. return;
  4301. if (!ha->fw_major_version)
  4302. return;
  4303. ret = qla2x00_stop_firmware(vha);
  4304. for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
  4305. ret != QLA_INVALID_COMMAND && retries ; retries--) {
  4306. ha->isp_ops->reset_chip(vha);
  4307. if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
  4308. continue;
  4309. if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
  4310. continue;
  4311. ql_log(ql_log_info, vha, 0x8015,
  4312. "Attempting retry of stop-firmware command.\n");
  4313. ret = qla2x00_stop_firmware(vha);
  4314. }
  4315. }
  4316. int
  4317. qla24xx_configure_vhba(scsi_qla_host_t *vha)
  4318. {
  4319. int rval = QLA_SUCCESS;
  4320. uint16_t mb[MAILBOX_REGISTER_COUNT];
  4321. struct qla_hw_data *ha = vha->hw;
  4322. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  4323. struct req_que *req;
  4324. struct rsp_que *rsp;
  4325. if (!vha->vp_idx)
  4326. return -EINVAL;
  4327. rval = qla2x00_fw_ready(base_vha);
  4328. if (ha->flags.cpu_affinity_enabled)
  4329. req = ha->req_q_map[0];
  4330. else
  4331. req = vha->req;
  4332. rsp = req->rsp;
  4333. if (rval == QLA_SUCCESS) {
  4334. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4335. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4336. }
  4337. vha->flags.management_server_logged_in = 0;
  4338. /* Login to SNS first */
  4339. ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, BIT_1);
  4340. if (mb[0] != MBS_COMMAND_COMPLETE) {
  4341. ql_dbg(ql_dbg_init, vha, 0x0103,
  4342. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
  4343. "mb[6]=%x mb[7]=%x.\n",
  4344. NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
  4345. return (QLA_FUNCTION_FAILED);
  4346. }
  4347. atomic_set(&vha->loop_down_timer, 0);
  4348. atomic_set(&vha->loop_state, LOOP_UP);
  4349. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4350. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  4351. rval = qla2x00_loop_resync(base_vha);
  4352. return rval;
  4353. }
  4354. /* 84XX Support **************************************************************/
  4355. static LIST_HEAD(qla_cs84xx_list);
  4356. static DEFINE_MUTEX(qla_cs84xx_mutex);
  4357. static struct qla_chip_state_84xx *
  4358. qla84xx_get_chip(struct scsi_qla_host *vha)
  4359. {
  4360. struct qla_chip_state_84xx *cs84xx;
  4361. struct qla_hw_data *ha = vha->hw;
  4362. mutex_lock(&qla_cs84xx_mutex);
  4363. /* Find any shared 84xx chip. */
  4364. list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
  4365. if (cs84xx->bus == ha->pdev->bus) {
  4366. kref_get(&cs84xx->kref);
  4367. goto done;
  4368. }
  4369. }
  4370. cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
  4371. if (!cs84xx)
  4372. goto done;
  4373. kref_init(&cs84xx->kref);
  4374. spin_lock_init(&cs84xx->access_lock);
  4375. mutex_init(&cs84xx->fw_update_mutex);
  4376. cs84xx->bus = ha->pdev->bus;
  4377. list_add_tail(&cs84xx->list, &qla_cs84xx_list);
  4378. done:
  4379. mutex_unlock(&qla_cs84xx_mutex);
  4380. return cs84xx;
  4381. }
  4382. static void
  4383. __qla84xx_chip_release(struct kref *kref)
  4384. {
  4385. struct qla_chip_state_84xx *cs84xx =
  4386. container_of(kref, struct qla_chip_state_84xx, kref);
  4387. mutex_lock(&qla_cs84xx_mutex);
  4388. list_del(&cs84xx->list);
  4389. mutex_unlock(&qla_cs84xx_mutex);
  4390. kfree(cs84xx);
  4391. }
  4392. void
  4393. qla84xx_put_chip(struct scsi_qla_host *vha)
  4394. {
  4395. struct qla_hw_data *ha = vha->hw;
  4396. if (ha->cs84xx)
  4397. kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
  4398. }
  4399. static int
  4400. qla84xx_init_chip(scsi_qla_host_t *vha)
  4401. {
  4402. int rval;
  4403. uint16_t status[2];
  4404. struct qla_hw_data *ha = vha->hw;
  4405. mutex_lock(&ha->cs84xx->fw_update_mutex);
  4406. rval = qla84xx_verify_chip(vha, status);
  4407. mutex_unlock(&ha->cs84xx->fw_update_mutex);
  4408. return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
  4409. QLA_SUCCESS;
  4410. }
  4411. /* 81XX Support **************************************************************/
  4412. int
  4413. qla81xx_nvram_config(scsi_qla_host_t *vha)
  4414. {
  4415. int rval;
  4416. struct init_cb_81xx *icb;
  4417. struct nvram_81xx *nv;
  4418. uint32_t *dptr;
  4419. uint8_t *dptr1, *dptr2;
  4420. uint32_t chksum;
  4421. uint16_t cnt;
  4422. struct qla_hw_data *ha = vha->hw;
  4423. rval = QLA_SUCCESS;
  4424. icb = (struct init_cb_81xx *)ha->init_cb;
  4425. nv = ha->nvram;
  4426. /* Determine NVRAM starting address. */
  4427. ha->nvram_size = sizeof(struct nvram_81xx);
  4428. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  4429. /* Get VPD data into cache */
  4430. ha->vpd = ha->nvram + VPD_OFFSET;
  4431. ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
  4432. ha->vpd_size);
  4433. /* Get NVRAM data into cache and calculate checksum. */
  4434. ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
  4435. ha->nvram_size);
  4436. dptr = (uint32_t *)nv;
  4437. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  4438. chksum += le32_to_cpu(*dptr++);
  4439. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
  4440. "Contents of NVRAM:\n");
  4441. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
  4442. (uint8_t *)nv, ha->nvram_size);
  4443. /* Bad NVRAM data, set defaults parameters. */
  4444. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  4445. || nv->id[3] != ' ' ||
  4446. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  4447. /* Reset NVRAM data. */
  4448. ql_log(ql_log_info, vha, 0x0073,
  4449. "Inconisistent NVRAM detected: checksum=0x%x id=%c "
  4450. "version=0x%x.\n", chksum, nv->id[0],
  4451. le16_to_cpu(nv->nvram_version));
  4452. ql_log(ql_log_info, vha, 0x0074,
  4453. "Falling back to functioning (yet invalid -- WWPN) "
  4454. "defaults.\n");
  4455. /*
  4456. * Set default initialization control block.
  4457. */
  4458. memset(nv, 0, ha->nvram_size);
  4459. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  4460. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  4461. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  4462. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4463. nv->exchange_count = __constant_cpu_to_le16(0);
  4464. nv->port_name[0] = 0x21;
  4465. nv->port_name[1] = 0x00 + ha->port_no;
  4466. nv->port_name[2] = 0x00;
  4467. nv->port_name[3] = 0xe0;
  4468. nv->port_name[4] = 0x8b;
  4469. nv->port_name[5] = 0x1c;
  4470. nv->port_name[6] = 0x55;
  4471. nv->port_name[7] = 0x86;
  4472. nv->node_name[0] = 0x20;
  4473. nv->node_name[1] = 0x00;
  4474. nv->node_name[2] = 0x00;
  4475. nv->node_name[3] = 0xe0;
  4476. nv->node_name[4] = 0x8b;
  4477. nv->node_name[5] = 0x1c;
  4478. nv->node_name[6] = 0x55;
  4479. nv->node_name[7] = 0x86;
  4480. nv->login_retry_count = __constant_cpu_to_le16(8);
  4481. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  4482. nv->login_timeout = __constant_cpu_to_le16(0);
  4483. nv->firmware_options_1 =
  4484. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  4485. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  4486. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  4487. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  4488. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  4489. nv->efi_parameters = __constant_cpu_to_le32(0);
  4490. nv->reset_delay = 5;
  4491. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  4492. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  4493. nv->link_down_timeout = __constant_cpu_to_le16(30);
  4494. nv->enode_mac[0] = 0x00;
  4495. nv->enode_mac[1] = 0x02;
  4496. nv->enode_mac[2] = 0x03;
  4497. nv->enode_mac[3] = 0x04;
  4498. nv->enode_mac[4] = 0x05;
  4499. nv->enode_mac[5] = 0x06 + ha->port_no;
  4500. rval = 1;
  4501. }
  4502. /* Reset Initialization control block */
  4503. memset(icb, 0, ha->init_cb_size);
  4504. /* Copy 1st segment. */
  4505. dptr1 = (uint8_t *)icb;
  4506. dptr2 = (uint8_t *)&nv->version;
  4507. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  4508. while (cnt--)
  4509. *dptr1++ = *dptr2++;
  4510. icb->login_retry_count = nv->login_retry_count;
  4511. /* Copy 2nd segment. */
  4512. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  4513. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  4514. cnt = (uint8_t *)&icb->reserved_5 -
  4515. (uint8_t *)&icb->interrupt_delay_timer;
  4516. while (cnt--)
  4517. *dptr1++ = *dptr2++;
  4518. memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
  4519. /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
  4520. if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
  4521. icb->enode_mac[0] = 0x01;
  4522. icb->enode_mac[1] = 0x02;
  4523. icb->enode_mac[2] = 0x03;
  4524. icb->enode_mac[3] = 0x04;
  4525. icb->enode_mac[4] = 0x05;
  4526. icb->enode_mac[5] = 0x06 + ha->port_no;
  4527. }
  4528. /* Use extended-initialization control block. */
  4529. memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
  4530. /*
  4531. * Setup driver NVRAM options.
  4532. */
  4533. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  4534. "QLE8XXX");
  4535. /* Use alternate WWN? */
  4536. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  4537. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  4538. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  4539. }
  4540. /* Prepare nodename */
  4541. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  4542. /*
  4543. * Firmware will apply the following mask if the nodename was
  4544. * not provided.
  4545. */
  4546. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  4547. icb->node_name[0] &= 0xF0;
  4548. }
  4549. /* Set host adapter parameters. */
  4550. ha->flags.disable_risc_code_load = 0;
  4551. ha->flags.enable_lip_reset = 0;
  4552. ha->flags.enable_lip_full_login =
  4553. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  4554. ha->flags.enable_target_reset =
  4555. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  4556. ha->flags.enable_led_scheme = 0;
  4557. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  4558. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  4559. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  4560. /* save HBA serial number */
  4561. ha->serial0 = icb->port_name[5];
  4562. ha->serial1 = icb->port_name[6];
  4563. ha->serial2 = icb->port_name[7];
  4564. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  4565. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  4566. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4567. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  4568. /* Set minimum login_timeout to 4 seconds. */
  4569. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  4570. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  4571. if (le16_to_cpu(nv->login_timeout) < 4)
  4572. nv->login_timeout = __constant_cpu_to_le16(4);
  4573. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  4574. icb->login_timeout = nv->login_timeout;
  4575. /* Set minimum RATOV to 100 tenths of a second. */
  4576. ha->r_a_tov = 100;
  4577. ha->loop_reset_delay = nv->reset_delay;
  4578. /* Link Down Timeout = 0:
  4579. *
  4580. * When Port Down timer expires we will start returning
  4581. * I/O's to OS with "DID_NO_CONNECT".
  4582. *
  4583. * Link Down Timeout != 0:
  4584. *
  4585. * The driver waits for the link to come up after link down
  4586. * before returning I/Os to OS with "DID_NO_CONNECT".
  4587. */
  4588. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  4589. ha->loop_down_abort_time =
  4590. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  4591. } else {
  4592. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  4593. ha->loop_down_abort_time =
  4594. (LOOP_DOWN_TIME - ha->link_down_timeout);
  4595. }
  4596. /* Need enough time to try and get the port back. */
  4597. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  4598. if (qlport_down_retry)
  4599. ha->port_down_retry_count = qlport_down_retry;
  4600. /* Set login_retry_count */
  4601. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  4602. if (ha->port_down_retry_count ==
  4603. le16_to_cpu(nv->port_down_retry_count) &&
  4604. ha->port_down_retry_count > 3)
  4605. ha->login_retry_count = ha->port_down_retry_count;
  4606. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  4607. ha->login_retry_count = ha->port_down_retry_count;
  4608. if (ql2xloginretrycount)
  4609. ha->login_retry_count = ql2xloginretrycount;
  4610. /* Enable ZIO. */
  4611. if (!vha->flags.init_done) {
  4612. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  4613. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  4614. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  4615. le16_to_cpu(icb->interrupt_delay_timer): 2;
  4616. }
  4617. icb->firmware_options_2 &= __constant_cpu_to_le32(
  4618. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  4619. vha->flags.process_response_queue = 0;
  4620. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  4621. ha->zio_mode = QLA_ZIO_MODE_6;
  4622. ql_log(ql_log_info, vha, 0x0075,
  4623. "ZIO mode %d enabled; timer delay (%d us).\n",
  4624. ha->zio_mode,
  4625. ha->zio_timer * 100);
  4626. icb->firmware_options_2 |= cpu_to_le32(
  4627. (uint32_t)ha->zio_mode);
  4628. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  4629. vha->flags.process_response_queue = 1;
  4630. }
  4631. if (rval) {
  4632. ql_log(ql_log_warn, vha, 0x0076,
  4633. "NVRAM configuration failed.\n");
  4634. }
  4635. return (rval);
  4636. }
  4637. int
  4638. qla82xx_restart_isp(scsi_qla_host_t *vha)
  4639. {
  4640. int status, rval;
  4641. uint32_t wait_time;
  4642. struct qla_hw_data *ha = vha->hw;
  4643. struct req_que *req = ha->req_q_map[0];
  4644. struct rsp_que *rsp = ha->rsp_q_map[0];
  4645. struct scsi_qla_host *vp;
  4646. unsigned long flags;
  4647. status = qla2x00_init_rings(vha);
  4648. if (!status) {
  4649. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4650. ha->flags.chip_reset_done = 1;
  4651. status = qla2x00_fw_ready(vha);
  4652. if (!status) {
  4653. ql_log(ql_log_info, vha, 0x803c,
  4654. "Start configure loop, status =%d.\n", status);
  4655. /* Issue a marker after FW becomes ready. */
  4656. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4657. vha->flags.online = 1;
  4658. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  4659. wait_time = 256;
  4660. do {
  4661. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4662. qla2x00_configure_loop(vha);
  4663. wait_time--;
  4664. } while (!atomic_read(&vha->loop_down_timer) &&
  4665. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
  4666. wait_time &&
  4667. (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
  4668. }
  4669. /* if no cable then assume it's good */
  4670. if ((vha->device_flags & DFLG_NO_CABLE))
  4671. status = 0;
  4672. ql_log(ql_log_info, vha, 0x8000,
  4673. "Configure loop done, status = 0x%x.\n", status);
  4674. }
  4675. if (!status) {
  4676. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4677. if (!atomic_read(&vha->loop_down_timer)) {
  4678. /*
  4679. * Issue marker command only when we are going
  4680. * to start the I/O .
  4681. */
  4682. vha->marker_needed = 1;
  4683. }
  4684. vha->flags.online = 1;
  4685. ha->isp_ops->enable_intrs(ha);
  4686. ha->isp_abort_cnt = 0;
  4687. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  4688. /* Update the firmware version */
  4689. status = qla82xx_check_md_needed(vha);
  4690. if (ha->fce) {
  4691. ha->flags.fce_enabled = 1;
  4692. memset(ha->fce, 0,
  4693. fce_calc_size(ha->fce_bufs));
  4694. rval = qla2x00_enable_fce_trace(vha,
  4695. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  4696. &ha->fce_bufs);
  4697. if (rval) {
  4698. ql_log(ql_log_warn, vha, 0x8001,
  4699. "Unable to reinitialize FCE (%d).\n",
  4700. rval);
  4701. ha->flags.fce_enabled = 0;
  4702. }
  4703. }
  4704. if (ha->eft) {
  4705. memset(ha->eft, 0, EFT_SIZE);
  4706. rval = qla2x00_enable_eft_trace(vha,
  4707. ha->eft_dma, EFT_NUM_BUFFERS);
  4708. if (rval) {
  4709. ql_log(ql_log_warn, vha, 0x8010,
  4710. "Unable to reinitialize EFT (%d).\n",
  4711. rval);
  4712. }
  4713. }
  4714. }
  4715. if (!status) {
  4716. ql_dbg(ql_dbg_taskm, vha, 0x8011,
  4717. "qla82xx_restart_isp succeeded.\n");
  4718. spin_lock_irqsave(&ha->vport_slock, flags);
  4719. list_for_each_entry(vp, &ha->vp_list, list) {
  4720. if (vp->vp_idx) {
  4721. atomic_inc(&vp->vref_count);
  4722. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4723. qla2x00_vp_abort_isp(vp);
  4724. spin_lock_irqsave(&ha->vport_slock, flags);
  4725. atomic_dec(&vp->vref_count);
  4726. }
  4727. }
  4728. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4729. } else {
  4730. ql_log(ql_log_warn, vha, 0x8016,
  4731. "qla82xx_restart_isp **** FAILED ****.\n");
  4732. }
  4733. return status;
  4734. }
  4735. void
  4736. qla81xx_update_fw_options(scsi_qla_host_t *vha)
  4737. {
  4738. struct qla_hw_data *ha = vha->hw;
  4739. if (!ql2xetsenable)
  4740. return;
  4741. /* Enable ETS Burst. */
  4742. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  4743. ha->fw_options[2] |= BIT_9;
  4744. qla2x00_set_fw_options(vha, ha->fw_options);
  4745. }
  4746. /*
  4747. * qla24xx_get_fcp_prio
  4748. * Gets the fcp cmd priority value for the logged in port.
  4749. * Looks for a match of the port descriptors within
  4750. * each of the fcp prio config entries. If a match is found,
  4751. * the tag (priority) value is returned.
  4752. *
  4753. * Input:
  4754. * vha = scsi host structure pointer.
  4755. * fcport = port structure pointer.
  4756. *
  4757. * Return:
  4758. * non-zero (if found)
  4759. * -1 (if not found)
  4760. *
  4761. * Context:
  4762. * Kernel context
  4763. */
  4764. static int
  4765. qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4766. {
  4767. int i, entries;
  4768. uint8_t pid_match, wwn_match;
  4769. int priority;
  4770. uint32_t pid1, pid2;
  4771. uint64_t wwn1, wwn2;
  4772. struct qla_fcp_prio_entry *pri_entry;
  4773. struct qla_hw_data *ha = vha->hw;
  4774. if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
  4775. return -1;
  4776. priority = -1;
  4777. entries = ha->fcp_prio_cfg->num_entries;
  4778. pri_entry = &ha->fcp_prio_cfg->entry[0];
  4779. for (i = 0; i < entries; i++) {
  4780. pid_match = wwn_match = 0;
  4781. if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
  4782. pri_entry++;
  4783. continue;
  4784. }
  4785. /* check source pid for a match */
  4786. if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
  4787. pid1 = pri_entry->src_pid & INVALID_PORT_ID;
  4788. pid2 = vha->d_id.b24 & INVALID_PORT_ID;
  4789. if (pid1 == INVALID_PORT_ID)
  4790. pid_match++;
  4791. else if (pid1 == pid2)
  4792. pid_match++;
  4793. }
  4794. /* check destination pid for a match */
  4795. if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
  4796. pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
  4797. pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
  4798. if (pid1 == INVALID_PORT_ID)
  4799. pid_match++;
  4800. else if (pid1 == pid2)
  4801. pid_match++;
  4802. }
  4803. /* check source WWN for a match */
  4804. if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
  4805. wwn1 = wwn_to_u64(vha->port_name);
  4806. wwn2 = wwn_to_u64(pri_entry->src_wwpn);
  4807. if (wwn2 == (uint64_t)-1)
  4808. wwn_match++;
  4809. else if (wwn1 == wwn2)
  4810. wwn_match++;
  4811. }
  4812. /* check destination WWN for a match */
  4813. if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
  4814. wwn1 = wwn_to_u64(fcport->port_name);
  4815. wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
  4816. if (wwn2 == (uint64_t)-1)
  4817. wwn_match++;
  4818. else if (wwn1 == wwn2)
  4819. wwn_match++;
  4820. }
  4821. if (pid_match == 2 || wwn_match == 2) {
  4822. /* Found a matching entry */
  4823. if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
  4824. priority = pri_entry->tag;
  4825. break;
  4826. }
  4827. pri_entry++;
  4828. }
  4829. return priority;
  4830. }
  4831. /*
  4832. * qla24xx_update_fcport_fcp_prio
  4833. * Activates fcp priority for the logged in fc port
  4834. *
  4835. * Input:
  4836. * vha = scsi host structure pointer.
  4837. * fcp = port structure pointer.
  4838. *
  4839. * Return:
  4840. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4841. *
  4842. * Context:
  4843. * Kernel context.
  4844. */
  4845. int
  4846. qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4847. {
  4848. int ret;
  4849. int priority;
  4850. uint16_t mb[5];
  4851. if (fcport->port_type != FCT_TARGET ||
  4852. fcport->loop_id == FC_NO_LOOP_ID)
  4853. return QLA_FUNCTION_FAILED;
  4854. priority = qla24xx_get_fcp_prio(vha, fcport);
  4855. if (priority < 0)
  4856. return QLA_FUNCTION_FAILED;
  4857. if (IS_QLA82XX(vha->hw)) {
  4858. fcport->fcp_prio = priority & 0xf;
  4859. return QLA_SUCCESS;
  4860. }
  4861. ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
  4862. if (ret == QLA_SUCCESS) {
  4863. if (fcport->fcp_prio != priority)
  4864. ql_dbg(ql_dbg_user, vha, 0x709e,
  4865. "Updated FCP_CMND priority - value=%d loop_id=%d "
  4866. "port_id=%02x%02x%02x.\n", priority,
  4867. fcport->loop_id, fcport->d_id.b.domain,
  4868. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  4869. fcport->fcp_prio = priority & 0xf;
  4870. } else
  4871. ql_dbg(ql_dbg_user, vha, 0x704f,
  4872. "Unable to update FCP_CMND priority - ret=0x%x for "
  4873. "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
  4874. fcport->d_id.b.domain, fcport->d_id.b.area,
  4875. fcport->d_id.b.al_pa);
  4876. return ret;
  4877. }
  4878. /*
  4879. * qla24xx_update_all_fcp_prio
  4880. * Activates fcp priority for all the logged in ports
  4881. *
  4882. * Input:
  4883. * ha = adapter block pointer.
  4884. *
  4885. * Return:
  4886. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4887. *
  4888. * Context:
  4889. * Kernel context.
  4890. */
  4891. int
  4892. qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
  4893. {
  4894. int ret;
  4895. fc_port_t *fcport;
  4896. ret = QLA_FUNCTION_FAILED;
  4897. /* We need to set priority for all logged in ports */
  4898. list_for_each_entry(fcport, &vha->vp_fcports, list)
  4899. ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
  4900. return ret;
  4901. }