fw-ohci.c 70 KB

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  1. /*
  2. * Driver for OHCI 1394 controllers
  3. *
  4. * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software Foundation,
  18. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. */
  20. #include <linux/compiler.h>
  21. #include <linux/delay.h>
  22. #include <linux/dma-mapping.h>
  23. #include <linux/gfp.h>
  24. #include <linux/init.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/kernel.h>
  27. #include <linux/mm.h>
  28. #include <linux/module.h>
  29. #include <linux/moduleparam.h>
  30. #include <linux/pci.h>
  31. #include <linux/spinlock.h>
  32. #include <asm/page.h>
  33. #include <asm/system.h>
  34. #ifdef CONFIG_PPC_PMAC
  35. #include <asm/pmac_feature.h>
  36. #endif
  37. #include "fw-ohci.h"
  38. #include "fw-transaction.h"
  39. #define DESCRIPTOR_OUTPUT_MORE 0
  40. #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
  41. #define DESCRIPTOR_INPUT_MORE (2 << 12)
  42. #define DESCRIPTOR_INPUT_LAST (3 << 12)
  43. #define DESCRIPTOR_STATUS (1 << 11)
  44. #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
  45. #define DESCRIPTOR_PING (1 << 7)
  46. #define DESCRIPTOR_YY (1 << 6)
  47. #define DESCRIPTOR_NO_IRQ (0 << 4)
  48. #define DESCRIPTOR_IRQ_ERROR (1 << 4)
  49. #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
  50. #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
  51. #define DESCRIPTOR_WAIT (3 << 0)
  52. struct descriptor {
  53. __le16 req_count;
  54. __le16 control;
  55. __le32 data_address;
  56. __le32 branch_address;
  57. __le16 res_count;
  58. __le16 transfer_status;
  59. } __attribute__((aligned(16)));
  60. struct db_descriptor {
  61. __le16 first_size;
  62. __le16 control;
  63. __le16 second_req_count;
  64. __le16 first_req_count;
  65. __le32 branch_address;
  66. __le16 second_res_count;
  67. __le16 first_res_count;
  68. __le32 reserved0;
  69. __le32 first_buffer;
  70. __le32 second_buffer;
  71. __le32 reserved1;
  72. } __attribute__((aligned(16)));
  73. #define CONTROL_SET(regs) (regs)
  74. #define CONTROL_CLEAR(regs) ((regs) + 4)
  75. #define COMMAND_PTR(regs) ((regs) + 12)
  76. #define CONTEXT_MATCH(regs) ((regs) + 16)
  77. struct ar_buffer {
  78. struct descriptor descriptor;
  79. struct ar_buffer *next;
  80. __le32 data[0];
  81. };
  82. struct ar_context {
  83. struct fw_ohci *ohci;
  84. struct ar_buffer *current_buffer;
  85. struct ar_buffer *last_buffer;
  86. void *pointer;
  87. u32 regs;
  88. struct tasklet_struct tasklet;
  89. };
  90. struct context;
  91. typedef int (*descriptor_callback_t)(struct context *ctx,
  92. struct descriptor *d,
  93. struct descriptor *last);
  94. /*
  95. * A buffer that contains a block of DMA-able coherent memory used for
  96. * storing a portion of a DMA descriptor program.
  97. */
  98. struct descriptor_buffer {
  99. struct list_head list;
  100. dma_addr_t buffer_bus;
  101. size_t buffer_size;
  102. size_t used;
  103. struct descriptor buffer[0];
  104. };
  105. struct context {
  106. struct fw_ohci *ohci;
  107. u32 regs;
  108. int total_allocation;
  109. /*
  110. * List of page-sized buffers for storing DMA descriptors.
  111. * Head of list contains buffers in use and tail of list contains
  112. * free buffers.
  113. */
  114. struct list_head buffer_list;
  115. /*
  116. * Pointer to a buffer inside buffer_list that contains the tail
  117. * end of the current DMA program.
  118. */
  119. struct descriptor_buffer *buffer_tail;
  120. /*
  121. * The descriptor containing the branch address of the first
  122. * descriptor that has not yet been filled by the device.
  123. */
  124. struct descriptor *last;
  125. /*
  126. * The last descriptor in the DMA program. It contains the branch
  127. * address that must be updated upon appending a new descriptor.
  128. */
  129. struct descriptor *prev;
  130. descriptor_callback_t callback;
  131. struct tasklet_struct tasklet;
  132. };
  133. #define IT_HEADER_SY(v) ((v) << 0)
  134. #define IT_HEADER_TCODE(v) ((v) << 4)
  135. #define IT_HEADER_CHANNEL(v) ((v) << 8)
  136. #define IT_HEADER_TAG(v) ((v) << 14)
  137. #define IT_HEADER_SPEED(v) ((v) << 16)
  138. #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
  139. struct iso_context {
  140. struct fw_iso_context base;
  141. struct context context;
  142. int excess_bytes;
  143. void *header;
  144. size_t header_length;
  145. };
  146. #define CONFIG_ROM_SIZE 1024
  147. struct fw_ohci {
  148. struct fw_card card;
  149. u32 version;
  150. __iomem char *registers;
  151. dma_addr_t self_id_bus;
  152. __le32 *self_id_cpu;
  153. struct tasklet_struct bus_reset_tasklet;
  154. int node_id;
  155. int generation;
  156. int request_generation;
  157. u32 bus_seconds;
  158. bool old_uninorth;
  159. /*
  160. * Spinlock for accessing fw_ohci data. Never call out of
  161. * this driver with this lock held.
  162. */
  163. spinlock_t lock;
  164. u32 self_id_buffer[512];
  165. /* Config rom buffers */
  166. __be32 *config_rom;
  167. dma_addr_t config_rom_bus;
  168. __be32 *next_config_rom;
  169. dma_addr_t next_config_rom_bus;
  170. u32 next_header;
  171. struct ar_context ar_request_ctx;
  172. struct ar_context ar_response_ctx;
  173. struct context at_request_ctx;
  174. struct context at_response_ctx;
  175. u32 it_context_mask;
  176. struct iso_context *it_context_list;
  177. u32 ir_context_mask;
  178. struct iso_context *ir_context_list;
  179. };
  180. static inline struct fw_ohci *fw_ohci(struct fw_card *card)
  181. {
  182. return container_of(card, struct fw_ohci, card);
  183. }
  184. #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
  185. #define IR_CONTEXT_BUFFER_FILL 0x80000000
  186. #define IR_CONTEXT_ISOCH_HEADER 0x40000000
  187. #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
  188. #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
  189. #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
  190. #define CONTEXT_RUN 0x8000
  191. #define CONTEXT_WAKE 0x1000
  192. #define CONTEXT_DEAD 0x0800
  193. #define CONTEXT_ACTIVE 0x0400
  194. #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
  195. #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
  196. #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
  197. #define FW_OHCI_MAJOR 240
  198. #define OHCI1394_REGISTER_SIZE 0x800
  199. #define OHCI_LOOP_COUNT 500
  200. #define OHCI1394_PCI_HCI_Control 0x40
  201. #define SELF_ID_BUF_SIZE 0x800
  202. #define OHCI_TCODE_PHY_PACKET 0x0e
  203. #define OHCI_VERSION_1_1 0x010010
  204. static char ohci_driver_name[] = KBUILD_MODNAME;
  205. #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
  206. #define OHCI_PARAM_DEBUG_AT_AR 1
  207. #define OHCI_PARAM_DEBUG_SELFIDS 2
  208. #define OHCI_PARAM_DEBUG_IRQS 4
  209. #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
  210. static int param_debug;
  211. module_param_named(debug, param_debug, int, 0644);
  212. MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
  213. ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
  214. ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
  215. ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
  216. ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
  217. ", or a combination, or all = -1)");
  218. static void log_irqs(u32 evt)
  219. {
  220. if (likely(!(param_debug &
  221. (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
  222. return;
  223. if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
  224. !(evt & OHCI1394_busReset))
  225. return;
  226. printk(KERN_DEBUG KBUILD_MODNAME ": IRQ "
  227. "%08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
  228. evt,
  229. evt & OHCI1394_selfIDComplete ? " selfID" : "",
  230. evt & OHCI1394_RQPkt ? " AR_req" : "",
  231. evt & OHCI1394_RSPkt ? " AR_resp" : "",
  232. evt & OHCI1394_reqTxComplete ? " AT_req" : "",
  233. evt & OHCI1394_respTxComplete ? " AT_resp" : "",
  234. evt & OHCI1394_isochRx ? " IR" : "",
  235. evt & OHCI1394_isochTx ? " IT" : "",
  236. evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
  237. evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
  238. evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
  239. evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
  240. evt & OHCI1394_busReset ? " busReset" : "",
  241. evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
  242. OHCI1394_RSPkt | OHCI1394_reqTxComplete |
  243. OHCI1394_respTxComplete | OHCI1394_isochRx |
  244. OHCI1394_isochTx | OHCI1394_postedWriteErr |
  245. OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
  246. OHCI1394_regAccessFail | OHCI1394_busReset)
  247. ? " ?" : "");
  248. }
  249. static const char *speed[] = {
  250. [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
  251. };
  252. static const char *power[] = {
  253. [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
  254. [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
  255. };
  256. static const char port[] = { '.', '-', 'p', 'c', };
  257. static char _p(u32 *s, int shift)
  258. {
  259. return port[*s >> shift & 3];
  260. }
  261. static void log_selfids(int generation, int self_id_count, u32 *s)
  262. {
  263. if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
  264. return;
  265. printk(KERN_DEBUG KBUILD_MODNAME ": %d selfIDs, generation %d\n",
  266. self_id_count, generation);
  267. for (; self_id_count--; ++s)
  268. if ((*s & 1 << 23) == 0)
  269. printk(KERN_DEBUG "selfID 0: %08x, phy %d [%c%c%c] "
  270. "%s gc=%d %s %s%s%s\n",
  271. *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
  272. speed[*s >> 14 & 3], *s >> 16 & 63,
  273. power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
  274. *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
  275. else
  276. printk(KERN_DEBUG "selfID n: %08x, phy %d "
  277. "[%c%c%c%c%c%c%c%c]\n",
  278. *s, *s >> 24 & 63,
  279. _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
  280. _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
  281. }
  282. static const char *evts[] = {
  283. [0x00] = "evt_no_status", [0x01] = "-reserved-",
  284. [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
  285. [0x04] = "evt_underrun", [0x05] = "evt_overrun",
  286. [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
  287. [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
  288. [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
  289. [0x0c] = "-reserved-", [0x0d] = "-reserved-",
  290. [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
  291. [0x10] = "-reserved-", [0x11] = "ack_complete",
  292. [0x12] = "ack_pending ", [0x13] = "-reserved-",
  293. [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
  294. [0x16] = "ack_busy_B", [0x17] = "-reserved-",
  295. [0x18] = "-reserved-", [0x19] = "-reserved-",
  296. [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
  297. [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
  298. [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
  299. [0x20] = "pending/cancelled",
  300. };
  301. static const char *tcodes[] = {
  302. [0x0] = "QW req", [0x1] = "BW req",
  303. [0x2] = "W resp", [0x3] = "-reserved-",
  304. [0x4] = "QR req", [0x5] = "BR req",
  305. [0x6] = "QR resp", [0x7] = "BR resp",
  306. [0x8] = "cycle start", [0x9] = "Lk req",
  307. [0xa] = "async stream packet", [0xb] = "Lk resp",
  308. [0xc] = "-reserved-", [0xd] = "-reserved-",
  309. [0xe] = "link internal", [0xf] = "-reserved-",
  310. };
  311. static const char *phys[] = {
  312. [0x0] = "phy config packet", [0x1] = "link-on packet",
  313. [0x2] = "self-id packet", [0x3] = "-reserved-",
  314. };
  315. static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
  316. {
  317. int tcode = header[0] >> 4 & 0xf;
  318. char specific[12];
  319. if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
  320. return;
  321. if (unlikely(evt >= ARRAY_SIZE(evts)))
  322. evt = 0x1f;
  323. if (header[0] == ~header[1]) {
  324. printk(KERN_DEBUG "A%c %s, %s, %08x\n",
  325. dir, evts[evt], phys[header[0] >> 30 & 0x3],
  326. header[0]);
  327. return;
  328. }
  329. switch (tcode) {
  330. case 0x0: case 0x6: case 0x8:
  331. snprintf(specific, sizeof(specific), " = %08x",
  332. be32_to_cpu((__force __be32)header[3]));
  333. break;
  334. case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
  335. snprintf(specific, sizeof(specific), " %x,%x",
  336. header[3] >> 16, header[3] & 0xffff);
  337. break;
  338. default:
  339. specific[0] = '\0';
  340. }
  341. switch (tcode) {
  342. case 0xe: case 0xa:
  343. printk(KERN_DEBUG "A%c %s, %s\n",
  344. dir, evts[evt], tcodes[tcode]);
  345. break;
  346. case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
  347. printk(KERN_DEBUG "A%c spd %x tl %02x, "
  348. "%04x -> %04x, %s, "
  349. "%s, %04x%08x%s\n",
  350. dir, speed, header[0] >> 10 & 0x3f,
  351. header[1] >> 16, header[0] >> 16, evts[evt],
  352. tcodes[tcode], header[1] & 0xffff, header[2], specific);
  353. break;
  354. default:
  355. printk(KERN_DEBUG "A%c spd %x tl %02x, "
  356. "%04x -> %04x, %s, "
  357. "%s%s\n",
  358. dir, speed, header[0] >> 10 & 0x3f,
  359. header[1] >> 16, header[0] >> 16, evts[evt],
  360. tcodes[tcode], specific);
  361. }
  362. }
  363. #else
  364. #define log_irqs(evt)
  365. #define log_selfids(generation, self_id_count, sid)
  366. #define log_ar_at_event(dir, speed, header, evt)
  367. #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
  368. static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
  369. {
  370. writel(data, ohci->registers + offset);
  371. }
  372. static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
  373. {
  374. return readl(ohci->registers + offset);
  375. }
  376. static inline void flush_writes(const struct fw_ohci *ohci)
  377. {
  378. /* Do a dummy read to flush writes. */
  379. reg_read(ohci, OHCI1394_Version);
  380. }
  381. static int
  382. ohci_update_phy_reg(struct fw_card *card, int addr,
  383. int clear_bits, int set_bits)
  384. {
  385. struct fw_ohci *ohci = fw_ohci(card);
  386. u32 val, old;
  387. reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
  388. flush_writes(ohci);
  389. msleep(2);
  390. val = reg_read(ohci, OHCI1394_PhyControl);
  391. if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
  392. fw_error("failed to set phy reg bits.\n");
  393. return -EBUSY;
  394. }
  395. old = OHCI1394_PhyControl_ReadData(val);
  396. old = (old & ~clear_bits) | set_bits;
  397. reg_write(ohci, OHCI1394_PhyControl,
  398. OHCI1394_PhyControl_Write(addr, old));
  399. return 0;
  400. }
  401. static int ar_context_add_page(struct ar_context *ctx)
  402. {
  403. struct device *dev = ctx->ohci->card.device;
  404. struct ar_buffer *ab;
  405. dma_addr_t uninitialized_var(ab_bus);
  406. size_t offset;
  407. ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
  408. if (ab == NULL)
  409. return -ENOMEM;
  410. memset(&ab->descriptor, 0, sizeof(ab->descriptor));
  411. ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
  412. DESCRIPTOR_STATUS |
  413. DESCRIPTOR_BRANCH_ALWAYS);
  414. offset = offsetof(struct ar_buffer, data);
  415. ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
  416. ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
  417. ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
  418. ab->descriptor.branch_address = 0;
  419. ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
  420. ctx->last_buffer->next = ab;
  421. ctx->last_buffer = ab;
  422. reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
  423. flush_writes(ctx->ohci);
  424. return 0;
  425. }
  426. #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
  427. #define cond_le32_to_cpu(v) \
  428. (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
  429. #else
  430. #define cond_le32_to_cpu(v) le32_to_cpu(v)
  431. #endif
  432. static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
  433. {
  434. struct fw_ohci *ohci = ctx->ohci;
  435. struct fw_packet p;
  436. u32 status, length, tcode;
  437. int evt;
  438. p.header[0] = cond_le32_to_cpu(buffer[0]);
  439. p.header[1] = cond_le32_to_cpu(buffer[1]);
  440. p.header[2] = cond_le32_to_cpu(buffer[2]);
  441. tcode = (p.header[0] >> 4) & 0x0f;
  442. switch (tcode) {
  443. case TCODE_WRITE_QUADLET_REQUEST:
  444. case TCODE_READ_QUADLET_RESPONSE:
  445. p.header[3] = (__force __u32) buffer[3];
  446. p.header_length = 16;
  447. p.payload_length = 0;
  448. break;
  449. case TCODE_READ_BLOCK_REQUEST :
  450. p.header[3] = cond_le32_to_cpu(buffer[3]);
  451. p.header_length = 16;
  452. p.payload_length = 0;
  453. break;
  454. case TCODE_WRITE_BLOCK_REQUEST:
  455. case TCODE_READ_BLOCK_RESPONSE:
  456. case TCODE_LOCK_REQUEST:
  457. case TCODE_LOCK_RESPONSE:
  458. p.header[3] = cond_le32_to_cpu(buffer[3]);
  459. p.header_length = 16;
  460. p.payload_length = p.header[3] >> 16;
  461. break;
  462. case TCODE_WRITE_RESPONSE:
  463. case TCODE_READ_QUADLET_REQUEST:
  464. case OHCI_TCODE_PHY_PACKET:
  465. p.header_length = 12;
  466. p.payload_length = 0;
  467. break;
  468. }
  469. p.payload = (void *) buffer + p.header_length;
  470. /* FIXME: What to do about evt_* errors? */
  471. length = (p.header_length + p.payload_length + 3) / 4;
  472. status = cond_le32_to_cpu(buffer[length]);
  473. evt = (status >> 16) & 0x1f;
  474. p.ack = evt - 16;
  475. p.speed = (status >> 21) & 0x7;
  476. p.timestamp = status & 0xffff;
  477. p.generation = ohci->request_generation;
  478. log_ar_at_event('R', p.speed, p.header, evt);
  479. /*
  480. * The OHCI bus reset handler synthesizes a phy packet with
  481. * the new generation number when a bus reset happens (see
  482. * section 8.4.2.3). This helps us determine when a request
  483. * was received and make sure we send the response in the same
  484. * generation. We only need this for requests; for responses
  485. * we use the unique tlabel for finding the matching
  486. * request.
  487. */
  488. if (evt == OHCI1394_evt_bus_reset)
  489. ohci->request_generation = (p.header[2] >> 16) & 0xff;
  490. else if (ctx == &ohci->ar_request_ctx)
  491. fw_core_handle_request(&ohci->card, &p);
  492. else
  493. fw_core_handle_response(&ohci->card, &p);
  494. return buffer + length + 1;
  495. }
  496. static void ar_context_tasklet(unsigned long data)
  497. {
  498. struct ar_context *ctx = (struct ar_context *)data;
  499. struct fw_ohci *ohci = ctx->ohci;
  500. struct ar_buffer *ab;
  501. struct descriptor *d;
  502. void *buffer, *end;
  503. ab = ctx->current_buffer;
  504. d = &ab->descriptor;
  505. if (d->res_count == 0) {
  506. size_t size, rest, offset;
  507. dma_addr_t start_bus;
  508. void *start;
  509. /*
  510. * This descriptor is finished and we may have a
  511. * packet split across this and the next buffer. We
  512. * reuse the page for reassembling the split packet.
  513. */
  514. offset = offsetof(struct ar_buffer, data);
  515. start = buffer = ab;
  516. start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
  517. ab = ab->next;
  518. d = &ab->descriptor;
  519. size = buffer + PAGE_SIZE - ctx->pointer;
  520. rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
  521. memmove(buffer, ctx->pointer, size);
  522. memcpy(buffer + size, ab->data, rest);
  523. ctx->current_buffer = ab;
  524. ctx->pointer = (void *) ab->data + rest;
  525. end = buffer + size + rest;
  526. while (buffer < end)
  527. buffer = handle_ar_packet(ctx, buffer);
  528. dma_free_coherent(ohci->card.device, PAGE_SIZE,
  529. start, start_bus);
  530. ar_context_add_page(ctx);
  531. } else {
  532. buffer = ctx->pointer;
  533. ctx->pointer = end =
  534. (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
  535. while (buffer < end)
  536. buffer = handle_ar_packet(ctx, buffer);
  537. }
  538. }
  539. static int
  540. ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
  541. {
  542. struct ar_buffer ab;
  543. ctx->regs = regs;
  544. ctx->ohci = ohci;
  545. ctx->last_buffer = &ab;
  546. tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
  547. ar_context_add_page(ctx);
  548. ar_context_add_page(ctx);
  549. ctx->current_buffer = ab.next;
  550. ctx->pointer = ctx->current_buffer->data;
  551. return 0;
  552. }
  553. static void ar_context_run(struct ar_context *ctx)
  554. {
  555. struct ar_buffer *ab = ctx->current_buffer;
  556. dma_addr_t ab_bus;
  557. size_t offset;
  558. offset = offsetof(struct ar_buffer, data);
  559. ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
  560. reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
  561. reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
  562. flush_writes(ctx->ohci);
  563. }
  564. static struct descriptor *
  565. find_branch_descriptor(struct descriptor *d, int z)
  566. {
  567. int b, key;
  568. b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
  569. key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
  570. /* figure out which descriptor the branch address goes in */
  571. if (z == 2 && (b == 3 || key == 2))
  572. return d;
  573. else
  574. return d + z - 1;
  575. }
  576. static void context_tasklet(unsigned long data)
  577. {
  578. struct context *ctx = (struct context *) data;
  579. struct descriptor *d, *last;
  580. u32 address;
  581. int z;
  582. struct descriptor_buffer *desc;
  583. desc = list_entry(ctx->buffer_list.next,
  584. struct descriptor_buffer, list);
  585. last = ctx->last;
  586. while (last->branch_address != 0) {
  587. struct descriptor_buffer *old_desc = desc;
  588. address = le32_to_cpu(last->branch_address);
  589. z = address & 0xf;
  590. address &= ~0xf;
  591. /* If the branch address points to a buffer outside of the
  592. * current buffer, advance to the next buffer. */
  593. if (address < desc->buffer_bus ||
  594. address >= desc->buffer_bus + desc->used)
  595. desc = list_entry(desc->list.next,
  596. struct descriptor_buffer, list);
  597. d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
  598. last = find_branch_descriptor(d, z);
  599. if (!ctx->callback(ctx, d, last))
  600. break;
  601. if (old_desc != desc) {
  602. /* If we've advanced to the next buffer, move the
  603. * previous buffer to the free list. */
  604. unsigned long flags;
  605. old_desc->used = 0;
  606. spin_lock_irqsave(&ctx->ohci->lock, flags);
  607. list_move_tail(&old_desc->list, &ctx->buffer_list);
  608. spin_unlock_irqrestore(&ctx->ohci->lock, flags);
  609. }
  610. ctx->last = last;
  611. }
  612. }
  613. /*
  614. * Allocate a new buffer and add it to the list of free buffers for this
  615. * context. Must be called with ohci->lock held.
  616. */
  617. static int
  618. context_add_buffer(struct context *ctx)
  619. {
  620. struct descriptor_buffer *desc;
  621. dma_addr_t uninitialized_var(bus_addr);
  622. int offset;
  623. /*
  624. * 16MB of descriptors should be far more than enough for any DMA
  625. * program. This will catch run-away userspace or DoS attacks.
  626. */
  627. if (ctx->total_allocation >= 16*1024*1024)
  628. return -ENOMEM;
  629. desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
  630. &bus_addr, GFP_ATOMIC);
  631. if (!desc)
  632. return -ENOMEM;
  633. offset = (void *)&desc->buffer - (void *)desc;
  634. desc->buffer_size = PAGE_SIZE - offset;
  635. desc->buffer_bus = bus_addr + offset;
  636. desc->used = 0;
  637. list_add_tail(&desc->list, &ctx->buffer_list);
  638. ctx->total_allocation += PAGE_SIZE;
  639. return 0;
  640. }
  641. static int
  642. context_init(struct context *ctx, struct fw_ohci *ohci,
  643. u32 regs, descriptor_callback_t callback)
  644. {
  645. ctx->ohci = ohci;
  646. ctx->regs = regs;
  647. ctx->total_allocation = 0;
  648. INIT_LIST_HEAD(&ctx->buffer_list);
  649. if (context_add_buffer(ctx) < 0)
  650. return -ENOMEM;
  651. ctx->buffer_tail = list_entry(ctx->buffer_list.next,
  652. struct descriptor_buffer, list);
  653. tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
  654. ctx->callback = callback;
  655. /*
  656. * We put a dummy descriptor in the buffer that has a NULL
  657. * branch address and looks like it's been sent. That way we
  658. * have a descriptor to append DMA programs to.
  659. */
  660. memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
  661. ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
  662. ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
  663. ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
  664. ctx->last = ctx->buffer_tail->buffer;
  665. ctx->prev = ctx->buffer_tail->buffer;
  666. return 0;
  667. }
  668. static void
  669. context_release(struct context *ctx)
  670. {
  671. struct fw_card *card = &ctx->ohci->card;
  672. struct descriptor_buffer *desc, *tmp;
  673. list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
  674. dma_free_coherent(card->device, PAGE_SIZE, desc,
  675. desc->buffer_bus -
  676. ((void *)&desc->buffer - (void *)desc));
  677. }
  678. /* Must be called with ohci->lock held */
  679. static struct descriptor *
  680. context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
  681. {
  682. struct descriptor *d = NULL;
  683. struct descriptor_buffer *desc = ctx->buffer_tail;
  684. if (z * sizeof(*d) > desc->buffer_size)
  685. return NULL;
  686. if (z * sizeof(*d) > desc->buffer_size - desc->used) {
  687. /* No room for the descriptor in this buffer, so advance to the
  688. * next one. */
  689. if (desc->list.next == &ctx->buffer_list) {
  690. /* If there is no free buffer next in the list,
  691. * allocate one. */
  692. if (context_add_buffer(ctx) < 0)
  693. return NULL;
  694. }
  695. desc = list_entry(desc->list.next,
  696. struct descriptor_buffer, list);
  697. ctx->buffer_tail = desc;
  698. }
  699. d = desc->buffer + desc->used / sizeof(*d);
  700. memset(d, 0, z * sizeof(*d));
  701. *d_bus = desc->buffer_bus + desc->used;
  702. return d;
  703. }
  704. static void context_run(struct context *ctx, u32 extra)
  705. {
  706. struct fw_ohci *ohci = ctx->ohci;
  707. reg_write(ohci, COMMAND_PTR(ctx->regs),
  708. le32_to_cpu(ctx->last->branch_address));
  709. reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
  710. reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
  711. flush_writes(ohci);
  712. }
  713. static void context_append(struct context *ctx,
  714. struct descriptor *d, int z, int extra)
  715. {
  716. dma_addr_t d_bus;
  717. struct descriptor_buffer *desc = ctx->buffer_tail;
  718. d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
  719. desc->used += (z + extra) * sizeof(*d);
  720. ctx->prev->branch_address = cpu_to_le32(d_bus | z);
  721. ctx->prev = find_branch_descriptor(d, z);
  722. reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
  723. flush_writes(ctx->ohci);
  724. }
  725. static void context_stop(struct context *ctx)
  726. {
  727. u32 reg;
  728. int i;
  729. reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
  730. flush_writes(ctx->ohci);
  731. for (i = 0; i < 10; i++) {
  732. reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
  733. if ((reg & CONTEXT_ACTIVE) == 0)
  734. break;
  735. fw_notify("context_stop: still active (0x%08x)\n", reg);
  736. mdelay(1);
  737. }
  738. }
  739. struct driver_data {
  740. struct fw_packet *packet;
  741. };
  742. /*
  743. * This function apppends a packet to the DMA queue for transmission.
  744. * Must always be called with the ochi->lock held to ensure proper
  745. * generation handling and locking around packet queue manipulation.
  746. */
  747. static int
  748. at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
  749. {
  750. struct fw_ohci *ohci = ctx->ohci;
  751. dma_addr_t d_bus, uninitialized_var(payload_bus);
  752. struct driver_data *driver_data;
  753. struct descriptor *d, *last;
  754. __le32 *header;
  755. int z, tcode;
  756. u32 reg;
  757. d = context_get_descriptors(ctx, 4, &d_bus);
  758. if (d == NULL) {
  759. packet->ack = RCODE_SEND_ERROR;
  760. return -1;
  761. }
  762. d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
  763. d[0].res_count = cpu_to_le16(packet->timestamp);
  764. /*
  765. * The DMA format for asyncronous link packets is different
  766. * from the IEEE1394 layout, so shift the fields around
  767. * accordingly. If header_length is 8, it's a PHY packet, to
  768. * which we need to prepend an extra quadlet.
  769. */
  770. header = (__le32 *) &d[1];
  771. if (packet->header_length > 8) {
  772. header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
  773. (packet->speed << 16));
  774. header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
  775. (packet->header[0] & 0xffff0000));
  776. header[2] = cpu_to_le32(packet->header[2]);
  777. tcode = (packet->header[0] >> 4) & 0x0f;
  778. if (TCODE_IS_BLOCK_PACKET(tcode))
  779. header[3] = cpu_to_le32(packet->header[3]);
  780. else
  781. header[3] = (__force __le32) packet->header[3];
  782. d[0].req_count = cpu_to_le16(packet->header_length);
  783. } else {
  784. header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
  785. (packet->speed << 16));
  786. header[1] = cpu_to_le32(packet->header[0]);
  787. header[2] = cpu_to_le32(packet->header[1]);
  788. d[0].req_count = cpu_to_le16(12);
  789. }
  790. driver_data = (struct driver_data *) &d[3];
  791. driver_data->packet = packet;
  792. packet->driver_data = driver_data;
  793. if (packet->payload_length > 0) {
  794. payload_bus =
  795. dma_map_single(ohci->card.device, packet->payload,
  796. packet->payload_length, DMA_TO_DEVICE);
  797. if (dma_mapping_error(payload_bus)) {
  798. packet->ack = RCODE_SEND_ERROR;
  799. return -1;
  800. }
  801. d[2].req_count = cpu_to_le16(packet->payload_length);
  802. d[2].data_address = cpu_to_le32(payload_bus);
  803. last = &d[2];
  804. z = 3;
  805. } else {
  806. last = &d[0];
  807. z = 2;
  808. }
  809. last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
  810. DESCRIPTOR_IRQ_ALWAYS |
  811. DESCRIPTOR_BRANCH_ALWAYS);
  812. /*
  813. * If the controller and packet generations don't match, we need to
  814. * bail out and try again. If IntEvent.busReset is set, the AT context
  815. * is halted, so appending to the context and trying to run it is
  816. * futile. Most controllers do the right thing and just flush the AT
  817. * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
  818. * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
  819. * up stalling out. So we just bail out in software and try again
  820. * later, and everyone is happy.
  821. * FIXME: Document how the locking works.
  822. */
  823. if (ohci->generation != packet->generation ||
  824. reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
  825. if (packet->payload_length > 0)
  826. dma_unmap_single(ohci->card.device, payload_bus,
  827. packet->payload_length, DMA_TO_DEVICE);
  828. packet->ack = RCODE_GENERATION;
  829. return -1;
  830. }
  831. context_append(ctx, d, z, 4 - z);
  832. /* If the context isn't already running, start it up. */
  833. reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
  834. if ((reg & CONTEXT_RUN) == 0)
  835. context_run(ctx, 0);
  836. return 0;
  837. }
  838. static int handle_at_packet(struct context *context,
  839. struct descriptor *d,
  840. struct descriptor *last)
  841. {
  842. struct driver_data *driver_data;
  843. struct fw_packet *packet;
  844. struct fw_ohci *ohci = context->ohci;
  845. dma_addr_t payload_bus;
  846. int evt;
  847. if (last->transfer_status == 0)
  848. /* This descriptor isn't done yet, stop iteration. */
  849. return 0;
  850. driver_data = (struct driver_data *) &d[3];
  851. packet = driver_data->packet;
  852. if (packet == NULL)
  853. /* This packet was cancelled, just continue. */
  854. return 1;
  855. payload_bus = le32_to_cpu(last->data_address);
  856. if (payload_bus != 0)
  857. dma_unmap_single(ohci->card.device, payload_bus,
  858. packet->payload_length, DMA_TO_DEVICE);
  859. evt = le16_to_cpu(last->transfer_status) & 0x1f;
  860. packet->timestamp = le16_to_cpu(last->res_count);
  861. log_ar_at_event('T', packet->speed, packet->header, evt);
  862. switch (evt) {
  863. case OHCI1394_evt_timeout:
  864. /* Async response transmit timed out. */
  865. packet->ack = RCODE_CANCELLED;
  866. break;
  867. case OHCI1394_evt_flushed:
  868. /*
  869. * The packet was flushed should give same error as
  870. * when we try to use a stale generation count.
  871. */
  872. packet->ack = RCODE_GENERATION;
  873. break;
  874. case OHCI1394_evt_missing_ack:
  875. /*
  876. * Using a valid (current) generation count, but the
  877. * node is not on the bus or not sending acks.
  878. */
  879. packet->ack = RCODE_NO_ACK;
  880. break;
  881. case ACK_COMPLETE + 0x10:
  882. case ACK_PENDING + 0x10:
  883. case ACK_BUSY_X + 0x10:
  884. case ACK_BUSY_A + 0x10:
  885. case ACK_BUSY_B + 0x10:
  886. case ACK_DATA_ERROR + 0x10:
  887. case ACK_TYPE_ERROR + 0x10:
  888. packet->ack = evt - 0x10;
  889. break;
  890. default:
  891. packet->ack = RCODE_SEND_ERROR;
  892. break;
  893. }
  894. packet->callback(packet, &ohci->card, packet->ack);
  895. return 1;
  896. }
  897. #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
  898. #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
  899. #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
  900. #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
  901. #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
  902. static void
  903. handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
  904. {
  905. struct fw_packet response;
  906. int tcode, length, i;
  907. tcode = HEADER_GET_TCODE(packet->header[0]);
  908. if (TCODE_IS_BLOCK_PACKET(tcode))
  909. length = HEADER_GET_DATA_LENGTH(packet->header[3]);
  910. else
  911. length = 4;
  912. i = csr - CSR_CONFIG_ROM;
  913. if (i + length > CONFIG_ROM_SIZE) {
  914. fw_fill_response(&response, packet->header,
  915. RCODE_ADDRESS_ERROR, NULL, 0);
  916. } else if (!TCODE_IS_READ_REQUEST(tcode)) {
  917. fw_fill_response(&response, packet->header,
  918. RCODE_TYPE_ERROR, NULL, 0);
  919. } else {
  920. fw_fill_response(&response, packet->header, RCODE_COMPLETE,
  921. (void *) ohci->config_rom + i, length);
  922. }
  923. fw_core_handle_response(&ohci->card, &response);
  924. }
  925. static void
  926. handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
  927. {
  928. struct fw_packet response;
  929. int tcode, length, ext_tcode, sel;
  930. __be32 *payload, lock_old;
  931. u32 lock_arg, lock_data;
  932. tcode = HEADER_GET_TCODE(packet->header[0]);
  933. length = HEADER_GET_DATA_LENGTH(packet->header[3]);
  934. payload = packet->payload;
  935. ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
  936. if (tcode == TCODE_LOCK_REQUEST &&
  937. ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
  938. lock_arg = be32_to_cpu(payload[0]);
  939. lock_data = be32_to_cpu(payload[1]);
  940. } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
  941. lock_arg = 0;
  942. lock_data = 0;
  943. } else {
  944. fw_fill_response(&response, packet->header,
  945. RCODE_TYPE_ERROR, NULL, 0);
  946. goto out;
  947. }
  948. sel = (csr - CSR_BUS_MANAGER_ID) / 4;
  949. reg_write(ohci, OHCI1394_CSRData, lock_data);
  950. reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
  951. reg_write(ohci, OHCI1394_CSRControl, sel);
  952. if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
  953. lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
  954. else
  955. fw_notify("swap not done yet\n");
  956. fw_fill_response(&response, packet->header,
  957. RCODE_COMPLETE, &lock_old, sizeof(lock_old));
  958. out:
  959. fw_core_handle_response(&ohci->card, &response);
  960. }
  961. static void
  962. handle_local_request(struct context *ctx, struct fw_packet *packet)
  963. {
  964. u64 offset;
  965. u32 csr;
  966. if (ctx == &ctx->ohci->at_request_ctx) {
  967. packet->ack = ACK_PENDING;
  968. packet->callback(packet, &ctx->ohci->card, packet->ack);
  969. }
  970. offset =
  971. ((unsigned long long)
  972. HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
  973. packet->header[2];
  974. csr = offset - CSR_REGISTER_BASE;
  975. /* Handle config rom reads. */
  976. if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
  977. handle_local_rom(ctx->ohci, packet, csr);
  978. else switch (csr) {
  979. case CSR_BUS_MANAGER_ID:
  980. case CSR_BANDWIDTH_AVAILABLE:
  981. case CSR_CHANNELS_AVAILABLE_HI:
  982. case CSR_CHANNELS_AVAILABLE_LO:
  983. handle_local_lock(ctx->ohci, packet, csr);
  984. break;
  985. default:
  986. if (ctx == &ctx->ohci->at_request_ctx)
  987. fw_core_handle_request(&ctx->ohci->card, packet);
  988. else
  989. fw_core_handle_response(&ctx->ohci->card, packet);
  990. break;
  991. }
  992. if (ctx == &ctx->ohci->at_response_ctx) {
  993. packet->ack = ACK_COMPLETE;
  994. packet->callback(packet, &ctx->ohci->card, packet->ack);
  995. }
  996. }
  997. static void
  998. at_context_transmit(struct context *ctx, struct fw_packet *packet)
  999. {
  1000. unsigned long flags;
  1001. int retval;
  1002. spin_lock_irqsave(&ctx->ohci->lock, flags);
  1003. if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
  1004. ctx->ohci->generation == packet->generation) {
  1005. spin_unlock_irqrestore(&ctx->ohci->lock, flags);
  1006. handle_local_request(ctx, packet);
  1007. return;
  1008. }
  1009. retval = at_context_queue_packet(ctx, packet);
  1010. spin_unlock_irqrestore(&ctx->ohci->lock, flags);
  1011. if (retval < 0)
  1012. packet->callback(packet, &ctx->ohci->card, packet->ack);
  1013. }
  1014. static void bus_reset_tasklet(unsigned long data)
  1015. {
  1016. struct fw_ohci *ohci = (struct fw_ohci *)data;
  1017. int self_id_count, i, j, reg;
  1018. int generation, new_generation;
  1019. unsigned long flags;
  1020. void *free_rom = NULL;
  1021. dma_addr_t free_rom_bus = 0;
  1022. reg = reg_read(ohci, OHCI1394_NodeID);
  1023. if (!(reg & OHCI1394_NodeID_idValid)) {
  1024. fw_notify("node ID not valid, new bus reset in progress\n");
  1025. return;
  1026. }
  1027. if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
  1028. fw_notify("malconfigured bus\n");
  1029. return;
  1030. }
  1031. ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
  1032. OHCI1394_NodeID_nodeNumber);
  1033. reg = reg_read(ohci, OHCI1394_SelfIDCount);
  1034. if (reg & OHCI1394_SelfIDCount_selfIDError) {
  1035. fw_notify("inconsistent self IDs\n");
  1036. return;
  1037. }
  1038. /*
  1039. * The count in the SelfIDCount register is the number of
  1040. * bytes in the self ID receive buffer. Since we also receive
  1041. * the inverted quadlets and a header quadlet, we shift one
  1042. * bit extra to get the actual number of self IDs.
  1043. */
  1044. self_id_count = (reg >> 3) & 0x3ff;
  1045. if (self_id_count == 0) {
  1046. fw_notify("inconsistent self IDs\n");
  1047. return;
  1048. }
  1049. generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
  1050. rmb();
  1051. for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
  1052. if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
  1053. fw_notify("inconsistent self IDs\n");
  1054. return;
  1055. }
  1056. ohci->self_id_buffer[j] =
  1057. cond_le32_to_cpu(ohci->self_id_cpu[i]);
  1058. }
  1059. rmb();
  1060. /*
  1061. * Check the consistency of the self IDs we just read. The
  1062. * problem we face is that a new bus reset can start while we
  1063. * read out the self IDs from the DMA buffer. If this happens,
  1064. * the DMA buffer will be overwritten with new self IDs and we
  1065. * will read out inconsistent data. The OHCI specification
  1066. * (section 11.2) recommends a technique similar to
  1067. * linux/seqlock.h, where we remember the generation of the
  1068. * self IDs in the buffer before reading them out and compare
  1069. * it to the current generation after reading them out. If
  1070. * the two generations match we know we have a consistent set
  1071. * of self IDs.
  1072. */
  1073. new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
  1074. if (new_generation != generation) {
  1075. fw_notify("recursive bus reset detected, "
  1076. "discarding self ids\n");
  1077. return;
  1078. }
  1079. /* FIXME: Document how the locking works. */
  1080. spin_lock_irqsave(&ohci->lock, flags);
  1081. ohci->generation = generation;
  1082. context_stop(&ohci->at_request_ctx);
  1083. context_stop(&ohci->at_response_ctx);
  1084. reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
  1085. /*
  1086. * This next bit is unrelated to the AT context stuff but we
  1087. * have to do it under the spinlock also. If a new config rom
  1088. * was set up before this reset, the old one is now no longer
  1089. * in use and we can free it. Update the config rom pointers
  1090. * to point to the current config rom and clear the
  1091. * next_config_rom pointer so a new udpate can take place.
  1092. */
  1093. if (ohci->next_config_rom != NULL) {
  1094. if (ohci->next_config_rom != ohci->config_rom) {
  1095. free_rom = ohci->config_rom;
  1096. free_rom_bus = ohci->config_rom_bus;
  1097. }
  1098. ohci->config_rom = ohci->next_config_rom;
  1099. ohci->config_rom_bus = ohci->next_config_rom_bus;
  1100. ohci->next_config_rom = NULL;
  1101. /*
  1102. * Restore config_rom image and manually update
  1103. * config_rom registers. Writing the header quadlet
  1104. * will indicate that the config rom is ready, so we
  1105. * do that last.
  1106. */
  1107. reg_write(ohci, OHCI1394_BusOptions,
  1108. be32_to_cpu(ohci->config_rom[2]));
  1109. ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
  1110. reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
  1111. }
  1112. #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
  1113. reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
  1114. reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
  1115. #endif
  1116. spin_unlock_irqrestore(&ohci->lock, flags);
  1117. if (free_rom)
  1118. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  1119. free_rom, free_rom_bus);
  1120. log_selfids(generation, self_id_count, ohci->self_id_buffer);
  1121. fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
  1122. self_id_count, ohci->self_id_buffer);
  1123. }
  1124. static irqreturn_t irq_handler(int irq, void *data)
  1125. {
  1126. struct fw_ohci *ohci = data;
  1127. u32 event, iso_event, cycle_time;
  1128. int i;
  1129. event = reg_read(ohci, OHCI1394_IntEventClear);
  1130. if (!event || !~event)
  1131. return IRQ_NONE;
  1132. /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
  1133. reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
  1134. log_irqs(event);
  1135. if (event & OHCI1394_selfIDComplete)
  1136. tasklet_schedule(&ohci->bus_reset_tasklet);
  1137. if (event & OHCI1394_RQPkt)
  1138. tasklet_schedule(&ohci->ar_request_ctx.tasklet);
  1139. if (event & OHCI1394_RSPkt)
  1140. tasklet_schedule(&ohci->ar_response_ctx.tasklet);
  1141. if (event & OHCI1394_reqTxComplete)
  1142. tasklet_schedule(&ohci->at_request_ctx.tasklet);
  1143. if (event & OHCI1394_respTxComplete)
  1144. tasklet_schedule(&ohci->at_response_ctx.tasklet);
  1145. iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
  1146. reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
  1147. while (iso_event) {
  1148. i = ffs(iso_event) - 1;
  1149. tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
  1150. iso_event &= ~(1 << i);
  1151. }
  1152. iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
  1153. reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
  1154. while (iso_event) {
  1155. i = ffs(iso_event) - 1;
  1156. tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
  1157. iso_event &= ~(1 << i);
  1158. }
  1159. if (unlikely(event & OHCI1394_regAccessFail))
  1160. fw_error("Register access failure - "
  1161. "please notify linux1394-devel@lists.sf.net\n");
  1162. if (unlikely(event & OHCI1394_postedWriteErr))
  1163. fw_error("PCI posted write error\n");
  1164. if (unlikely(event & OHCI1394_cycleTooLong)) {
  1165. if (printk_ratelimit())
  1166. fw_notify("isochronous cycle too long\n");
  1167. reg_write(ohci, OHCI1394_LinkControlSet,
  1168. OHCI1394_LinkControl_cycleMaster);
  1169. }
  1170. if (event & OHCI1394_cycle64Seconds) {
  1171. cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  1172. if ((cycle_time & 0x80000000) == 0)
  1173. ohci->bus_seconds++;
  1174. }
  1175. return IRQ_HANDLED;
  1176. }
  1177. static int software_reset(struct fw_ohci *ohci)
  1178. {
  1179. int i;
  1180. reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
  1181. for (i = 0; i < OHCI_LOOP_COUNT; i++) {
  1182. if ((reg_read(ohci, OHCI1394_HCControlSet) &
  1183. OHCI1394_HCControl_softReset) == 0)
  1184. return 0;
  1185. msleep(1);
  1186. }
  1187. return -EBUSY;
  1188. }
  1189. static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
  1190. {
  1191. struct fw_ohci *ohci = fw_ohci(card);
  1192. struct pci_dev *dev = to_pci_dev(card->device);
  1193. u32 lps;
  1194. int i;
  1195. if (software_reset(ohci)) {
  1196. fw_error("Failed to reset ohci card.\n");
  1197. return -EBUSY;
  1198. }
  1199. /*
  1200. * Now enable LPS, which we need in order to start accessing
  1201. * most of the registers. In fact, on some cards (ALI M5251),
  1202. * accessing registers in the SClk domain without LPS enabled
  1203. * will lock up the machine. Wait 50msec to make sure we have
  1204. * full link enabled. However, with some cards (well, at least
  1205. * a JMicron PCIe card), we have to try again sometimes.
  1206. */
  1207. reg_write(ohci, OHCI1394_HCControlSet,
  1208. OHCI1394_HCControl_LPS |
  1209. OHCI1394_HCControl_postedWriteEnable);
  1210. flush_writes(ohci);
  1211. for (lps = 0, i = 0; !lps && i < 3; i++) {
  1212. msleep(50);
  1213. lps = reg_read(ohci, OHCI1394_HCControlSet) &
  1214. OHCI1394_HCControl_LPS;
  1215. }
  1216. if (!lps) {
  1217. fw_error("Failed to set Link Power Status\n");
  1218. return -EIO;
  1219. }
  1220. reg_write(ohci, OHCI1394_HCControlClear,
  1221. OHCI1394_HCControl_noByteSwapData);
  1222. reg_write(ohci, OHCI1394_LinkControlSet,
  1223. OHCI1394_LinkControl_rcvSelfID |
  1224. OHCI1394_LinkControl_cycleTimerEnable |
  1225. OHCI1394_LinkControl_cycleMaster);
  1226. reg_write(ohci, OHCI1394_ATRetries,
  1227. OHCI1394_MAX_AT_REQ_RETRIES |
  1228. (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
  1229. (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
  1230. ar_context_run(&ohci->ar_request_ctx);
  1231. ar_context_run(&ohci->ar_response_ctx);
  1232. reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
  1233. reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
  1234. reg_write(ohci, OHCI1394_IntEventClear, ~0);
  1235. reg_write(ohci, OHCI1394_IntMaskClear, ~0);
  1236. reg_write(ohci, OHCI1394_IntMaskSet,
  1237. OHCI1394_selfIDComplete |
  1238. OHCI1394_RQPkt | OHCI1394_RSPkt |
  1239. OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
  1240. OHCI1394_isochRx | OHCI1394_isochTx |
  1241. OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
  1242. OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
  1243. OHCI1394_masterIntEnable);
  1244. if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
  1245. reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
  1246. /* Activate link_on bit and contender bit in our self ID packets.*/
  1247. if (ohci_update_phy_reg(card, 4, 0,
  1248. PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
  1249. return -EIO;
  1250. /*
  1251. * When the link is not yet enabled, the atomic config rom
  1252. * update mechanism described below in ohci_set_config_rom()
  1253. * is not active. We have to update ConfigRomHeader and
  1254. * BusOptions manually, and the write to ConfigROMmap takes
  1255. * effect immediately. We tie this to the enabling of the
  1256. * link, so we have a valid config rom before enabling - the
  1257. * OHCI requires that ConfigROMhdr and BusOptions have valid
  1258. * values before enabling.
  1259. *
  1260. * However, when the ConfigROMmap is written, some controllers
  1261. * always read back quadlets 0 and 2 from the config rom to
  1262. * the ConfigRomHeader and BusOptions registers on bus reset.
  1263. * They shouldn't do that in this initial case where the link
  1264. * isn't enabled. This means we have to use the same
  1265. * workaround here, setting the bus header to 0 and then write
  1266. * the right values in the bus reset tasklet.
  1267. */
  1268. if (config_rom) {
  1269. ohci->next_config_rom =
  1270. dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  1271. &ohci->next_config_rom_bus,
  1272. GFP_KERNEL);
  1273. if (ohci->next_config_rom == NULL)
  1274. return -ENOMEM;
  1275. memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
  1276. fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
  1277. } else {
  1278. /*
  1279. * In the suspend case, config_rom is NULL, which
  1280. * means that we just reuse the old config rom.
  1281. */
  1282. ohci->next_config_rom = ohci->config_rom;
  1283. ohci->next_config_rom_bus = ohci->config_rom_bus;
  1284. }
  1285. ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
  1286. ohci->next_config_rom[0] = 0;
  1287. reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
  1288. reg_write(ohci, OHCI1394_BusOptions,
  1289. be32_to_cpu(ohci->next_config_rom[2]));
  1290. reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
  1291. reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
  1292. if (request_irq(dev->irq, irq_handler,
  1293. IRQF_SHARED, ohci_driver_name, ohci)) {
  1294. fw_error("Failed to allocate shared interrupt %d.\n",
  1295. dev->irq);
  1296. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  1297. ohci->config_rom, ohci->config_rom_bus);
  1298. return -EIO;
  1299. }
  1300. reg_write(ohci, OHCI1394_HCControlSet,
  1301. OHCI1394_HCControl_linkEnable |
  1302. OHCI1394_HCControl_BIBimageValid);
  1303. flush_writes(ohci);
  1304. /*
  1305. * We are ready to go, initiate bus reset to finish the
  1306. * initialization.
  1307. */
  1308. fw_core_initiate_bus_reset(&ohci->card, 1);
  1309. return 0;
  1310. }
  1311. static int
  1312. ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
  1313. {
  1314. struct fw_ohci *ohci;
  1315. unsigned long flags;
  1316. int retval = -EBUSY;
  1317. __be32 *next_config_rom;
  1318. dma_addr_t uninitialized_var(next_config_rom_bus);
  1319. ohci = fw_ohci(card);
  1320. /*
  1321. * When the OHCI controller is enabled, the config rom update
  1322. * mechanism is a bit tricky, but easy enough to use. See
  1323. * section 5.5.6 in the OHCI specification.
  1324. *
  1325. * The OHCI controller caches the new config rom address in a
  1326. * shadow register (ConfigROMmapNext) and needs a bus reset
  1327. * for the changes to take place. When the bus reset is
  1328. * detected, the controller loads the new values for the
  1329. * ConfigRomHeader and BusOptions registers from the specified
  1330. * config rom and loads ConfigROMmap from the ConfigROMmapNext
  1331. * shadow register. All automatically and atomically.
  1332. *
  1333. * Now, there's a twist to this story. The automatic load of
  1334. * ConfigRomHeader and BusOptions doesn't honor the
  1335. * noByteSwapData bit, so with a be32 config rom, the
  1336. * controller will load be32 values in to these registers
  1337. * during the atomic update, even on litte endian
  1338. * architectures. The workaround we use is to put a 0 in the
  1339. * header quadlet; 0 is endian agnostic and means that the
  1340. * config rom isn't ready yet. In the bus reset tasklet we
  1341. * then set up the real values for the two registers.
  1342. *
  1343. * We use ohci->lock to avoid racing with the code that sets
  1344. * ohci->next_config_rom to NULL (see bus_reset_tasklet).
  1345. */
  1346. next_config_rom =
  1347. dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  1348. &next_config_rom_bus, GFP_KERNEL);
  1349. if (next_config_rom == NULL)
  1350. return -ENOMEM;
  1351. spin_lock_irqsave(&ohci->lock, flags);
  1352. if (ohci->next_config_rom == NULL) {
  1353. ohci->next_config_rom = next_config_rom;
  1354. ohci->next_config_rom_bus = next_config_rom_bus;
  1355. memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
  1356. fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
  1357. length * 4);
  1358. ohci->next_header = config_rom[0];
  1359. ohci->next_config_rom[0] = 0;
  1360. reg_write(ohci, OHCI1394_ConfigROMmap,
  1361. ohci->next_config_rom_bus);
  1362. retval = 0;
  1363. }
  1364. spin_unlock_irqrestore(&ohci->lock, flags);
  1365. /*
  1366. * Now initiate a bus reset to have the changes take
  1367. * effect. We clean up the old config rom memory and DMA
  1368. * mappings in the bus reset tasklet, since the OHCI
  1369. * controller could need to access it before the bus reset
  1370. * takes effect.
  1371. */
  1372. if (retval == 0)
  1373. fw_core_initiate_bus_reset(&ohci->card, 1);
  1374. else
  1375. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  1376. next_config_rom, next_config_rom_bus);
  1377. return retval;
  1378. }
  1379. static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
  1380. {
  1381. struct fw_ohci *ohci = fw_ohci(card);
  1382. at_context_transmit(&ohci->at_request_ctx, packet);
  1383. }
  1384. static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
  1385. {
  1386. struct fw_ohci *ohci = fw_ohci(card);
  1387. at_context_transmit(&ohci->at_response_ctx, packet);
  1388. }
  1389. static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
  1390. {
  1391. struct fw_ohci *ohci = fw_ohci(card);
  1392. struct context *ctx = &ohci->at_request_ctx;
  1393. struct driver_data *driver_data = packet->driver_data;
  1394. int retval = -ENOENT;
  1395. tasklet_disable(&ctx->tasklet);
  1396. if (packet->ack != 0)
  1397. goto out;
  1398. log_ar_at_event('T', packet->speed, packet->header, 0x20);
  1399. driver_data->packet = NULL;
  1400. packet->ack = RCODE_CANCELLED;
  1401. packet->callback(packet, &ohci->card, packet->ack);
  1402. retval = 0;
  1403. out:
  1404. tasklet_enable(&ctx->tasklet);
  1405. return retval;
  1406. }
  1407. static int
  1408. ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
  1409. {
  1410. #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
  1411. return 0;
  1412. #else
  1413. struct fw_ohci *ohci = fw_ohci(card);
  1414. unsigned long flags;
  1415. int n, retval = 0;
  1416. /*
  1417. * FIXME: Make sure this bitmask is cleared when we clear the busReset
  1418. * interrupt bit. Clear physReqResourceAllBuses on bus reset.
  1419. */
  1420. spin_lock_irqsave(&ohci->lock, flags);
  1421. if (ohci->generation != generation) {
  1422. retval = -ESTALE;
  1423. goto out;
  1424. }
  1425. /*
  1426. * Note, if the node ID contains a non-local bus ID, physical DMA is
  1427. * enabled for _all_ nodes on remote buses.
  1428. */
  1429. n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
  1430. if (n < 32)
  1431. reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
  1432. else
  1433. reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
  1434. flush_writes(ohci);
  1435. out:
  1436. spin_unlock_irqrestore(&ohci->lock, flags);
  1437. return retval;
  1438. #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
  1439. }
  1440. static u64
  1441. ohci_get_bus_time(struct fw_card *card)
  1442. {
  1443. struct fw_ohci *ohci = fw_ohci(card);
  1444. u32 cycle_time;
  1445. u64 bus_time;
  1446. cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  1447. bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
  1448. return bus_time;
  1449. }
  1450. static int handle_ir_dualbuffer_packet(struct context *context,
  1451. struct descriptor *d,
  1452. struct descriptor *last)
  1453. {
  1454. struct iso_context *ctx =
  1455. container_of(context, struct iso_context, context);
  1456. struct db_descriptor *db = (struct db_descriptor *) d;
  1457. __le32 *ir_header;
  1458. size_t header_length;
  1459. void *p, *end;
  1460. int i;
  1461. if (db->first_res_count != 0 && db->second_res_count != 0) {
  1462. if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
  1463. /* This descriptor isn't done yet, stop iteration. */
  1464. return 0;
  1465. }
  1466. ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
  1467. }
  1468. header_length = le16_to_cpu(db->first_req_count) -
  1469. le16_to_cpu(db->first_res_count);
  1470. i = ctx->header_length;
  1471. p = db + 1;
  1472. end = p + header_length;
  1473. while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
  1474. /*
  1475. * The iso header is byteswapped to little endian by
  1476. * the controller, but the remaining header quadlets
  1477. * are big endian. We want to present all the headers
  1478. * as big endian, so we have to swap the first
  1479. * quadlet.
  1480. */
  1481. *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
  1482. memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
  1483. i += ctx->base.header_size;
  1484. ctx->excess_bytes +=
  1485. (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
  1486. p += ctx->base.header_size + 4;
  1487. }
  1488. ctx->header_length = i;
  1489. ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
  1490. le16_to_cpu(db->second_res_count);
  1491. if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
  1492. ir_header = (__le32 *) (db + 1);
  1493. ctx->base.callback(&ctx->base,
  1494. le32_to_cpu(ir_header[0]) & 0xffff,
  1495. ctx->header_length, ctx->header,
  1496. ctx->base.callback_data);
  1497. ctx->header_length = 0;
  1498. }
  1499. return 1;
  1500. }
  1501. static int handle_ir_packet_per_buffer(struct context *context,
  1502. struct descriptor *d,
  1503. struct descriptor *last)
  1504. {
  1505. struct iso_context *ctx =
  1506. container_of(context, struct iso_context, context);
  1507. struct descriptor *pd;
  1508. __le32 *ir_header;
  1509. void *p;
  1510. int i;
  1511. for (pd = d; pd <= last; pd++) {
  1512. if (pd->transfer_status)
  1513. break;
  1514. }
  1515. if (pd > last)
  1516. /* Descriptor(s) not done yet, stop iteration */
  1517. return 0;
  1518. i = ctx->header_length;
  1519. p = last + 1;
  1520. if (ctx->base.header_size > 0 &&
  1521. i + ctx->base.header_size <= PAGE_SIZE) {
  1522. /*
  1523. * The iso header is byteswapped to little endian by
  1524. * the controller, but the remaining header quadlets
  1525. * are big endian. We want to present all the headers
  1526. * as big endian, so we have to swap the first quadlet.
  1527. */
  1528. *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
  1529. memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
  1530. ctx->header_length += ctx->base.header_size;
  1531. }
  1532. if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
  1533. ir_header = (__le32 *) p;
  1534. ctx->base.callback(&ctx->base,
  1535. le32_to_cpu(ir_header[0]) & 0xffff,
  1536. ctx->header_length, ctx->header,
  1537. ctx->base.callback_data);
  1538. ctx->header_length = 0;
  1539. }
  1540. return 1;
  1541. }
  1542. static int handle_it_packet(struct context *context,
  1543. struct descriptor *d,
  1544. struct descriptor *last)
  1545. {
  1546. struct iso_context *ctx =
  1547. container_of(context, struct iso_context, context);
  1548. if (last->transfer_status == 0)
  1549. /* This descriptor isn't done yet, stop iteration. */
  1550. return 0;
  1551. if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
  1552. ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
  1553. 0, NULL, ctx->base.callback_data);
  1554. return 1;
  1555. }
  1556. static struct fw_iso_context *
  1557. ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
  1558. {
  1559. struct fw_ohci *ohci = fw_ohci(card);
  1560. struct iso_context *ctx, *list;
  1561. descriptor_callback_t callback;
  1562. u32 *mask, regs;
  1563. unsigned long flags;
  1564. int index, retval = -ENOMEM;
  1565. if (type == FW_ISO_CONTEXT_TRANSMIT) {
  1566. mask = &ohci->it_context_mask;
  1567. list = ohci->it_context_list;
  1568. callback = handle_it_packet;
  1569. } else {
  1570. mask = &ohci->ir_context_mask;
  1571. list = ohci->ir_context_list;
  1572. if (ohci->version >= OHCI_VERSION_1_1)
  1573. callback = handle_ir_dualbuffer_packet;
  1574. else
  1575. callback = handle_ir_packet_per_buffer;
  1576. }
  1577. spin_lock_irqsave(&ohci->lock, flags);
  1578. index = ffs(*mask) - 1;
  1579. if (index >= 0)
  1580. *mask &= ~(1 << index);
  1581. spin_unlock_irqrestore(&ohci->lock, flags);
  1582. if (index < 0)
  1583. return ERR_PTR(-EBUSY);
  1584. if (type == FW_ISO_CONTEXT_TRANSMIT)
  1585. regs = OHCI1394_IsoXmitContextBase(index);
  1586. else
  1587. regs = OHCI1394_IsoRcvContextBase(index);
  1588. ctx = &list[index];
  1589. memset(ctx, 0, sizeof(*ctx));
  1590. ctx->header_length = 0;
  1591. ctx->header = (void *) __get_free_page(GFP_KERNEL);
  1592. if (ctx->header == NULL)
  1593. goto out;
  1594. retval = context_init(&ctx->context, ohci, regs, callback);
  1595. if (retval < 0)
  1596. goto out_with_header;
  1597. return &ctx->base;
  1598. out_with_header:
  1599. free_page((unsigned long)ctx->header);
  1600. out:
  1601. spin_lock_irqsave(&ohci->lock, flags);
  1602. *mask |= 1 << index;
  1603. spin_unlock_irqrestore(&ohci->lock, flags);
  1604. return ERR_PTR(retval);
  1605. }
  1606. static int ohci_start_iso(struct fw_iso_context *base,
  1607. s32 cycle, u32 sync, u32 tags)
  1608. {
  1609. struct iso_context *ctx = container_of(base, struct iso_context, base);
  1610. struct fw_ohci *ohci = ctx->context.ohci;
  1611. u32 control, match;
  1612. int index;
  1613. if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
  1614. index = ctx - ohci->it_context_list;
  1615. match = 0;
  1616. if (cycle >= 0)
  1617. match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
  1618. (cycle & 0x7fff) << 16;
  1619. reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
  1620. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
  1621. context_run(&ctx->context, match);
  1622. } else {
  1623. index = ctx - ohci->ir_context_list;
  1624. control = IR_CONTEXT_ISOCH_HEADER;
  1625. if (ohci->version >= OHCI_VERSION_1_1)
  1626. control |= IR_CONTEXT_DUAL_BUFFER_MODE;
  1627. match = (tags << 28) | (sync << 8) | ctx->base.channel;
  1628. if (cycle >= 0) {
  1629. match |= (cycle & 0x07fff) << 12;
  1630. control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
  1631. }
  1632. reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
  1633. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
  1634. reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
  1635. context_run(&ctx->context, control);
  1636. }
  1637. return 0;
  1638. }
  1639. static int ohci_stop_iso(struct fw_iso_context *base)
  1640. {
  1641. struct fw_ohci *ohci = fw_ohci(base->card);
  1642. struct iso_context *ctx = container_of(base, struct iso_context, base);
  1643. int index;
  1644. if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
  1645. index = ctx - ohci->it_context_list;
  1646. reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
  1647. } else {
  1648. index = ctx - ohci->ir_context_list;
  1649. reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
  1650. }
  1651. flush_writes(ohci);
  1652. context_stop(&ctx->context);
  1653. return 0;
  1654. }
  1655. static void ohci_free_iso_context(struct fw_iso_context *base)
  1656. {
  1657. struct fw_ohci *ohci = fw_ohci(base->card);
  1658. struct iso_context *ctx = container_of(base, struct iso_context, base);
  1659. unsigned long flags;
  1660. int index;
  1661. ohci_stop_iso(base);
  1662. context_release(&ctx->context);
  1663. free_page((unsigned long)ctx->header);
  1664. spin_lock_irqsave(&ohci->lock, flags);
  1665. if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
  1666. index = ctx - ohci->it_context_list;
  1667. ohci->it_context_mask |= 1 << index;
  1668. } else {
  1669. index = ctx - ohci->ir_context_list;
  1670. ohci->ir_context_mask |= 1 << index;
  1671. }
  1672. spin_unlock_irqrestore(&ohci->lock, flags);
  1673. }
  1674. static int
  1675. ohci_queue_iso_transmit(struct fw_iso_context *base,
  1676. struct fw_iso_packet *packet,
  1677. struct fw_iso_buffer *buffer,
  1678. unsigned long payload)
  1679. {
  1680. struct iso_context *ctx = container_of(base, struct iso_context, base);
  1681. struct descriptor *d, *last, *pd;
  1682. struct fw_iso_packet *p;
  1683. __le32 *header;
  1684. dma_addr_t d_bus, page_bus;
  1685. u32 z, header_z, payload_z, irq;
  1686. u32 payload_index, payload_end_index, next_page_index;
  1687. int page, end_page, i, length, offset;
  1688. /*
  1689. * FIXME: Cycle lost behavior should be configurable: lose
  1690. * packet, retransmit or terminate..
  1691. */
  1692. p = packet;
  1693. payload_index = payload;
  1694. if (p->skip)
  1695. z = 1;
  1696. else
  1697. z = 2;
  1698. if (p->header_length > 0)
  1699. z++;
  1700. /* Determine the first page the payload isn't contained in. */
  1701. end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
  1702. if (p->payload_length > 0)
  1703. payload_z = end_page - (payload_index >> PAGE_SHIFT);
  1704. else
  1705. payload_z = 0;
  1706. z += payload_z;
  1707. /* Get header size in number of descriptors. */
  1708. header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
  1709. d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
  1710. if (d == NULL)
  1711. return -ENOMEM;
  1712. if (!p->skip) {
  1713. d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
  1714. d[0].req_count = cpu_to_le16(8);
  1715. header = (__le32 *) &d[1];
  1716. header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
  1717. IT_HEADER_TAG(p->tag) |
  1718. IT_HEADER_TCODE(TCODE_STREAM_DATA) |
  1719. IT_HEADER_CHANNEL(ctx->base.channel) |
  1720. IT_HEADER_SPEED(ctx->base.speed));
  1721. header[1] =
  1722. cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
  1723. p->payload_length));
  1724. }
  1725. if (p->header_length > 0) {
  1726. d[2].req_count = cpu_to_le16(p->header_length);
  1727. d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
  1728. memcpy(&d[z], p->header, p->header_length);
  1729. }
  1730. pd = d + z - payload_z;
  1731. payload_end_index = payload_index + p->payload_length;
  1732. for (i = 0; i < payload_z; i++) {
  1733. page = payload_index >> PAGE_SHIFT;
  1734. offset = payload_index & ~PAGE_MASK;
  1735. next_page_index = (page + 1) << PAGE_SHIFT;
  1736. length =
  1737. min(next_page_index, payload_end_index) - payload_index;
  1738. pd[i].req_count = cpu_to_le16(length);
  1739. page_bus = page_private(buffer->pages[page]);
  1740. pd[i].data_address = cpu_to_le32(page_bus + offset);
  1741. payload_index += length;
  1742. }
  1743. if (p->interrupt)
  1744. irq = DESCRIPTOR_IRQ_ALWAYS;
  1745. else
  1746. irq = DESCRIPTOR_NO_IRQ;
  1747. last = z == 2 ? d : d + z - 1;
  1748. last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
  1749. DESCRIPTOR_STATUS |
  1750. DESCRIPTOR_BRANCH_ALWAYS |
  1751. irq);
  1752. context_append(&ctx->context, d, z, header_z);
  1753. return 0;
  1754. }
  1755. static int
  1756. ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
  1757. struct fw_iso_packet *packet,
  1758. struct fw_iso_buffer *buffer,
  1759. unsigned long payload)
  1760. {
  1761. struct iso_context *ctx = container_of(base, struct iso_context, base);
  1762. struct db_descriptor *db = NULL;
  1763. struct descriptor *d;
  1764. struct fw_iso_packet *p;
  1765. dma_addr_t d_bus, page_bus;
  1766. u32 z, header_z, length, rest;
  1767. int page, offset, packet_count, header_size;
  1768. /*
  1769. * FIXME: Cycle lost behavior should be configurable: lose
  1770. * packet, retransmit or terminate..
  1771. */
  1772. p = packet;
  1773. z = 2;
  1774. /*
  1775. * The OHCI controller puts the status word in the header
  1776. * buffer too, so we need 4 extra bytes per packet.
  1777. */
  1778. packet_count = p->header_length / ctx->base.header_size;
  1779. header_size = packet_count * (ctx->base.header_size + 4);
  1780. /* Get header size in number of descriptors. */
  1781. header_z = DIV_ROUND_UP(header_size, sizeof(*d));
  1782. page = payload >> PAGE_SHIFT;
  1783. offset = payload & ~PAGE_MASK;
  1784. rest = p->payload_length;
  1785. /* FIXME: make packet-per-buffer/dual-buffer a context option */
  1786. while (rest > 0) {
  1787. d = context_get_descriptors(&ctx->context,
  1788. z + header_z, &d_bus);
  1789. if (d == NULL)
  1790. return -ENOMEM;
  1791. db = (struct db_descriptor *) d;
  1792. db->control = cpu_to_le16(DESCRIPTOR_STATUS |
  1793. DESCRIPTOR_BRANCH_ALWAYS);
  1794. db->first_size = cpu_to_le16(ctx->base.header_size + 4);
  1795. if (p->skip && rest == p->payload_length) {
  1796. db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
  1797. db->first_req_count = db->first_size;
  1798. } else {
  1799. db->first_req_count = cpu_to_le16(header_size);
  1800. }
  1801. db->first_res_count = db->first_req_count;
  1802. db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
  1803. if (p->skip && rest == p->payload_length)
  1804. length = 4;
  1805. else if (offset + rest < PAGE_SIZE)
  1806. length = rest;
  1807. else
  1808. length = PAGE_SIZE - offset;
  1809. db->second_req_count = cpu_to_le16(length);
  1810. db->second_res_count = db->second_req_count;
  1811. page_bus = page_private(buffer->pages[page]);
  1812. db->second_buffer = cpu_to_le32(page_bus + offset);
  1813. if (p->interrupt && length == rest)
  1814. db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
  1815. context_append(&ctx->context, d, z, header_z);
  1816. offset = (offset + length) & ~PAGE_MASK;
  1817. rest -= length;
  1818. if (offset == 0)
  1819. page++;
  1820. }
  1821. return 0;
  1822. }
  1823. static int
  1824. ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
  1825. struct fw_iso_packet *packet,
  1826. struct fw_iso_buffer *buffer,
  1827. unsigned long payload)
  1828. {
  1829. struct iso_context *ctx = container_of(base, struct iso_context, base);
  1830. struct descriptor *d = NULL, *pd = NULL;
  1831. struct fw_iso_packet *p = packet;
  1832. dma_addr_t d_bus, page_bus;
  1833. u32 z, header_z, rest;
  1834. int i, j, length;
  1835. int page, offset, packet_count, header_size, payload_per_buffer;
  1836. /*
  1837. * The OHCI controller puts the status word in the
  1838. * buffer too, so we need 4 extra bytes per packet.
  1839. */
  1840. packet_count = p->header_length / ctx->base.header_size;
  1841. header_size = ctx->base.header_size + 4;
  1842. /* Get header size in number of descriptors. */
  1843. header_z = DIV_ROUND_UP(header_size, sizeof(*d));
  1844. page = payload >> PAGE_SHIFT;
  1845. offset = payload & ~PAGE_MASK;
  1846. payload_per_buffer = p->payload_length / packet_count;
  1847. for (i = 0; i < packet_count; i++) {
  1848. /* d points to the header descriptor */
  1849. z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
  1850. d = context_get_descriptors(&ctx->context,
  1851. z + header_z, &d_bus);
  1852. if (d == NULL)
  1853. return -ENOMEM;
  1854. d->control = cpu_to_le16(DESCRIPTOR_STATUS |
  1855. DESCRIPTOR_INPUT_MORE);
  1856. if (p->skip && i == 0)
  1857. d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
  1858. d->req_count = cpu_to_le16(header_size);
  1859. d->res_count = d->req_count;
  1860. d->transfer_status = 0;
  1861. d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
  1862. rest = payload_per_buffer;
  1863. for (j = 1; j < z; j++) {
  1864. pd = d + j;
  1865. pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
  1866. DESCRIPTOR_INPUT_MORE);
  1867. if (offset + rest < PAGE_SIZE)
  1868. length = rest;
  1869. else
  1870. length = PAGE_SIZE - offset;
  1871. pd->req_count = cpu_to_le16(length);
  1872. pd->res_count = pd->req_count;
  1873. pd->transfer_status = 0;
  1874. page_bus = page_private(buffer->pages[page]);
  1875. pd->data_address = cpu_to_le32(page_bus + offset);
  1876. offset = (offset + length) & ~PAGE_MASK;
  1877. rest -= length;
  1878. if (offset == 0)
  1879. page++;
  1880. }
  1881. pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
  1882. DESCRIPTOR_INPUT_LAST |
  1883. DESCRIPTOR_BRANCH_ALWAYS);
  1884. if (p->interrupt && i == packet_count - 1)
  1885. pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
  1886. context_append(&ctx->context, d, z, header_z);
  1887. }
  1888. return 0;
  1889. }
  1890. static int
  1891. ohci_queue_iso(struct fw_iso_context *base,
  1892. struct fw_iso_packet *packet,
  1893. struct fw_iso_buffer *buffer,
  1894. unsigned long payload)
  1895. {
  1896. struct iso_context *ctx = container_of(base, struct iso_context, base);
  1897. unsigned long flags;
  1898. int retval;
  1899. spin_lock_irqsave(&ctx->context.ohci->lock, flags);
  1900. if (base->type == FW_ISO_CONTEXT_TRANSMIT)
  1901. retval = ohci_queue_iso_transmit(base, packet, buffer, payload);
  1902. else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
  1903. retval = ohci_queue_iso_receive_dualbuffer(base, packet,
  1904. buffer, payload);
  1905. else
  1906. retval = ohci_queue_iso_receive_packet_per_buffer(base, packet,
  1907. buffer,
  1908. payload);
  1909. spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
  1910. return retval;
  1911. }
  1912. static const struct fw_card_driver ohci_driver = {
  1913. .name = ohci_driver_name,
  1914. .enable = ohci_enable,
  1915. .update_phy_reg = ohci_update_phy_reg,
  1916. .set_config_rom = ohci_set_config_rom,
  1917. .send_request = ohci_send_request,
  1918. .send_response = ohci_send_response,
  1919. .cancel_packet = ohci_cancel_packet,
  1920. .enable_phys_dma = ohci_enable_phys_dma,
  1921. .get_bus_time = ohci_get_bus_time,
  1922. .allocate_iso_context = ohci_allocate_iso_context,
  1923. .free_iso_context = ohci_free_iso_context,
  1924. .queue_iso = ohci_queue_iso,
  1925. .start_iso = ohci_start_iso,
  1926. .stop_iso = ohci_stop_iso,
  1927. };
  1928. #ifdef CONFIG_PPC_PMAC
  1929. static void ohci_pmac_on(struct pci_dev *dev)
  1930. {
  1931. if (machine_is(powermac)) {
  1932. struct device_node *ofn = pci_device_to_OF_node(dev);
  1933. if (ofn) {
  1934. pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
  1935. pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
  1936. }
  1937. }
  1938. }
  1939. static void ohci_pmac_off(struct pci_dev *dev)
  1940. {
  1941. if (machine_is(powermac)) {
  1942. struct device_node *ofn = pci_device_to_OF_node(dev);
  1943. if (ofn) {
  1944. pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
  1945. pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
  1946. }
  1947. }
  1948. }
  1949. #else
  1950. #define ohci_pmac_on(dev)
  1951. #define ohci_pmac_off(dev)
  1952. #endif /* CONFIG_PPC_PMAC */
  1953. static int __devinit
  1954. pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
  1955. {
  1956. struct fw_ohci *ohci;
  1957. u32 bus_options, max_receive, link_speed;
  1958. u64 guid;
  1959. int err;
  1960. size_t size;
  1961. ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
  1962. if (ohci == NULL) {
  1963. fw_error("Could not malloc fw_ohci data.\n");
  1964. return -ENOMEM;
  1965. }
  1966. fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
  1967. ohci_pmac_on(dev);
  1968. err = pci_enable_device(dev);
  1969. if (err) {
  1970. fw_error("Failed to enable OHCI hardware.\n");
  1971. goto fail_free;
  1972. }
  1973. pci_set_master(dev);
  1974. pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
  1975. pci_set_drvdata(dev, ohci);
  1976. #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
  1977. ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
  1978. dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
  1979. #endif
  1980. spin_lock_init(&ohci->lock);
  1981. tasklet_init(&ohci->bus_reset_tasklet,
  1982. bus_reset_tasklet, (unsigned long)ohci);
  1983. err = pci_request_region(dev, 0, ohci_driver_name);
  1984. if (err) {
  1985. fw_error("MMIO resource unavailable\n");
  1986. goto fail_disable;
  1987. }
  1988. ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
  1989. if (ohci->registers == NULL) {
  1990. fw_error("Failed to remap registers\n");
  1991. err = -ENXIO;
  1992. goto fail_iomem;
  1993. }
  1994. ar_context_init(&ohci->ar_request_ctx, ohci,
  1995. OHCI1394_AsReqRcvContextControlSet);
  1996. ar_context_init(&ohci->ar_response_ctx, ohci,
  1997. OHCI1394_AsRspRcvContextControlSet);
  1998. context_init(&ohci->at_request_ctx, ohci,
  1999. OHCI1394_AsReqTrContextControlSet, handle_at_packet);
  2000. context_init(&ohci->at_response_ctx, ohci,
  2001. OHCI1394_AsRspTrContextControlSet, handle_at_packet);
  2002. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
  2003. ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
  2004. reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
  2005. size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
  2006. ohci->it_context_list = kzalloc(size, GFP_KERNEL);
  2007. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
  2008. ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
  2009. reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
  2010. size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
  2011. ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
  2012. if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
  2013. fw_error("Out of memory for it/ir contexts.\n");
  2014. err = -ENOMEM;
  2015. goto fail_registers;
  2016. }
  2017. /* self-id dma buffer allocation */
  2018. ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
  2019. SELF_ID_BUF_SIZE,
  2020. &ohci->self_id_bus,
  2021. GFP_KERNEL);
  2022. if (ohci->self_id_cpu == NULL) {
  2023. fw_error("Out of memory for self ID buffer.\n");
  2024. err = -ENOMEM;
  2025. goto fail_registers;
  2026. }
  2027. bus_options = reg_read(ohci, OHCI1394_BusOptions);
  2028. max_receive = (bus_options >> 12) & 0xf;
  2029. link_speed = bus_options & 0x7;
  2030. guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
  2031. reg_read(ohci, OHCI1394_GUIDLo);
  2032. err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
  2033. if (err < 0)
  2034. goto fail_self_id;
  2035. ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
  2036. fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
  2037. dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
  2038. return 0;
  2039. fail_self_id:
  2040. dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
  2041. ohci->self_id_cpu, ohci->self_id_bus);
  2042. fail_registers:
  2043. kfree(ohci->it_context_list);
  2044. kfree(ohci->ir_context_list);
  2045. pci_iounmap(dev, ohci->registers);
  2046. fail_iomem:
  2047. pci_release_region(dev, 0);
  2048. fail_disable:
  2049. pci_disable_device(dev);
  2050. fail_free:
  2051. kfree(&ohci->card);
  2052. ohci_pmac_off(dev);
  2053. return err;
  2054. }
  2055. static void pci_remove(struct pci_dev *dev)
  2056. {
  2057. struct fw_ohci *ohci;
  2058. ohci = pci_get_drvdata(dev);
  2059. reg_write(ohci, OHCI1394_IntMaskClear, ~0);
  2060. flush_writes(ohci);
  2061. fw_core_remove_card(&ohci->card);
  2062. /*
  2063. * FIXME: Fail all pending packets here, now that the upper
  2064. * layers can't queue any more.
  2065. */
  2066. software_reset(ohci);
  2067. free_irq(dev->irq, ohci);
  2068. dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
  2069. ohci->self_id_cpu, ohci->self_id_bus);
  2070. kfree(ohci->it_context_list);
  2071. kfree(ohci->ir_context_list);
  2072. pci_iounmap(dev, ohci->registers);
  2073. pci_release_region(dev, 0);
  2074. pci_disable_device(dev);
  2075. kfree(&ohci->card);
  2076. ohci_pmac_off(dev);
  2077. fw_notify("Removed fw-ohci device.\n");
  2078. }
  2079. #ifdef CONFIG_PM
  2080. static int pci_suspend(struct pci_dev *dev, pm_message_t state)
  2081. {
  2082. struct fw_ohci *ohci = pci_get_drvdata(dev);
  2083. int err;
  2084. software_reset(ohci);
  2085. free_irq(dev->irq, ohci);
  2086. err = pci_save_state(dev);
  2087. if (err) {
  2088. fw_error("pci_save_state failed\n");
  2089. return err;
  2090. }
  2091. err = pci_set_power_state(dev, pci_choose_state(dev, state));
  2092. if (err)
  2093. fw_error("pci_set_power_state failed with %d\n", err);
  2094. ohci_pmac_off(dev);
  2095. return 0;
  2096. }
  2097. static int pci_resume(struct pci_dev *dev)
  2098. {
  2099. struct fw_ohci *ohci = pci_get_drvdata(dev);
  2100. int err;
  2101. ohci_pmac_on(dev);
  2102. pci_set_power_state(dev, PCI_D0);
  2103. pci_restore_state(dev);
  2104. err = pci_enable_device(dev);
  2105. if (err) {
  2106. fw_error("pci_enable_device failed\n");
  2107. return err;
  2108. }
  2109. return ohci_enable(&ohci->card, NULL, 0);
  2110. }
  2111. #endif
  2112. static struct pci_device_id pci_table[] = {
  2113. { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
  2114. { }
  2115. };
  2116. MODULE_DEVICE_TABLE(pci, pci_table);
  2117. static struct pci_driver fw_ohci_pci_driver = {
  2118. .name = ohci_driver_name,
  2119. .id_table = pci_table,
  2120. .probe = pci_probe,
  2121. .remove = pci_remove,
  2122. #ifdef CONFIG_PM
  2123. .resume = pci_resume,
  2124. .suspend = pci_suspend,
  2125. #endif
  2126. };
  2127. MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
  2128. MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
  2129. MODULE_LICENSE("GPL");
  2130. /* Provide a module alias so root-on-sbp2 initrds don't break. */
  2131. #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
  2132. MODULE_ALIAS("ohci1394");
  2133. #endif
  2134. static int __init fw_ohci_init(void)
  2135. {
  2136. return pci_register_driver(&fw_ohci_pci_driver);
  2137. }
  2138. static void __exit fw_ohci_cleanup(void)
  2139. {
  2140. pci_unregister_driver(&fw_ohci_pci_driver);
  2141. }
  2142. module_init(fw_ohci_init);
  2143. module_exit(fw_ohci_cleanup);