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imx6dl.dtsi

imx6dl.dtsi 8.1 KB
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  1. 

  2. /*
    3. 

  3.  * Copyright 2013 Freescale Semiconductor, Inc.
    4. 

  4.  *
    5. 

  5.  * This program is free software; you can redistribute it and/or modify
    6. 

  6.  * it under the terms of the GNU General Public License version 2 as
    7. 

  7.  * published by the Free Software Foundation.
    8. 

  8.  *
    9. 

  9.  */
    10. 

  10. 

  11. #include "imx6qdl.dtsi"
    12. 

  12. #include "imx6dl-pinfunc.h"
    13. 

  13. 

  14. / {
    15. 

  15. 	cpus {
    16. 

  16. 		#address-cells = <1>;
    17. 

  17. 		#size-cells = <0>;
    18. 

  18. 

  19. 		cpu@0 {
    20. 

  20. 			compatible = "arm,cortex-a9";
    21. 

  21. 			reg = <0>;
    22. 

  22. 			next-level-cache = <&L2>;
    23. 

  23. 		};
    24. 

  24. 

  25. 		cpu@1 {
    26. 

  26. 			compatible = "arm,cortex-a9";
    27. 

  27. 			reg = <1>;
    28. 

  28. 			next-level-cache = <&L2>;
    29. 

  29. 		};
    30. 

  30. 	};
    31. 

  31. 

  32. 	soc {
    33. 

  33. 		aips1: aips-bus@02000000 {
    34. 

  34. 			iomuxc: iomuxc@020e0000 {
    35. 

  35. 				compatible = "fsl,imx6dl-iomuxc";
    36. 

  36. 				reg = <0x020e0000 0x4000>;
    37. 

  37. 

  38. 				ecspi1 {
    39. 

  39. 					pinctrl_ecspi1_1: ecspi1grp-1 {
    40. 

  40. 						fsl,pins = <
    41. 

  41. 							MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
    42. 

  42. 							MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
    43. 

  43. 							MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
    44. 

  44. 						>;
    45. 

  45. 					};
    46. 

  46. 				};
    47. 

  47. 

  48. 				enet {
    49. 

  49. 					pinctrl_enet_1: enetgrp-1 {
    50. 

  50. 						fsl,pins = <
    51. 

  51. 							MX6DL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
    52. 

  52. 							MX6DL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
    53. 

  53. 							MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
    54. 

  54. 							MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
    55. 

  55. 							MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
    56. 

  56. 							MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
    57. 

  57. 							MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
    58. 

  58. 							MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
    59. 

  59. 							MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
    60. 

  60. 							MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
    61. 

  61. 							MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
    62. 

  62. 							MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
    63. 

  63. 							MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
    64. 

  64. 							MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
    65. 

  65. 							MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
    66. 

  66. 							MX6DL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
    67. 

  67. 						>;
    68. 

  68. 					};
    69. 

  69. 

  70. 					pinctrl_enet_2: enetgrp-2 {
    71. 

  71. 						fsl,pins = <
    72. 

  72. 							MX6DL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
    73. 

  73. 							MX6DL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
    74. 

  74. 							MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
    75. 

  75. 							MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
    76. 

  76. 							MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
    77. 

  77. 							MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
    78. 

  78. 							MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
    79. 

  79. 							MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
    80. 

  80. 							MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
    81. 

  81. 							MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
    82. 

  82. 							MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
    83. 

  83. 							MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
    84. 

  84. 							MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
    85. 

  85. 							MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
    86. 

  86. 							MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
    87. 

  87. 						>;
    88. 

  88. 					};
    89. 

  89. 				};
    90. 

  90. 

  91. 				gpmi-nand {
    92. 

  92. 					pinctrl_gpmi_nand_1: gpmi-nand-1 {
    93. 

  93. 						fsl,pins = <
    94. 

  94. 							MX6DL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
    95. 

  95. 							MX6DL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
    96. 

  96. 							MX6DL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
    97. 

  97. 							MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
    98. 

  98. 							MX6DL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
    99. 

  99. 							MX6DL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
    100. 

  100. 							MX6DL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
    101. 

  101. 							MX6DL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
    102. 

  102. 							MX6DL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
    103. 

  103. 							MX6DL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
    104. 

  104. 							MX6DL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
    105. 

  105. 							MX6DL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
    106. 

  106. 							MX6DL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
    107. 

  107. 							MX6DL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
    108. 

  108. 							MX6DL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
    109. 

  109. 							MX6DL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
    110. 

  110. 							MX6DL_PAD_SD4_DAT0__NAND_DQS      0x00b1
    111. 

  111. 						>;
    112. 

  112. 					};
    113. 

  113. 				};
    114. 

  114. 

  115. 				uart1 {
    116. 

  116. 					pinctrl_uart1_1: uart1grp-1 {
    117. 

  117. 						fsl,pins = <
    118. 

  118. 							MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
    119. 

  119. 							MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
    120. 

  120. 						>;
    121. 

  121. 					};
    122. 

  122. 				};
    123. 

  123. 

  124. 				uart4 {
    125. 

  125. 					pinctrl_uart4_1: uart4grp-1 {
    126. 

  126. 						fsl,pins = <
    127. 

  127. 							MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
    128. 

  128. 							MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
    129. 

  129. 						>;
    130. 

  130. 					};
    131. 

  131. 				};
    132. 

  132. 

  133. 				usbotg {
    134. 

  134. 					pinctrl_usbotg_2: usbotggrp-2 {
    135. 

  135. 						fsl,pins = <
    136. 

  136. 							MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
    137. 

  137. 						>;
    138. 

  138. 					};
    139. 

  139. 				};
    140. 

  140. 

  141. 				usdhc2 {
    142. 

  142. 					pinctrl_usdhc2_1: usdhc2grp-1 {
    143. 

  143. 						fsl,pins = <
    144. 

  144. 							MX6DL_PAD_SD2_CMD__SD2_CMD    0x17059
    145. 

  145. 							MX6DL_PAD_SD2_CLK__SD2_CLK    0x10059
    146. 

  146. 							MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
    147. 

  147. 							MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
    148. 

  148. 							MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
    149. 

  149. 							MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
    150. 

  150. 							MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
    151. 

  151. 							MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
    152. 

  152. 							MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
    153. 

  153. 							MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
    154. 

  154. 						>;
    155. 

  155. 					};
    156. 

  156. 				};
    157. 

  157. 

  158. 				usdhc3 {
    159. 

  159. 					pinctrl_usdhc3_1: usdhc3grp-1 {
    160. 

  160. 						fsl,pins = <
    161. 

  161. 							MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
    162. 

  162. 							MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
    163. 

  163. 							MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
    164. 

  164. 							MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
    165. 

  165. 							MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
    166. 

  166. 							MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
    167. 

  167. 							MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
    168. 

  168. 							MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
    169. 

  169. 							MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
    170. 

  170. 							MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
    171. 

  171. 						>;
    172. 

  172. 					};
    173. 

  173. 

  174. 					pinctrl_usdhc3_2: usdhc3grp_2 {
    175. 

  175. 						fsl,pins = <
    176. 

  176. 							MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
    177. 

  177. 							MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
    178. 

  178. 							MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
    179. 

  179. 							MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
    180. 

  180. 							MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
    181. 

  181. 							MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
    182. 

  182. 						>;
    183. 

  183. 					};
    184. 

  184. 				};
    185. 

  185. 

  186. 				weim {
    187. 

  187. 					pinctrl_weim_cs0_1: weim_cs0grp-1 {
    188. 

  188. 						fsl,pins = <
    189. 

  189. 							MX6DL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
    190. 

  190. 						>;
    191. 

  191. 					};
    192. 

  192. 

  193. 					pinctrl_weim_nor_1: weim_norgrp-1 {
    194. 

  194. 						fsl,pins = <
    195. 

  195. 							MX6DL_PAD_EIM_OE__EIM_OE_B     0xb0b1
    196. 

  196. 							MX6DL_PAD_EIM_RW__EIM_RW       0xb0b1
    197. 

  197. 							MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
    198. 

  198. 							/* data */
    199. 

  199. 							MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
    200. 

  200. 							MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
    201. 

  201. 							MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
    202. 

  202. 							MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
    203. 

  203. 							MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
    204. 

  204. 							MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
    205. 

  205. 							MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
    206. 

  206. 							MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
    207. 

  207. 							MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
    208. 

  208. 							MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
    209. 

  209. 							MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
    210. 

  210. 							MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
    211. 

  211. 							MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
    212. 

  212. 							MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
    213. 

  213. 							MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
    214. 

  214. 							MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
    215. 

  215. 							/* address */
    216. 

  216. 							MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
    217. 

  217. 							MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
    218. 

  218. 							MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
    219. 

  219. 							MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
    220. 

  220. 							MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
    221. 

  221. 							MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
    222. 

  222. 							MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
    223. 

  223. 							MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
    224. 

  224. 							MX6DL_PAD_EIM_DA15__EIM_AD15  0xb0b1
    225. 

  225. 							MX6DL_PAD_EIM_DA14__EIM_AD14  0xb0b1
    226. 

  226. 							MX6DL_PAD_EIM_DA13__EIM_AD13  0xb0b1
    227. 

  227. 							MX6DL_PAD_EIM_DA12__EIM_AD12  0xb0b1
    228. 

  228. 							MX6DL_PAD_EIM_DA11__EIM_AD11  0xb0b1
    229. 

  229. 							MX6DL_PAD_EIM_DA10__EIM_AD10  0xb0b1
    230. 

  230. 							MX6DL_PAD_EIM_DA9__EIM_AD09   0xb0b1
    231. 

  231. 							MX6DL_PAD_EIM_DA8__EIM_AD08   0xb0b1
    232. 

  232. 							MX6DL_PAD_EIM_DA7__EIM_AD07   0xb0b1
    233. 

  233. 							MX6DL_PAD_EIM_DA6__EIM_AD06   0xb0b1
    234. 

  234. 							MX6DL_PAD_EIM_DA5__EIM_AD05   0xb0b1
    235. 

  235. 							MX6DL_PAD_EIM_DA4__EIM_AD04   0xb0b1
    236. 

  236. 							MX6DL_PAD_EIM_DA3__EIM_AD03   0xb0b1
    237. 

  237. 							MX6DL_PAD_EIM_DA2__EIM_AD02   0xb0b1
    238. 

  238. 							MX6DL_PAD_EIM_DA1__EIM_AD01   0xb0b1
    239. 

  239. 							MX6DL_PAD_EIM_DA0__EIM_AD00   0xb0b1
    240. 

  240. 						>;
    241. 

  241. 					};
    242. 

  242. 

  243. 				};
    244. 

  244. 

  245. 			};
    246. 

  246. 

  247. 			pxp: pxp@020f0000 {
    248. 

  248. 				reg = <0x020f0000 0x4000>;
    249. 

  249. 				interrupts = <0 98 0x04>;
    250. 

  250. 			};
    251. 

  251. 

  252. 			epdc: epdc@020f4000 {
    253. 

  253. 				reg = <0x020f4000 0x4000>;
    254. 

  254. 				interrupts = <0 97 0x04>;
    255. 

  255. 			};
    256. 

  256. 

  257. 			lcdif: lcdif@020f8000 {
    258. 

  258. 				reg = <0x020f8000 0x4000>;
    259. 

  259. 				interrupts = <0 39 0x04>;
    260. 

  260. 			};
    261. 

  261. 		};
    262. 

  262. 

  263. 		aips2: aips-bus@02100000 {
    264. 

  264. 			i2c4: i2c@021f8000 {
    265. 

  265. 				#address-cells = <1>;
    266. 

  266. 				#size-cells = <0>;
    267. 

  267. 				compatible = "fsl,imx1-i2c";
    268. 

  268. 				reg = <0x021f8000 0x4000>;
    269. 

  269. 				interrupts = <0 35 0x04>;
    270. 

  270. 				status = "disabled";
    271. 

  271. 			};
    272. 

  272. 		};
    273. 

  273. 	};
    274. 

  274. };
    275.