twl4030.c 69 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl.h>
  29. #include <linux/slab.h>
  30. #include <sound/core.h>
  31. #include <sound/pcm.h>
  32. #include <sound/pcm_params.h>
  33. #include <sound/soc.h>
  34. #include <sound/soc-dapm.h>
  35. #include <sound/initval.h>
  36. #include <sound/tlv.h>
  37. #include "twl4030.h"
  38. /*
  39. * twl4030 register cache & default register settings
  40. */
  41. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  42. 0x00, /* this register not used */
  43. 0x91, /* REG_CODEC_MODE (0x1) */
  44. 0xc3, /* REG_OPTION (0x2) */
  45. 0x00, /* REG_UNKNOWN (0x3) */
  46. 0x00, /* REG_MICBIAS_CTL (0x4) */
  47. 0x20, /* REG_ANAMICL (0x5) */
  48. 0x00, /* REG_ANAMICR (0x6) */
  49. 0x00, /* REG_AVADC_CTL (0x7) */
  50. 0x00, /* REG_ADCMICSEL (0x8) */
  51. 0x00, /* REG_DIGMIXING (0x9) */
  52. 0x0c, /* REG_ATXL1PGA (0xA) */
  53. 0x0c, /* REG_ATXR1PGA (0xB) */
  54. 0x00, /* REG_AVTXL2PGA (0xC) */
  55. 0x00, /* REG_AVTXR2PGA (0xD) */
  56. 0x00, /* REG_AUDIO_IF (0xE) */
  57. 0x00, /* REG_VOICE_IF (0xF) */
  58. 0x00, /* REG_ARXR1PGA (0x10) */
  59. 0x00, /* REG_ARXL1PGA (0x11) */
  60. 0x6c, /* REG_ARXR2PGA (0x12) */
  61. 0x6c, /* REG_ARXL2PGA (0x13) */
  62. 0x00, /* REG_VRXPGA (0x14) */
  63. 0x00, /* REG_VSTPGA (0x15) */
  64. 0x00, /* REG_VRX2ARXPGA (0x16) */
  65. 0x00, /* REG_AVDAC_CTL (0x17) */
  66. 0x00, /* REG_ARX2VTXPGA (0x18) */
  67. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  68. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  69. 0x4a, /* REG_ARXL2_APGA_CTL (0x1B) */
  70. 0x4a, /* REG_ARXR2_APGA_CTL (0x1C) */
  71. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  72. 0x00, /* REG_BT_IF (0x1E) */
  73. 0x00, /* REG_BTPGA (0x1F) */
  74. 0x00, /* REG_BTSTPGA (0x20) */
  75. 0x00, /* REG_EAR_CTL (0x21) */
  76. 0x00, /* REG_HS_SEL (0x22) */
  77. 0x00, /* REG_HS_GAIN_SET (0x23) */
  78. 0x00, /* REG_HS_POPN_SET (0x24) */
  79. 0x00, /* REG_PREDL_CTL (0x25) */
  80. 0x00, /* REG_PREDR_CTL (0x26) */
  81. 0x00, /* REG_PRECKL_CTL (0x27) */
  82. 0x00, /* REG_PRECKR_CTL (0x28) */
  83. 0x00, /* REG_HFL_CTL (0x29) */
  84. 0x00, /* REG_HFR_CTL (0x2A) */
  85. 0x00, /* REG_ALC_CTL (0x2B) */
  86. 0x00, /* REG_ALC_SET1 (0x2C) */
  87. 0x00, /* REG_ALC_SET2 (0x2D) */
  88. 0x00, /* REG_BOOST_CTL (0x2E) */
  89. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  90. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  91. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  92. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  93. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  94. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  95. 0x00, /* REG_DTMF_TONOFF (0x35) */
  96. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  99. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  100. 0x06, /* REG_APLL_CTL (0x3A) */
  101. 0x00, /* REG_DTMF_CTL (0x3B) */
  102. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  103. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  104. 0x00, /* REG_MISC_SET_1 (0x3E) */
  105. 0x00, /* REG_PCMBTMUX (0x3F) */
  106. 0x00, /* not used (0x40) */
  107. 0x00, /* not used (0x41) */
  108. 0x00, /* not used (0x42) */
  109. 0x00, /* REG_RX_PATH_SEL (0x43) */
  110. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  111. 0x00, /* REG_VIBRA_CTL (0x45) */
  112. 0x00, /* REG_VIBRA_SET (0x46) */
  113. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  114. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  115. 0x00, /* REG_MISC_SET_2 (0x49) */
  116. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  117. };
  118. /* codec private data */
  119. struct twl4030_priv {
  120. struct snd_soc_codec codec;
  121. unsigned int codec_powered;
  122. unsigned int apll_enabled;
  123. struct snd_pcm_substream *master_substream;
  124. struct snd_pcm_substream *slave_substream;
  125. unsigned int configured;
  126. unsigned int rate;
  127. unsigned int sample_bits;
  128. unsigned int channels;
  129. unsigned int sysclk;
  130. /* Headset output state handling */
  131. unsigned int hsl_enabled;
  132. unsigned int hsr_enabled;
  133. };
  134. /*
  135. * read twl4030 register cache
  136. */
  137. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  138. unsigned int reg)
  139. {
  140. u8 *cache = codec->reg_cache;
  141. if (reg >= TWL4030_CACHEREGNUM)
  142. return -EIO;
  143. return cache[reg];
  144. }
  145. /*
  146. * write twl4030 register cache
  147. */
  148. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  149. u8 reg, u8 value)
  150. {
  151. u8 *cache = codec->reg_cache;
  152. if (reg >= TWL4030_CACHEREGNUM)
  153. return;
  154. cache[reg] = value;
  155. }
  156. /*
  157. * write to the twl4030 register space
  158. */
  159. static int twl4030_write(struct snd_soc_codec *codec,
  160. unsigned int reg, unsigned int value)
  161. {
  162. twl4030_write_reg_cache(codec, reg, value);
  163. if (likely(reg < TWL4030_REG_SW_SHADOW))
  164. return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
  165. reg);
  166. else
  167. return 0;
  168. }
  169. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  170. {
  171. struct twl4030_priv *twl4030 = codec->private_data;
  172. int mode;
  173. if (enable == twl4030->codec_powered)
  174. return;
  175. if (enable)
  176. mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
  177. else
  178. mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
  179. if (mode >= 0) {
  180. twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
  181. twl4030->codec_powered = enable;
  182. }
  183. /* REVISIT: this delay is present in TI sample drivers */
  184. /* but there seems to be no TRM requirement for it */
  185. udelay(10);
  186. }
  187. static void twl4030_init_chip(struct snd_soc_codec *codec)
  188. {
  189. u8 *cache = codec->reg_cache;
  190. int i;
  191. /* clear CODECPDZ prior to setting register defaults */
  192. twl4030_codec_enable(codec, 0);
  193. /* set all audio section registers to reasonable defaults */
  194. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  195. if (i != TWL4030_REG_APLL_CTL)
  196. twl4030_write(codec, i, cache[i]);
  197. }
  198. static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
  199. {
  200. struct twl4030_priv *twl4030 = codec->private_data;
  201. int status;
  202. if (enable == twl4030->apll_enabled)
  203. return;
  204. if (enable)
  205. /* Enable PLL */
  206. status = twl4030_codec_enable_resource(TWL4030_CODEC_RES_APLL);
  207. else
  208. /* Disable PLL */
  209. status = twl4030_codec_disable_resource(TWL4030_CODEC_RES_APLL);
  210. if (status >= 0)
  211. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
  212. twl4030->apll_enabled = enable;
  213. }
  214. static void twl4030_power_up(struct snd_soc_codec *codec)
  215. {
  216. struct twl4030_priv *twl4030 = codec->private_data;
  217. u8 anamicl, regmisc1, byte;
  218. int i = 0;
  219. if (twl4030->codec_powered)
  220. return;
  221. /* set CODECPDZ to turn on codec */
  222. twl4030_codec_enable(codec, 1);
  223. /* initiate offset cancellation */
  224. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  225. twl4030_write(codec, TWL4030_REG_ANAMICL,
  226. anamicl | TWL4030_CNCL_OFFSET_START);
  227. /* wait for offset cancellation to complete */
  228. do {
  229. /* this takes a little while, so don't slam i2c */
  230. udelay(2000);
  231. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  232. TWL4030_REG_ANAMICL);
  233. } while ((i++ < 100) &&
  234. ((byte & TWL4030_CNCL_OFFSET_START) ==
  235. TWL4030_CNCL_OFFSET_START));
  236. /* Make sure that the reg_cache has the same value as the HW */
  237. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  238. /* anti-pop when changing analog gain */
  239. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  240. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  241. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  242. /* toggle CODECPDZ as per TRM */
  243. twl4030_codec_enable(codec, 0);
  244. twl4030_codec_enable(codec, 1);
  245. }
  246. /*
  247. * Unconditional power down
  248. */
  249. static void twl4030_power_down(struct snd_soc_codec *codec)
  250. {
  251. /* power down */
  252. twl4030_codec_enable(codec, 0);
  253. }
  254. /* Earpiece */
  255. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  256. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  257. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  258. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  259. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  260. };
  261. /* PreDrive Left */
  262. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  263. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  264. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  265. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  266. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  267. };
  268. /* PreDrive Right */
  269. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  270. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  271. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  272. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  273. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  274. };
  275. /* Headset Left */
  276. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  277. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  278. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  279. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  280. };
  281. /* Headset Right */
  282. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  283. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  284. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  285. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  286. };
  287. /* Carkit Left */
  288. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  289. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  290. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  291. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  292. };
  293. /* Carkit Right */
  294. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  295. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  296. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  297. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  298. };
  299. /* Handsfree Left */
  300. static const char *twl4030_handsfreel_texts[] =
  301. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  302. static const struct soc_enum twl4030_handsfreel_enum =
  303. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  304. ARRAY_SIZE(twl4030_handsfreel_texts),
  305. twl4030_handsfreel_texts);
  306. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  307. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  308. /* Handsfree Left virtual mute */
  309. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  310. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  311. /* Handsfree Right */
  312. static const char *twl4030_handsfreer_texts[] =
  313. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  314. static const struct soc_enum twl4030_handsfreer_enum =
  315. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  316. ARRAY_SIZE(twl4030_handsfreer_texts),
  317. twl4030_handsfreer_texts);
  318. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  319. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  320. /* Handsfree Right virtual mute */
  321. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  322. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  323. /* Vibra */
  324. /* Vibra audio path selection */
  325. static const char *twl4030_vibra_texts[] =
  326. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  327. static const struct soc_enum twl4030_vibra_enum =
  328. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  329. ARRAY_SIZE(twl4030_vibra_texts),
  330. twl4030_vibra_texts);
  331. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  332. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  333. /* Vibra path selection: local vibrator (PWM) or audio driven */
  334. static const char *twl4030_vibrapath_texts[] =
  335. {"Local vibrator", "Audio"};
  336. static const struct soc_enum twl4030_vibrapath_enum =
  337. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  338. ARRAY_SIZE(twl4030_vibrapath_texts),
  339. twl4030_vibrapath_texts);
  340. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  341. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  342. /* Left analog microphone selection */
  343. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  344. SOC_DAPM_SINGLE("Main Mic Capture Switch",
  345. TWL4030_REG_ANAMICL, 0, 1, 0),
  346. SOC_DAPM_SINGLE("Headset Mic Capture Switch",
  347. TWL4030_REG_ANAMICL, 1, 1, 0),
  348. SOC_DAPM_SINGLE("AUXL Capture Switch",
  349. TWL4030_REG_ANAMICL, 2, 1, 0),
  350. SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
  351. TWL4030_REG_ANAMICL, 3, 1, 0),
  352. };
  353. /* Right analog microphone selection */
  354. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  355. SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
  356. SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
  357. };
  358. /* TX1 L/R Analog/Digital microphone selection */
  359. static const char *twl4030_micpathtx1_texts[] =
  360. {"Analog", "Digimic0"};
  361. static const struct soc_enum twl4030_micpathtx1_enum =
  362. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  363. ARRAY_SIZE(twl4030_micpathtx1_texts),
  364. twl4030_micpathtx1_texts);
  365. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  366. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  367. /* TX2 L/R Analog/Digital microphone selection */
  368. static const char *twl4030_micpathtx2_texts[] =
  369. {"Analog", "Digimic1"};
  370. static const struct soc_enum twl4030_micpathtx2_enum =
  371. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  372. ARRAY_SIZE(twl4030_micpathtx2_texts),
  373. twl4030_micpathtx2_texts);
  374. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  375. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  376. /* Analog bypass for AudioR1 */
  377. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  378. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  379. /* Analog bypass for AudioL1 */
  380. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  381. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  382. /* Analog bypass for AudioR2 */
  383. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  384. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  385. /* Analog bypass for AudioL2 */
  386. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  387. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  388. /* Analog bypass for Voice */
  389. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  390. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  391. /* Digital bypass gain, 0 mutes the bypass */
  392. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  393. TLV_DB_RANGE_HEAD(2),
  394. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  395. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  396. };
  397. /* Digital bypass left (TX1L -> RX2L) */
  398. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  399. SOC_DAPM_SINGLE_TLV("Volume",
  400. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  401. twl4030_dapm_dbypass_tlv);
  402. /* Digital bypass right (TX1R -> RX2R) */
  403. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  404. SOC_DAPM_SINGLE_TLV("Volume",
  405. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  406. twl4030_dapm_dbypass_tlv);
  407. /*
  408. * Voice Sidetone GAIN volume control:
  409. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  410. */
  411. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  412. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  413. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  414. SOC_DAPM_SINGLE_TLV("Volume",
  415. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  416. twl4030_dapm_dbypassv_tlv);
  417. static int micpath_event(struct snd_soc_dapm_widget *w,
  418. struct snd_kcontrol *kcontrol, int event)
  419. {
  420. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  421. unsigned char adcmicsel, micbias_ctl;
  422. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  423. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  424. /* Prepare the bits for the given TX path:
  425. * shift_l == 0: TX1 microphone path
  426. * shift_l == 2: TX2 microphone path */
  427. if (e->shift_l) {
  428. /* TX2 microphone path */
  429. if (adcmicsel & TWL4030_TX2IN_SEL)
  430. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  431. else
  432. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  433. } else {
  434. /* TX1 microphone path */
  435. if (adcmicsel & TWL4030_TX1IN_SEL)
  436. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  437. else
  438. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  439. }
  440. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  441. return 0;
  442. }
  443. /*
  444. * Output PGA builder:
  445. * Handle the muting and unmuting of the given output (turning off the
  446. * amplifier associated with the output pin)
  447. * On mute bypass the reg_cache and mute the volume
  448. * On unmute: restore the register content
  449. * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
  450. */
  451. #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
  452. static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
  453. struct snd_kcontrol *kcontrol, int event) \
  454. { \
  455. u8 reg_val; \
  456. \
  457. switch (event) { \
  458. case SND_SOC_DAPM_POST_PMU: \
  459. twl4030_write(w->codec, reg, \
  460. twl4030_read_reg_cache(w->codec, reg)); \
  461. break; \
  462. case SND_SOC_DAPM_POST_PMD: \
  463. reg_val = twl4030_read_reg_cache(w->codec, reg); \
  464. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
  465. reg_val & (~mask), \
  466. reg); \
  467. break; \
  468. } \
  469. return 0; \
  470. }
  471. TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
  472. TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
  473. TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
  474. TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
  475. TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
  476. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  477. {
  478. unsigned char hs_ctl;
  479. hs_ctl = twl4030_read_reg_cache(codec, reg);
  480. if (ramp) {
  481. /* HF ramp-up */
  482. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  483. twl4030_write(codec, reg, hs_ctl);
  484. udelay(10);
  485. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  486. twl4030_write(codec, reg, hs_ctl);
  487. udelay(40);
  488. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  489. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  490. twl4030_write(codec, reg, hs_ctl);
  491. } else {
  492. /* HF ramp-down */
  493. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  494. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  495. twl4030_write(codec, reg, hs_ctl);
  496. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  497. twl4030_write(codec, reg, hs_ctl);
  498. udelay(40);
  499. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  500. twl4030_write(codec, reg, hs_ctl);
  501. }
  502. }
  503. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  504. struct snd_kcontrol *kcontrol, int event)
  505. {
  506. switch (event) {
  507. case SND_SOC_DAPM_POST_PMU:
  508. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  509. break;
  510. case SND_SOC_DAPM_POST_PMD:
  511. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  512. break;
  513. }
  514. return 0;
  515. }
  516. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  517. struct snd_kcontrol *kcontrol, int event)
  518. {
  519. switch (event) {
  520. case SND_SOC_DAPM_POST_PMU:
  521. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  522. break;
  523. case SND_SOC_DAPM_POST_PMD:
  524. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  525. break;
  526. }
  527. return 0;
  528. }
  529. static int vibramux_event(struct snd_soc_dapm_widget *w,
  530. struct snd_kcontrol *kcontrol, int event)
  531. {
  532. twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
  533. return 0;
  534. }
  535. static int apll_event(struct snd_soc_dapm_widget *w,
  536. struct snd_kcontrol *kcontrol, int event)
  537. {
  538. switch (event) {
  539. case SND_SOC_DAPM_PRE_PMU:
  540. twl4030_apll_enable(w->codec, 1);
  541. break;
  542. case SND_SOC_DAPM_POST_PMD:
  543. twl4030_apll_enable(w->codec, 0);
  544. break;
  545. }
  546. return 0;
  547. }
  548. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  549. {
  550. struct snd_soc_device *socdev = codec->socdev;
  551. struct twl4030_setup_data *setup = socdev->codec_data;
  552. unsigned char hs_gain, hs_pop;
  553. struct twl4030_priv *twl4030 = codec->private_data;
  554. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  555. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  556. 8388608, 16777216, 33554432, 67108864};
  557. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  558. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  559. /* Enable external mute control, this dramatically reduces
  560. * the pop-noise */
  561. if (setup && setup->hs_extmute) {
  562. if (setup->set_hs_extmute) {
  563. setup->set_hs_extmute(1);
  564. } else {
  565. hs_pop |= TWL4030_EXTMUTE;
  566. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  567. }
  568. }
  569. if (ramp) {
  570. /* Headset ramp-up according to the TRM */
  571. hs_pop |= TWL4030_VMID_EN;
  572. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  573. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  574. hs_pop |= TWL4030_RAMP_EN;
  575. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  576. /* Wait ramp delay time + 1, so the VMID can settle */
  577. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  578. twl4030->sysclk) + 1);
  579. } else {
  580. /* Headset ramp-down _not_ according to
  581. * the TRM, but in a way that it is working */
  582. hs_pop &= ~TWL4030_RAMP_EN;
  583. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  584. /* Wait ramp delay time + 1, so the VMID can settle */
  585. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  586. twl4030->sysclk) + 1);
  587. /* Bypass the reg_cache to mute the headset */
  588. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  589. hs_gain & (~0x0f),
  590. TWL4030_REG_HS_GAIN_SET);
  591. hs_pop &= ~TWL4030_VMID_EN;
  592. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  593. }
  594. /* Disable external mute */
  595. if (setup && setup->hs_extmute) {
  596. if (setup->set_hs_extmute) {
  597. setup->set_hs_extmute(0);
  598. } else {
  599. hs_pop &= ~TWL4030_EXTMUTE;
  600. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  601. }
  602. }
  603. }
  604. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  605. struct snd_kcontrol *kcontrol, int event)
  606. {
  607. struct twl4030_priv *twl4030 = w->codec->private_data;
  608. switch (event) {
  609. case SND_SOC_DAPM_POST_PMU:
  610. /* Do the ramp-up only once */
  611. if (!twl4030->hsr_enabled)
  612. headset_ramp(w->codec, 1);
  613. twl4030->hsl_enabled = 1;
  614. break;
  615. case SND_SOC_DAPM_POST_PMD:
  616. /* Do the ramp-down only if both headsetL/R is disabled */
  617. if (!twl4030->hsr_enabled)
  618. headset_ramp(w->codec, 0);
  619. twl4030->hsl_enabled = 0;
  620. break;
  621. }
  622. return 0;
  623. }
  624. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  625. struct snd_kcontrol *kcontrol, int event)
  626. {
  627. struct twl4030_priv *twl4030 = w->codec->private_data;
  628. switch (event) {
  629. case SND_SOC_DAPM_POST_PMU:
  630. /* Do the ramp-up only once */
  631. if (!twl4030->hsl_enabled)
  632. headset_ramp(w->codec, 1);
  633. twl4030->hsr_enabled = 1;
  634. break;
  635. case SND_SOC_DAPM_POST_PMD:
  636. /* Do the ramp-down only if both headsetL/R is disabled */
  637. if (!twl4030->hsl_enabled)
  638. headset_ramp(w->codec, 0);
  639. twl4030->hsr_enabled = 0;
  640. break;
  641. }
  642. return 0;
  643. }
  644. /*
  645. * Some of the gain controls in TWL (mostly those which are associated with
  646. * the outputs) are implemented in an interesting way:
  647. * 0x0 : Power down (mute)
  648. * 0x1 : 6dB
  649. * 0x2 : 0 dB
  650. * 0x3 : -6 dB
  651. * Inverting not going to help with these.
  652. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  653. */
  654. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  655. xinvert, tlv_array) \
  656. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  657. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  658. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  659. .tlv.p = (tlv_array), \
  660. .info = snd_soc_info_volsw, \
  661. .get = snd_soc_get_volsw_twl4030, \
  662. .put = snd_soc_put_volsw_twl4030, \
  663. .private_value = (unsigned long)&(struct soc_mixer_control) \
  664. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  665. .max = xmax, .invert = xinvert} }
  666. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  667. xinvert, tlv_array) \
  668. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  669. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  670. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  671. .tlv.p = (tlv_array), \
  672. .info = snd_soc_info_volsw_2r, \
  673. .get = snd_soc_get_volsw_r2_twl4030,\
  674. .put = snd_soc_put_volsw_r2_twl4030, \
  675. .private_value = (unsigned long)&(struct soc_mixer_control) \
  676. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  677. .rshift = xshift, .max = xmax, .invert = xinvert} }
  678. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  679. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  680. xinvert, tlv_array)
  681. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  682. struct snd_ctl_elem_value *ucontrol)
  683. {
  684. struct soc_mixer_control *mc =
  685. (struct soc_mixer_control *)kcontrol->private_value;
  686. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  687. unsigned int reg = mc->reg;
  688. unsigned int shift = mc->shift;
  689. unsigned int rshift = mc->rshift;
  690. int max = mc->max;
  691. int mask = (1 << fls(max)) - 1;
  692. ucontrol->value.integer.value[0] =
  693. (snd_soc_read(codec, reg) >> shift) & mask;
  694. if (ucontrol->value.integer.value[0])
  695. ucontrol->value.integer.value[0] =
  696. max + 1 - ucontrol->value.integer.value[0];
  697. if (shift != rshift) {
  698. ucontrol->value.integer.value[1] =
  699. (snd_soc_read(codec, reg) >> rshift) & mask;
  700. if (ucontrol->value.integer.value[1])
  701. ucontrol->value.integer.value[1] =
  702. max + 1 - ucontrol->value.integer.value[1];
  703. }
  704. return 0;
  705. }
  706. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  707. struct snd_ctl_elem_value *ucontrol)
  708. {
  709. struct soc_mixer_control *mc =
  710. (struct soc_mixer_control *)kcontrol->private_value;
  711. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  712. unsigned int reg = mc->reg;
  713. unsigned int shift = mc->shift;
  714. unsigned int rshift = mc->rshift;
  715. int max = mc->max;
  716. int mask = (1 << fls(max)) - 1;
  717. unsigned short val, val2, val_mask;
  718. val = (ucontrol->value.integer.value[0] & mask);
  719. val_mask = mask << shift;
  720. if (val)
  721. val = max + 1 - val;
  722. val = val << shift;
  723. if (shift != rshift) {
  724. val2 = (ucontrol->value.integer.value[1] & mask);
  725. val_mask |= mask << rshift;
  726. if (val2)
  727. val2 = max + 1 - val2;
  728. val |= val2 << rshift;
  729. }
  730. return snd_soc_update_bits(codec, reg, val_mask, val);
  731. }
  732. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  733. struct snd_ctl_elem_value *ucontrol)
  734. {
  735. struct soc_mixer_control *mc =
  736. (struct soc_mixer_control *)kcontrol->private_value;
  737. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  738. unsigned int reg = mc->reg;
  739. unsigned int reg2 = mc->rreg;
  740. unsigned int shift = mc->shift;
  741. int max = mc->max;
  742. int mask = (1<<fls(max))-1;
  743. ucontrol->value.integer.value[0] =
  744. (snd_soc_read(codec, reg) >> shift) & mask;
  745. ucontrol->value.integer.value[1] =
  746. (snd_soc_read(codec, reg2) >> shift) & mask;
  747. if (ucontrol->value.integer.value[0])
  748. ucontrol->value.integer.value[0] =
  749. max + 1 - ucontrol->value.integer.value[0];
  750. if (ucontrol->value.integer.value[1])
  751. ucontrol->value.integer.value[1] =
  752. max + 1 - ucontrol->value.integer.value[1];
  753. return 0;
  754. }
  755. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  756. struct snd_ctl_elem_value *ucontrol)
  757. {
  758. struct soc_mixer_control *mc =
  759. (struct soc_mixer_control *)kcontrol->private_value;
  760. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  761. unsigned int reg = mc->reg;
  762. unsigned int reg2 = mc->rreg;
  763. unsigned int shift = mc->shift;
  764. int max = mc->max;
  765. int mask = (1 << fls(max)) - 1;
  766. int err;
  767. unsigned short val, val2, val_mask;
  768. val_mask = mask << shift;
  769. val = (ucontrol->value.integer.value[0] & mask);
  770. val2 = (ucontrol->value.integer.value[1] & mask);
  771. if (val)
  772. val = max + 1 - val;
  773. if (val2)
  774. val2 = max + 1 - val2;
  775. val = val << shift;
  776. val2 = val2 << shift;
  777. err = snd_soc_update_bits(codec, reg, val_mask, val);
  778. if (err < 0)
  779. return err;
  780. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  781. return err;
  782. }
  783. /* Codec operation modes */
  784. static const char *twl4030_op_modes_texts[] = {
  785. "Option 2 (voice/audio)", "Option 1 (audio)"
  786. };
  787. static const struct soc_enum twl4030_op_modes_enum =
  788. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  789. ARRAY_SIZE(twl4030_op_modes_texts),
  790. twl4030_op_modes_texts);
  791. static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  792. struct snd_ctl_elem_value *ucontrol)
  793. {
  794. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  795. struct twl4030_priv *twl4030 = codec->private_data;
  796. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  797. unsigned short val;
  798. unsigned short mask, bitmask;
  799. if (twl4030->configured) {
  800. printk(KERN_ERR "twl4030 operation mode cannot be "
  801. "changed on-the-fly\n");
  802. return -EBUSY;
  803. }
  804. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  805. ;
  806. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  807. return -EINVAL;
  808. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  809. mask = (bitmask - 1) << e->shift_l;
  810. if (e->shift_l != e->shift_r) {
  811. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  812. return -EINVAL;
  813. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  814. mask |= (bitmask - 1) << e->shift_r;
  815. }
  816. return snd_soc_update_bits(codec, e->reg, mask, val);
  817. }
  818. /*
  819. * FGAIN volume control:
  820. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  821. */
  822. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  823. /*
  824. * CGAIN volume control:
  825. * 0 dB to 12 dB in 6 dB steps
  826. * value 2 and 3 means 12 dB
  827. */
  828. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  829. /*
  830. * Voice Downlink GAIN volume control:
  831. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  832. */
  833. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  834. /*
  835. * Analog playback gain
  836. * -24 dB to 12 dB in 2 dB steps
  837. */
  838. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  839. /*
  840. * Gain controls tied to outputs
  841. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  842. */
  843. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  844. /*
  845. * Gain control for earpiece amplifier
  846. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  847. */
  848. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  849. /*
  850. * Capture gain after the ADCs
  851. * from 0 dB to 31 dB in 1 dB steps
  852. */
  853. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  854. /*
  855. * Gain control for input amplifiers
  856. * 0 dB to 30 dB in 6 dB steps
  857. */
  858. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  859. /* AVADC clock priority */
  860. static const char *twl4030_avadc_clk_priority_texts[] = {
  861. "Voice high priority", "HiFi high priority"
  862. };
  863. static const struct soc_enum twl4030_avadc_clk_priority_enum =
  864. SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
  865. ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
  866. twl4030_avadc_clk_priority_texts);
  867. static const char *twl4030_rampdelay_texts[] = {
  868. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  869. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  870. "3495/2581/1748 ms"
  871. };
  872. static const struct soc_enum twl4030_rampdelay_enum =
  873. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  874. ARRAY_SIZE(twl4030_rampdelay_texts),
  875. twl4030_rampdelay_texts);
  876. /* Vibra H-bridge direction mode */
  877. static const char *twl4030_vibradirmode_texts[] = {
  878. "Vibra H-bridge direction", "Audio data MSB",
  879. };
  880. static const struct soc_enum twl4030_vibradirmode_enum =
  881. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  882. ARRAY_SIZE(twl4030_vibradirmode_texts),
  883. twl4030_vibradirmode_texts);
  884. /* Vibra H-bridge direction */
  885. static const char *twl4030_vibradir_texts[] = {
  886. "Positive polarity", "Negative polarity",
  887. };
  888. static const struct soc_enum twl4030_vibradir_enum =
  889. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  890. ARRAY_SIZE(twl4030_vibradir_texts),
  891. twl4030_vibradir_texts);
  892. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  893. /* Codec operation mode control */
  894. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  895. snd_soc_get_enum_double,
  896. snd_soc_put_twl4030_opmode_enum_double),
  897. /* Common playback gain controls */
  898. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  899. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  900. 0, 0x3f, 0, digital_fine_tlv),
  901. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  902. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  903. 0, 0x3f, 0, digital_fine_tlv),
  904. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  905. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  906. 6, 0x2, 0, digital_coarse_tlv),
  907. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  908. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  909. 6, 0x2, 0, digital_coarse_tlv),
  910. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  911. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  912. 3, 0x12, 1, analog_tlv),
  913. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  914. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  915. 3, 0x12, 1, analog_tlv),
  916. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  917. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  918. 1, 1, 0),
  919. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  920. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  921. 1, 1, 0),
  922. /* Common voice downlink gain controls */
  923. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  924. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  925. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  926. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  927. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  928. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  929. /* Separate output gain controls */
  930. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  931. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  932. 4, 3, 0, output_tvl),
  933. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  934. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  935. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  936. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  937. 4, 3, 0, output_tvl),
  938. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  939. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  940. /* Common capture gain controls */
  941. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  942. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  943. 0, 0x1f, 0, digital_capture_tlv),
  944. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  945. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  946. 0, 0x1f, 0, digital_capture_tlv),
  947. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  948. 0, 3, 5, 0, input_gain_tlv),
  949. SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
  950. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  951. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  952. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  953. };
  954. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  955. /* Left channel inputs */
  956. SND_SOC_DAPM_INPUT("MAINMIC"),
  957. SND_SOC_DAPM_INPUT("HSMIC"),
  958. SND_SOC_DAPM_INPUT("AUXL"),
  959. SND_SOC_DAPM_INPUT("CARKITMIC"),
  960. /* Right channel inputs */
  961. SND_SOC_DAPM_INPUT("SUBMIC"),
  962. SND_SOC_DAPM_INPUT("AUXR"),
  963. /* Digital microphones (Stereo) */
  964. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  965. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  966. /* Outputs */
  967. SND_SOC_DAPM_OUTPUT("OUTL"),
  968. SND_SOC_DAPM_OUTPUT("OUTR"),
  969. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  970. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  971. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  972. SND_SOC_DAPM_OUTPUT("HSOL"),
  973. SND_SOC_DAPM_OUTPUT("HSOR"),
  974. SND_SOC_DAPM_OUTPUT("CARKITL"),
  975. SND_SOC_DAPM_OUTPUT("CARKITR"),
  976. SND_SOC_DAPM_OUTPUT("HFL"),
  977. SND_SOC_DAPM_OUTPUT("HFR"),
  978. SND_SOC_DAPM_OUTPUT("VIBRA"),
  979. /* DACs */
  980. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  981. SND_SOC_NOPM, 0, 0),
  982. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  983. SND_SOC_NOPM, 0, 0),
  984. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  985. SND_SOC_NOPM, 0, 0),
  986. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  987. SND_SOC_NOPM, 0, 0),
  988. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  989. SND_SOC_NOPM, 0, 0),
  990. /* Analog bypasses */
  991. SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  992. &twl4030_dapm_abypassr1_control),
  993. SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  994. &twl4030_dapm_abypassl1_control),
  995. SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  996. &twl4030_dapm_abypassr2_control),
  997. SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  998. &twl4030_dapm_abypassl2_control),
  999. SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  1000. &twl4030_dapm_abypassv_control),
  1001. /* Master analog loopback switch */
  1002. SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
  1003. NULL, 0),
  1004. /* Digital bypasses */
  1005. SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1006. &twl4030_dapm_dbypassl_control),
  1007. SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1008. &twl4030_dapm_dbypassr_control),
  1009. SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1010. &twl4030_dapm_dbypassv_control),
  1011. /* Digital mixers, power control for the physical DACs */
  1012. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1013. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1014. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1015. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1016. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1017. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1018. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1019. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1020. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1021. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1022. /* Analog mixers, power control for the physical PGAs */
  1023. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1024. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1025. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1026. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1027. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1028. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1029. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1030. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1031. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1032. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1033. SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
  1034. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1035. SND_SOC_DAPM_SUPPLY("AIF Enable", TWL4030_REG_AUDIO_IF, 0, 0, NULL, 0),
  1036. /* Output MIXER controls */
  1037. /* Earpiece */
  1038. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1039. &twl4030_dapm_earpiece_controls[0],
  1040. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1041. SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
  1042. 0, 0, NULL, 0, earpiecepga_event,
  1043. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1044. /* PreDrivL/R */
  1045. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1046. &twl4030_dapm_predrivel_controls[0],
  1047. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1048. SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
  1049. 0, 0, NULL, 0, predrivelpga_event,
  1050. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1051. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1052. &twl4030_dapm_predriver_controls[0],
  1053. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1054. SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
  1055. 0, 0, NULL, 0, predriverpga_event,
  1056. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1057. /* HeadsetL/R */
  1058. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1059. &twl4030_dapm_hsol_controls[0],
  1060. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1061. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1062. 0, 0, NULL, 0, headsetlpga_event,
  1063. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1064. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1065. &twl4030_dapm_hsor_controls[0],
  1066. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1067. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1068. 0, 0, NULL, 0, headsetrpga_event,
  1069. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1070. /* CarkitL/R */
  1071. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1072. &twl4030_dapm_carkitl_controls[0],
  1073. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1074. SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
  1075. 0, 0, NULL, 0, carkitlpga_event,
  1076. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1077. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1078. &twl4030_dapm_carkitr_controls[0],
  1079. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1080. SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
  1081. 0, 0, NULL, 0, carkitrpga_event,
  1082. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1083. /* Output MUX controls */
  1084. /* HandsfreeL/R */
  1085. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1086. &twl4030_dapm_handsfreel_control),
  1087. SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
  1088. &twl4030_dapm_handsfreelmute_control),
  1089. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1090. 0, 0, NULL, 0, handsfreelpga_event,
  1091. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1092. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1093. &twl4030_dapm_handsfreer_control),
  1094. SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
  1095. &twl4030_dapm_handsfreermute_control),
  1096. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1097. 0, 0, NULL, 0, handsfreerpga_event,
  1098. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1099. /* Vibra */
  1100. SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1101. &twl4030_dapm_vibra_control, vibramux_event,
  1102. SND_SOC_DAPM_PRE_PMU),
  1103. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1104. &twl4030_dapm_vibrapath_control),
  1105. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1106. capture */
  1107. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1108. SND_SOC_NOPM, 0, 0),
  1109. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1110. SND_SOC_NOPM, 0, 0),
  1111. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1112. SND_SOC_NOPM, 0, 0),
  1113. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1114. SND_SOC_NOPM, 0, 0),
  1115. /* Analog/Digital mic path selection.
  1116. TX1 Left/Right: either analog Left/Right or Digimic0
  1117. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1118. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1119. &twl4030_dapm_micpathtx1_control, micpath_event,
  1120. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1121. SND_SOC_DAPM_POST_REG),
  1122. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1123. &twl4030_dapm_micpathtx2_control, micpath_event,
  1124. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1125. SND_SOC_DAPM_POST_REG),
  1126. /* Analog input mixers for the capture amplifiers */
  1127. SND_SOC_DAPM_MIXER("Analog Left",
  1128. TWL4030_REG_ANAMICL, 4, 0,
  1129. &twl4030_dapm_analoglmic_controls[0],
  1130. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1131. SND_SOC_DAPM_MIXER("Analog Right",
  1132. TWL4030_REG_ANAMICR, 4, 0,
  1133. &twl4030_dapm_analogrmic_controls[0],
  1134. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1135. SND_SOC_DAPM_PGA("ADC Physical Left",
  1136. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1137. SND_SOC_DAPM_PGA("ADC Physical Right",
  1138. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1139. SND_SOC_DAPM_PGA("Digimic0 Enable",
  1140. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  1141. SND_SOC_DAPM_PGA("Digimic1 Enable",
  1142. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  1143. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1144. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1145. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1146. };
  1147. static const struct snd_soc_dapm_route intercon[] = {
  1148. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1149. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1150. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1151. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1152. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1153. /* Supply for the digital part (APLL) */
  1154. {"Digital R1 Playback Mixer", NULL, "APLL Enable"},
  1155. {"Digital L1 Playback Mixer", NULL, "APLL Enable"},
  1156. {"Digital R2 Playback Mixer", NULL, "APLL Enable"},
  1157. {"Digital L2 Playback Mixer", NULL, "APLL Enable"},
  1158. {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
  1159. {"Digital R1 Playback Mixer", NULL, "AIF Enable"},
  1160. {"Digital L1 Playback Mixer", NULL, "AIF Enable"},
  1161. {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
  1162. {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
  1163. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1164. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1165. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1166. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1167. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1168. /* Internal playback routings */
  1169. /* Earpiece */
  1170. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1171. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1172. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1173. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1174. {"Earpiece PGA", NULL, "Earpiece Mixer"},
  1175. /* PreDrivL */
  1176. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1177. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1178. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1179. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1180. {"PredriveL PGA", NULL, "PredriveL Mixer"},
  1181. /* PreDrivR */
  1182. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1183. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1184. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1185. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1186. {"PredriveR PGA", NULL, "PredriveR Mixer"},
  1187. /* HeadsetL */
  1188. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1189. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1190. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1191. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1192. /* HeadsetR */
  1193. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1194. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1195. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1196. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1197. /* CarkitL */
  1198. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1199. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1200. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1201. {"CarkitL PGA", NULL, "CarkitL Mixer"},
  1202. /* CarkitR */
  1203. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1204. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1205. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1206. {"CarkitR PGA", NULL, "CarkitR Mixer"},
  1207. /* HandsfreeL */
  1208. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1209. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1210. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1211. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1212. {"HandsfreeL", "Switch", "HandsfreeL Mux"},
  1213. {"HandsfreeL PGA", NULL, "HandsfreeL"},
  1214. /* HandsfreeR */
  1215. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1216. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1217. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1218. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1219. {"HandsfreeR", "Switch", "HandsfreeR Mux"},
  1220. {"HandsfreeR PGA", NULL, "HandsfreeR"},
  1221. /* Vibra */
  1222. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1223. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1224. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1225. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1226. /* outputs */
  1227. {"OUTL", NULL, "Analog L2 Playback Mixer"},
  1228. {"OUTR", NULL, "Analog R2 Playback Mixer"},
  1229. {"EARPIECE", NULL, "Earpiece PGA"},
  1230. {"PREDRIVEL", NULL, "PredriveL PGA"},
  1231. {"PREDRIVER", NULL, "PredriveR PGA"},
  1232. {"HSOL", NULL, "HeadsetL PGA"},
  1233. {"HSOR", NULL, "HeadsetR PGA"},
  1234. {"CARKITL", NULL, "CarkitL PGA"},
  1235. {"CARKITR", NULL, "CarkitR PGA"},
  1236. {"HFL", NULL, "HandsfreeL PGA"},
  1237. {"HFR", NULL, "HandsfreeR PGA"},
  1238. {"Vibra Route", "Audio", "Vibra Mux"},
  1239. {"VIBRA", NULL, "Vibra Route"},
  1240. /* Capture path */
  1241. {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
  1242. {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
  1243. {"Analog Left", "AUXL Capture Switch", "AUXL"},
  1244. {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
  1245. {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
  1246. {"Analog Right", "AUXR Capture Switch", "AUXR"},
  1247. {"ADC Physical Left", NULL, "Analog Left"},
  1248. {"ADC Physical Right", NULL, "Analog Right"},
  1249. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1250. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1251. /* TX1 Left capture path */
  1252. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1253. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1254. /* TX1 Right capture path */
  1255. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1256. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1257. /* TX2 Left capture path */
  1258. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1259. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1260. /* TX2 Right capture path */
  1261. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1262. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1263. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1264. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1265. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1266. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1267. {"ADC Virtual Left1", NULL, "APLL Enable"},
  1268. {"ADC Virtual Right1", NULL, "APLL Enable"},
  1269. {"ADC Virtual Left2", NULL, "APLL Enable"},
  1270. {"ADC Virtual Right2", NULL, "APLL Enable"},
  1271. {"ADC Virtual Left1", NULL, "AIF Enable"},
  1272. {"ADC Virtual Right1", NULL, "AIF Enable"},
  1273. {"ADC Virtual Left2", NULL, "AIF Enable"},
  1274. {"ADC Virtual Right2", NULL, "AIF Enable"},
  1275. /* Analog bypass routes */
  1276. {"Right1 Analog Loopback", "Switch", "Analog Right"},
  1277. {"Left1 Analog Loopback", "Switch", "Analog Left"},
  1278. {"Right2 Analog Loopback", "Switch", "Analog Right"},
  1279. {"Left2 Analog Loopback", "Switch", "Analog Left"},
  1280. {"Voice Analog Loopback", "Switch", "Analog Left"},
  1281. /* Supply for the Analog loopbacks */
  1282. {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
  1283. {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
  1284. {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
  1285. {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
  1286. {"Voice Analog Loopback", NULL, "FM Loop Enable"},
  1287. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1288. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1289. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1290. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1291. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1292. /* Digital bypass routes */
  1293. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1294. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1295. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1296. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1297. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1298. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1299. };
  1300. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1301. {
  1302. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1303. ARRAY_SIZE(twl4030_dapm_widgets));
  1304. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1305. return 0;
  1306. }
  1307. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1308. enum snd_soc_bias_level level)
  1309. {
  1310. switch (level) {
  1311. case SND_SOC_BIAS_ON:
  1312. break;
  1313. case SND_SOC_BIAS_PREPARE:
  1314. break;
  1315. case SND_SOC_BIAS_STANDBY:
  1316. if (codec->bias_level == SND_SOC_BIAS_OFF)
  1317. twl4030_power_up(codec);
  1318. break;
  1319. case SND_SOC_BIAS_OFF:
  1320. twl4030_power_down(codec);
  1321. break;
  1322. }
  1323. codec->bias_level = level;
  1324. return 0;
  1325. }
  1326. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1327. struct snd_pcm_substream *mst_substream)
  1328. {
  1329. struct snd_pcm_substream *slv_substream;
  1330. /* Pick the stream, which need to be constrained */
  1331. if (mst_substream == twl4030->master_substream)
  1332. slv_substream = twl4030->slave_substream;
  1333. else if (mst_substream == twl4030->slave_substream)
  1334. slv_substream = twl4030->master_substream;
  1335. else /* This should not happen.. */
  1336. return;
  1337. /* Set the constraints according to the already configured stream */
  1338. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1339. SNDRV_PCM_HW_PARAM_RATE,
  1340. twl4030->rate,
  1341. twl4030->rate);
  1342. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1343. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1344. twl4030->sample_bits,
  1345. twl4030->sample_bits);
  1346. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1347. SNDRV_PCM_HW_PARAM_CHANNELS,
  1348. twl4030->channels,
  1349. twl4030->channels);
  1350. }
  1351. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1352. * capture has to be enabled/disabled. */
  1353. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1354. int enable)
  1355. {
  1356. u8 reg, mask;
  1357. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1358. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1359. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1360. else
  1361. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1362. if (enable)
  1363. reg |= mask;
  1364. else
  1365. reg &= ~mask;
  1366. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1367. }
  1368. static int twl4030_startup(struct snd_pcm_substream *substream,
  1369. struct snd_soc_dai *dai)
  1370. {
  1371. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1372. struct snd_soc_device *socdev = rtd->socdev;
  1373. struct snd_soc_codec *codec = socdev->card->codec;
  1374. struct twl4030_priv *twl4030 = codec->private_data;
  1375. if (twl4030->master_substream) {
  1376. twl4030->slave_substream = substream;
  1377. /* The DAI has one configuration for playback and capture, so
  1378. * if the DAI has been already configured then constrain this
  1379. * substream to match it. */
  1380. if (twl4030->configured)
  1381. twl4030_constraints(twl4030, twl4030->master_substream);
  1382. } else {
  1383. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1384. TWL4030_OPTION_1)) {
  1385. /* In option2 4 channel is not supported, set the
  1386. * constraint for the first stream for channels, the
  1387. * second stream will 'inherit' this cosntraint */
  1388. snd_pcm_hw_constraint_minmax(substream->runtime,
  1389. SNDRV_PCM_HW_PARAM_CHANNELS,
  1390. 2, 2);
  1391. }
  1392. twl4030->master_substream = substream;
  1393. }
  1394. return 0;
  1395. }
  1396. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1397. struct snd_soc_dai *dai)
  1398. {
  1399. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1400. struct snd_soc_device *socdev = rtd->socdev;
  1401. struct snd_soc_codec *codec = socdev->card->codec;
  1402. struct twl4030_priv *twl4030 = codec->private_data;
  1403. if (twl4030->master_substream == substream)
  1404. twl4030->master_substream = twl4030->slave_substream;
  1405. twl4030->slave_substream = NULL;
  1406. /* If all streams are closed, or the remaining stream has not yet
  1407. * been configured than set the DAI as not configured. */
  1408. if (!twl4030->master_substream)
  1409. twl4030->configured = 0;
  1410. else if (!twl4030->master_substream->runtime->channels)
  1411. twl4030->configured = 0;
  1412. /* If the closing substream had 4 channel, do the necessary cleanup */
  1413. if (substream->runtime->channels == 4)
  1414. twl4030_tdm_enable(codec, substream->stream, 0);
  1415. }
  1416. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1417. struct snd_pcm_hw_params *params,
  1418. struct snd_soc_dai *dai)
  1419. {
  1420. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1421. struct snd_soc_device *socdev = rtd->socdev;
  1422. struct snd_soc_codec *codec = socdev->card->codec;
  1423. struct twl4030_priv *twl4030 = codec->private_data;
  1424. u8 mode, old_mode, format, old_format;
  1425. /* If the substream has 4 channel, do the necessary setup */
  1426. if (params_channels(params) == 4) {
  1427. format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1428. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  1429. /* Safety check: are we in the correct operating mode and
  1430. * the interface is in TDM mode? */
  1431. if ((mode & TWL4030_OPTION_1) &&
  1432. ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
  1433. twl4030_tdm_enable(codec, substream->stream, 1);
  1434. else
  1435. return -EINVAL;
  1436. }
  1437. if (twl4030->configured)
  1438. /* Ignoring hw_params for already configured DAI */
  1439. return 0;
  1440. /* bit rate */
  1441. old_mode = twl4030_read_reg_cache(codec,
  1442. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1443. mode = old_mode & ~TWL4030_APLL_RATE;
  1444. switch (params_rate(params)) {
  1445. case 8000:
  1446. mode |= TWL4030_APLL_RATE_8000;
  1447. break;
  1448. case 11025:
  1449. mode |= TWL4030_APLL_RATE_11025;
  1450. break;
  1451. case 12000:
  1452. mode |= TWL4030_APLL_RATE_12000;
  1453. break;
  1454. case 16000:
  1455. mode |= TWL4030_APLL_RATE_16000;
  1456. break;
  1457. case 22050:
  1458. mode |= TWL4030_APLL_RATE_22050;
  1459. break;
  1460. case 24000:
  1461. mode |= TWL4030_APLL_RATE_24000;
  1462. break;
  1463. case 32000:
  1464. mode |= TWL4030_APLL_RATE_32000;
  1465. break;
  1466. case 44100:
  1467. mode |= TWL4030_APLL_RATE_44100;
  1468. break;
  1469. case 48000:
  1470. mode |= TWL4030_APLL_RATE_48000;
  1471. break;
  1472. case 96000:
  1473. mode |= TWL4030_APLL_RATE_96000;
  1474. break;
  1475. default:
  1476. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1477. params_rate(params));
  1478. return -EINVAL;
  1479. }
  1480. if (mode != old_mode) {
  1481. /* change rate and set CODECPDZ */
  1482. twl4030_codec_enable(codec, 0);
  1483. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1484. twl4030_codec_enable(codec, 1);
  1485. }
  1486. /* sample size */
  1487. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1488. format = old_format;
  1489. format &= ~TWL4030_DATA_WIDTH;
  1490. switch (params_format(params)) {
  1491. case SNDRV_PCM_FORMAT_S16_LE:
  1492. format |= TWL4030_DATA_WIDTH_16S_16W;
  1493. break;
  1494. case SNDRV_PCM_FORMAT_S24_LE:
  1495. format |= TWL4030_DATA_WIDTH_32S_24W;
  1496. break;
  1497. default:
  1498. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1499. params_format(params));
  1500. return -EINVAL;
  1501. }
  1502. if (format != old_format) {
  1503. /* clear CODECPDZ before changing format (codec requirement) */
  1504. twl4030_codec_enable(codec, 0);
  1505. /* change format */
  1506. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1507. /* set CODECPDZ afterwards */
  1508. twl4030_codec_enable(codec, 1);
  1509. }
  1510. /* Store the important parameters for the DAI configuration and set
  1511. * the DAI as configured */
  1512. twl4030->configured = 1;
  1513. twl4030->rate = params_rate(params);
  1514. twl4030->sample_bits = hw_param_interval(params,
  1515. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1516. twl4030->channels = params_channels(params);
  1517. /* If both playback and capture streams are open, and one of them
  1518. * is setting the hw parameters right now (since we are here), set
  1519. * constraints to the other stream to match the current one. */
  1520. if (twl4030->slave_substream)
  1521. twl4030_constraints(twl4030, substream);
  1522. return 0;
  1523. }
  1524. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1525. int clk_id, unsigned int freq, int dir)
  1526. {
  1527. struct snd_soc_codec *codec = codec_dai->codec;
  1528. struct twl4030_priv *twl4030 = codec->private_data;
  1529. switch (freq) {
  1530. case 19200000:
  1531. case 26000000:
  1532. case 38400000:
  1533. break;
  1534. default:
  1535. dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
  1536. return -EINVAL;
  1537. }
  1538. if ((freq / 1000) != twl4030->sysclk) {
  1539. dev_err(codec->dev,
  1540. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1541. freq, twl4030->sysclk * 1000);
  1542. return -EINVAL;
  1543. }
  1544. return 0;
  1545. }
  1546. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1547. unsigned int fmt)
  1548. {
  1549. struct snd_soc_codec *codec = codec_dai->codec;
  1550. u8 old_format, format;
  1551. /* get format */
  1552. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1553. format = old_format;
  1554. /* set master/slave audio interface */
  1555. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1556. case SND_SOC_DAIFMT_CBM_CFM:
  1557. format &= ~(TWL4030_AIF_SLAVE_EN);
  1558. format &= ~(TWL4030_CLK256FS_EN);
  1559. break;
  1560. case SND_SOC_DAIFMT_CBS_CFS:
  1561. format |= TWL4030_AIF_SLAVE_EN;
  1562. format |= TWL4030_CLK256FS_EN;
  1563. break;
  1564. default:
  1565. return -EINVAL;
  1566. }
  1567. /* interface format */
  1568. format &= ~TWL4030_AIF_FORMAT;
  1569. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1570. case SND_SOC_DAIFMT_I2S:
  1571. format |= TWL4030_AIF_FORMAT_CODEC;
  1572. break;
  1573. case SND_SOC_DAIFMT_DSP_A:
  1574. format |= TWL4030_AIF_FORMAT_TDM;
  1575. break;
  1576. default:
  1577. return -EINVAL;
  1578. }
  1579. if (format != old_format) {
  1580. /* clear CODECPDZ before changing format (codec requirement) */
  1581. twl4030_codec_enable(codec, 0);
  1582. /* change format */
  1583. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1584. /* set CODECPDZ afterwards */
  1585. twl4030_codec_enable(codec, 1);
  1586. }
  1587. return 0;
  1588. }
  1589. static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
  1590. {
  1591. struct snd_soc_codec *codec = dai->codec;
  1592. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1593. if (tristate)
  1594. reg |= TWL4030_AIF_TRI_EN;
  1595. else
  1596. reg &= ~TWL4030_AIF_TRI_EN;
  1597. return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
  1598. }
  1599. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1600. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1601. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1602. int enable)
  1603. {
  1604. u8 reg, mask;
  1605. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1606. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1607. mask = TWL4030_ARXL1_VRX_EN;
  1608. else
  1609. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1610. if (enable)
  1611. reg |= mask;
  1612. else
  1613. reg &= ~mask;
  1614. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1615. }
  1616. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1617. struct snd_soc_dai *dai)
  1618. {
  1619. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1620. struct snd_soc_device *socdev = rtd->socdev;
  1621. struct snd_soc_codec *codec = socdev->card->codec;
  1622. struct twl4030_priv *twl4030 = codec->private_data;
  1623. u8 mode;
  1624. /* If the system master clock is not 26MHz, the voice PCM interface is
  1625. * not avilable.
  1626. */
  1627. if (twl4030->sysclk != 26000) {
  1628. dev_err(codec->dev, "The board is configured for %u Hz, while"
  1629. "the Voice interface needs 26MHz APLL mclk\n",
  1630. twl4030->sysclk * 1000);
  1631. return -EINVAL;
  1632. }
  1633. /* If the codec mode is not option2, the voice PCM interface is not
  1634. * avilable.
  1635. */
  1636. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1637. & TWL4030_OPT_MODE;
  1638. if (mode != TWL4030_OPTION_2) {
  1639. printk(KERN_ERR "TWL4030 voice startup: "
  1640. "the codec mode is not option2\n");
  1641. return -EINVAL;
  1642. }
  1643. return 0;
  1644. }
  1645. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1646. struct snd_soc_dai *dai)
  1647. {
  1648. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1649. struct snd_soc_device *socdev = rtd->socdev;
  1650. struct snd_soc_codec *codec = socdev->card->codec;
  1651. /* Enable voice digital filters */
  1652. twl4030_voice_enable(codec, substream->stream, 0);
  1653. }
  1654. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1655. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1656. {
  1657. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1658. struct snd_soc_device *socdev = rtd->socdev;
  1659. struct snd_soc_codec *codec = socdev->card->codec;
  1660. u8 old_mode, mode;
  1661. /* Enable voice digital filters */
  1662. twl4030_voice_enable(codec, substream->stream, 1);
  1663. /* bit rate */
  1664. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1665. & ~(TWL4030_CODECPDZ);
  1666. mode = old_mode;
  1667. switch (params_rate(params)) {
  1668. case 8000:
  1669. mode &= ~(TWL4030_SEL_16K);
  1670. break;
  1671. case 16000:
  1672. mode |= TWL4030_SEL_16K;
  1673. break;
  1674. default:
  1675. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1676. params_rate(params));
  1677. return -EINVAL;
  1678. }
  1679. if (mode != old_mode) {
  1680. /* change rate and set CODECPDZ */
  1681. twl4030_codec_enable(codec, 0);
  1682. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1683. twl4030_codec_enable(codec, 1);
  1684. }
  1685. return 0;
  1686. }
  1687. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1688. int clk_id, unsigned int freq, int dir)
  1689. {
  1690. struct snd_soc_codec *codec = codec_dai->codec;
  1691. struct twl4030_priv *twl4030 = codec->private_data;
  1692. if (freq != 26000000) {
  1693. dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
  1694. "interface needs 26MHz APLL mclk\n", freq);
  1695. return -EINVAL;
  1696. }
  1697. if ((freq / 1000) != twl4030->sysclk) {
  1698. dev_err(codec->dev,
  1699. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1700. freq, twl4030->sysclk * 1000);
  1701. return -EINVAL;
  1702. }
  1703. return 0;
  1704. }
  1705. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1706. unsigned int fmt)
  1707. {
  1708. struct snd_soc_codec *codec = codec_dai->codec;
  1709. u8 old_format, format;
  1710. /* get format */
  1711. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1712. format = old_format;
  1713. /* set master/slave audio interface */
  1714. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1715. case SND_SOC_DAIFMT_CBM_CFM:
  1716. format &= ~(TWL4030_VIF_SLAVE_EN);
  1717. break;
  1718. case SND_SOC_DAIFMT_CBS_CFS:
  1719. format |= TWL4030_VIF_SLAVE_EN;
  1720. break;
  1721. default:
  1722. return -EINVAL;
  1723. }
  1724. /* clock inversion */
  1725. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1726. case SND_SOC_DAIFMT_IB_NF:
  1727. format &= ~(TWL4030_VIF_FORMAT);
  1728. break;
  1729. case SND_SOC_DAIFMT_NB_IF:
  1730. format |= TWL4030_VIF_FORMAT;
  1731. break;
  1732. default:
  1733. return -EINVAL;
  1734. }
  1735. if (format != old_format) {
  1736. /* change format and set CODECPDZ */
  1737. twl4030_codec_enable(codec, 0);
  1738. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1739. twl4030_codec_enable(codec, 1);
  1740. }
  1741. return 0;
  1742. }
  1743. static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
  1744. {
  1745. struct snd_soc_codec *codec = dai->codec;
  1746. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1747. if (tristate)
  1748. reg |= TWL4030_VIF_TRI_EN;
  1749. else
  1750. reg &= ~TWL4030_VIF_TRI_EN;
  1751. return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
  1752. }
  1753. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1754. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1755. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1756. .startup = twl4030_startup,
  1757. .shutdown = twl4030_shutdown,
  1758. .hw_params = twl4030_hw_params,
  1759. .set_sysclk = twl4030_set_dai_sysclk,
  1760. .set_fmt = twl4030_set_dai_fmt,
  1761. .set_tristate = twl4030_set_tristate,
  1762. };
  1763. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1764. .startup = twl4030_voice_startup,
  1765. .shutdown = twl4030_voice_shutdown,
  1766. .hw_params = twl4030_voice_hw_params,
  1767. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1768. .set_fmt = twl4030_voice_set_dai_fmt,
  1769. .set_tristate = twl4030_voice_set_tristate,
  1770. };
  1771. struct snd_soc_dai twl4030_dai[] = {
  1772. {
  1773. .name = "twl4030",
  1774. .playback = {
  1775. .stream_name = "HiFi Playback",
  1776. .channels_min = 2,
  1777. .channels_max = 4,
  1778. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1779. .formats = TWL4030_FORMATS,},
  1780. .capture = {
  1781. .stream_name = "Capture",
  1782. .channels_min = 2,
  1783. .channels_max = 4,
  1784. .rates = TWL4030_RATES,
  1785. .formats = TWL4030_FORMATS,},
  1786. .ops = &twl4030_dai_ops,
  1787. },
  1788. {
  1789. .name = "twl4030 Voice",
  1790. .playback = {
  1791. .stream_name = "Voice Playback",
  1792. .channels_min = 1,
  1793. .channels_max = 1,
  1794. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1795. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1796. .capture = {
  1797. .stream_name = "Capture",
  1798. .channels_min = 1,
  1799. .channels_max = 2,
  1800. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1801. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1802. .ops = &twl4030_dai_voice_ops,
  1803. },
  1804. };
  1805. EXPORT_SYMBOL_GPL(twl4030_dai);
  1806. static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
  1807. {
  1808. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1809. struct snd_soc_codec *codec = socdev->card->codec;
  1810. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1811. return 0;
  1812. }
  1813. static int twl4030_soc_resume(struct platform_device *pdev)
  1814. {
  1815. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1816. struct snd_soc_codec *codec = socdev->card->codec;
  1817. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1818. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1819. return 0;
  1820. }
  1821. static struct snd_soc_codec *twl4030_codec;
  1822. static int twl4030_soc_probe(struct platform_device *pdev)
  1823. {
  1824. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1825. struct twl4030_setup_data *setup = socdev->codec_data;
  1826. struct snd_soc_codec *codec;
  1827. struct twl4030_priv *twl4030;
  1828. int ret;
  1829. BUG_ON(!twl4030_codec);
  1830. codec = twl4030_codec;
  1831. twl4030 = codec->private_data;
  1832. socdev->card->codec = codec;
  1833. /* Configuration for headset ramp delay from setup data */
  1834. if (setup) {
  1835. unsigned char hs_pop;
  1836. if (setup->sysclk != twl4030->sysclk)
  1837. dev_warn(&pdev->dev,
  1838. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1839. setup->sysclk, twl4030->sysclk);
  1840. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  1841. hs_pop &= ~TWL4030_RAMP_DELAY;
  1842. hs_pop |= (setup->ramp_delay_value << 2);
  1843. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  1844. }
  1845. /* register pcms */
  1846. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1847. if (ret < 0) {
  1848. dev_err(&pdev->dev, "failed to create pcms\n");
  1849. return ret;
  1850. }
  1851. snd_soc_add_controls(codec, twl4030_snd_controls,
  1852. ARRAY_SIZE(twl4030_snd_controls));
  1853. twl4030_add_widgets(codec);
  1854. return 0;
  1855. }
  1856. static int twl4030_soc_remove(struct platform_device *pdev)
  1857. {
  1858. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1859. struct snd_soc_codec *codec = socdev->card->codec;
  1860. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1861. snd_soc_free_pcms(socdev);
  1862. snd_soc_dapm_free(socdev);
  1863. return 0;
  1864. }
  1865. static int __devinit twl4030_codec_probe(struct platform_device *pdev)
  1866. {
  1867. struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
  1868. struct snd_soc_codec *codec;
  1869. struct twl4030_priv *twl4030;
  1870. int ret;
  1871. if (!pdata) {
  1872. dev_err(&pdev->dev, "platform_data is missing\n");
  1873. return -EINVAL;
  1874. }
  1875. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1876. if (twl4030 == NULL) {
  1877. dev_err(&pdev->dev, "Can not allocate memroy\n");
  1878. return -ENOMEM;
  1879. }
  1880. codec = &twl4030->codec;
  1881. codec->private_data = twl4030;
  1882. codec->dev = &pdev->dev;
  1883. twl4030_dai[0].dev = &pdev->dev;
  1884. twl4030_dai[1].dev = &pdev->dev;
  1885. mutex_init(&codec->mutex);
  1886. INIT_LIST_HEAD(&codec->dapm_widgets);
  1887. INIT_LIST_HEAD(&codec->dapm_paths);
  1888. codec->name = "twl4030";
  1889. codec->owner = THIS_MODULE;
  1890. codec->read = twl4030_read_reg_cache;
  1891. codec->write = twl4030_write;
  1892. codec->set_bias_level = twl4030_set_bias_level;
  1893. codec->dai = twl4030_dai;
  1894. codec->num_dai = ARRAY_SIZE(twl4030_dai);
  1895. codec->reg_cache_size = sizeof(twl4030_reg);
  1896. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1897. GFP_KERNEL);
  1898. if (codec->reg_cache == NULL) {
  1899. ret = -ENOMEM;
  1900. goto error_cache;
  1901. }
  1902. platform_set_drvdata(pdev, twl4030);
  1903. twl4030_codec = codec;
  1904. /* Set the defaults, and power up the codec */
  1905. twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
  1906. twl4030_init_chip(codec);
  1907. codec->bias_level = SND_SOC_BIAS_OFF;
  1908. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1909. ret = snd_soc_register_codec(codec);
  1910. if (ret != 0) {
  1911. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  1912. goto error_codec;
  1913. }
  1914. ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1915. if (ret != 0) {
  1916. dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
  1917. snd_soc_unregister_codec(codec);
  1918. goto error_codec;
  1919. }
  1920. return 0;
  1921. error_codec:
  1922. twl4030_power_down(codec);
  1923. kfree(codec->reg_cache);
  1924. error_cache:
  1925. kfree(twl4030);
  1926. return ret;
  1927. }
  1928. static int __devexit twl4030_codec_remove(struct platform_device *pdev)
  1929. {
  1930. struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
  1931. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1932. snd_soc_unregister_codec(&twl4030->codec);
  1933. kfree(twl4030->codec.reg_cache);
  1934. kfree(twl4030);
  1935. twl4030_codec = NULL;
  1936. return 0;
  1937. }
  1938. MODULE_ALIAS("platform:twl4030_codec_audio");
  1939. static struct platform_driver twl4030_codec_driver = {
  1940. .probe = twl4030_codec_probe,
  1941. .remove = __devexit_p(twl4030_codec_remove),
  1942. .driver = {
  1943. .name = "twl4030_codec_audio",
  1944. .owner = THIS_MODULE,
  1945. },
  1946. };
  1947. static int __init twl4030_modinit(void)
  1948. {
  1949. return platform_driver_register(&twl4030_codec_driver);
  1950. }
  1951. module_init(twl4030_modinit);
  1952. static void __exit twl4030_exit(void)
  1953. {
  1954. platform_driver_unregister(&twl4030_codec_driver);
  1955. }
  1956. module_exit(twl4030_exit);
  1957. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1958. .probe = twl4030_soc_probe,
  1959. .remove = twl4030_soc_remove,
  1960. .suspend = twl4030_soc_suspend,
  1961. .resume = twl4030_soc_resume,
  1962. };
  1963. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1964. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1965. MODULE_AUTHOR("Steve Sakoman");
  1966. MODULE_LICENSE("GPL");