atmel_usba_udc.c 50 KB

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  1. /*
  2. * Driver for the Atmel USBA high speed USB device controller
  3. *
  4. * Copyright (C) 2005-2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/slab.h>
  16. #include <linux/device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/list.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/usb/ch9.h>
  21. #include <linux/usb/gadget.h>
  22. #include <linux/usb/atmel_usba_udc.h>
  23. #include <linux/delay.h>
  24. #include <asm/gpio.h>
  25. #include <mach/board.h>
  26. #include "atmel_usba_udc.h"
  27. static struct usba_udc the_udc;
  28. static struct usba_ep *usba_ep;
  29. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  30. #include <linux/debugfs.h>
  31. #include <linux/uaccess.h>
  32. static int queue_dbg_open(struct inode *inode, struct file *file)
  33. {
  34. struct usba_ep *ep = inode->i_private;
  35. struct usba_request *req, *req_copy;
  36. struct list_head *queue_data;
  37. queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
  38. if (!queue_data)
  39. return -ENOMEM;
  40. INIT_LIST_HEAD(queue_data);
  41. spin_lock_irq(&ep->udc->lock);
  42. list_for_each_entry(req, &ep->queue, queue) {
  43. req_copy = kmalloc(sizeof(*req_copy), GFP_ATOMIC);
  44. if (!req_copy)
  45. goto fail;
  46. memcpy(req_copy, req, sizeof(*req_copy));
  47. list_add_tail(&req_copy->queue, queue_data);
  48. }
  49. spin_unlock_irq(&ep->udc->lock);
  50. file->private_data = queue_data;
  51. return 0;
  52. fail:
  53. spin_unlock_irq(&ep->udc->lock);
  54. list_for_each_entry_safe(req, req_copy, queue_data, queue) {
  55. list_del(&req->queue);
  56. kfree(req);
  57. }
  58. kfree(queue_data);
  59. return -ENOMEM;
  60. }
  61. /*
  62. * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
  63. *
  64. * b: buffer address
  65. * l: buffer length
  66. * I/i: interrupt/no interrupt
  67. * Z/z: zero/no zero
  68. * S/s: short ok/short not ok
  69. * s: status
  70. * n: nr_packets
  71. * F/f: submitted/not submitted to FIFO
  72. * D/d: using/not using DMA
  73. * L/l: last transaction/not last transaction
  74. */
  75. static ssize_t queue_dbg_read(struct file *file, char __user *buf,
  76. size_t nbytes, loff_t *ppos)
  77. {
  78. struct list_head *queue = file->private_data;
  79. struct usba_request *req, *tmp_req;
  80. size_t len, remaining, actual = 0;
  81. char tmpbuf[38];
  82. if (!access_ok(VERIFY_WRITE, buf, nbytes))
  83. return -EFAULT;
  84. mutex_lock(&file->f_dentry->d_inode->i_mutex);
  85. list_for_each_entry_safe(req, tmp_req, queue, queue) {
  86. len = snprintf(tmpbuf, sizeof(tmpbuf),
  87. "%8p %08x %c%c%c %5d %c%c%c\n",
  88. req->req.buf, req->req.length,
  89. req->req.no_interrupt ? 'i' : 'I',
  90. req->req.zero ? 'Z' : 'z',
  91. req->req.short_not_ok ? 's' : 'S',
  92. req->req.status,
  93. req->submitted ? 'F' : 'f',
  94. req->using_dma ? 'D' : 'd',
  95. req->last_transaction ? 'L' : 'l');
  96. len = min(len, sizeof(tmpbuf));
  97. if (len > nbytes)
  98. break;
  99. list_del(&req->queue);
  100. kfree(req);
  101. remaining = __copy_to_user(buf, tmpbuf, len);
  102. actual += len - remaining;
  103. if (remaining)
  104. break;
  105. nbytes -= len;
  106. buf += len;
  107. }
  108. mutex_unlock(&file->f_dentry->d_inode->i_mutex);
  109. return actual;
  110. }
  111. static int queue_dbg_release(struct inode *inode, struct file *file)
  112. {
  113. struct list_head *queue_data = file->private_data;
  114. struct usba_request *req, *tmp_req;
  115. list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
  116. list_del(&req->queue);
  117. kfree(req);
  118. }
  119. kfree(queue_data);
  120. return 0;
  121. }
  122. static int regs_dbg_open(struct inode *inode, struct file *file)
  123. {
  124. struct usba_udc *udc;
  125. unsigned int i;
  126. u32 *data;
  127. int ret = -ENOMEM;
  128. mutex_lock(&inode->i_mutex);
  129. udc = inode->i_private;
  130. data = kmalloc(inode->i_size, GFP_KERNEL);
  131. if (!data)
  132. goto out;
  133. spin_lock_irq(&udc->lock);
  134. for (i = 0; i < inode->i_size / 4; i++)
  135. data[i] = __raw_readl(udc->regs + i * 4);
  136. spin_unlock_irq(&udc->lock);
  137. file->private_data = data;
  138. ret = 0;
  139. out:
  140. mutex_unlock(&inode->i_mutex);
  141. return ret;
  142. }
  143. static ssize_t regs_dbg_read(struct file *file, char __user *buf,
  144. size_t nbytes, loff_t *ppos)
  145. {
  146. struct inode *inode = file->f_dentry->d_inode;
  147. int ret;
  148. mutex_lock(&inode->i_mutex);
  149. ret = simple_read_from_buffer(buf, nbytes, ppos,
  150. file->private_data,
  151. file->f_dentry->d_inode->i_size);
  152. mutex_unlock(&inode->i_mutex);
  153. return ret;
  154. }
  155. static int regs_dbg_release(struct inode *inode, struct file *file)
  156. {
  157. kfree(file->private_data);
  158. return 0;
  159. }
  160. const struct file_operations queue_dbg_fops = {
  161. .owner = THIS_MODULE,
  162. .open = queue_dbg_open,
  163. .llseek = no_llseek,
  164. .read = queue_dbg_read,
  165. .release = queue_dbg_release,
  166. };
  167. const struct file_operations regs_dbg_fops = {
  168. .owner = THIS_MODULE,
  169. .open = regs_dbg_open,
  170. .llseek = generic_file_llseek,
  171. .read = regs_dbg_read,
  172. .release = regs_dbg_release,
  173. };
  174. static void usba_ep_init_debugfs(struct usba_udc *udc,
  175. struct usba_ep *ep)
  176. {
  177. struct dentry *ep_root;
  178. ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
  179. if (!ep_root)
  180. goto err_root;
  181. ep->debugfs_dir = ep_root;
  182. ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
  183. ep, &queue_dbg_fops);
  184. if (!ep->debugfs_queue)
  185. goto err_queue;
  186. if (ep->can_dma) {
  187. ep->debugfs_dma_status
  188. = debugfs_create_u32("dma_status", 0400, ep_root,
  189. &ep->last_dma_status);
  190. if (!ep->debugfs_dma_status)
  191. goto err_dma_status;
  192. }
  193. if (ep_is_control(ep)) {
  194. ep->debugfs_state
  195. = debugfs_create_u32("state", 0400, ep_root,
  196. &ep->state);
  197. if (!ep->debugfs_state)
  198. goto err_state;
  199. }
  200. return;
  201. err_state:
  202. if (ep->can_dma)
  203. debugfs_remove(ep->debugfs_dma_status);
  204. err_dma_status:
  205. debugfs_remove(ep->debugfs_queue);
  206. err_queue:
  207. debugfs_remove(ep_root);
  208. err_root:
  209. dev_err(&ep->udc->pdev->dev,
  210. "failed to create debugfs directory for %s\n", ep->ep.name);
  211. }
  212. static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  213. {
  214. debugfs_remove(ep->debugfs_queue);
  215. debugfs_remove(ep->debugfs_dma_status);
  216. debugfs_remove(ep->debugfs_state);
  217. debugfs_remove(ep->debugfs_dir);
  218. ep->debugfs_dma_status = NULL;
  219. ep->debugfs_dir = NULL;
  220. }
  221. static void usba_init_debugfs(struct usba_udc *udc)
  222. {
  223. struct dentry *root, *regs;
  224. struct resource *regs_resource;
  225. root = debugfs_create_dir(udc->gadget.name, NULL);
  226. if (IS_ERR(root) || !root)
  227. goto err_root;
  228. udc->debugfs_root = root;
  229. regs = debugfs_create_file("regs", 0400, root, udc, &regs_dbg_fops);
  230. if (!regs)
  231. goto err_regs;
  232. regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
  233. CTRL_IOMEM_ID);
  234. regs->d_inode->i_size = regs_resource->end - regs_resource->start + 1;
  235. udc->debugfs_regs = regs;
  236. usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
  237. return;
  238. err_regs:
  239. debugfs_remove(root);
  240. err_root:
  241. udc->debugfs_root = NULL;
  242. dev_err(&udc->pdev->dev, "debugfs is not available\n");
  243. }
  244. static void usba_cleanup_debugfs(struct usba_udc *udc)
  245. {
  246. usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
  247. debugfs_remove(udc->debugfs_regs);
  248. debugfs_remove(udc->debugfs_root);
  249. udc->debugfs_regs = NULL;
  250. udc->debugfs_root = NULL;
  251. }
  252. #else
  253. static inline void usba_ep_init_debugfs(struct usba_udc *udc,
  254. struct usba_ep *ep)
  255. {
  256. }
  257. static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  258. {
  259. }
  260. static inline void usba_init_debugfs(struct usba_udc *udc)
  261. {
  262. }
  263. static inline void usba_cleanup_debugfs(struct usba_udc *udc)
  264. {
  265. }
  266. #endif
  267. static int vbus_is_present(struct usba_udc *udc)
  268. {
  269. if (gpio_is_valid(udc->vbus_pin))
  270. return gpio_get_value(udc->vbus_pin) ^ udc->vbus_pin_inverted;
  271. /* No Vbus detection: Assume always present */
  272. return 1;
  273. }
  274. #if defined(CONFIG_ARCH_AT91SAM9RL)
  275. #include <mach/at91_pmc.h>
  276. static void toggle_bias(int is_on)
  277. {
  278. unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
  279. if (is_on)
  280. at91_sys_write(AT91_CKGR_UCKR, uckr | AT91_PMC_BIASEN);
  281. else
  282. at91_sys_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
  283. }
  284. #else
  285. static void toggle_bias(int is_on)
  286. {
  287. }
  288. #endif /* CONFIG_ARCH_AT91SAM9RL */
  289. static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
  290. {
  291. unsigned int transaction_len;
  292. transaction_len = req->req.length - req->req.actual;
  293. req->last_transaction = 1;
  294. if (transaction_len > ep->ep.maxpacket) {
  295. transaction_len = ep->ep.maxpacket;
  296. req->last_transaction = 0;
  297. } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
  298. req->last_transaction = 0;
  299. DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
  300. ep->ep.name, req, transaction_len,
  301. req->last_transaction ? ", done" : "");
  302. memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
  303. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  304. req->req.actual += transaction_len;
  305. }
  306. static void submit_request(struct usba_ep *ep, struct usba_request *req)
  307. {
  308. DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
  309. ep->ep.name, req, req->req.length);
  310. req->req.actual = 0;
  311. req->submitted = 1;
  312. if (req->using_dma) {
  313. if (req->req.length == 0) {
  314. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  315. return;
  316. }
  317. if (req->req.zero)
  318. usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
  319. else
  320. usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
  321. usba_dma_writel(ep, ADDRESS, req->req.dma);
  322. usba_dma_writel(ep, CONTROL, req->ctrl);
  323. } else {
  324. next_fifo_transaction(ep, req);
  325. if (req->last_transaction) {
  326. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  327. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  328. } else {
  329. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  330. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  331. }
  332. }
  333. }
  334. static void submit_next_request(struct usba_ep *ep)
  335. {
  336. struct usba_request *req;
  337. if (list_empty(&ep->queue)) {
  338. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
  339. return;
  340. }
  341. req = list_entry(ep->queue.next, struct usba_request, queue);
  342. if (!req->submitted)
  343. submit_request(ep, req);
  344. }
  345. static void send_status(struct usba_udc *udc, struct usba_ep *ep)
  346. {
  347. ep->state = STATUS_STAGE_IN;
  348. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  349. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  350. }
  351. static void receive_data(struct usba_ep *ep)
  352. {
  353. struct usba_udc *udc = ep->udc;
  354. struct usba_request *req;
  355. unsigned long status;
  356. unsigned int bytecount, nr_busy;
  357. int is_complete = 0;
  358. status = usba_ep_readl(ep, STA);
  359. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  360. DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
  361. while (nr_busy > 0) {
  362. if (list_empty(&ep->queue)) {
  363. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  364. break;
  365. }
  366. req = list_entry(ep->queue.next,
  367. struct usba_request, queue);
  368. bytecount = USBA_BFEXT(BYTE_COUNT, status);
  369. if (status & (1 << 31))
  370. is_complete = 1;
  371. if (req->req.actual + bytecount >= req->req.length) {
  372. is_complete = 1;
  373. bytecount = req->req.length - req->req.actual;
  374. }
  375. memcpy_fromio(req->req.buf + req->req.actual,
  376. ep->fifo, bytecount);
  377. req->req.actual += bytecount;
  378. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  379. if (is_complete) {
  380. DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
  381. req->req.status = 0;
  382. list_del_init(&req->queue);
  383. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  384. spin_unlock(&udc->lock);
  385. req->req.complete(&ep->ep, &req->req);
  386. spin_lock(&udc->lock);
  387. }
  388. status = usba_ep_readl(ep, STA);
  389. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  390. if (is_complete && ep_is_control(ep)) {
  391. send_status(udc, ep);
  392. break;
  393. }
  394. }
  395. }
  396. static void
  397. request_complete(struct usba_ep *ep, struct usba_request *req, int status)
  398. {
  399. struct usba_udc *udc = ep->udc;
  400. WARN_ON(!list_empty(&req->queue));
  401. if (req->req.status == -EINPROGRESS)
  402. req->req.status = status;
  403. if (req->mapped) {
  404. dma_unmap_single(
  405. &udc->pdev->dev, req->req.dma, req->req.length,
  406. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  407. req->req.dma = DMA_ADDR_INVALID;
  408. req->mapped = 0;
  409. }
  410. DBG(DBG_GADGET | DBG_REQ,
  411. "%s: req %p complete: status %d, actual %u\n",
  412. ep->ep.name, req, req->req.status, req->req.actual);
  413. spin_unlock(&udc->lock);
  414. req->req.complete(&ep->ep, &req->req);
  415. spin_lock(&udc->lock);
  416. }
  417. static void
  418. request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
  419. {
  420. struct usba_request *req, *tmp_req;
  421. list_for_each_entry_safe(req, tmp_req, list, queue) {
  422. list_del_init(&req->queue);
  423. request_complete(ep, req, status);
  424. }
  425. }
  426. static int
  427. usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
  428. {
  429. struct usba_ep *ep = to_usba_ep(_ep);
  430. struct usba_udc *udc = ep->udc;
  431. unsigned long flags, ept_cfg, maxpacket;
  432. unsigned int nr_trans;
  433. DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
  434. maxpacket = le16_to_cpu(desc->wMaxPacketSize) & 0x7ff;
  435. if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
  436. || ep->index == 0
  437. || desc->bDescriptorType != USB_DT_ENDPOINT
  438. || maxpacket == 0
  439. || maxpacket > ep->fifo_size) {
  440. DBG(DBG_ERR, "ep_enable: Invalid argument");
  441. return -EINVAL;
  442. }
  443. ep->is_isoc = 0;
  444. ep->is_in = 0;
  445. if (maxpacket <= 8)
  446. ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
  447. else
  448. /* LSB is bit 1, not 0 */
  449. ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
  450. DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
  451. ep->ep.name, ept_cfg, maxpacket);
  452. if (usb_endpoint_dir_in(desc)) {
  453. ep->is_in = 1;
  454. ept_cfg |= USBA_EPT_DIR_IN;
  455. }
  456. switch (usb_endpoint_type(desc)) {
  457. case USB_ENDPOINT_XFER_CONTROL:
  458. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
  459. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
  460. break;
  461. case USB_ENDPOINT_XFER_ISOC:
  462. if (!ep->can_isoc) {
  463. DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
  464. ep->ep.name);
  465. return -EINVAL;
  466. }
  467. /*
  468. * Bits 11:12 specify number of _additional_
  469. * transactions per microframe.
  470. */
  471. nr_trans = ((le16_to_cpu(desc->wMaxPacketSize) >> 11) & 3) + 1;
  472. if (nr_trans > 3)
  473. return -EINVAL;
  474. ep->is_isoc = 1;
  475. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
  476. /*
  477. * Do triple-buffering on high-bandwidth iso endpoints.
  478. */
  479. if (nr_trans > 1 && ep->nr_banks == 3)
  480. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_TRIPLE);
  481. else
  482. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  483. ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
  484. break;
  485. case USB_ENDPOINT_XFER_BULK:
  486. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
  487. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  488. break;
  489. case USB_ENDPOINT_XFER_INT:
  490. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
  491. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  492. break;
  493. }
  494. spin_lock_irqsave(&ep->udc->lock, flags);
  495. if (ep->desc) {
  496. spin_unlock_irqrestore(&ep->udc->lock, flags);
  497. DBG(DBG_ERR, "ep%d already enabled\n", ep->index);
  498. return -EBUSY;
  499. }
  500. ep->desc = desc;
  501. ep->ep.maxpacket = maxpacket;
  502. usba_ep_writel(ep, CFG, ept_cfg);
  503. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  504. if (ep->can_dma) {
  505. u32 ctrl;
  506. usba_writel(udc, INT_ENB,
  507. (usba_readl(udc, INT_ENB)
  508. | USBA_BF(EPT_INT, 1 << ep->index)
  509. | USBA_BF(DMA_INT, 1 << ep->index)));
  510. ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
  511. usba_ep_writel(ep, CTL_ENB, ctrl);
  512. } else {
  513. usba_writel(udc, INT_ENB,
  514. (usba_readl(udc, INT_ENB)
  515. | USBA_BF(EPT_INT, 1 << ep->index)));
  516. }
  517. spin_unlock_irqrestore(&udc->lock, flags);
  518. DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
  519. (unsigned long)usba_ep_readl(ep, CFG));
  520. DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
  521. (unsigned long)usba_readl(udc, INT_ENB));
  522. return 0;
  523. }
  524. static int usba_ep_disable(struct usb_ep *_ep)
  525. {
  526. struct usba_ep *ep = to_usba_ep(_ep);
  527. struct usba_udc *udc = ep->udc;
  528. LIST_HEAD(req_list);
  529. unsigned long flags;
  530. DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
  531. spin_lock_irqsave(&udc->lock, flags);
  532. if (!ep->desc) {
  533. spin_unlock_irqrestore(&udc->lock, flags);
  534. /* REVISIT because this driver disables endpoints in
  535. * reset_all_endpoints() before calling disconnect(),
  536. * most gadget drivers would trigger this non-error ...
  537. */
  538. if (udc->gadget.speed != USB_SPEED_UNKNOWN)
  539. DBG(DBG_ERR, "ep_disable: %s not enabled\n",
  540. ep->ep.name);
  541. return -EINVAL;
  542. }
  543. ep->desc = NULL;
  544. list_splice_init(&ep->queue, &req_list);
  545. if (ep->can_dma) {
  546. usba_dma_writel(ep, CONTROL, 0);
  547. usba_dma_writel(ep, ADDRESS, 0);
  548. usba_dma_readl(ep, STATUS);
  549. }
  550. usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
  551. usba_writel(udc, INT_ENB,
  552. usba_readl(udc, INT_ENB)
  553. & ~USBA_BF(EPT_INT, 1 << ep->index));
  554. request_complete_list(ep, &req_list, -ESHUTDOWN);
  555. spin_unlock_irqrestore(&udc->lock, flags);
  556. return 0;
  557. }
  558. static struct usb_request *
  559. usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  560. {
  561. struct usba_request *req;
  562. DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
  563. req = kzalloc(sizeof(*req), gfp_flags);
  564. if (!req)
  565. return NULL;
  566. INIT_LIST_HEAD(&req->queue);
  567. req->req.dma = DMA_ADDR_INVALID;
  568. return &req->req;
  569. }
  570. static void
  571. usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
  572. {
  573. struct usba_request *req = to_usba_req(_req);
  574. DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
  575. kfree(req);
  576. }
  577. static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
  578. struct usba_request *req, gfp_t gfp_flags)
  579. {
  580. unsigned long flags;
  581. int ret;
  582. DBG(DBG_DMA, "%s: req l/%u d/%08x %c%c%c\n",
  583. ep->ep.name, req->req.length, req->req.dma,
  584. req->req.zero ? 'Z' : 'z',
  585. req->req.short_not_ok ? 'S' : 's',
  586. req->req.no_interrupt ? 'I' : 'i');
  587. if (req->req.length > 0x10000) {
  588. /* Lengths from 0 to 65536 (inclusive) are supported */
  589. DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
  590. return -EINVAL;
  591. }
  592. req->using_dma = 1;
  593. if (req->req.dma == DMA_ADDR_INVALID) {
  594. req->req.dma = dma_map_single(
  595. &udc->pdev->dev, req->req.buf, req->req.length,
  596. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  597. req->mapped = 1;
  598. } else {
  599. dma_sync_single_for_device(
  600. &udc->pdev->dev, req->req.dma, req->req.length,
  601. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  602. req->mapped = 0;
  603. }
  604. req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
  605. | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
  606. | USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
  607. if (ep->is_in)
  608. req->ctrl |= USBA_DMA_END_BUF_EN;
  609. /*
  610. * Add this request to the queue and submit for DMA if
  611. * possible. Check if we're still alive first -- we may have
  612. * received a reset since last time we checked.
  613. */
  614. ret = -ESHUTDOWN;
  615. spin_lock_irqsave(&udc->lock, flags);
  616. if (ep->desc) {
  617. if (list_empty(&ep->queue))
  618. submit_request(ep, req);
  619. list_add_tail(&req->queue, &ep->queue);
  620. ret = 0;
  621. }
  622. spin_unlock_irqrestore(&udc->lock, flags);
  623. return ret;
  624. }
  625. static int
  626. usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  627. {
  628. struct usba_request *req = to_usba_req(_req);
  629. struct usba_ep *ep = to_usba_ep(_ep);
  630. struct usba_udc *udc = ep->udc;
  631. unsigned long flags;
  632. int ret;
  633. DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
  634. ep->ep.name, req, _req->length);
  635. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN || !ep->desc)
  636. return -ESHUTDOWN;
  637. req->submitted = 0;
  638. req->using_dma = 0;
  639. req->last_transaction = 0;
  640. _req->status = -EINPROGRESS;
  641. _req->actual = 0;
  642. if (ep->can_dma)
  643. return queue_dma(udc, ep, req, gfp_flags);
  644. /* May have received a reset since last time we checked */
  645. ret = -ESHUTDOWN;
  646. spin_lock_irqsave(&udc->lock, flags);
  647. if (ep->desc) {
  648. list_add_tail(&req->queue, &ep->queue);
  649. if ((!ep_is_control(ep) && ep->is_in) ||
  650. (ep_is_control(ep)
  651. && (ep->state == DATA_STAGE_IN
  652. || ep->state == STATUS_STAGE_IN)))
  653. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  654. else
  655. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  656. ret = 0;
  657. }
  658. spin_unlock_irqrestore(&udc->lock, flags);
  659. return ret;
  660. }
  661. static void
  662. usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
  663. {
  664. req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
  665. }
  666. static int stop_dma(struct usba_ep *ep, u32 *pstatus)
  667. {
  668. unsigned int timeout;
  669. u32 status;
  670. /*
  671. * Stop the DMA controller. When writing both CH_EN
  672. * and LINK to 0, the other bits are not affected.
  673. */
  674. usba_dma_writel(ep, CONTROL, 0);
  675. /* Wait for the FIFO to empty */
  676. for (timeout = 40; timeout; --timeout) {
  677. status = usba_dma_readl(ep, STATUS);
  678. if (!(status & USBA_DMA_CH_EN))
  679. break;
  680. udelay(1);
  681. }
  682. if (pstatus)
  683. *pstatus = status;
  684. if (timeout == 0) {
  685. dev_err(&ep->udc->pdev->dev,
  686. "%s: timed out waiting for DMA FIFO to empty\n",
  687. ep->ep.name);
  688. return -ETIMEDOUT;
  689. }
  690. return 0;
  691. }
  692. static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  693. {
  694. struct usba_ep *ep = to_usba_ep(_ep);
  695. struct usba_udc *udc = ep->udc;
  696. struct usba_request *req = to_usba_req(_req);
  697. unsigned long flags;
  698. u32 status;
  699. DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
  700. ep->ep.name, req);
  701. spin_lock_irqsave(&udc->lock, flags);
  702. if (req->using_dma) {
  703. /*
  704. * If this request is currently being transferred,
  705. * stop the DMA controller and reset the FIFO.
  706. */
  707. if (ep->queue.next == &req->queue) {
  708. status = usba_dma_readl(ep, STATUS);
  709. if (status & USBA_DMA_CH_EN)
  710. stop_dma(ep, &status);
  711. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  712. ep->last_dma_status = status;
  713. #endif
  714. usba_writel(udc, EPT_RST, 1 << ep->index);
  715. usba_update_req(ep, req, status);
  716. }
  717. }
  718. /*
  719. * Errors should stop the queue from advancing until the
  720. * completion function returns.
  721. */
  722. list_del_init(&req->queue);
  723. request_complete(ep, req, -ECONNRESET);
  724. /* Process the next request if any */
  725. submit_next_request(ep);
  726. spin_unlock_irqrestore(&udc->lock, flags);
  727. return 0;
  728. }
  729. static int usba_ep_set_halt(struct usb_ep *_ep, int value)
  730. {
  731. struct usba_ep *ep = to_usba_ep(_ep);
  732. struct usba_udc *udc = ep->udc;
  733. unsigned long flags;
  734. int ret = 0;
  735. DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
  736. value ? "set" : "clear");
  737. if (!ep->desc) {
  738. DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
  739. ep->ep.name);
  740. return -ENODEV;
  741. }
  742. if (ep->is_isoc) {
  743. DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
  744. ep->ep.name);
  745. return -ENOTTY;
  746. }
  747. spin_lock_irqsave(&udc->lock, flags);
  748. /*
  749. * We can't halt IN endpoints while there are still data to be
  750. * transferred
  751. */
  752. if (!list_empty(&ep->queue)
  753. || ((value && ep->is_in && (usba_ep_readl(ep, STA)
  754. & USBA_BF(BUSY_BANKS, -1L))))) {
  755. ret = -EAGAIN;
  756. } else {
  757. if (value)
  758. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  759. else
  760. usba_ep_writel(ep, CLR_STA,
  761. USBA_FORCE_STALL | USBA_TOGGLE_CLR);
  762. usba_ep_readl(ep, STA);
  763. }
  764. spin_unlock_irqrestore(&udc->lock, flags);
  765. return ret;
  766. }
  767. static int usba_ep_fifo_status(struct usb_ep *_ep)
  768. {
  769. struct usba_ep *ep = to_usba_ep(_ep);
  770. return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  771. }
  772. static void usba_ep_fifo_flush(struct usb_ep *_ep)
  773. {
  774. struct usba_ep *ep = to_usba_ep(_ep);
  775. struct usba_udc *udc = ep->udc;
  776. usba_writel(udc, EPT_RST, 1 << ep->index);
  777. }
  778. static const struct usb_ep_ops usba_ep_ops = {
  779. .enable = usba_ep_enable,
  780. .disable = usba_ep_disable,
  781. .alloc_request = usba_ep_alloc_request,
  782. .free_request = usba_ep_free_request,
  783. .queue = usba_ep_queue,
  784. .dequeue = usba_ep_dequeue,
  785. .set_halt = usba_ep_set_halt,
  786. .fifo_status = usba_ep_fifo_status,
  787. .fifo_flush = usba_ep_fifo_flush,
  788. };
  789. static int usba_udc_get_frame(struct usb_gadget *gadget)
  790. {
  791. struct usba_udc *udc = to_usba_udc(gadget);
  792. return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
  793. }
  794. static int usba_udc_wakeup(struct usb_gadget *gadget)
  795. {
  796. struct usba_udc *udc = to_usba_udc(gadget);
  797. unsigned long flags;
  798. u32 ctrl;
  799. int ret = -EINVAL;
  800. spin_lock_irqsave(&udc->lock, flags);
  801. if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
  802. ctrl = usba_readl(udc, CTRL);
  803. usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
  804. ret = 0;
  805. }
  806. spin_unlock_irqrestore(&udc->lock, flags);
  807. return ret;
  808. }
  809. static int
  810. usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
  811. {
  812. struct usba_udc *udc = to_usba_udc(gadget);
  813. unsigned long flags;
  814. spin_lock_irqsave(&udc->lock, flags);
  815. if (is_selfpowered)
  816. udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
  817. else
  818. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  819. spin_unlock_irqrestore(&udc->lock, flags);
  820. return 0;
  821. }
  822. static const struct usb_gadget_ops usba_udc_ops = {
  823. .get_frame = usba_udc_get_frame,
  824. .wakeup = usba_udc_wakeup,
  825. .set_selfpowered = usba_udc_set_selfpowered,
  826. };
  827. static struct usb_endpoint_descriptor usba_ep0_desc = {
  828. .bLength = USB_DT_ENDPOINT_SIZE,
  829. .bDescriptorType = USB_DT_ENDPOINT,
  830. .bEndpointAddress = 0,
  831. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  832. .wMaxPacketSize = cpu_to_le16(64),
  833. /* FIXME: I have no idea what to put here */
  834. .bInterval = 1,
  835. };
  836. static void nop_release(struct device *dev)
  837. {
  838. }
  839. static struct usba_udc the_udc = {
  840. .gadget = {
  841. .ops = &usba_udc_ops,
  842. .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
  843. .is_dualspeed = 1,
  844. .name = "atmel_usba_udc",
  845. .dev = {
  846. .init_name = "gadget",
  847. .release = nop_release,
  848. },
  849. },
  850. };
  851. /*
  852. * Called with interrupts disabled and udc->lock held.
  853. */
  854. static void reset_all_endpoints(struct usba_udc *udc)
  855. {
  856. struct usba_ep *ep;
  857. struct usba_request *req, *tmp_req;
  858. usba_writel(udc, EPT_RST, ~0UL);
  859. ep = to_usba_ep(udc->gadget.ep0);
  860. list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
  861. list_del_init(&req->queue);
  862. request_complete(ep, req, -ECONNRESET);
  863. }
  864. /* NOTE: normally, the next call to the gadget driver is in
  865. * charge of disabling endpoints... usually disconnect().
  866. * The exception would be entering a high speed test mode.
  867. *
  868. * FIXME remove this code ... and retest thoroughly.
  869. */
  870. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
  871. if (ep->desc) {
  872. spin_unlock(&udc->lock);
  873. usba_ep_disable(&ep->ep);
  874. spin_lock(&udc->lock);
  875. }
  876. }
  877. }
  878. static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
  879. {
  880. struct usba_ep *ep;
  881. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  882. return to_usba_ep(udc->gadget.ep0);
  883. list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
  884. u8 bEndpointAddress;
  885. if (!ep->desc)
  886. continue;
  887. bEndpointAddress = ep->desc->bEndpointAddress;
  888. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  889. continue;
  890. if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
  891. == (wIndex & USB_ENDPOINT_NUMBER_MASK))
  892. return ep;
  893. }
  894. return NULL;
  895. }
  896. /* Called with interrupts disabled and udc->lock held */
  897. static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
  898. {
  899. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  900. ep->state = WAIT_FOR_SETUP;
  901. }
  902. static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
  903. {
  904. if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
  905. return 1;
  906. return 0;
  907. }
  908. static inline void set_address(struct usba_udc *udc, unsigned int addr)
  909. {
  910. u32 regval;
  911. DBG(DBG_BUS, "setting address %u...\n", addr);
  912. regval = usba_readl(udc, CTRL);
  913. regval = USBA_BFINS(DEV_ADDR, addr, regval);
  914. usba_writel(udc, CTRL, regval);
  915. }
  916. static int do_test_mode(struct usba_udc *udc)
  917. {
  918. static const char test_packet_buffer[] = {
  919. /* JKJKJKJK * 9 */
  920. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  921. /* JJKKJJKK * 8 */
  922. 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
  923. /* JJKKJJKK * 8 */
  924. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  925. /* JJJJJJJKKKKKKK * 8 */
  926. 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  927. 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  928. /* JJJJJJJK * 8 */
  929. 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
  930. /* {JKKKKKKK * 10}, JK */
  931. 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
  932. };
  933. struct usba_ep *ep;
  934. struct device *dev = &udc->pdev->dev;
  935. int test_mode;
  936. test_mode = udc->test_mode;
  937. /* Start from a clean slate */
  938. reset_all_endpoints(udc);
  939. switch (test_mode) {
  940. case 0x0100:
  941. /* Test_J */
  942. usba_writel(udc, TST, USBA_TST_J_MODE);
  943. dev_info(dev, "Entering Test_J mode...\n");
  944. break;
  945. case 0x0200:
  946. /* Test_K */
  947. usba_writel(udc, TST, USBA_TST_K_MODE);
  948. dev_info(dev, "Entering Test_K mode...\n");
  949. break;
  950. case 0x0300:
  951. /*
  952. * Test_SE0_NAK: Force high-speed mode and set up ep0
  953. * for Bulk IN transfers
  954. */
  955. ep = &usba_ep[0];
  956. usba_writel(udc, TST,
  957. USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
  958. usba_ep_writel(ep, CFG,
  959. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  960. | USBA_EPT_DIR_IN
  961. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  962. | USBA_BF(BK_NUMBER, 1));
  963. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  964. set_protocol_stall(udc, ep);
  965. dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
  966. } else {
  967. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  968. dev_info(dev, "Entering Test_SE0_NAK mode...\n");
  969. }
  970. break;
  971. case 0x0400:
  972. /* Test_Packet */
  973. ep = &usba_ep[0];
  974. usba_ep_writel(ep, CFG,
  975. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  976. | USBA_EPT_DIR_IN
  977. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  978. | USBA_BF(BK_NUMBER, 1));
  979. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  980. set_protocol_stall(udc, ep);
  981. dev_err(dev, "Test_Packet: ep0 not mapped\n");
  982. } else {
  983. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  984. usba_writel(udc, TST, USBA_TST_PKT_MODE);
  985. memcpy_toio(ep->fifo, test_packet_buffer,
  986. sizeof(test_packet_buffer));
  987. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  988. dev_info(dev, "Entering Test_Packet mode...\n");
  989. }
  990. break;
  991. default:
  992. dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
  993. return -EINVAL;
  994. }
  995. return 0;
  996. }
  997. /* Avoid overly long expressions */
  998. static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
  999. {
  1000. if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
  1001. return true;
  1002. return false;
  1003. }
  1004. static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
  1005. {
  1006. if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE))
  1007. return true;
  1008. return false;
  1009. }
  1010. static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
  1011. {
  1012. if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT))
  1013. return true;
  1014. return false;
  1015. }
  1016. static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
  1017. struct usb_ctrlrequest *crq)
  1018. {
  1019. int retval = 0;
  1020. switch (crq->bRequest) {
  1021. case USB_REQ_GET_STATUS: {
  1022. u16 status;
  1023. if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
  1024. status = cpu_to_le16(udc->devstatus);
  1025. } else if (crq->bRequestType
  1026. == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
  1027. status = cpu_to_le16(0);
  1028. } else if (crq->bRequestType
  1029. == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
  1030. struct usba_ep *target;
  1031. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1032. if (!target)
  1033. goto stall;
  1034. status = 0;
  1035. if (is_stalled(udc, target))
  1036. status |= cpu_to_le16(1);
  1037. } else
  1038. goto delegate;
  1039. /* Write directly to the FIFO. No queueing is done. */
  1040. if (crq->wLength != cpu_to_le16(sizeof(status)))
  1041. goto stall;
  1042. ep->state = DATA_STAGE_IN;
  1043. __raw_writew(status, ep->fifo);
  1044. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1045. break;
  1046. }
  1047. case USB_REQ_CLEAR_FEATURE: {
  1048. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1049. if (feature_is_dev_remote_wakeup(crq))
  1050. udc->devstatus
  1051. &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
  1052. else
  1053. /* Can't CLEAR_FEATURE TEST_MODE */
  1054. goto stall;
  1055. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1056. struct usba_ep *target;
  1057. if (crq->wLength != cpu_to_le16(0)
  1058. || !feature_is_ep_halt(crq))
  1059. goto stall;
  1060. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1061. if (!target)
  1062. goto stall;
  1063. usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
  1064. if (target->index != 0)
  1065. usba_ep_writel(target, CLR_STA,
  1066. USBA_TOGGLE_CLR);
  1067. } else {
  1068. goto delegate;
  1069. }
  1070. send_status(udc, ep);
  1071. break;
  1072. }
  1073. case USB_REQ_SET_FEATURE: {
  1074. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1075. if (feature_is_dev_test_mode(crq)) {
  1076. send_status(udc, ep);
  1077. ep->state = STATUS_STAGE_TEST;
  1078. udc->test_mode = le16_to_cpu(crq->wIndex);
  1079. return 0;
  1080. } else if (feature_is_dev_remote_wakeup(crq)) {
  1081. udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
  1082. } else {
  1083. goto stall;
  1084. }
  1085. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1086. struct usba_ep *target;
  1087. if (crq->wLength != cpu_to_le16(0)
  1088. || !feature_is_ep_halt(crq))
  1089. goto stall;
  1090. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1091. if (!target)
  1092. goto stall;
  1093. usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
  1094. } else
  1095. goto delegate;
  1096. send_status(udc, ep);
  1097. break;
  1098. }
  1099. case USB_REQ_SET_ADDRESS:
  1100. if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
  1101. goto delegate;
  1102. set_address(udc, le16_to_cpu(crq->wValue));
  1103. send_status(udc, ep);
  1104. ep->state = STATUS_STAGE_ADDR;
  1105. break;
  1106. default:
  1107. delegate:
  1108. spin_unlock(&udc->lock);
  1109. retval = udc->driver->setup(&udc->gadget, crq);
  1110. spin_lock(&udc->lock);
  1111. }
  1112. return retval;
  1113. stall:
  1114. pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
  1115. "halting endpoint...\n",
  1116. ep->ep.name, crq->bRequestType, crq->bRequest,
  1117. le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
  1118. le16_to_cpu(crq->wLength));
  1119. set_protocol_stall(udc, ep);
  1120. return -1;
  1121. }
  1122. static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
  1123. {
  1124. struct usba_request *req;
  1125. u32 epstatus;
  1126. u32 epctrl;
  1127. restart:
  1128. epstatus = usba_ep_readl(ep, STA);
  1129. epctrl = usba_ep_readl(ep, CTL);
  1130. DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
  1131. ep->ep.name, ep->state, epstatus, epctrl);
  1132. req = NULL;
  1133. if (!list_empty(&ep->queue))
  1134. req = list_entry(ep->queue.next,
  1135. struct usba_request, queue);
  1136. if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1137. if (req->submitted)
  1138. next_fifo_transaction(ep, req);
  1139. else
  1140. submit_request(ep, req);
  1141. if (req->last_transaction) {
  1142. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1143. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  1144. }
  1145. goto restart;
  1146. }
  1147. if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
  1148. usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
  1149. switch (ep->state) {
  1150. case DATA_STAGE_IN:
  1151. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  1152. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1153. ep->state = STATUS_STAGE_OUT;
  1154. break;
  1155. case STATUS_STAGE_ADDR:
  1156. /* Activate our new address */
  1157. usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
  1158. | USBA_FADDR_EN));
  1159. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1160. ep->state = WAIT_FOR_SETUP;
  1161. break;
  1162. case STATUS_STAGE_IN:
  1163. if (req) {
  1164. list_del_init(&req->queue);
  1165. request_complete(ep, req, 0);
  1166. submit_next_request(ep);
  1167. }
  1168. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1169. ep->state = WAIT_FOR_SETUP;
  1170. break;
  1171. case STATUS_STAGE_TEST:
  1172. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1173. ep->state = WAIT_FOR_SETUP;
  1174. if (do_test_mode(udc))
  1175. set_protocol_stall(udc, ep);
  1176. break;
  1177. default:
  1178. pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
  1179. "halting endpoint...\n",
  1180. ep->ep.name, ep->state);
  1181. set_protocol_stall(udc, ep);
  1182. break;
  1183. }
  1184. goto restart;
  1185. }
  1186. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1187. switch (ep->state) {
  1188. case STATUS_STAGE_OUT:
  1189. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1190. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1191. if (req) {
  1192. list_del_init(&req->queue);
  1193. request_complete(ep, req, 0);
  1194. }
  1195. ep->state = WAIT_FOR_SETUP;
  1196. break;
  1197. case DATA_STAGE_OUT:
  1198. receive_data(ep);
  1199. break;
  1200. default:
  1201. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1202. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1203. pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
  1204. "halting endpoint...\n",
  1205. ep->ep.name, ep->state);
  1206. set_protocol_stall(udc, ep);
  1207. break;
  1208. }
  1209. goto restart;
  1210. }
  1211. if (epstatus & USBA_RX_SETUP) {
  1212. union {
  1213. struct usb_ctrlrequest crq;
  1214. unsigned long data[2];
  1215. } crq;
  1216. unsigned int pkt_len;
  1217. int ret;
  1218. if (ep->state != WAIT_FOR_SETUP) {
  1219. /*
  1220. * Didn't expect a SETUP packet at this
  1221. * point. Clean up any pending requests (which
  1222. * may be successful).
  1223. */
  1224. int status = -EPROTO;
  1225. /*
  1226. * RXRDY and TXCOMP are dropped when SETUP
  1227. * packets arrive. Just pretend we received
  1228. * the status packet.
  1229. */
  1230. if (ep->state == STATUS_STAGE_OUT
  1231. || ep->state == STATUS_STAGE_IN) {
  1232. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1233. status = 0;
  1234. }
  1235. if (req) {
  1236. list_del_init(&req->queue);
  1237. request_complete(ep, req, status);
  1238. }
  1239. }
  1240. pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  1241. DBG(DBG_HW, "Packet length: %u\n", pkt_len);
  1242. if (pkt_len != sizeof(crq)) {
  1243. pr_warning("udc: Invalid packet length %u "
  1244. "(expected %zu)\n", pkt_len, sizeof(crq));
  1245. set_protocol_stall(udc, ep);
  1246. return;
  1247. }
  1248. DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
  1249. memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
  1250. /* Free up one bank in the FIFO so that we can
  1251. * generate or receive a reply right away. */
  1252. usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
  1253. /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
  1254. ep->state, crq.crq.bRequestType,
  1255. crq.crq.bRequest); */
  1256. if (crq.crq.bRequestType & USB_DIR_IN) {
  1257. /*
  1258. * The USB 2.0 spec states that "if wLength is
  1259. * zero, there is no data transfer phase."
  1260. * However, testusb #14 seems to actually
  1261. * expect a data phase even if wLength = 0...
  1262. */
  1263. ep->state = DATA_STAGE_IN;
  1264. } else {
  1265. if (crq.crq.wLength != cpu_to_le16(0))
  1266. ep->state = DATA_STAGE_OUT;
  1267. else
  1268. ep->state = STATUS_STAGE_IN;
  1269. }
  1270. ret = -1;
  1271. if (ep->index == 0)
  1272. ret = handle_ep0_setup(udc, ep, &crq.crq);
  1273. else {
  1274. spin_unlock(&udc->lock);
  1275. ret = udc->driver->setup(&udc->gadget, &crq.crq);
  1276. spin_lock(&udc->lock);
  1277. }
  1278. DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
  1279. crq.crq.bRequestType, crq.crq.bRequest,
  1280. le16_to_cpu(crq.crq.wLength), ep->state, ret);
  1281. if (ret < 0) {
  1282. /* Let the host know that we failed */
  1283. set_protocol_stall(udc, ep);
  1284. }
  1285. }
  1286. }
  1287. static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
  1288. {
  1289. struct usba_request *req;
  1290. u32 epstatus;
  1291. u32 epctrl;
  1292. epstatus = usba_ep_readl(ep, STA);
  1293. epctrl = usba_ep_readl(ep, CTL);
  1294. DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
  1295. while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1296. DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
  1297. if (list_empty(&ep->queue)) {
  1298. dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
  1299. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1300. return;
  1301. }
  1302. req = list_entry(ep->queue.next, struct usba_request, queue);
  1303. if (req->using_dma) {
  1304. /* Send a zero-length packet */
  1305. usba_ep_writel(ep, SET_STA,
  1306. USBA_TX_PK_RDY);
  1307. usba_ep_writel(ep, CTL_DIS,
  1308. USBA_TX_PK_RDY);
  1309. list_del_init(&req->queue);
  1310. submit_next_request(ep);
  1311. request_complete(ep, req, 0);
  1312. } else {
  1313. if (req->submitted)
  1314. next_fifo_transaction(ep, req);
  1315. else
  1316. submit_request(ep, req);
  1317. if (req->last_transaction) {
  1318. list_del_init(&req->queue);
  1319. submit_next_request(ep);
  1320. request_complete(ep, req, 0);
  1321. }
  1322. }
  1323. epstatus = usba_ep_readl(ep, STA);
  1324. epctrl = usba_ep_readl(ep, CTL);
  1325. }
  1326. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1327. DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
  1328. receive_data(ep);
  1329. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1330. }
  1331. }
  1332. static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
  1333. {
  1334. struct usba_request *req;
  1335. u32 status, control, pending;
  1336. status = usba_dma_readl(ep, STATUS);
  1337. control = usba_dma_readl(ep, CONTROL);
  1338. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  1339. ep->last_dma_status = status;
  1340. #endif
  1341. pending = status & control;
  1342. DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
  1343. if (status & USBA_DMA_CH_EN) {
  1344. dev_err(&udc->pdev->dev,
  1345. "DMA_CH_EN is set after transfer is finished!\n");
  1346. dev_err(&udc->pdev->dev,
  1347. "status=%#08x, pending=%#08x, control=%#08x\n",
  1348. status, pending, control);
  1349. /*
  1350. * try to pretend nothing happened. We might have to
  1351. * do something here...
  1352. */
  1353. }
  1354. if (list_empty(&ep->queue))
  1355. /* Might happen if a reset comes along at the right moment */
  1356. return;
  1357. if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
  1358. req = list_entry(ep->queue.next, struct usba_request, queue);
  1359. usba_update_req(ep, req, status);
  1360. list_del_init(&req->queue);
  1361. submit_next_request(ep);
  1362. request_complete(ep, req, 0);
  1363. }
  1364. }
  1365. static irqreturn_t usba_udc_irq(int irq, void *devid)
  1366. {
  1367. struct usba_udc *udc = devid;
  1368. u32 status;
  1369. u32 dma_status;
  1370. u32 ep_status;
  1371. spin_lock(&udc->lock);
  1372. status = usba_readl(udc, INT_STA);
  1373. DBG(DBG_INT, "irq, status=%#08x\n", status);
  1374. if (status & USBA_DET_SUSPEND) {
  1375. toggle_bias(0);
  1376. usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
  1377. DBG(DBG_BUS, "Suspend detected\n");
  1378. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1379. && udc->driver && udc->driver->suspend) {
  1380. spin_unlock(&udc->lock);
  1381. udc->driver->suspend(&udc->gadget);
  1382. spin_lock(&udc->lock);
  1383. }
  1384. }
  1385. if (status & USBA_WAKE_UP) {
  1386. toggle_bias(1);
  1387. usba_writel(udc, INT_CLR, USBA_WAKE_UP);
  1388. DBG(DBG_BUS, "Wake Up CPU detected\n");
  1389. }
  1390. if (status & USBA_END_OF_RESUME) {
  1391. usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
  1392. DBG(DBG_BUS, "Resume detected\n");
  1393. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1394. && udc->driver && udc->driver->resume) {
  1395. spin_unlock(&udc->lock);
  1396. udc->driver->resume(&udc->gadget);
  1397. spin_lock(&udc->lock);
  1398. }
  1399. }
  1400. dma_status = USBA_BFEXT(DMA_INT, status);
  1401. if (dma_status) {
  1402. int i;
  1403. for (i = 1; i < USBA_NR_ENDPOINTS; i++)
  1404. if (dma_status & (1 << i))
  1405. usba_dma_irq(udc, &usba_ep[i]);
  1406. }
  1407. ep_status = USBA_BFEXT(EPT_INT, status);
  1408. if (ep_status) {
  1409. int i;
  1410. for (i = 0; i < USBA_NR_ENDPOINTS; i++)
  1411. if (ep_status & (1 << i)) {
  1412. if (ep_is_control(&usba_ep[i]))
  1413. usba_control_irq(udc, &usba_ep[i]);
  1414. else
  1415. usba_ep_irq(udc, &usba_ep[i]);
  1416. }
  1417. }
  1418. if (status & USBA_END_OF_RESET) {
  1419. struct usba_ep *ep0;
  1420. usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
  1421. reset_all_endpoints(udc);
  1422. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1423. && udc->driver->disconnect) {
  1424. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1425. spin_unlock(&udc->lock);
  1426. udc->driver->disconnect(&udc->gadget);
  1427. spin_lock(&udc->lock);
  1428. }
  1429. if (status & USBA_HIGH_SPEED) {
  1430. DBG(DBG_BUS, "High-speed bus reset detected\n");
  1431. udc->gadget.speed = USB_SPEED_HIGH;
  1432. } else {
  1433. DBG(DBG_BUS, "Full-speed bus reset detected\n");
  1434. udc->gadget.speed = USB_SPEED_FULL;
  1435. }
  1436. ep0 = &usba_ep[0];
  1437. ep0->desc = &usba_ep0_desc;
  1438. ep0->state = WAIT_FOR_SETUP;
  1439. usba_ep_writel(ep0, CFG,
  1440. (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
  1441. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
  1442. | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
  1443. usba_ep_writel(ep0, CTL_ENB,
  1444. USBA_EPT_ENABLE | USBA_RX_SETUP);
  1445. usba_writel(udc, INT_ENB,
  1446. (usba_readl(udc, INT_ENB)
  1447. | USBA_BF(EPT_INT, 1)
  1448. | USBA_DET_SUSPEND
  1449. | USBA_END_OF_RESUME));
  1450. /*
  1451. * Unclear why we hit this irregularly, e.g. in usbtest,
  1452. * but it's clearly harmless...
  1453. */
  1454. if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
  1455. dev_dbg(&udc->pdev->dev,
  1456. "ODD: EP0 configuration is invalid!\n");
  1457. }
  1458. spin_unlock(&udc->lock);
  1459. return IRQ_HANDLED;
  1460. }
  1461. static irqreturn_t usba_vbus_irq(int irq, void *devid)
  1462. {
  1463. struct usba_udc *udc = devid;
  1464. int vbus;
  1465. /* debounce */
  1466. udelay(10);
  1467. spin_lock(&udc->lock);
  1468. /* May happen if Vbus pin toggles during probe() */
  1469. if (!udc->driver)
  1470. goto out;
  1471. vbus = vbus_is_present(udc);
  1472. if (vbus != udc->vbus_prev) {
  1473. if (vbus) {
  1474. toggle_bias(1);
  1475. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1476. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1477. } else {
  1478. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1479. reset_all_endpoints(udc);
  1480. toggle_bias(0);
  1481. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1482. if (udc->driver->disconnect) {
  1483. spin_unlock(&udc->lock);
  1484. udc->driver->disconnect(&udc->gadget);
  1485. spin_lock(&udc->lock);
  1486. }
  1487. }
  1488. udc->vbus_prev = vbus;
  1489. }
  1490. out:
  1491. spin_unlock(&udc->lock);
  1492. return IRQ_HANDLED;
  1493. }
  1494. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1495. {
  1496. struct usba_udc *udc = &the_udc;
  1497. unsigned long flags;
  1498. int ret;
  1499. if (!udc->pdev)
  1500. return -ENODEV;
  1501. spin_lock_irqsave(&udc->lock, flags);
  1502. if (udc->driver) {
  1503. spin_unlock_irqrestore(&udc->lock, flags);
  1504. return -EBUSY;
  1505. }
  1506. udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
  1507. udc->driver = driver;
  1508. udc->gadget.dev.driver = &driver->driver;
  1509. spin_unlock_irqrestore(&udc->lock, flags);
  1510. clk_enable(udc->pclk);
  1511. clk_enable(udc->hclk);
  1512. ret = driver->bind(&udc->gadget);
  1513. if (ret) {
  1514. DBG(DBG_ERR, "Could not bind to driver %s: error %d\n",
  1515. driver->driver.name, ret);
  1516. goto err_driver_bind;
  1517. }
  1518. DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
  1519. udc->vbus_prev = 0;
  1520. if (gpio_is_valid(udc->vbus_pin))
  1521. enable_irq(gpio_to_irq(udc->vbus_pin));
  1522. /* If Vbus is present, enable the controller and wait for reset */
  1523. spin_lock_irqsave(&udc->lock, flags);
  1524. if (vbus_is_present(udc) && udc->vbus_prev == 0) {
  1525. toggle_bias(1);
  1526. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1527. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1528. }
  1529. spin_unlock_irqrestore(&udc->lock, flags);
  1530. return 0;
  1531. err_driver_bind:
  1532. udc->driver = NULL;
  1533. udc->gadget.dev.driver = NULL;
  1534. return ret;
  1535. }
  1536. EXPORT_SYMBOL(usb_gadget_register_driver);
  1537. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1538. {
  1539. struct usba_udc *udc = &the_udc;
  1540. unsigned long flags;
  1541. if (!udc->pdev)
  1542. return -ENODEV;
  1543. if (driver != udc->driver || !driver->unbind)
  1544. return -EINVAL;
  1545. if (gpio_is_valid(udc->vbus_pin))
  1546. disable_irq(gpio_to_irq(udc->vbus_pin));
  1547. spin_lock_irqsave(&udc->lock, flags);
  1548. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1549. reset_all_endpoints(udc);
  1550. spin_unlock_irqrestore(&udc->lock, flags);
  1551. /* This will also disable the DP pullup */
  1552. toggle_bias(0);
  1553. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1554. if (udc->driver->disconnect)
  1555. udc->driver->disconnect(&udc->gadget);
  1556. driver->unbind(&udc->gadget);
  1557. udc->gadget.dev.driver = NULL;
  1558. udc->driver = NULL;
  1559. clk_disable(udc->hclk);
  1560. clk_disable(udc->pclk);
  1561. DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
  1562. return 0;
  1563. }
  1564. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1565. static int __init usba_udc_probe(struct platform_device *pdev)
  1566. {
  1567. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1568. struct resource *regs, *fifo;
  1569. struct clk *pclk, *hclk;
  1570. struct usba_udc *udc = &the_udc;
  1571. int irq, ret, i;
  1572. regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
  1573. fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
  1574. if (!regs || !fifo || !pdata)
  1575. return -ENXIO;
  1576. irq = platform_get_irq(pdev, 0);
  1577. if (irq < 0)
  1578. return irq;
  1579. pclk = clk_get(&pdev->dev, "pclk");
  1580. if (IS_ERR(pclk))
  1581. return PTR_ERR(pclk);
  1582. hclk = clk_get(&pdev->dev, "hclk");
  1583. if (IS_ERR(hclk)) {
  1584. ret = PTR_ERR(hclk);
  1585. goto err_get_hclk;
  1586. }
  1587. spin_lock_init(&udc->lock);
  1588. udc->pdev = pdev;
  1589. udc->pclk = pclk;
  1590. udc->hclk = hclk;
  1591. udc->vbus_pin = -ENODEV;
  1592. ret = -ENOMEM;
  1593. udc->regs = ioremap(regs->start, resource_size(regs));
  1594. if (!udc->regs) {
  1595. dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
  1596. goto err_map_regs;
  1597. }
  1598. dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
  1599. (unsigned long)regs->start, udc->regs);
  1600. udc->fifo = ioremap(fifo->start, resource_size(fifo));
  1601. if (!udc->fifo) {
  1602. dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
  1603. goto err_map_fifo;
  1604. }
  1605. dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
  1606. (unsigned long)fifo->start, udc->fifo);
  1607. device_initialize(&udc->gadget.dev);
  1608. udc->gadget.dev.parent = &pdev->dev;
  1609. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1610. platform_set_drvdata(pdev, udc);
  1611. /* Make sure we start from a clean slate */
  1612. clk_enable(pclk);
  1613. toggle_bias(0);
  1614. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1615. clk_disable(pclk);
  1616. usba_ep = kzalloc(sizeof(struct usba_ep) * pdata->num_ep,
  1617. GFP_KERNEL);
  1618. if (!usba_ep)
  1619. goto err_alloc_ep;
  1620. the_udc.gadget.ep0 = &usba_ep[0].ep;
  1621. INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
  1622. usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
  1623. usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
  1624. usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
  1625. usba_ep[0].ep.ops = &usba_ep_ops;
  1626. usba_ep[0].ep.name = pdata->ep[0].name;
  1627. usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
  1628. usba_ep[0].udc = &the_udc;
  1629. INIT_LIST_HEAD(&usba_ep[0].queue);
  1630. usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
  1631. usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
  1632. usba_ep[0].index = pdata->ep[0].index;
  1633. usba_ep[0].can_dma = pdata->ep[0].can_dma;
  1634. usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
  1635. for (i = 1; i < pdata->num_ep; i++) {
  1636. struct usba_ep *ep = &usba_ep[i];
  1637. ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
  1638. ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
  1639. ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
  1640. ep->ep.ops = &usba_ep_ops;
  1641. ep->ep.name = pdata->ep[i].name;
  1642. ep->ep.maxpacket = pdata->ep[i].fifo_size;
  1643. ep->udc = &the_udc;
  1644. INIT_LIST_HEAD(&ep->queue);
  1645. ep->fifo_size = pdata->ep[i].fifo_size;
  1646. ep->nr_banks = pdata->ep[i].nr_banks;
  1647. ep->index = pdata->ep[i].index;
  1648. ep->can_dma = pdata->ep[i].can_dma;
  1649. ep->can_isoc = pdata->ep[i].can_isoc;
  1650. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1651. }
  1652. ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
  1653. if (ret) {
  1654. dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
  1655. irq, ret);
  1656. goto err_request_irq;
  1657. }
  1658. udc->irq = irq;
  1659. ret = device_add(&udc->gadget.dev);
  1660. if (ret) {
  1661. dev_dbg(&pdev->dev, "Could not add gadget: %d\n", ret);
  1662. goto err_device_add;
  1663. }
  1664. if (gpio_is_valid(pdata->vbus_pin)) {
  1665. if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
  1666. udc->vbus_pin = pdata->vbus_pin;
  1667. udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
  1668. ret = request_irq(gpio_to_irq(udc->vbus_pin),
  1669. usba_vbus_irq, 0,
  1670. "atmel_usba_udc", udc);
  1671. if (ret) {
  1672. gpio_free(udc->vbus_pin);
  1673. udc->vbus_pin = -ENODEV;
  1674. dev_warn(&udc->pdev->dev,
  1675. "failed to request vbus irq; "
  1676. "assuming always on\n");
  1677. } else {
  1678. disable_irq(gpio_to_irq(udc->vbus_pin));
  1679. }
  1680. }
  1681. }
  1682. usba_init_debugfs(udc);
  1683. for (i = 1; i < pdata->num_ep; i++)
  1684. usba_ep_init_debugfs(udc, &usba_ep[i]);
  1685. return 0;
  1686. err_device_add:
  1687. free_irq(irq, udc);
  1688. err_request_irq:
  1689. kfree(usba_ep);
  1690. err_alloc_ep:
  1691. iounmap(udc->fifo);
  1692. err_map_fifo:
  1693. iounmap(udc->regs);
  1694. err_map_regs:
  1695. clk_put(hclk);
  1696. err_get_hclk:
  1697. clk_put(pclk);
  1698. platform_set_drvdata(pdev, NULL);
  1699. return ret;
  1700. }
  1701. static int __exit usba_udc_remove(struct platform_device *pdev)
  1702. {
  1703. struct usba_udc *udc;
  1704. int i;
  1705. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1706. udc = platform_get_drvdata(pdev);
  1707. for (i = 1; i < pdata->num_ep; i++)
  1708. usba_ep_cleanup_debugfs(&usba_ep[i]);
  1709. usba_cleanup_debugfs(udc);
  1710. if (gpio_is_valid(udc->vbus_pin))
  1711. gpio_free(udc->vbus_pin);
  1712. free_irq(udc->irq, udc);
  1713. kfree(usba_ep);
  1714. iounmap(udc->fifo);
  1715. iounmap(udc->regs);
  1716. clk_put(udc->hclk);
  1717. clk_put(udc->pclk);
  1718. device_unregister(&udc->gadget.dev);
  1719. return 0;
  1720. }
  1721. static struct platform_driver udc_driver = {
  1722. .remove = __exit_p(usba_udc_remove),
  1723. .driver = {
  1724. .name = "atmel_usba_udc",
  1725. .owner = THIS_MODULE,
  1726. },
  1727. };
  1728. static int __init udc_init(void)
  1729. {
  1730. return platform_driver_probe(&udc_driver, usba_udc_probe);
  1731. }
  1732. module_init(udc_init);
  1733. static void __exit udc_exit(void)
  1734. {
  1735. platform_driver_unregister(&udc_driver);
  1736. }
  1737. module_exit(udc_exit);
  1738. MODULE_DESCRIPTION("Atmel USBA UDC driver");
  1739. MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
  1740. MODULE_LICENSE("GPL");
  1741. MODULE_ALIAS("platform:atmel_usba_udc");