pcie_pme.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506
  1. /*
  2. * PCIe Native PME support
  3. *
  4. * Copyright (C) 2007 - 2009 Intel Corp
  5. * Copyright (C) 2007 - 2009 Shaohua Li <shaohua.li@intel.com>
  6. * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License V2. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/pci.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/slab.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/device.h>
  20. #include <linux/pcieport_if.h>
  21. #include <linux/acpi.h>
  22. #include <linux/pci-acpi.h>
  23. #include <linux/pm_runtime.h>
  24. #include "../../pci.h"
  25. #include "pcie_pme.h"
  26. #define PCI_EXP_RTSTA_PME 0x10000 /* PME status */
  27. #define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
  28. /*
  29. * If set, this switch will prevent the PCIe root port PME service driver from
  30. * being registered. Consequently, the interrupt-based PCIe PME signaling will
  31. * not be used by any PCIe root ports in that case.
  32. */
  33. static bool pcie_pme_disabled;
  34. /*
  35. * The PCI Express Base Specification 2.0, Section 6.1.8, states the following:
  36. * "In order to maintain compatibility with non-PCI Express-aware system
  37. * software, system power management logic must be configured by firmware to use
  38. * the legacy mechanism of signaling PME by default. PCI Express-aware system
  39. * software must notify the firmware prior to enabling native, interrupt-based
  40. * PME signaling." However, if the platform doesn't provide us with a suitable
  41. * notification mechanism or the notification fails, it is not clear whether or
  42. * not we are supposed to use the interrupt-based PCIe PME signaling. The
  43. * switch below can be used to indicate the desired behaviour. When set, it
  44. * will make the kernel use the interrupt-based PCIe PME signaling regardless of
  45. * the platform notification status, although the kernel will attempt to notify
  46. * the platform anyway. When unset, it will prevent the kernel from using the
  47. * the interrupt-based PCIe PME signaling if the platform notification fails,
  48. * which is the default.
  49. */
  50. static bool pcie_pme_force_enable;
  51. /*
  52. * If this switch is set, MSI will not be used for PCIe PME signaling. This
  53. * causes the PCIe port driver to use INTx interrupts only, but it turns out
  54. * that using MSI for PCIe PME signaling doesn't play well with PCIe PME-based
  55. * wake-up from system sleep states.
  56. */
  57. bool pcie_pme_msi_disabled;
  58. static int __init pcie_pme_setup(char *str)
  59. {
  60. if (!strcmp(str, "off"))
  61. pcie_pme_disabled = true;
  62. else if (!strcmp(str, "force"))
  63. pcie_pme_force_enable = true;
  64. else if (!strcmp(str, "nomsi"))
  65. pcie_pme_msi_disabled = true;
  66. return 1;
  67. }
  68. __setup("pcie_pme=", pcie_pme_setup);
  69. /**
  70. * pcie_pme_platform_setup - Ensure that the kernel controls the PCIe PME.
  71. * @srv: PCIe PME root port service to use for carrying out the check.
  72. *
  73. * Notify the platform that the native PCIe PME is going to be used and return
  74. * 'true' if the control of the PCIe PME registers has been acquired from the
  75. * platform.
  76. */
  77. static bool pcie_pme_platform_setup(struct pcie_device *srv)
  78. {
  79. if (!pcie_pme_platform_notify(srv))
  80. return true;
  81. return pcie_pme_force_enable;
  82. }
  83. struct pcie_pme_service_data {
  84. spinlock_t lock;
  85. struct pcie_device *srv;
  86. struct work_struct work;
  87. bool noirq; /* Don't enable the PME interrupt used by this service. */
  88. };
  89. /**
  90. * pcie_pme_interrupt_enable - Enable/disable PCIe PME interrupt generation.
  91. * @dev: PCIe root port or event collector.
  92. * @enable: Enable or disable the interrupt.
  93. */
  94. static void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable)
  95. {
  96. int rtctl_pos;
  97. u16 rtctl;
  98. rtctl_pos = pci_pcie_cap(dev) + PCI_EXP_RTCTL;
  99. pci_read_config_word(dev, rtctl_pos, &rtctl);
  100. if (enable)
  101. rtctl |= PCI_EXP_RTCTL_PMEIE;
  102. else
  103. rtctl &= ~PCI_EXP_RTCTL_PMEIE;
  104. pci_write_config_word(dev, rtctl_pos, rtctl);
  105. }
  106. /**
  107. * pcie_pme_clear_status - Clear root port PME interrupt status.
  108. * @dev: PCIe root port or event collector.
  109. */
  110. static void pcie_pme_clear_status(struct pci_dev *dev)
  111. {
  112. int rtsta_pos;
  113. u32 rtsta;
  114. rtsta_pos = pci_pcie_cap(dev) + PCI_EXP_RTSTA;
  115. pci_read_config_dword(dev, rtsta_pos, &rtsta);
  116. rtsta |= PCI_EXP_RTSTA_PME;
  117. pci_write_config_dword(dev, rtsta_pos, rtsta);
  118. }
  119. /**
  120. * pcie_pme_walk_bus - Scan a PCI bus for devices asserting PME#.
  121. * @bus: PCI bus to scan.
  122. *
  123. * Scan given PCI bus and all buses under it for devices asserting PME#.
  124. */
  125. static bool pcie_pme_walk_bus(struct pci_bus *bus)
  126. {
  127. struct pci_dev *dev;
  128. bool ret = false;
  129. list_for_each_entry(dev, &bus->devices, bus_list) {
  130. /* Skip PCIe devices in case we started from a root port. */
  131. if (!pci_is_pcie(dev) && pci_check_pme_status(dev)) {
  132. pm_request_resume(&dev->dev);
  133. ret = true;
  134. }
  135. if (dev->subordinate && pcie_pme_walk_bus(dev->subordinate))
  136. ret = true;
  137. }
  138. return ret;
  139. }
  140. /**
  141. * pcie_pme_from_pci_bridge - Check if PCIe-PCI bridge generated a PME.
  142. * @bus: Secondary bus of the bridge.
  143. * @devfn: Device/function number to check.
  144. *
  145. * PME from PCI devices under a PCIe-PCI bridge may be converted to an in-band
  146. * PCIe PME message. In such that case the bridge should use the Requester ID
  147. * of device/function number 0 on its secondary bus.
  148. */
  149. static bool pcie_pme_from_pci_bridge(struct pci_bus *bus, u8 devfn)
  150. {
  151. struct pci_dev *dev;
  152. bool found = false;
  153. if (devfn)
  154. return false;
  155. dev = pci_dev_get(bus->self);
  156. if (!dev)
  157. return false;
  158. if (pci_is_pcie(dev) && dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
  159. down_read(&pci_bus_sem);
  160. if (pcie_pme_walk_bus(bus))
  161. found = true;
  162. up_read(&pci_bus_sem);
  163. }
  164. pci_dev_put(dev);
  165. return found;
  166. }
  167. /**
  168. * pcie_pme_handle_request - Find device that generated PME and handle it.
  169. * @port: Root port or event collector that generated the PME interrupt.
  170. * @req_id: PCIe Requester ID of the device that generated the PME.
  171. */
  172. static void pcie_pme_handle_request(struct pci_dev *port, u16 req_id)
  173. {
  174. u8 busnr = req_id >> 8, devfn = req_id & 0xff;
  175. struct pci_bus *bus;
  176. struct pci_dev *dev;
  177. bool found = false;
  178. /* First, check if the PME is from the root port itself. */
  179. if (port->devfn == devfn && port->bus->number == busnr) {
  180. if (pci_check_pme_status(port)) {
  181. pm_request_resume(&port->dev);
  182. found = true;
  183. } else {
  184. /*
  185. * Apparently, the root port generated the PME on behalf
  186. * of a non-PCIe device downstream. If this is done by
  187. * a root port, the Requester ID field in its status
  188. * register may contain either the root port's, or the
  189. * source device's information (PCI Express Base
  190. * Specification, Rev. 2.0, Section 6.1.9).
  191. */
  192. down_read(&pci_bus_sem);
  193. found = pcie_pme_walk_bus(port->subordinate);
  194. up_read(&pci_bus_sem);
  195. }
  196. goto out;
  197. }
  198. /* Second, find the bus the source device is on. */
  199. bus = pci_find_bus(pci_domain_nr(port->bus), busnr);
  200. if (!bus)
  201. goto out;
  202. /* Next, check if the PME is from a PCIe-PCI bridge. */
  203. found = pcie_pme_from_pci_bridge(bus, devfn);
  204. if (found)
  205. goto out;
  206. /* Finally, try to find the PME source on the bus. */
  207. down_read(&pci_bus_sem);
  208. list_for_each_entry(dev, &bus->devices, bus_list) {
  209. pci_dev_get(dev);
  210. if (dev->devfn == devfn) {
  211. found = true;
  212. break;
  213. }
  214. pci_dev_put(dev);
  215. }
  216. up_read(&pci_bus_sem);
  217. if (found) {
  218. /* The device is there, but we have to check its PME status. */
  219. found = pci_check_pme_status(dev);
  220. if (found)
  221. pm_request_resume(&dev->dev);
  222. pci_dev_put(dev);
  223. } else if (devfn) {
  224. /*
  225. * The device is not there, but we can still try to recover by
  226. * assuming that the PME was reported by a PCIe-PCI bridge that
  227. * used devfn different from zero.
  228. */
  229. dev_dbg(&port->dev, "PME interrupt generated for "
  230. "non-existent device %02x:%02x.%d\n",
  231. busnr, PCI_SLOT(devfn), PCI_FUNC(devfn));
  232. found = pcie_pme_from_pci_bridge(bus, 0);
  233. }
  234. out:
  235. if (!found)
  236. dev_dbg(&port->dev, "Spurious native PME interrupt!\n");
  237. }
  238. /**
  239. * pcie_pme_work_fn - Work handler for PCIe PME interrupt.
  240. * @work: Work structure giving access to service data.
  241. */
  242. static void pcie_pme_work_fn(struct work_struct *work)
  243. {
  244. struct pcie_pme_service_data *data =
  245. container_of(work, struct pcie_pme_service_data, work);
  246. struct pci_dev *port = data->srv->port;
  247. int rtsta_pos;
  248. u32 rtsta;
  249. rtsta_pos = pci_pcie_cap(port) + PCI_EXP_RTSTA;
  250. spin_lock_irq(&data->lock);
  251. for (;;) {
  252. if (data->noirq)
  253. break;
  254. pci_read_config_dword(port, rtsta_pos, &rtsta);
  255. if (rtsta & PCI_EXP_RTSTA_PME) {
  256. /*
  257. * Clear PME status of the port. If there are other
  258. * pending PMEs, the status will be set again.
  259. */
  260. pcie_pme_clear_status(port);
  261. spin_unlock_irq(&data->lock);
  262. pcie_pme_handle_request(port, rtsta & 0xffff);
  263. spin_lock_irq(&data->lock);
  264. continue;
  265. }
  266. /* No need to loop if there are no more PMEs pending. */
  267. if (!(rtsta & PCI_EXP_RTSTA_PENDING))
  268. break;
  269. spin_unlock_irq(&data->lock);
  270. cpu_relax();
  271. spin_lock_irq(&data->lock);
  272. }
  273. if (!data->noirq)
  274. pcie_pme_interrupt_enable(port, true);
  275. spin_unlock_irq(&data->lock);
  276. }
  277. /**
  278. * pcie_pme_irq - Interrupt handler for PCIe root port PME interrupt.
  279. * @irq: Interrupt vector.
  280. * @context: Interrupt context pointer.
  281. */
  282. static irqreturn_t pcie_pme_irq(int irq, void *context)
  283. {
  284. struct pci_dev *port;
  285. struct pcie_pme_service_data *data;
  286. int rtsta_pos;
  287. u32 rtsta;
  288. unsigned long flags;
  289. port = ((struct pcie_device *)context)->port;
  290. data = get_service_data((struct pcie_device *)context);
  291. rtsta_pos = pci_pcie_cap(port) + PCI_EXP_RTSTA;
  292. spin_lock_irqsave(&data->lock, flags);
  293. pci_read_config_dword(port, rtsta_pos, &rtsta);
  294. if (!(rtsta & PCI_EXP_RTSTA_PME)) {
  295. spin_unlock_irqrestore(&data->lock, flags);
  296. return IRQ_NONE;
  297. }
  298. pcie_pme_interrupt_enable(port, false);
  299. spin_unlock_irqrestore(&data->lock, flags);
  300. /* We don't use pm_wq, because it's freezable. */
  301. schedule_work(&data->work);
  302. return IRQ_HANDLED;
  303. }
  304. /**
  305. * pcie_pme_set_native - Set the PME interrupt flag for given device.
  306. * @dev: PCI device to handle.
  307. * @ign: Ignored.
  308. */
  309. static int pcie_pme_set_native(struct pci_dev *dev, void *ign)
  310. {
  311. dev_info(&dev->dev, "Signaling PME through PCIe PME interrupt\n");
  312. device_set_run_wake(&dev->dev, true);
  313. dev->pme_interrupt = true;
  314. return 0;
  315. }
  316. /**
  317. * pcie_pme_mark_devices - Set the PME interrupt flag for devices below a port.
  318. * @port: PCIe root port or event collector to handle.
  319. *
  320. * For each device below given root port, including the port itself (or for each
  321. * root complex integrated endpoint if @port is a root complex event collector)
  322. * set the flag indicating that it can signal run-time wake-up events via PCIe
  323. * PME interrupts.
  324. */
  325. static void pcie_pme_mark_devices(struct pci_dev *port)
  326. {
  327. pcie_pme_set_native(port, NULL);
  328. if (port->subordinate) {
  329. pci_walk_bus(port->subordinate, pcie_pme_set_native, NULL);
  330. } else {
  331. struct pci_bus *bus = port->bus;
  332. struct pci_dev *dev;
  333. /* Check if this is a root port event collector. */
  334. if (port->pcie_type != PCI_EXP_TYPE_RC_EC || !bus)
  335. return;
  336. down_read(&pci_bus_sem);
  337. list_for_each_entry(dev, &bus->devices, bus_list)
  338. if (pci_is_pcie(dev)
  339. && dev->pcie_type == PCI_EXP_TYPE_RC_END)
  340. pcie_pme_set_native(dev, NULL);
  341. up_read(&pci_bus_sem);
  342. }
  343. }
  344. /**
  345. * pcie_pme_probe - Initialize PCIe PME service for given root port.
  346. * @srv: PCIe service to initialize.
  347. */
  348. static int pcie_pme_probe(struct pcie_device *srv)
  349. {
  350. struct pci_dev *port;
  351. struct pcie_pme_service_data *data;
  352. int ret;
  353. if (!pcie_pme_platform_setup(srv))
  354. return -EACCES;
  355. data = kzalloc(sizeof(*data), GFP_KERNEL);
  356. if (!data)
  357. return -ENOMEM;
  358. spin_lock_init(&data->lock);
  359. INIT_WORK(&data->work, pcie_pme_work_fn);
  360. data->srv = srv;
  361. set_service_data(srv, data);
  362. port = srv->port;
  363. pcie_pme_interrupt_enable(port, false);
  364. pcie_pme_clear_status(port);
  365. ret = request_irq(srv->irq, pcie_pme_irq, IRQF_SHARED, "PCIe PME", srv);
  366. if (ret) {
  367. kfree(data);
  368. } else {
  369. pcie_pme_mark_devices(port);
  370. pcie_pme_interrupt_enable(port, true);
  371. }
  372. return ret;
  373. }
  374. /**
  375. * pcie_pme_suspend - Suspend PCIe PME service device.
  376. * @srv: PCIe service device to suspend.
  377. */
  378. static int pcie_pme_suspend(struct pcie_device *srv)
  379. {
  380. struct pcie_pme_service_data *data = get_service_data(srv);
  381. struct pci_dev *port = srv->port;
  382. spin_lock_irq(&data->lock);
  383. pcie_pme_interrupt_enable(port, false);
  384. pcie_pme_clear_status(port);
  385. data->noirq = true;
  386. spin_unlock_irq(&data->lock);
  387. synchronize_irq(srv->irq);
  388. return 0;
  389. }
  390. /**
  391. * pcie_pme_resume - Resume PCIe PME service device.
  392. * @srv - PCIe service device to resume.
  393. */
  394. static int pcie_pme_resume(struct pcie_device *srv)
  395. {
  396. struct pcie_pme_service_data *data = get_service_data(srv);
  397. struct pci_dev *port = srv->port;
  398. spin_lock_irq(&data->lock);
  399. data->noirq = false;
  400. pcie_pme_clear_status(port);
  401. pcie_pme_interrupt_enable(port, true);
  402. spin_unlock_irq(&data->lock);
  403. return 0;
  404. }
  405. /**
  406. * pcie_pme_remove - Prepare PCIe PME service device for removal.
  407. * @srv - PCIe service device to resume.
  408. */
  409. static void pcie_pme_remove(struct pcie_device *srv)
  410. {
  411. pcie_pme_suspend(srv);
  412. free_irq(srv->irq, srv);
  413. kfree(get_service_data(srv));
  414. }
  415. static struct pcie_port_service_driver pcie_pme_driver = {
  416. .name = "pcie_pme",
  417. .port_type = PCI_EXP_TYPE_ROOT_PORT,
  418. .service = PCIE_PORT_SERVICE_PME,
  419. .probe = pcie_pme_probe,
  420. .suspend = pcie_pme_suspend,
  421. .resume = pcie_pme_resume,
  422. .remove = pcie_pme_remove,
  423. };
  424. /**
  425. * pcie_pme_service_init - Register the PCIe PME service driver.
  426. */
  427. static int __init pcie_pme_service_init(void)
  428. {
  429. return pcie_pme_disabled ?
  430. -ENODEV : pcie_port_service_register(&pcie_pme_driver);
  431. }
  432. module_init(pcie_pme_service_init);