p54pci.c 16 KB

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  1. /*
  2. * Linux device driver for PCI based Prism54
  3. *
  4. * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
  5. * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
  6. *
  7. * Based on the islsm (softmac prism54) driver, which is:
  8. * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/pci.h>
  16. #include <linux/slab.h>
  17. #include <linux/firmware.h>
  18. #include <linux/etherdevice.h>
  19. #include <linux/delay.h>
  20. #include <linux/completion.h>
  21. #include <net/mac80211.h>
  22. #include "p54.h"
  23. #include "lmac.h"
  24. #include "p54pci.h"
  25. MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  26. MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  27. MODULE_LICENSE("GPL");
  28. MODULE_ALIAS("prism54pci");
  29. MODULE_FIRMWARE("isl3886pci");
  30. static DEFINE_PCI_DEVICE_TABLE(p54p_table) = {
  31. /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  32. { PCI_DEVICE(0x1260, 0x3890) },
  33. /* 3COM 3CRWE154G72 Wireless LAN adapter */
  34. { PCI_DEVICE(0x10b7, 0x6001) },
  35. /* Intersil PRISM Indigo Wireless LAN adapter */
  36. { PCI_DEVICE(0x1260, 0x3877) },
  37. /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  38. { PCI_DEVICE(0x1260, 0x3886) },
  39. { },
  40. };
  41. MODULE_DEVICE_TABLE(pci, p54p_table);
  42. static int p54p_upload_firmware(struct ieee80211_hw *dev)
  43. {
  44. struct p54p_priv *priv = dev->priv;
  45. __le32 reg;
  46. int err;
  47. __le32 *data;
  48. u32 remains, left, device_addr;
  49. P54P_WRITE(int_enable, cpu_to_le32(0));
  50. P54P_READ(int_enable);
  51. udelay(10);
  52. reg = P54P_READ(ctrl_stat);
  53. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  54. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  55. P54P_WRITE(ctrl_stat, reg);
  56. P54P_READ(ctrl_stat);
  57. udelay(10);
  58. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  59. P54P_WRITE(ctrl_stat, reg);
  60. wmb();
  61. udelay(10);
  62. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  63. P54P_WRITE(ctrl_stat, reg);
  64. wmb();
  65. /* wait for the firmware to reset properly */
  66. mdelay(10);
  67. err = p54_parse_firmware(dev, priv->firmware);
  68. if (err)
  69. return err;
  70. if (priv->common.fw_interface != FW_LM86) {
  71. dev_err(&priv->pdev->dev, "wrong firmware, "
  72. "please get a LM86(PCI) firmware a try again.\n");
  73. return -EINVAL;
  74. }
  75. data = (__le32 *) priv->firmware->data;
  76. remains = priv->firmware->size;
  77. device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  78. while (remains) {
  79. u32 i = 0;
  80. left = min((u32)0x1000, remains);
  81. P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  82. P54P_READ(int_enable);
  83. device_addr += 0x1000;
  84. while (i < left) {
  85. P54P_WRITE(direct_mem_win[i], *data++);
  86. i += sizeof(u32);
  87. }
  88. remains -= left;
  89. P54P_READ(int_enable);
  90. }
  91. reg = P54P_READ(ctrl_stat);
  92. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
  93. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  94. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
  95. P54P_WRITE(ctrl_stat, reg);
  96. P54P_READ(ctrl_stat);
  97. udelay(10);
  98. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  99. P54P_WRITE(ctrl_stat, reg);
  100. wmb();
  101. udelay(10);
  102. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  103. P54P_WRITE(ctrl_stat, reg);
  104. wmb();
  105. udelay(10);
  106. /* wait for the firmware to boot properly */
  107. mdelay(100);
  108. return 0;
  109. }
  110. static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
  111. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  112. struct sk_buff **rx_buf)
  113. {
  114. struct p54p_priv *priv = dev->priv;
  115. struct p54p_ring_control *ring_control = priv->ring_control;
  116. u32 limit, idx, i;
  117. idx = le32_to_cpu(ring_control->host_idx[ring_index]);
  118. limit = idx;
  119. limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
  120. limit = ring_limit - limit;
  121. i = idx % ring_limit;
  122. while (limit-- > 1) {
  123. struct p54p_desc *desc = &ring[i];
  124. if (!desc->host_addr) {
  125. struct sk_buff *skb;
  126. dma_addr_t mapping;
  127. skb = dev_alloc_skb(priv->common.rx_mtu + 32);
  128. if (!skb)
  129. break;
  130. mapping = pci_map_single(priv->pdev,
  131. skb_tail_pointer(skb),
  132. priv->common.rx_mtu + 32,
  133. PCI_DMA_FROMDEVICE);
  134. if (pci_dma_mapping_error(priv->pdev, mapping)) {
  135. dev_kfree_skb_any(skb);
  136. dev_err(&priv->pdev->dev,
  137. "RX DMA Mapping error\n");
  138. break;
  139. }
  140. desc->host_addr = cpu_to_le32(mapping);
  141. desc->device_addr = 0; // FIXME: necessary?
  142. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  143. desc->flags = 0;
  144. rx_buf[i] = skb;
  145. }
  146. i++;
  147. idx++;
  148. i %= ring_limit;
  149. }
  150. wmb();
  151. ring_control->host_idx[ring_index] = cpu_to_le32(idx);
  152. }
  153. static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
  154. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  155. struct sk_buff **rx_buf)
  156. {
  157. struct p54p_priv *priv = dev->priv;
  158. struct p54p_ring_control *ring_control = priv->ring_control;
  159. struct p54p_desc *desc;
  160. u32 idx, i;
  161. i = (*index) % ring_limit;
  162. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  163. idx %= ring_limit;
  164. while (i != idx) {
  165. u16 len;
  166. struct sk_buff *skb;
  167. desc = &ring[i];
  168. len = le16_to_cpu(desc->len);
  169. skb = rx_buf[i];
  170. if (!skb) {
  171. i++;
  172. i %= ring_limit;
  173. continue;
  174. }
  175. if (unlikely(len > priv->common.rx_mtu)) {
  176. if (net_ratelimit())
  177. dev_err(&priv->pdev->dev, "rx'd frame size "
  178. "exceeds length threshold.\n");
  179. len = priv->common.rx_mtu;
  180. }
  181. skb_put(skb, len);
  182. if (p54_rx(dev, skb)) {
  183. pci_unmap_single(priv->pdev,
  184. le32_to_cpu(desc->host_addr),
  185. priv->common.rx_mtu + 32,
  186. PCI_DMA_FROMDEVICE);
  187. rx_buf[i] = NULL;
  188. desc->host_addr = 0;
  189. } else {
  190. skb_trim(skb, 0);
  191. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  192. }
  193. i++;
  194. i %= ring_limit;
  195. }
  196. p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
  197. }
  198. static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
  199. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  200. struct sk_buff **tx_buf)
  201. {
  202. struct p54p_priv *priv = dev->priv;
  203. struct p54p_ring_control *ring_control = priv->ring_control;
  204. struct p54p_desc *desc;
  205. struct sk_buff *skb;
  206. u32 idx, i;
  207. i = (*index) % ring_limit;
  208. (*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
  209. idx %= ring_limit;
  210. while (i != idx) {
  211. desc = &ring[i];
  212. skb = tx_buf[i];
  213. tx_buf[i] = NULL;
  214. pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
  215. le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
  216. desc->host_addr = 0;
  217. desc->device_addr = 0;
  218. desc->len = 0;
  219. desc->flags = 0;
  220. if (skb && FREE_AFTER_TX(skb))
  221. p54_free_skb(dev, skb);
  222. i++;
  223. i %= ring_limit;
  224. }
  225. }
  226. static void p54p_tasklet(unsigned long dev_id)
  227. {
  228. struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
  229. struct p54p_priv *priv = dev->priv;
  230. struct p54p_ring_control *ring_control = priv->ring_control;
  231. p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
  232. ARRAY_SIZE(ring_control->tx_mgmt),
  233. priv->tx_buf_mgmt);
  234. p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
  235. ARRAY_SIZE(ring_control->tx_data),
  236. priv->tx_buf_data);
  237. p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
  238. ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
  239. p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
  240. ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
  241. wmb();
  242. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  243. }
  244. static irqreturn_t p54p_interrupt(int irq, void *dev_id)
  245. {
  246. struct ieee80211_hw *dev = dev_id;
  247. struct p54p_priv *priv = dev->priv;
  248. __le32 reg;
  249. reg = P54P_READ(int_ident);
  250. if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
  251. goto out;
  252. }
  253. P54P_WRITE(int_ack, reg);
  254. reg &= P54P_READ(int_enable);
  255. if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
  256. tasklet_schedule(&priv->tasklet);
  257. else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
  258. complete(&priv->boot_comp);
  259. out:
  260. return reg ? IRQ_HANDLED : IRQ_NONE;
  261. }
  262. static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
  263. {
  264. unsigned long flags;
  265. struct p54p_priv *priv = dev->priv;
  266. struct p54p_ring_control *ring_control = priv->ring_control;
  267. struct p54p_desc *desc;
  268. dma_addr_t mapping;
  269. u32 device_idx, idx, i;
  270. spin_lock_irqsave(&priv->lock, flags);
  271. device_idx = le32_to_cpu(ring_control->device_idx[1]);
  272. idx = le32_to_cpu(ring_control->host_idx[1]);
  273. i = idx % ARRAY_SIZE(ring_control->tx_data);
  274. mapping = pci_map_single(priv->pdev, skb->data, skb->len,
  275. PCI_DMA_TODEVICE);
  276. if (pci_dma_mapping_error(priv->pdev, mapping)) {
  277. spin_unlock_irqrestore(&priv->lock, flags);
  278. p54_free_skb(dev, skb);
  279. dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
  280. return ;
  281. }
  282. priv->tx_buf_data[i] = skb;
  283. desc = &ring_control->tx_data[i];
  284. desc->host_addr = cpu_to_le32(mapping);
  285. desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
  286. desc->len = cpu_to_le16(skb->len);
  287. desc->flags = 0;
  288. wmb();
  289. ring_control->host_idx[1] = cpu_to_le32(idx + 1);
  290. spin_unlock_irqrestore(&priv->lock, flags);
  291. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  292. P54P_READ(dev_int);
  293. }
  294. static void p54p_stop(struct ieee80211_hw *dev)
  295. {
  296. struct p54p_priv *priv = dev->priv;
  297. struct p54p_ring_control *ring_control = priv->ring_control;
  298. unsigned int i;
  299. struct p54p_desc *desc;
  300. P54P_WRITE(int_enable, cpu_to_le32(0));
  301. P54P_READ(int_enable);
  302. udelay(10);
  303. free_irq(priv->pdev->irq, dev);
  304. tasklet_kill(&priv->tasklet);
  305. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  306. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
  307. desc = &ring_control->rx_data[i];
  308. if (desc->host_addr)
  309. pci_unmap_single(priv->pdev,
  310. le32_to_cpu(desc->host_addr),
  311. priv->common.rx_mtu + 32,
  312. PCI_DMA_FROMDEVICE);
  313. kfree_skb(priv->rx_buf_data[i]);
  314. priv->rx_buf_data[i] = NULL;
  315. }
  316. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
  317. desc = &ring_control->rx_mgmt[i];
  318. if (desc->host_addr)
  319. pci_unmap_single(priv->pdev,
  320. le32_to_cpu(desc->host_addr),
  321. priv->common.rx_mtu + 32,
  322. PCI_DMA_FROMDEVICE);
  323. kfree_skb(priv->rx_buf_mgmt[i]);
  324. priv->rx_buf_mgmt[i] = NULL;
  325. }
  326. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
  327. desc = &ring_control->tx_data[i];
  328. if (desc->host_addr)
  329. pci_unmap_single(priv->pdev,
  330. le32_to_cpu(desc->host_addr),
  331. le16_to_cpu(desc->len),
  332. PCI_DMA_TODEVICE);
  333. p54_free_skb(dev, priv->tx_buf_data[i]);
  334. priv->tx_buf_data[i] = NULL;
  335. }
  336. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
  337. desc = &ring_control->tx_mgmt[i];
  338. if (desc->host_addr)
  339. pci_unmap_single(priv->pdev,
  340. le32_to_cpu(desc->host_addr),
  341. le16_to_cpu(desc->len),
  342. PCI_DMA_TODEVICE);
  343. p54_free_skb(dev, priv->tx_buf_mgmt[i]);
  344. priv->tx_buf_mgmt[i] = NULL;
  345. }
  346. memset(ring_control, 0, sizeof(*ring_control));
  347. }
  348. static int p54p_open(struct ieee80211_hw *dev)
  349. {
  350. struct p54p_priv *priv = dev->priv;
  351. int err;
  352. init_completion(&priv->boot_comp);
  353. err = request_irq(priv->pdev->irq, p54p_interrupt,
  354. IRQF_SHARED, "p54pci", dev);
  355. if (err) {
  356. dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
  357. return err;
  358. }
  359. memset(priv->ring_control, 0, sizeof(*priv->ring_control));
  360. err = p54p_upload_firmware(dev);
  361. if (err) {
  362. free_irq(priv->pdev->irq, dev);
  363. return err;
  364. }
  365. priv->rx_idx_data = priv->tx_idx_data = 0;
  366. priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
  367. p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
  368. ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
  369. p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
  370. ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
  371. P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
  372. P54P_READ(ring_control_base);
  373. wmb();
  374. udelay(10);
  375. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
  376. P54P_READ(int_enable);
  377. wmb();
  378. udelay(10);
  379. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  380. P54P_READ(dev_int);
  381. if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
  382. printk(KERN_ERR "%s: Cannot boot firmware!\n",
  383. wiphy_name(dev->wiphy));
  384. p54p_stop(dev);
  385. return -ETIMEDOUT;
  386. }
  387. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
  388. P54P_READ(int_enable);
  389. wmb();
  390. udelay(10);
  391. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  392. P54P_READ(dev_int);
  393. wmb();
  394. udelay(10);
  395. return 0;
  396. }
  397. static int __devinit p54p_probe(struct pci_dev *pdev,
  398. const struct pci_device_id *id)
  399. {
  400. struct p54p_priv *priv;
  401. struct ieee80211_hw *dev;
  402. unsigned long mem_addr, mem_len;
  403. int err;
  404. err = pci_enable_device(pdev);
  405. if (err) {
  406. dev_err(&pdev->dev, "Cannot enable new PCI device\n");
  407. return err;
  408. }
  409. mem_addr = pci_resource_start(pdev, 0);
  410. mem_len = pci_resource_len(pdev, 0);
  411. if (mem_len < sizeof(struct p54p_csr)) {
  412. dev_err(&pdev->dev, "Too short PCI resources\n");
  413. goto err_disable_dev;
  414. }
  415. err = pci_request_regions(pdev, "p54pci");
  416. if (err) {
  417. dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
  418. goto err_disable_dev;
  419. }
  420. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
  421. pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  422. dev_err(&pdev->dev, "No suitable DMA available\n");
  423. goto err_free_reg;
  424. }
  425. pci_set_master(pdev);
  426. pci_try_set_mwi(pdev);
  427. pci_write_config_byte(pdev, 0x40, 0);
  428. pci_write_config_byte(pdev, 0x41, 0);
  429. dev = p54_init_common(sizeof(*priv));
  430. if (!dev) {
  431. dev_err(&pdev->dev, "ieee80211 alloc failed\n");
  432. err = -ENOMEM;
  433. goto err_free_reg;
  434. }
  435. priv = dev->priv;
  436. priv->pdev = pdev;
  437. SET_IEEE80211_DEV(dev, &pdev->dev);
  438. pci_set_drvdata(pdev, dev);
  439. priv->map = ioremap(mem_addr, mem_len);
  440. if (!priv->map) {
  441. dev_err(&pdev->dev, "Cannot map device memory\n");
  442. err = -ENOMEM;
  443. goto err_free_dev;
  444. }
  445. priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
  446. &priv->ring_control_dma);
  447. if (!priv->ring_control) {
  448. dev_err(&pdev->dev, "Cannot allocate rings\n");
  449. err = -ENOMEM;
  450. goto err_iounmap;
  451. }
  452. priv->common.open = p54p_open;
  453. priv->common.stop = p54p_stop;
  454. priv->common.tx = p54p_tx;
  455. spin_lock_init(&priv->lock);
  456. tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
  457. err = request_firmware(&priv->firmware, "isl3886pci",
  458. &priv->pdev->dev);
  459. if (err) {
  460. dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
  461. err = request_firmware(&priv->firmware, "isl3886",
  462. &priv->pdev->dev);
  463. if (err)
  464. goto err_free_common;
  465. }
  466. err = p54p_open(dev);
  467. if (err)
  468. goto err_free_common;
  469. err = p54_read_eeprom(dev);
  470. p54p_stop(dev);
  471. if (err)
  472. goto err_free_common;
  473. err = p54_register_common(dev, &pdev->dev);
  474. if (err)
  475. goto err_free_common;
  476. return 0;
  477. err_free_common:
  478. release_firmware(priv->firmware);
  479. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  480. priv->ring_control, priv->ring_control_dma);
  481. err_iounmap:
  482. iounmap(priv->map);
  483. err_free_dev:
  484. pci_set_drvdata(pdev, NULL);
  485. p54_free_common(dev);
  486. err_free_reg:
  487. pci_release_regions(pdev);
  488. err_disable_dev:
  489. pci_disable_device(pdev);
  490. return err;
  491. }
  492. static void __devexit p54p_remove(struct pci_dev *pdev)
  493. {
  494. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  495. struct p54p_priv *priv;
  496. if (!dev)
  497. return;
  498. p54_unregister_common(dev);
  499. priv = dev->priv;
  500. release_firmware(priv->firmware);
  501. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  502. priv->ring_control, priv->ring_control_dma);
  503. iounmap(priv->map);
  504. pci_release_regions(pdev);
  505. pci_disable_device(pdev);
  506. p54_free_common(dev);
  507. }
  508. #ifdef CONFIG_PM
  509. static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
  510. {
  511. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  512. struct p54p_priv *priv = dev->priv;
  513. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  514. ieee80211_stop_queues(dev);
  515. p54p_stop(dev);
  516. }
  517. pci_save_state(pdev);
  518. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  519. return 0;
  520. }
  521. static int p54p_resume(struct pci_dev *pdev)
  522. {
  523. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  524. struct p54p_priv *priv = dev->priv;
  525. pci_set_power_state(pdev, PCI_D0);
  526. pci_restore_state(pdev);
  527. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  528. p54p_open(dev);
  529. ieee80211_wake_queues(dev);
  530. }
  531. return 0;
  532. }
  533. #endif /* CONFIG_PM */
  534. static struct pci_driver p54p_driver = {
  535. .name = "p54pci",
  536. .id_table = p54p_table,
  537. .probe = p54p_probe,
  538. .remove = __devexit_p(p54p_remove),
  539. #ifdef CONFIG_PM
  540. .suspend = p54p_suspend,
  541. .resume = p54p_resume,
  542. #endif /* CONFIG_PM */
  543. };
  544. static int __init p54p_init(void)
  545. {
  546. return pci_register_driver(&p54p_driver);
  547. }
  548. static void __exit p54p_exit(void)
  549. {
  550. pci_unregister_driver(&p54p_driver);
  551. }
  552. module_init(p54p_init);
  553. module_exit(p54p_exit);