recv.c 17 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "ath9k.h"
  17. static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
  18. struct ieee80211_hdr *hdr)
  19. {
  20. struct ieee80211_hw *hw = sc->pri_wiphy->hw;
  21. int i;
  22. spin_lock_bh(&sc->wiphy_lock);
  23. for (i = 0; i < sc->num_sec_wiphy; i++) {
  24. struct ath_wiphy *aphy = sc->sec_wiphy[i];
  25. if (aphy == NULL)
  26. continue;
  27. if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr)
  28. == 0) {
  29. hw = aphy->hw;
  30. break;
  31. }
  32. }
  33. spin_unlock_bh(&sc->wiphy_lock);
  34. return hw;
  35. }
  36. /*
  37. * Setup and link descriptors.
  38. *
  39. * 11N: we can no longer afford to self link the last descriptor.
  40. * MAC acknowledges BA status as long as it copies frames to host
  41. * buffer (or rx fifo). This can incorrectly acknowledge packets
  42. * to a sender if last desc is self-linked.
  43. */
  44. static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
  45. {
  46. struct ath_hw *ah = sc->sc_ah;
  47. struct ath_common *common = ath9k_hw_common(ah);
  48. struct ath_desc *ds;
  49. struct sk_buff *skb;
  50. ATH_RXBUF_RESET(bf);
  51. ds = bf->bf_desc;
  52. ds->ds_link = 0; /* link to null */
  53. ds->ds_data = bf->bf_buf_addr;
  54. /* virtual addr of the beginning of the buffer. */
  55. skb = bf->bf_mpdu;
  56. BUG_ON(skb == NULL);
  57. ds->ds_vdata = skb->data;
  58. /*
  59. * setup rx descriptors. The rx_bufsize here tells the hardware
  60. * how much data it can DMA to us and that we are prepared
  61. * to process
  62. */
  63. ath9k_hw_setuprxdesc(ah, ds,
  64. common->rx_bufsize,
  65. 0);
  66. if (sc->rx.rxlink == NULL)
  67. ath9k_hw_putrxbuf(ah, bf->bf_daddr);
  68. else
  69. *sc->rx.rxlink = bf->bf_daddr;
  70. sc->rx.rxlink = &ds->ds_link;
  71. ath9k_hw_rxena(ah);
  72. }
  73. static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
  74. {
  75. /* XXX block beacon interrupts */
  76. ath9k_hw_setantenna(sc->sc_ah, antenna);
  77. sc->rx.defant = antenna;
  78. sc->rx.rxotherant = 0;
  79. }
  80. static void ath_opmode_init(struct ath_softc *sc)
  81. {
  82. struct ath_hw *ah = sc->sc_ah;
  83. struct ath_common *common = ath9k_hw_common(ah);
  84. u32 rfilt, mfilt[2];
  85. /* configure rx filter */
  86. rfilt = ath_calcrxfilter(sc);
  87. ath9k_hw_setrxfilter(ah, rfilt);
  88. /* configure bssid mask */
  89. if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
  90. ath_hw_setbssidmask(common);
  91. /* configure operational mode */
  92. ath9k_hw_setopmode(ah);
  93. /* Handle any link-level address change. */
  94. ath9k_hw_setmac(ah, common->macaddr);
  95. /* calculate and install multicast filter */
  96. mfilt[0] = mfilt[1] = ~0;
  97. ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
  98. }
  99. int ath_rx_init(struct ath_softc *sc, int nbufs)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. struct sk_buff *skb;
  103. struct ath_buf *bf;
  104. int error = 0;
  105. spin_lock_init(&sc->rx.rxflushlock);
  106. sc->sc_flags &= ~SC_OP_RXFLUSH;
  107. spin_lock_init(&sc->rx.rxbuflock);
  108. common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
  109. min(common->cachelsz, (u16)64));
  110. ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
  111. common->cachelsz, common->rx_bufsize);
  112. /* Initialize rx descriptors */
  113. error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
  114. "rx", nbufs, 1);
  115. if (error != 0) {
  116. ath_print(common, ATH_DBG_FATAL,
  117. "failed to allocate rx descriptors: %d\n", error);
  118. goto err;
  119. }
  120. list_for_each_entry(bf, &sc->rx.rxbuf, list) {
  121. skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
  122. if (skb == NULL) {
  123. error = -ENOMEM;
  124. goto err;
  125. }
  126. bf->bf_mpdu = skb;
  127. bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
  128. common->rx_bufsize,
  129. DMA_FROM_DEVICE);
  130. if (unlikely(dma_mapping_error(sc->dev,
  131. bf->bf_buf_addr))) {
  132. dev_kfree_skb_any(skb);
  133. bf->bf_mpdu = NULL;
  134. ath_print(common, ATH_DBG_FATAL,
  135. "dma_mapping_error() on RX init\n");
  136. error = -ENOMEM;
  137. goto err;
  138. }
  139. bf->bf_dmacontext = bf->bf_buf_addr;
  140. }
  141. sc->rx.rxlink = NULL;
  142. err:
  143. if (error)
  144. ath_rx_cleanup(sc);
  145. return error;
  146. }
  147. void ath_rx_cleanup(struct ath_softc *sc)
  148. {
  149. struct ath_hw *ah = sc->sc_ah;
  150. struct ath_common *common = ath9k_hw_common(ah);
  151. struct sk_buff *skb;
  152. struct ath_buf *bf;
  153. list_for_each_entry(bf, &sc->rx.rxbuf, list) {
  154. skb = bf->bf_mpdu;
  155. if (skb) {
  156. dma_unmap_single(sc->dev, bf->bf_buf_addr,
  157. common->rx_bufsize, DMA_FROM_DEVICE);
  158. dev_kfree_skb(skb);
  159. }
  160. }
  161. if (sc->rx.rxdma.dd_desc_len != 0)
  162. ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
  163. }
  164. /*
  165. * Calculate the receive filter according to the
  166. * operating mode and state:
  167. *
  168. * o always accept unicast, broadcast, and multicast traffic
  169. * o maintain current state of phy error reception (the hal
  170. * may enable phy error frames for noise immunity work)
  171. * o probe request frames are accepted only when operating in
  172. * hostap, adhoc, or monitor modes
  173. * o enable promiscuous mode according to the interface state
  174. * o accept beacons:
  175. * - when operating in adhoc mode so the 802.11 layer creates
  176. * node table entries for peers,
  177. * - when operating in station mode for collecting rssi data when
  178. * the station is otherwise quiet, or
  179. * - when operating as a repeater so we see repeater-sta beacons
  180. * - when scanning
  181. */
  182. u32 ath_calcrxfilter(struct ath_softc *sc)
  183. {
  184. #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
  185. u32 rfilt;
  186. rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
  187. | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
  188. | ATH9K_RX_FILTER_MCAST;
  189. /* If not a STA, enable processing of Probe Requests */
  190. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  191. rfilt |= ATH9K_RX_FILTER_PROBEREQ;
  192. /*
  193. * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
  194. * mode interface or when in monitor mode. AP mode does not need this
  195. * since it receives all in-BSS frames anyway.
  196. */
  197. if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) &&
  198. (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) ||
  199. (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR))
  200. rfilt |= ATH9K_RX_FILTER_PROM;
  201. if (sc->rx.rxfilter & FIF_CONTROL)
  202. rfilt |= ATH9K_RX_FILTER_CONTROL;
  203. if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
  204. !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
  205. rfilt |= ATH9K_RX_FILTER_MYBEACON;
  206. else
  207. rfilt |= ATH9K_RX_FILTER_BEACON;
  208. if ((AR_SREV_9280_10_OR_LATER(sc->sc_ah) ||
  209. AR_SREV_9285_10_OR_LATER(sc->sc_ah)) &&
  210. (sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
  211. (sc->rx.rxfilter & FIF_PSPOLL))
  212. rfilt |= ATH9K_RX_FILTER_PSPOLL;
  213. if (conf_is_ht(&sc->hw->conf))
  214. rfilt |= ATH9K_RX_FILTER_COMP_BAR;
  215. if (sc->sec_wiphy || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
  216. /* TODO: only needed if more than one BSSID is in use in
  217. * station/adhoc mode */
  218. /* The following may also be needed for other older chips */
  219. if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
  220. rfilt |= ATH9K_RX_FILTER_PROM;
  221. rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
  222. }
  223. return rfilt;
  224. #undef RX_FILTER_PRESERVE
  225. }
  226. int ath_startrecv(struct ath_softc *sc)
  227. {
  228. struct ath_hw *ah = sc->sc_ah;
  229. struct ath_buf *bf, *tbf;
  230. spin_lock_bh(&sc->rx.rxbuflock);
  231. if (list_empty(&sc->rx.rxbuf))
  232. goto start_recv;
  233. sc->rx.rxlink = NULL;
  234. list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
  235. ath_rx_buf_link(sc, bf);
  236. }
  237. /* We could have deleted elements so the list may be empty now */
  238. if (list_empty(&sc->rx.rxbuf))
  239. goto start_recv;
  240. bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
  241. ath9k_hw_putrxbuf(ah, bf->bf_daddr);
  242. ath9k_hw_rxena(ah);
  243. start_recv:
  244. spin_unlock_bh(&sc->rx.rxbuflock);
  245. ath_opmode_init(sc);
  246. ath9k_hw_startpcureceive(ah);
  247. return 0;
  248. }
  249. bool ath_stoprecv(struct ath_softc *sc)
  250. {
  251. struct ath_hw *ah = sc->sc_ah;
  252. bool stopped;
  253. ath9k_hw_stoppcurecv(ah);
  254. ath9k_hw_setrxfilter(ah, 0);
  255. stopped = ath9k_hw_stopdmarecv(ah);
  256. sc->rx.rxlink = NULL;
  257. return stopped;
  258. }
  259. void ath_flushrecv(struct ath_softc *sc)
  260. {
  261. spin_lock_bh(&sc->rx.rxflushlock);
  262. sc->sc_flags |= SC_OP_RXFLUSH;
  263. ath_rx_tasklet(sc, 1);
  264. sc->sc_flags &= ~SC_OP_RXFLUSH;
  265. spin_unlock_bh(&sc->rx.rxflushlock);
  266. }
  267. static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
  268. {
  269. /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
  270. struct ieee80211_mgmt *mgmt;
  271. u8 *pos, *end, id, elen;
  272. struct ieee80211_tim_ie *tim;
  273. mgmt = (struct ieee80211_mgmt *)skb->data;
  274. pos = mgmt->u.beacon.variable;
  275. end = skb->data + skb->len;
  276. while (pos + 2 < end) {
  277. id = *pos++;
  278. elen = *pos++;
  279. if (pos + elen > end)
  280. break;
  281. if (id == WLAN_EID_TIM) {
  282. if (elen < sizeof(*tim))
  283. break;
  284. tim = (struct ieee80211_tim_ie *) pos;
  285. if (tim->dtim_count != 0)
  286. break;
  287. return tim->bitmap_ctrl & 0x01;
  288. }
  289. pos += elen;
  290. }
  291. return false;
  292. }
  293. static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
  294. {
  295. struct ieee80211_mgmt *mgmt;
  296. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  297. if (skb->len < 24 + 8 + 2 + 2)
  298. return;
  299. mgmt = (struct ieee80211_mgmt *)skb->data;
  300. if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0)
  301. return; /* not from our current AP */
  302. sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
  303. if (sc->ps_flags & PS_BEACON_SYNC) {
  304. sc->ps_flags &= ~PS_BEACON_SYNC;
  305. ath_print(common, ATH_DBG_PS,
  306. "Reconfigure Beacon timers based on "
  307. "timestamp from the AP\n");
  308. ath_beacon_config(sc, NULL);
  309. }
  310. if (ath_beacon_dtim_pending_cab(skb)) {
  311. /*
  312. * Remain awake waiting for buffered broadcast/multicast
  313. * frames. If the last broadcast/multicast frame is not
  314. * received properly, the next beacon frame will work as
  315. * a backup trigger for returning into NETWORK SLEEP state,
  316. * so we are waiting for it as well.
  317. */
  318. ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating "
  319. "buffered broadcast/multicast frame(s)\n");
  320. sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
  321. return;
  322. }
  323. if (sc->ps_flags & PS_WAIT_FOR_CAB) {
  324. /*
  325. * This can happen if a broadcast frame is dropped or the AP
  326. * fails to send a frame indicating that all CAB frames have
  327. * been delivered.
  328. */
  329. sc->ps_flags &= ~PS_WAIT_FOR_CAB;
  330. ath_print(common, ATH_DBG_PS,
  331. "PS wait for CAB frames timed out\n");
  332. }
  333. }
  334. static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
  335. {
  336. struct ieee80211_hdr *hdr;
  337. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  338. hdr = (struct ieee80211_hdr *)skb->data;
  339. /* Process Beacon and CAB receive in PS state */
  340. if ((sc->ps_flags & PS_WAIT_FOR_BEACON) &&
  341. ieee80211_is_beacon(hdr->frame_control))
  342. ath_rx_ps_beacon(sc, skb);
  343. else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
  344. (ieee80211_is_data(hdr->frame_control) ||
  345. ieee80211_is_action(hdr->frame_control)) &&
  346. is_multicast_ether_addr(hdr->addr1) &&
  347. !ieee80211_has_moredata(hdr->frame_control)) {
  348. /*
  349. * No more broadcast/multicast frames to be received at this
  350. * point.
  351. */
  352. sc->ps_flags &= ~PS_WAIT_FOR_CAB;
  353. ath_print(common, ATH_DBG_PS,
  354. "All PS CAB frames received, back to sleep\n");
  355. } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
  356. !is_multicast_ether_addr(hdr->addr1) &&
  357. !ieee80211_has_morefrags(hdr->frame_control)) {
  358. sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
  359. ath_print(common, ATH_DBG_PS,
  360. "Going back to sleep after having received "
  361. "PS-Poll data (0x%lx)\n",
  362. sc->ps_flags & (PS_WAIT_FOR_BEACON |
  363. PS_WAIT_FOR_CAB |
  364. PS_WAIT_FOR_PSPOLL_DATA |
  365. PS_WAIT_FOR_TX_ACK));
  366. }
  367. }
  368. static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
  369. struct ath_softc *sc, struct sk_buff *skb,
  370. struct ieee80211_rx_status *rxs)
  371. {
  372. struct ieee80211_hdr *hdr;
  373. hdr = (struct ieee80211_hdr *)skb->data;
  374. /* Send the frame to mac80211 */
  375. if (is_multicast_ether_addr(hdr->addr1)) {
  376. int i;
  377. /*
  378. * Deliver broadcast/multicast frames to all suitable
  379. * virtual wiphys.
  380. */
  381. /* TODO: filter based on channel configuration */
  382. for (i = 0; i < sc->num_sec_wiphy; i++) {
  383. struct ath_wiphy *aphy = sc->sec_wiphy[i];
  384. struct sk_buff *nskb;
  385. if (aphy == NULL)
  386. continue;
  387. nskb = skb_copy(skb, GFP_ATOMIC);
  388. if (!nskb)
  389. continue;
  390. ieee80211_rx(aphy->hw, nskb);
  391. }
  392. ieee80211_rx(sc->hw, skb);
  393. } else
  394. /* Deliver unicast frames based on receiver address */
  395. ieee80211_rx(hw, skb);
  396. }
  397. int ath_rx_tasklet(struct ath_softc *sc, int flush)
  398. {
  399. #define PA2DESC(_sc, _pa) \
  400. ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \
  401. ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr)))
  402. struct ath_buf *bf;
  403. struct ath_desc *ds;
  404. struct ath_rx_status *rx_stats;
  405. struct sk_buff *skb = NULL, *requeue_skb;
  406. struct ieee80211_rx_status *rxs;
  407. struct ath_hw *ah = sc->sc_ah;
  408. struct ath_common *common = ath9k_hw_common(ah);
  409. /*
  410. * The hw can techncically differ from common->hw when using ath9k
  411. * virtual wiphy so to account for that we iterate over the active
  412. * wiphys and find the appropriate wiphy and therefore hw.
  413. */
  414. struct ieee80211_hw *hw = NULL;
  415. struct ieee80211_hdr *hdr;
  416. int retval;
  417. bool decrypt_error = false;
  418. spin_lock_bh(&sc->rx.rxbuflock);
  419. do {
  420. /* If handling rx interrupt and flush is in progress => exit */
  421. if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
  422. break;
  423. if (list_empty(&sc->rx.rxbuf)) {
  424. sc->rx.rxlink = NULL;
  425. break;
  426. }
  427. bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
  428. ds = bf->bf_desc;
  429. /*
  430. * Must provide the virtual address of the current
  431. * descriptor, the physical address, and the virtual
  432. * address of the next descriptor in the h/w chain.
  433. * This allows the HAL to look ahead to see if the
  434. * hardware is done with a descriptor by checking the
  435. * done bit in the following descriptor and the address
  436. * of the current descriptor the DMA engine is working
  437. * on. All this is necessary because of our use of
  438. * a self-linked list to avoid rx overruns.
  439. */
  440. retval = ath9k_hw_rxprocdesc(ah, ds,
  441. bf->bf_daddr,
  442. PA2DESC(sc, ds->ds_link),
  443. 0);
  444. if (retval == -EINPROGRESS) {
  445. struct ath_buf *tbf;
  446. struct ath_desc *tds;
  447. if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
  448. sc->rx.rxlink = NULL;
  449. break;
  450. }
  451. tbf = list_entry(bf->list.next, struct ath_buf, list);
  452. /*
  453. * On some hardware the descriptor status words could
  454. * get corrupted, including the done bit. Because of
  455. * this, check if the next descriptor's done bit is
  456. * set or not.
  457. *
  458. * If the next descriptor's done bit is set, the current
  459. * descriptor has been corrupted. Force s/w to discard
  460. * this descriptor and continue...
  461. */
  462. tds = tbf->bf_desc;
  463. retval = ath9k_hw_rxprocdesc(ah, tds, tbf->bf_daddr,
  464. PA2DESC(sc, tds->ds_link), 0);
  465. if (retval == -EINPROGRESS) {
  466. break;
  467. }
  468. }
  469. skb = bf->bf_mpdu;
  470. if (!skb)
  471. continue;
  472. /*
  473. * Synchronize the DMA transfer with CPU before
  474. * 1. accessing the frame
  475. * 2. requeueing the same buffer to h/w
  476. */
  477. dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
  478. common->rx_bufsize,
  479. DMA_FROM_DEVICE);
  480. hdr = (struct ieee80211_hdr *) skb->data;
  481. rxs = IEEE80211_SKB_RXCB(skb);
  482. hw = ath_get_virt_hw(sc, hdr);
  483. rx_stats = &ds->ds_rxstat;
  484. ath_debug_stat_rx(sc, bf);
  485. /*
  486. * If we're asked to flush receive queue, directly
  487. * chain it back at the queue without processing it.
  488. */
  489. if (flush)
  490. goto requeue;
  491. retval = ath9k_cmn_rx_skb_preprocess(common, hw, skb, rx_stats,
  492. rxs, &decrypt_error);
  493. if (retval)
  494. goto requeue;
  495. /* Ensure we always have an skb to requeue once we are done
  496. * processing the current buffer's skb */
  497. requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
  498. /* If there is no memory we ignore the current RX'd frame,
  499. * tell hardware it can give us a new frame using the old
  500. * skb and put it at the tail of the sc->rx.rxbuf list for
  501. * processing. */
  502. if (!requeue_skb)
  503. goto requeue;
  504. /* Unmap the frame */
  505. dma_unmap_single(sc->dev, bf->bf_buf_addr,
  506. common->rx_bufsize,
  507. DMA_FROM_DEVICE);
  508. skb_put(skb, rx_stats->rs_datalen);
  509. ath9k_cmn_rx_skb_postprocess(common, skb, rx_stats,
  510. rxs, decrypt_error);
  511. /* We will now give hardware our shiny new allocated skb */
  512. bf->bf_mpdu = requeue_skb;
  513. bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
  514. common->rx_bufsize,
  515. DMA_FROM_DEVICE);
  516. if (unlikely(dma_mapping_error(sc->dev,
  517. bf->bf_buf_addr))) {
  518. dev_kfree_skb_any(requeue_skb);
  519. bf->bf_mpdu = NULL;
  520. ath_print(common, ATH_DBG_FATAL,
  521. "dma_mapping_error() on RX\n");
  522. ath_rx_send_to_mac80211(hw, sc, skb, rxs);
  523. break;
  524. }
  525. bf->bf_dmacontext = bf->bf_buf_addr;
  526. /*
  527. * change the default rx antenna if rx diversity chooses the
  528. * other antenna 3 times in a row.
  529. */
  530. if (sc->rx.defant != ds->ds_rxstat.rs_antenna) {
  531. if (++sc->rx.rxotherant >= 3)
  532. ath_setdefantenna(sc, rx_stats->rs_antenna);
  533. } else {
  534. sc->rx.rxotherant = 0;
  535. }
  536. if (unlikely(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  537. PS_WAIT_FOR_CAB |
  538. PS_WAIT_FOR_PSPOLL_DATA)))
  539. ath_rx_ps(sc, skb);
  540. ath_rx_send_to_mac80211(hw, sc, skb, rxs);
  541. requeue:
  542. list_move_tail(&bf->list, &sc->rx.rxbuf);
  543. ath_rx_buf_link(sc, bf);
  544. } while (1);
  545. spin_unlock_bh(&sc->rx.rxbuflock);
  546. return 0;
  547. #undef PA2DESC
  548. }