eeprom.c 7.1 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "hw.h"
  17. static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
  18. {
  19. if (fbin == AR5416_BCHAN_UNUSED)
  20. return fbin;
  21. return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
  22. }
  23. void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
  24. u32 shift, u32 val)
  25. {
  26. u32 regVal;
  27. regVal = REG_READ(ah, reg) & ~mask;
  28. regVal |= (val << shift) & mask;
  29. REG_WRITE(ah, reg, regVal);
  30. if (ah->config.analog_shiftreg)
  31. udelay(100);
  32. return;
  33. }
  34. int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
  35. int16_t targetLeft, int16_t targetRight)
  36. {
  37. int16_t rv;
  38. if (srcRight == srcLeft) {
  39. rv = targetLeft;
  40. } else {
  41. rv = (int16_t) (((target - srcLeft) * targetRight +
  42. (srcRight - target) * targetLeft) /
  43. (srcRight - srcLeft));
  44. }
  45. return rv;
  46. }
  47. bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
  48. u16 *indexL, u16 *indexR)
  49. {
  50. u16 i;
  51. if (target <= pList[0]) {
  52. *indexL = *indexR = 0;
  53. return true;
  54. }
  55. if (target >= pList[listSize - 1]) {
  56. *indexL = *indexR = (u16) (listSize - 1);
  57. return true;
  58. }
  59. for (i = 0; i < listSize - 1; i++) {
  60. if (pList[i] == target) {
  61. *indexL = *indexR = i;
  62. return true;
  63. }
  64. if (target < pList[i + 1]) {
  65. *indexL = i;
  66. *indexR = (u16) (i + 1);
  67. return false;
  68. }
  69. }
  70. return false;
  71. }
  72. bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
  73. {
  74. return common->bus_ops->eeprom_read(common, off, data);
  75. }
  76. void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
  77. u8 *pVpdList, u16 numIntercepts,
  78. u8 *pRetVpdList)
  79. {
  80. u16 i, k;
  81. u8 currPwr = pwrMin;
  82. u16 idxL = 0, idxR = 0;
  83. for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
  84. ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
  85. numIntercepts, &(idxL),
  86. &(idxR));
  87. if (idxR < 1)
  88. idxR = 1;
  89. if (idxL == numIntercepts - 1)
  90. idxL = (u16) (numIntercepts - 2);
  91. if (pPwrList[idxL] == pPwrList[idxR])
  92. k = pVpdList[idxL];
  93. else
  94. k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
  95. (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
  96. (pPwrList[idxR] - pPwrList[idxL]));
  97. pRetVpdList[i] = (u8) k;
  98. currPwr += 2;
  99. }
  100. }
  101. void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
  102. struct ath9k_channel *chan,
  103. struct cal_target_power_leg *powInfo,
  104. u16 numChannels,
  105. struct cal_target_power_leg *pNewPower,
  106. u16 numRates, bool isExtTarget)
  107. {
  108. struct chan_centers centers;
  109. u16 clo, chi;
  110. int i;
  111. int matchIndex = -1, lowIndex = -1;
  112. u16 freq;
  113. ath9k_hw_get_channel_centers(ah, chan, &centers);
  114. freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
  115. if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
  116. IS_CHAN_2GHZ(chan))) {
  117. matchIndex = 0;
  118. } else {
  119. for (i = 0; (i < numChannels) &&
  120. (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  121. if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
  122. IS_CHAN_2GHZ(chan))) {
  123. matchIndex = i;
  124. break;
  125. } else if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
  126. IS_CHAN_2GHZ(chan)) && i > 0 &&
  127. freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
  128. IS_CHAN_2GHZ(chan))) {
  129. lowIndex = i - 1;
  130. break;
  131. }
  132. }
  133. if ((matchIndex == -1) && (lowIndex == -1))
  134. matchIndex = i - 1;
  135. }
  136. if (matchIndex != -1) {
  137. *pNewPower = powInfo[matchIndex];
  138. } else {
  139. clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
  140. IS_CHAN_2GHZ(chan));
  141. chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
  142. IS_CHAN_2GHZ(chan));
  143. for (i = 0; i < numRates; i++) {
  144. pNewPower->tPow2x[i] =
  145. (u8)ath9k_hw_interpolate(freq, clo, chi,
  146. powInfo[lowIndex].tPow2x[i],
  147. powInfo[lowIndex + 1].tPow2x[i]);
  148. }
  149. }
  150. }
  151. void ath9k_hw_get_target_powers(struct ath_hw *ah,
  152. struct ath9k_channel *chan,
  153. struct cal_target_power_ht *powInfo,
  154. u16 numChannels,
  155. struct cal_target_power_ht *pNewPower,
  156. u16 numRates, bool isHt40Target)
  157. {
  158. struct chan_centers centers;
  159. u16 clo, chi;
  160. int i;
  161. int matchIndex = -1, lowIndex = -1;
  162. u16 freq;
  163. ath9k_hw_get_channel_centers(ah, chan, &centers);
  164. freq = isHt40Target ? centers.synth_center : centers.ctl_center;
  165. if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
  166. matchIndex = 0;
  167. } else {
  168. for (i = 0; (i < numChannels) &&
  169. (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  170. if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
  171. IS_CHAN_2GHZ(chan))) {
  172. matchIndex = i;
  173. break;
  174. } else
  175. if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
  176. IS_CHAN_2GHZ(chan)) && i > 0 &&
  177. freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
  178. IS_CHAN_2GHZ(chan))) {
  179. lowIndex = i - 1;
  180. break;
  181. }
  182. }
  183. if ((matchIndex == -1) && (lowIndex == -1))
  184. matchIndex = i - 1;
  185. }
  186. if (matchIndex != -1) {
  187. *pNewPower = powInfo[matchIndex];
  188. } else {
  189. clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
  190. IS_CHAN_2GHZ(chan));
  191. chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
  192. IS_CHAN_2GHZ(chan));
  193. for (i = 0; i < numRates; i++) {
  194. pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
  195. clo, chi,
  196. powInfo[lowIndex].tPow2x[i],
  197. powInfo[lowIndex + 1].tPow2x[i]);
  198. }
  199. }
  200. }
  201. u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
  202. bool is2GHz, int num_band_edges)
  203. {
  204. u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
  205. int i;
  206. for (i = 0; (i < num_band_edges) &&
  207. (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  208. if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
  209. twiceMaxEdgePower = pRdEdgesPower[i].tPower;
  210. break;
  211. } else if ((i > 0) &&
  212. (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
  213. is2GHz))) {
  214. if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
  215. is2GHz) < freq &&
  216. pRdEdgesPower[i - 1].flag) {
  217. twiceMaxEdgePower =
  218. pRdEdgesPower[i - 1].tPower;
  219. }
  220. break;
  221. }
  222. }
  223. return twiceMaxEdgePower;
  224. }
  225. int ath9k_hw_eeprom_init(struct ath_hw *ah)
  226. {
  227. int status;
  228. if (AR_SREV_9287(ah)) {
  229. ah->eep_map = EEP_MAP_AR9287;
  230. ah->eep_ops = &eep_AR9287_ops;
  231. } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
  232. ah->eep_map = EEP_MAP_4KBITS;
  233. ah->eep_ops = &eep_4k_ops;
  234. } else {
  235. ah->eep_map = EEP_MAP_DEFAULT;
  236. ah->eep_ops = &eep_def_ops;
  237. }
  238. if (!ah->eep_ops->fill_eeprom(ah))
  239. return -EIO;
  240. status = ah->eep_ops->check_eeprom(ah);
  241. return status;
  242. }