attach.c 9.8 KB

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  1. /*
  2. * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
  3. * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
  4. *
  5. * Permission to use, copy, modify, and distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. *
  17. */
  18. /*************************************\
  19. * Attach/Detach Functions and helpers *
  20. \*************************************/
  21. #include <linux/pci.h>
  22. #include <linux/slab.h>
  23. #include "ath5k.h"
  24. #include "reg.h"
  25. #include "debug.h"
  26. #include "base.h"
  27. /**
  28. * ath5k_hw_post - Power On Self Test helper function
  29. *
  30. * @ah: The &struct ath5k_hw
  31. */
  32. static int ath5k_hw_post(struct ath5k_hw *ah)
  33. {
  34. static const u32 static_pattern[4] = {
  35. 0x55555555, 0xaaaaaaaa,
  36. 0x66666666, 0x99999999
  37. };
  38. static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
  39. int i, c;
  40. u16 cur_reg;
  41. u32 var_pattern;
  42. u32 init_val;
  43. u32 cur_val;
  44. for (c = 0; c < 2; c++) {
  45. cur_reg = regs[c];
  46. /* Save previous value */
  47. init_val = ath5k_hw_reg_read(ah, cur_reg);
  48. for (i = 0; i < 256; i++) {
  49. var_pattern = i << 16 | i;
  50. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  51. cur_val = ath5k_hw_reg_read(ah, cur_reg);
  52. if (cur_val != var_pattern) {
  53. ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
  54. return -EAGAIN;
  55. }
  56. /* Found on ndiswrapper dumps */
  57. var_pattern = 0x0039080f;
  58. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  59. }
  60. for (i = 0; i < 4; i++) {
  61. var_pattern = static_pattern[i];
  62. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  63. cur_val = ath5k_hw_reg_read(ah, cur_reg);
  64. if (cur_val != var_pattern) {
  65. ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
  66. return -EAGAIN;
  67. }
  68. /* Found on ndiswrapper dumps */
  69. var_pattern = 0x003b080f;
  70. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  71. }
  72. /* Restore previous value */
  73. ath5k_hw_reg_write(ah, init_val, cur_reg);
  74. }
  75. return 0;
  76. }
  77. /**
  78. * ath5k_hw_attach - Check if hw is supported and init the needed structs
  79. *
  80. * @sc: The &struct ath5k_softc we got from the driver's attach function
  81. *
  82. * Check if the device is supported, perform a POST and initialize the needed
  83. * structs. Returns -ENOMEM if we don't have memory for the needed structs,
  84. * -ENODEV if the device is not supported or prints an error msg if something
  85. * else went wrong.
  86. */
  87. int ath5k_hw_attach(struct ath5k_softc *sc)
  88. {
  89. struct ath5k_hw *ah = sc->ah;
  90. struct ath_common *common = ath5k_hw_common(ah);
  91. struct pci_dev *pdev = sc->pdev;
  92. struct ath5k_eeprom_info *ee;
  93. int ret;
  94. u32 srev;
  95. /*
  96. * HW information
  97. */
  98. ah->ah_op_mode = NL80211_IFTYPE_STATION;
  99. ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
  100. ah->ah_turbo = false;
  101. ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
  102. ah->ah_imr = 0;
  103. ah->ah_atim_window = 0;
  104. ah->ah_aifs = AR5K_TUNE_AIFS;
  105. ah->ah_cw_min = AR5K_TUNE_CWMIN;
  106. ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
  107. ah->ah_software_retry = false;
  108. /*
  109. * Find the mac version
  110. */
  111. srev = ath5k_hw_reg_read(ah, AR5K_SREV);
  112. if (srev < AR5K_SREV_AR5311)
  113. ah->ah_version = AR5K_AR5210;
  114. else if (srev < AR5K_SREV_AR5212)
  115. ah->ah_version = AR5K_AR5211;
  116. else
  117. ah->ah_version = AR5K_AR5212;
  118. /*Fill the ath5k_hw struct with the needed functions*/
  119. ret = ath5k_hw_init_desc_functions(ah);
  120. if (ret)
  121. goto err_free;
  122. /* Bring device out of sleep and reset it's units */
  123. ret = ath5k_hw_nic_wakeup(ah, 0, true);
  124. if (ret)
  125. goto err_free;
  126. /* Get MAC, PHY and RADIO revisions */
  127. ah->ah_mac_srev = srev;
  128. ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
  129. ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
  130. ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
  131. 0xffffffff;
  132. ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
  133. CHANNEL_5GHZ);
  134. ah->ah_phy = AR5K_PHY(0);
  135. /* Try to identify radio chip based on it's srev */
  136. switch (ah->ah_radio_5ghz_revision & 0xf0) {
  137. case AR5K_SREV_RAD_5111:
  138. ah->ah_radio = AR5K_RF5111;
  139. ah->ah_single_chip = false;
  140. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  141. CHANNEL_2GHZ);
  142. break;
  143. case AR5K_SREV_RAD_5112:
  144. case AR5K_SREV_RAD_2112:
  145. ah->ah_radio = AR5K_RF5112;
  146. ah->ah_single_chip = false;
  147. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  148. CHANNEL_2GHZ);
  149. break;
  150. case AR5K_SREV_RAD_2413:
  151. ah->ah_radio = AR5K_RF2413;
  152. ah->ah_single_chip = true;
  153. break;
  154. case AR5K_SREV_RAD_5413:
  155. ah->ah_radio = AR5K_RF5413;
  156. ah->ah_single_chip = true;
  157. break;
  158. case AR5K_SREV_RAD_2316:
  159. ah->ah_radio = AR5K_RF2316;
  160. ah->ah_single_chip = true;
  161. break;
  162. case AR5K_SREV_RAD_2317:
  163. ah->ah_radio = AR5K_RF2317;
  164. ah->ah_single_chip = true;
  165. break;
  166. case AR5K_SREV_RAD_5424:
  167. if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
  168. ah->ah_mac_version == AR5K_SREV_AR2417){
  169. ah->ah_radio = AR5K_RF2425;
  170. ah->ah_single_chip = true;
  171. } else {
  172. ah->ah_radio = AR5K_RF5413;
  173. ah->ah_single_chip = true;
  174. }
  175. break;
  176. default:
  177. /* Identify radio based on mac/phy srev */
  178. if (ah->ah_version == AR5K_AR5210) {
  179. ah->ah_radio = AR5K_RF5110;
  180. ah->ah_single_chip = false;
  181. } else if (ah->ah_version == AR5K_AR5211) {
  182. ah->ah_radio = AR5K_RF5111;
  183. ah->ah_single_chip = false;
  184. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  185. CHANNEL_2GHZ);
  186. } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
  187. ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
  188. ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
  189. ah->ah_radio = AR5K_RF2425;
  190. ah->ah_single_chip = true;
  191. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
  192. } else if (srev == AR5K_SREV_AR5213A &&
  193. ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
  194. ah->ah_radio = AR5K_RF5112;
  195. ah->ah_single_chip = false;
  196. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
  197. } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
  198. ah->ah_radio = AR5K_RF2316;
  199. ah->ah_single_chip = true;
  200. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
  201. } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
  202. ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
  203. ah->ah_radio = AR5K_RF5413;
  204. ah->ah_single_chip = true;
  205. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
  206. } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
  207. ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
  208. ah->ah_radio = AR5K_RF2413;
  209. ah->ah_single_chip = true;
  210. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
  211. } else {
  212. ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
  213. ret = -ENODEV;
  214. goto err_free;
  215. }
  216. }
  217. /* Return on unsuported chips (unsupported eeprom etc) */
  218. if ((srev >= AR5K_SREV_AR5416) &&
  219. (srev < AR5K_SREV_AR2425)) {
  220. ATH5K_ERR(sc, "Device not yet supported.\n");
  221. ret = -ENODEV;
  222. goto err_free;
  223. }
  224. /*
  225. * POST
  226. */
  227. ret = ath5k_hw_post(ah);
  228. if (ret)
  229. goto err_free;
  230. /* Enable pci core retry fix on Hainan (5213A) and later chips */
  231. if (srev >= AR5K_SREV_AR5213A)
  232. AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
  233. /*
  234. * Get card capabilities, calibration values etc
  235. * TODO: EEPROM work
  236. */
  237. ret = ath5k_eeprom_init(ah);
  238. if (ret) {
  239. ATH5K_ERR(sc, "unable to init EEPROM\n");
  240. goto err_free;
  241. }
  242. ee = &ah->ah_capabilities.cap_eeprom;
  243. /*
  244. * Write PCI-E power save settings
  245. */
  246. if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
  247. ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
  248. ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
  249. /* Shut off RX when elecidle is asserted */
  250. ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
  251. ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
  252. /* If serdes programing is enabled, increase PCI-E
  253. * tx power for systems with long trace from host
  254. * to minicard connector. */
  255. if (ee->ee_serdes)
  256. ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
  257. else
  258. ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
  259. /* Shut off PLL and CLKREQ active in L1 */
  260. ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
  261. /* Preserve other settings */
  262. ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
  263. ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
  264. ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
  265. /* Reset SERDES to load new settings */
  266. ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
  267. mdelay(1);
  268. }
  269. /* Get misc capabilities */
  270. ret = ath5k_hw_set_capabilities(ah);
  271. if (ret) {
  272. ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
  273. sc->pdev->device);
  274. goto err_free;
  275. }
  276. /* Crypto settings */
  277. ah->ah_aes_support = srev >= AR5K_SREV_AR5212_V4 &&
  278. (ee->ee_version >= AR5K_EEPROM_VERSION_5_0 &&
  279. !AR5K_EEPROM_AES_DIS(ee->ee_misc5));
  280. if (srev >= AR5K_SREV_AR2414) {
  281. ah->ah_combined_mic = true;
  282. AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
  283. AR5K_MISC_MODE_COMBINED_MIC);
  284. }
  285. /* MAC address is cleared until add_interface */
  286. ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){});
  287. /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
  288. memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
  289. ath5k_hw_set_associd(ah);
  290. ath5k_hw_set_opmode(ah);
  291. ath5k_hw_rfgain_opt_init(ah);
  292. ath5k_hw_init_nfcal_hist(ah);
  293. /* turn on HW LEDs */
  294. ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
  295. return 0;
  296. err_free:
  297. kfree(ah);
  298. return ret;
  299. }
  300. /**
  301. * ath5k_hw_detach - Free the ath5k_hw struct
  302. *
  303. * @ah: The &struct ath5k_hw
  304. */
  305. void ath5k_hw_detach(struct ath5k_hw *ah)
  306. {
  307. ATH5K_TRACE(ah->ah_sc);
  308. __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
  309. if (ah->ah_rf_banks != NULL)
  310. kfree(ah->ah_rf_banks);
  311. ath5k_eeprom_detach(ah);
  312. /* assume interrupts are down */
  313. }