smsc95xx.c 34 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2008 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. *
  19. *****************************************************************************/
  20. #include <linux/module.h>
  21. #include <linux/kmod.h>
  22. #include <linux/init.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/mii.h>
  27. #include <linux/usb.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include <linux/slab.h>
  31. #include "smsc95xx.h"
  32. #define SMSC_CHIPNAME "smsc95xx"
  33. #define SMSC_DRIVER_VERSION "1.0.4"
  34. #define HS_USB_PKT_SIZE (512)
  35. #define FS_USB_PKT_SIZE (64)
  36. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  37. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  38. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  39. #define MAX_SINGLE_PACKET_SIZE (2048)
  40. #define LAN95XX_EEPROM_MAGIC (0x9500)
  41. #define EEPROM_MAC_OFFSET (0x01)
  42. #define DEFAULT_TX_CSUM_ENABLE (true)
  43. #define DEFAULT_RX_CSUM_ENABLE (true)
  44. #define SMSC95XX_INTERNAL_PHY_ID (1)
  45. #define SMSC95XX_TX_OVERHEAD (8)
  46. #define SMSC95XX_TX_OVERHEAD_CSUM (12)
  47. struct smsc95xx_priv {
  48. u32 mac_cr;
  49. spinlock_t mac_cr_lock;
  50. bool use_tx_csum;
  51. bool use_rx_csum;
  52. };
  53. struct usb_context {
  54. struct usb_ctrlrequest req;
  55. struct usbnet *dev;
  56. };
  57. static int turbo_mode = true;
  58. module_param(turbo_mode, bool, 0644);
  59. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  60. static int smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data)
  61. {
  62. u32 *buf = kmalloc(4, GFP_KERNEL);
  63. int ret;
  64. BUG_ON(!dev);
  65. if (!buf)
  66. return -ENOMEM;
  67. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
  68. USB_VENDOR_REQUEST_READ_REGISTER,
  69. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  70. 00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
  71. if (unlikely(ret < 0))
  72. netdev_warn(dev->net, "Failed to read register index 0x%08x\n", index);
  73. le32_to_cpus(buf);
  74. *data = *buf;
  75. kfree(buf);
  76. return ret;
  77. }
  78. static int smsc95xx_write_reg(struct usbnet *dev, u32 index, u32 data)
  79. {
  80. u32 *buf = kmalloc(4, GFP_KERNEL);
  81. int ret;
  82. BUG_ON(!dev);
  83. if (!buf)
  84. return -ENOMEM;
  85. *buf = data;
  86. cpu_to_le32s(buf);
  87. ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
  88. USB_VENDOR_REQUEST_WRITE_REGISTER,
  89. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  90. 00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
  91. if (unlikely(ret < 0))
  92. netdev_warn(dev->net, "Failed to write register index 0x%08x\n", index);
  93. kfree(buf);
  94. return ret;
  95. }
  96. /* Loop until the read is completed with timeout
  97. * called with phy_mutex held */
  98. static int smsc95xx_phy_wait_not_busy(struct usbnet *dev)
  99. {
  100. unsigned long start_time = jiffies;
  101. u32 val;
  102. do {
  103. smsc95xx_read_reg(dev, MII_ADDR, &val);
  104. if (!(val & MII_BUSY_))
  105. return 0;
  106. } while (!time_after(jiffies, start_time + HZ));
  107. return -EIO;
  108. }
  109. static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  110. {
  111. struct usbnet *dev = netdev_priv(netdev);
  112. u32 val, addr;
  113. mutex_lock(&dev->phy_mutex);
  114. /* confirm MII not busy */
  115. if (smsc95xx_phy_wait_not_busy(dev)) {
  116. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_read\n");
  117. mutex_unlock(&dev->phy_mutex);
  118. return -EIO;
  119. }
  120. /* set the address, index & direction (read from PHY) */
  121. phy_id &= dev->mii.phy_id_mask;
  122. idx &= dev->mii.reg_num_mask;
  123. addr = (phy_id << 11) | (idx << 6) | MII_READ_;
  124. smsc95xx_write_reg(dev, MII_ADDR, addr);
  125. if (smsc95xx_phy_wait_not_busy(dev)) {
  126. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  127. mutex_unlock(&dev->phy_mutex);
  128. return -EIO;
  129. }
  130. smsc95xx_read_reg(dev, MII_DATA, &val);
  131. mutex_unlock(&dev->phy_mutex);
  132. return (u16)(val & 0xFFFF);
  133. }
  134. static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  135. int regval)
  136. {
  137. struct usbnet *dev = netdev_priv(netdev);
  138. u32 val, addr;
  139. mutex_lock(&dev->phy_mutex);
  140. /* confirm MII not busy */
  141. if (smsc95xx_phy_wait_not_busy(dev)) {
  142. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_write\n");
  143. mutex_unlock(&dev->phy_mutex);
  144. return;
  145. }
  146. val = regval;
  147. smsc95xx_write_reg(dev, MII_DATA, val);
  148. /* set the address, index & direction (write to PHY) */
  149. phy_id &= dev->mii.phy_id_mask;
  150. idx &= dev->mii.reg_num_mask;
  151. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
  152. smsc95xx_write_reg(dev, MII_ADDR, addr);
  153. if (smsc95xx_phy_wait_not_busy(dev))
  154. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  155. mutex_unlock(&dev->phy_mutex);
  156. }
  157. static int smsc95xx_wait_eeprom(struct usbnet *dev)
  158. {
  159. unsigned long start_time = jiffies;
  160. u32 val;
  161. do {
  162. smsc95xx_read_reg(dev, E2P_CMD, &val);
  163. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  164. break;
  165. udelay(40);
  166. } while (!time_after(jiffies, start_time + HZ));
  167. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  168. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  169. return -EIO;
  170. }
  171. return 0;
  172. }
  173. static int smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
  174. {
  175. unsigned long start_time = jiffies;
  176. u32 val;
  177. do {
  178. smsc95xx_read_reg(dev, E2P_CMD, &val);
  179. if (!(val & E2P_CMD_BUSY_))
  180. return 0;
  181. udelay(40);
  182. } while (!time_after(jiffies, start_time + HZ));
  183. netdev_warn(dev->net, "EEPROM is busy\n");
  184. return -EIO;
  185. }
  186. static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  187. u8 *data)
  188. {
  189. u32 val;
  190. int i, ret;
  191. BUG_ON(!dev);
  192. BUG_ON(!data);
  193. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  194. if (ret)
  195. return ret;
  196. for (i = 0; i < length; i++) {
  197. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  198. smsc95xx_write_reg(dev, E2P_CMD, val);
  199. ret = smsc95xx_wait_eeprom(dev);
  200. if (ret < 0)
  201. return ret;
  202. smsc95xx_read_reg(dev, E2P_DATA, &val);
  203. data[i] = val & 0xFF;
  204. offset++;
  205. }
  206. return 0;
  207. }
  208. static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  209. u8 *data)
  210. {
  211. u32 val;
  212. int i, ret;
  213. BUG_ON(!dev);
  214. BUG_ON(!data);
  215. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  216. if (ret)
  217. return ret;
  218. /* Issue write/erase enable command */
  219. val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
  220. smsc95xx_write_reg(dev, E2P_CMD, val);
  221. ret = smsc95xx_wait_eeprom(dev);
  222. if (ret < 0)
  223. return ret;
  224. for (i = 0; i < length; i++) {
  225. /* Fill data register */
  226. val = data[i];
  227. smsc95xx_write_reg(dev, E2P_DATA, val);
  228. /* Send "write" command */
  229. val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
  230. smsc95xx_write_reg(dev, E2P_CMD, val);
  231. ret = smsc95xx_wait_eeprom(dev);
  232. if (ret < 0)
  233. return ret;
  234. offset++;
  235. }
  236. return 0;
  237. }
  238. static void smsc95xx_async_cmd_callback(struct urb *urb)
  239. {
  240. struct usb_context *usb_context = urb->context;
  241. struct usbnet *dev = usb_context->dev;
  242. int status = urb->status;
  243. if (status < 0)
  244. netdev_warn(dev->net, "async callback failed with %d\n", status);
  245. kfree(usb_context);
  246. usb_free_urb(urb);
  247. }
  248. static int smsc95xx_write_reg_async(struct usbnet *dev, u16 index, u32 *data)
  249. {
  250. struct usb_context *usb_context;
  251. int status;
  252. struct urb *urb;
  253. const u16 size = 4;
  254. urb = usb_alloc_urb(0, GFP_ATOMIC);
  255. if (!urb) {
  256. netdev_warn(dev->net, "Error allocating URB\n");
  257. return -ENOMEM;
  258. }
  259. usb_context = kmalloc(sizeof(struct usb_context), GFP_ATOMIC);
  260. if (usb_context == NULL) {
  261. netdev_warn(dev->net, "Error allocating control msg\n");
  262. usb_free_urb(urb);
  263. return -ENOMEM;
  264. }
  265. usb_context->req.bRequestType =
  266. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
  267. usb_context->req.bRequest = USB_VENDOR_REQUEST_WRITE_REGISTER;
  268. usb_context->req.wValue = 00;
  269. usb_context->req.wIndex = cpu_to_le16(index);
  270. usb_context->req.wLength = cpu_to_le16(size);
  271. usb_fill_control_urb(urb, dev->udev, usb_sndctrlpipe(dev->udev, 0),
  272. (void *)&usb_context->req, data, size,
  273. smsc95xx_async_cmd_callback,
  274. (void *)usb_context);
  275. status = usb_submit_urb(urb, GFP_ATOMIC);
  276. if (status < 0) {
  277. netdev_warn(dev->net, "Error submitting control msg, sts=%d\n",
  278. status);
  279. kfree(usb_context);
  280. usb_free_urb(urb);
  281. }
  282. return status;
  283. }
  284. /* returns hash bit number for given MAC address
  285. * example:
  286. * 01 00 5E 00 00 01 -> returns bit number 31 */
  287. static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
  288. {
  289. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  290. }
  291. static void smsc95xx_set_multicast(struct net_device *netdev)
  292. {
  293. struct usbnet *dev = netdev_priv(netdev);
  294. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  295. u32 hash_hi = 0;
  296. u32 hash_lo = 0;
  297. unsigned long flags;
  298. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  299. if (dev->net->flags & IFF_PROMISC) {
  300. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  301. pdata->mac_cr |= MAC_CR_PRMS_;
  302. pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  303. } else if (dev->net->flags & IFF_ALLMULTI) {
  304. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  305. pdata->mac_cr |= MAC_CR_MCPAS_;
  306. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  307. } else if (!netdev_mc_empty(dev->net)) {
  308. struct dev_mc_list *mc_list;
  309. pdata->mac_cr |= MAC_CR_HPFILT_;
  310. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  311. netdev_for_each_mc_addr(mc_list, netdev) {
  312. u32 bitnum = smsc95xx_hash(mc_list->dmi_addr);
  313. u32 mask = 0x01 << (bitnum & 0x1F);
  314. if (bitnum & 0x20)
  315. hash_hi |= mask;
  316. else
  317. hash_lo |= mask;
  318. }
  319. netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n",
  320. hash_hi, hash_lo);
  321. } else {
  322. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  323. pdata->mac_cr &=
  324. ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  325. }
  326. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  327. /* Initiate async writes, as we can't wait for completion here */
  328. smsc95xx_write_reg_async(dev, HASHH, &hash_hi);
  329. smsc95xx_write_reg_async(dev, HASHL, &hash_lo);
  330. smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr);
  331. }
  332. static void smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
  333. u16 lcladv, u16 rmtadv)
  334. {
  335. u32 flow, afc_cfg = 0;
  336. int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
  337. if (ret < 0) {
  338. netdev_warn(dev->net, "error reading AFC_CFG\n");
  339. return;
  340. }
  341. if (duplex == DUPLEX_FULL) {
  342. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  343. if (cap & FLOW_CTRL_RX)
  344. flow = 0xFFFF0002;
  345. else
  346. flow = 0;
  347. if (cap & FLOW_CTRL_TX)
  348. afc_cfg |= 0xF;
  349. else
  350. afc_cfg &= ~0xF;
  351. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  352. cap & FLOW_CTRL_RX ? "enabled" : "disabled",
  353. cap & FLOW_CTRL_TX ? "enabled" : "disabled");
  354. } else {
  355. netif_dbg(dev, link, dev->net, "half duplex\n");
  356. flow = 0;
  357. afc_cfg |= 0xF;
  358. }
  359. smsc95xx_write_reg(dev, FLOW, flow);
  360. smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
  361. }
  362. static int smsc95xx_link_reset(struct usbnet *dev)
  363. {
  364. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  365. struct mii_if_info *mii = &dev->mii;
  366. struct ethtool_cmd ecmd;
  367. unsigned long flags;
  368. u16 lcladv, rmtadv;
  369. u32 intdata;
  370. /* clear interrupt status */
  371. smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
  372. intdata = 0xFFFFFFFF;
  373. smsc95xx_write_reg(dev, INT_STS, intdata);
  374. mii_check_media(mii, 1, 1);
  375. mii_ethtool_gset(&dev->mii, &ecmd);
  376. lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  377. rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  378. netif_dbg(dev, link, dev->net, "speed: %d duplex: %d lcladv: %04x rmtadv: %04x\n",
  379. ecmd.speed, ecmd.duplex, lcladv, rmtadv);
  380. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  381. if (ecmd.duplex != DUPLEX_FULL) {
  382. pdata->mac_cr &= ~MAC_CR_FDPX_;
  383. pdata->mac_cr |= MAC_CR_RCVOWN_;
  384. } else {
  385. pdata->mac_cr &= ~MAC_CR_RCVOWN_;
  386. pdata->mac_cr |= MAC_CR_FDPX_;
  387. }
  388. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  389. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  390. smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  391. return 0;
  392. }
  393. static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
  394. {
  395. u32 intdata;
  396. if (urb->actual_length != 4) {
  397. netdev_warn(dev->net, "unexpected urb length %d\n",
  398. urb->actual_length);
  399. return;
  400. }
  401. memcpy(&intdata, urb->transfer_buffer, 4);
  402. le32_to_cpus(&intdata);
  403. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  404. if (intdata & INT_ENP_PHY_INT_)
  405. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  406. else
  407. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  408. intdata);
  409. }
  410. /* Enable or disable Tx & Rx checksum offload engines */
  411. static int smsc95xx_set_csums(struct usbnet *dev)
  412. {
  413. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  414. u32 read_buf;
  415. int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
  416. if (ret < 0) {
  417. netdev_warn(dev->net, "Failed to read COE_CR: %d\n", ret);
  418. return ret;
  419. }
  420. if (pdata->use_tx_csum)
  421. read_buf |= Tx_COE_EN_;
  422. else
  423. read_buf &= ~Tx_COE_EN_;
  424. if (pdata->use_rx_csum)
  425. read_buf |= Rx_COE_EN_;
  426. else
  427. read_buf &= ~Rx_COE_EN_;
  428. ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
  429. if (ret < 0) {
  430. netdev_warn(dev->net, "Failed to write COE_CR: %d\n", ret);
  431. return ret;
  432. }
  433. netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf);
  434. return 0;
  435. }
  436. static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
  437. {
  438. return MAX_EEPROM_SIZE;
  439. }
  440. static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
  441. struct ethtool_eeprom *ee, u8 *data)
  442. {
  443. struct usbnet *dev = netdev_priv(netdev);
  444. ee->magic = LAN95XX_EEPROM_MAGIC;
  445. return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
  446. }
  447. static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
  448. struct ethtool_eeprom *ee, u8 *data)
  449. {
  450. struct usbnet *dev = netdev_priv(netdev);
  451. if (ee->magic != LAN95XX_EEPROM_MAGIC) {
  452. netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n",
  453. ee->magic);
  454. return -EINVAL;
  455. }
  456. return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
  457. }
  458. static u32 smsc95xx_ethtool_get_rx_csum(struct net_device *netdev)
  459. {
  460. struct usbnet *dev = netdev_priv(netdev);
  461. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  462. return pdata->use_rx_csum;
  463. }
  464. static int smsc95xx_ethtool_set_rx_csum(struct net_device *netdev, u32 val)
  465. {
  466. struct usbnet *dev = netdev_priv(netdev);
  467. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  468. pdata->use_rx_csum = !!val;
  469. return smsc95xx_set_csums(dev);
  470. }
  471. static u32 smsc95xx_ethtool_get_tx_csum(struct net_device *netdev)
  472. {
  473. struct usbnet *dev = netdev_priv(netdev);
  474. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  475. return pdata->use_tx_csum;
  476. }
  477. static int smsc95xx_ethtool_set_tx_csum(struct net_device *netdev, u32 val)
  478. {
  479. struct usbnet *dev = netdev_priv(netdev);
  480. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  481. pdata->use_tx_csum = !!val;
  482. ethtool_op_set_tx_hw_csum(netdev, pdata->use_tx_csum);
  483. return smsc95xx_set_csums(dev);
  484. }
  485. static const struct ethtool_ops smsc95xx_ethtool_ops = {
  486. .get_link = usbnet_get_link,
  487. .nway_reset = usbnet_nway_reset,
  488. .get_drvinfo = usbnet_get_drvinfo,
  489. .get_msglevel = usbnet_get_msglevel,
  490. .set_msglevel = usbnet_set_msglevel,
  491. .get_settings = usbnet_get_settings,
  492. .set_settings = usbnet_set_settings,
  493. .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
  494. .get_eeprom = smsc95xx_ethtool_get_eeprom,
  495. .set_eeprom = smsc95xx_ethtool_set_eeprom,
  496. .get_tx_csum = smsc95xx_ethtool_get_tx_csum,
  497. .set_tx_csum = smsc95xx_ethtool_set_tx_csum,
  498. .get_rx_csum = smsc95xx_ethtool_get_rx_csum,
  499. .set_rx_csum = smsc95xx_ethtool_set_rx_csum,
  500. };
  501. static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  502. {
  503. struct usbnet *dev = netdev_priv(netdev);
  504. if (!netif_running(netdev))
  505. return -EINVAL;
  506. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  507. }
  508. static void smsc95xx_init_mac_address(struct usbnet *dev)
  509. {
  510. /* try reading mac address from EEPROM */
  511. if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  512. dev->net->dev_addr) == 0) {
  513. if (is_valid_ether_addr(dev->net->dev_addr)) {
  514. /* eeprom values are valid so use them */
  515. netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n");
  516. return;
  517. }
  518. }
  519. /* no eeprom, or eeprom values are invalid. generate random MAC */
  520. random_ether_addr(dev->net->dev_addr);
  521. netif_dbg(dev, ifup, dev->net, "MAC address set to random_ether_addr\n");
  522. }
  523. static int smsc95xx_set_mac_address(struct usbnet *dev)
  524. {
  525. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  526. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  527. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  528. int ret;
  529. ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
  530. if (ret < 0) {
  531. netdev_warn(dev->net, "Failed to write ADDRL: %d\n", ret);
  532. return ret;
  533. }
  534. ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
  535. if (ret < 0) {
  536. netdev_warn(dev->net, "Failed to write ADDRH: %d\n", ret);
  537. return ret;
  538. }
  539. return 0;
  540. }
  541. /* starts the TX path */
  542. static void smsc95xx_start_tx_path(struct usbnet *dev)
  543. {
  544. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  545. unsigned long flags;
  546. u32 reg_val;
  547. /* Enable Tx at MAC */
  548. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  549. pdata->mac_cr |= MAC_CR_TXEN_;
  550. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  551. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  552. /* Enable Tx at SCSRs */
  553. reg_val = TX_CFG_ON_;
  554. smsc95xx_write_reg(dev, TX_CFG, reg_val);
  555. }
  556. /* Starts the Receive path */
  557. static void smsc95xx_start_rx_path(struct usbnet *dev)
  558. {
  559. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  560. unsigned long flags;
  561. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  562. pdata->mac_cr |= MAC_CR_RXEN_;
  563. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  564. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  565. }
  566. static int smsc95xx_phy_initialize(struct usbnet *dev)
  567. {
  568. int bmcr, timeout = 0;
  569. /* Initialize MII structure */
  570. dev->mii.dev = dev->net;
  571. dev->mii.mdio_read = smsc95xx_mdio_read;
  572. dev->mii.mdio_write = smsc95xx_mdio_write;
  573. dev->mii.phy_id_mask = 0x1f;
  574. dev->mii.reg_num_mask = 0x1f;
  575. dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
  576. /* reset phy and wait for reset to complete */
  577. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  578. do {
  579. msleep(10);
  580. bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  581. timeout++;
  582. } while ((bmcr & MII_BMCR) && (timeout < 100));
  583. if (timeout >= 100) {
  584. netdev_warn(dev->net, "timeout on PHY Reset");
  585. return -EIO;
  586. }
  587. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  588. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  589. ADVERTISE_PAUSE_ASYM);
  590. /* read to clear */
  591. smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  592. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  593. PHY_INT_MASK_DEFAULT_);
  594. mii_nway_restart(&dev->mii);
  595. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  596. return 0;
  597. }
  598. static int smsc95xx_reset(struct usbnet *dev)
  599. {
  600. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  601. struct net_device *netdev = dev->net;
  602. u32 read_buf, write_buf, burst_cap;
  603. int ret = 0, timeout;
  604. netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n");
  605. write_buf = HW_CFG_LRST_;
  606. ret = smsc95xx_write_reg(dev, HW_CFG, write_buf);
  607. if (ret < 0) {
  608. netdev_warn(dev->net, "Failed to write HW_CFG_LRST_ bit in HW_CFG register, ret = %d\n",
  609. ret);
  610. return ret;
  611. }
  612. timeout = 0;
  613. do {
  614. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  615. if (ret < 0) {
  616. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  617. return ret;
  618. }
  619. msleep(10);
  620. timeout++;
  621. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  622. if (timeout >= 100) {
  623. netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
  624. return ret;
  625. }
  626. write_buf = PM_CTL_PHY_RST_;
  627. ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);
  628. if (ret < 0) {
  629. netdev_warn(dev->net, "Failed to write PM_CTRL: %d\n", ret);
  630. return ret;
  631. }
  632. timeout = 0;
  633. do {
  634. ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
  635. if (ret < 0) {
  636. netdev_warn(dev->net, "Failed to read PM_CTRL: %d\n", ret);
  637. return ret;
  638. }
  639. msleep(10);
  640. timeout++;
  641. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  642. if (timeout >= 100) {
  643. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  644. return ret;
  645. }
  646. smsc95xx_init_mac_address(dev);
  647. ret = smsc95xx_set_mac_address(dev);
  648. if (ret < 0)
  649. return ret;
  650. netif_dbg(dev, ifup, dev->net,
  651. "MAC Address: %pM\n", dev->net->dev_addr);
  652. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  653. if (ret < 0) {
  654. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  655. return ret;
  656. }
  657. netif_dbg(dev, ifup, dev->net,
  658. "Read Value from HW_CFG : 0x%08x\n", read_buf);
  659. read_buf |= HW_CFG_BIR_;
  660. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  661. if (ret < 0) {
  662. netdev_warn(dev->net, "Failed to write HW_CFG_BIR_ bit in HW_CFG register, ret = %d\n",
  663. ret);
  664. return ret;
  665. }
  666. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  667. if (ret < 0) {
  668. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  669. return ret;
  670. }
  671. netif_dbg(dev, ifup, dev->net,
  672. "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n",
  673. read_buf);
  674. if (!turbo_mode) {
  675. burst_cap = 0;
  676. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  677. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  678. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  679. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  680. } else {
  681. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  682. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  683. }
  684. netif_dbg(dev, ifup, dev->net,
  685. "rx_urb_size=%ld\n", (ulong)dev->rx_urb_size);
  686. ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
  687. if (ret < 0) {
  688. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  689. return ret;
  690. }
  691. ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
  692. if (ret < 0) {
  693. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  694. return ret;
  695. }
  696. netif_dbg(dev, ifup, dev->net,
  697. "Read Value from BURST_CAP after writing: 0x%08x\n",
  698. read_buf);
  699. read_buf = DEFAULT_BULK_IN_DELAY;
  700. ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);
  701. if (ret < 0) {
  702. netdev_warn(dev->net, "ret = %d\n", ret);
  703. return ret;
  704. }
  705. ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
  706. if (ret < 0) {
  707. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  708. return ret;
  709. }
  710. netif_dbg(dev, ifup, dev->net,
  711. "Read Value from BULK_IN_DLY after writing: 0x%08x\n",
  712. read_buf);
  713. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  714. if (ret < 0) {
  715. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  716. return ret;
  717. }
  718. netif_dbg(dev, ifup, dev->net,
  719. "Read Value from HW_CFG: 0x%08x\n", read_buf);
  720. if (turbo_mode)
  721. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  722. read_buf &= ~HW_CFG_RXDOFF_;
  723. /* set Rx data offset=2, Make IP header aligns on word boundary. */
  724. read_buf |= NET_IP_ALIGN << 9;
  725. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  726. if (ret < 0) {
  727. netdev_warn(dev->net, "Failed to write HW_CFG register, ret=%d\n",
  728. ret);
  729. return ret;
  730. }
  731. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  732. if (ret < 0) {
  733. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  734. return ret;
  735. }
  736. netif_dbg(dev, ifup, dev->net,
  737. "Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
  738. write_buf = 0xFFFFFFFF;
  739. ret = smsc95xx_write_reg(dev, INT_STS, write_buf);
  740. if (ret < 0) {
  741. netdev_warn(dev->net, "Failed to write INT_STS register, ret=%d\n",
  742. ret);
  743. return ret;
  744. }
  745. ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
  746. if (ret < 0) {
  747. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  748. return ret;
  749. }
  750. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf);
  751. /* Configure GPIO pins as LED outputs */
  752. write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
  753. LED_GPIO_CFG_FDX_LED;
  754. ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
  755. if (ret < 0) {
  756. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG register, ret=%d\n",
  757. ret);
  758. return ret;
  759. }
  760. /* Init Tx */
  761. write_buf = 0;
  762. ret = smsc95xx_write_reg(dev, FLOW, write_buf);
  763. if (ret < 0) {
  764. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  765. return ret;
  766. }
  767. read_buf = AFC_CFG_DEFAULT;
  768. ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);
  769. if (ret < 0) {
  770. netdev_warn(dev->net, "Failed to write AFC_CFG: %d\n", ret);
  771. return ret;
  772. }
  773. /* Don't need mac_cr_lock during initialisation */
  774. ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
  775. if (ret < 0) {
  776. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  777. return ret;
  778. }
  779. /* Init Rx */
  780. /* Set Vlan */
  781. write_buf = (u32)ETH_P_8021Q;
  782. ret = smsc95xx_write_reg(dev, VLAN1, write_buf);
  783. if (ret < 0) {
  784. netdev_warn(dev->net, "Failed to write VAN1: %d\n", ret);
  785. return ret;
  786. }
  787. /* Enable or disable checksum offload engines */
  788. ethtool_op_set_tx_hw_csum(netdev, pdata->use_tx_csum);
  789. ret = smsc95xx_set_csums(dev);
  790. if (ret < 0) {
  791. netdev_warn(dev->net, "Failed to set csum offload: %d\n", ret);
  792. return ret;
  793. }
  794. smsc95xx_set_multicast(dev->net);
  795. if (smsc95xx_phy_initialize(dev) < 0)
  796. return -EIO;
  797. ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
  798. if (ret < 0) {
  799. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  800. return ret;
  801. }
  802. /* enable PHY interrupts */
  803. read_buf |= INT_EP_CTL_PHY_INT_;
  804. ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
  805. if (ret < 0) {
  806. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  807. return ret;
  808. }
  809. smsc95xx_start_tx_path(dev);
  810. smsc95xx_start_rx_path(dev);
  811. netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n");
  812. return 0;
  813. }
  814. static const struct net_device_ops smsc95xx_netdev_ops = {
  815. .ndo_open = usbnet_open,
  816. .ndo_stop = usbnet_stop,
  817. .ndo_start_xmit = usbnet_start_xmit,
  818. .ndo_tx_timeout = usbnet_tx_timeout,
  819. .ndo_change_mtu = usbnet_change_mtu,
  820. .ndo_set_mac_address = eth_mac_addr,
  821. .ndo_validate_addr = eth_validate_addr,
  822. .ndo_do_ioctl = smsc95xx_ioctl,
  823. .ndo_set_multicast_list = smsc95xx_set_multicast,
  824. };
  825. static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
  826. {
  827. struct smsc95xx_priv *pdata = NULL;
  828. int ret;
  829. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  830. ret = usbnet_get_endpoints(dev, intf);
  831. if (ret < 0) {
  832. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  833. return ret;
  834. }
  835. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
  836. GFP_KERNEL);
  837. pdata = (struct smsc95xx_priv *)(dev->data[0]);
  838. if (!pdata) {
  839. netdev_warn(dev->net, "Unable to allocate struct smsc95xx_priv\n");
  840. return -ENOMEM;
  841. }
  842. spin_lock_init(&pdata->mac_cr_lock);
  843. pdata->use_tx_csum = DEFAULT_TX_CSUM_ENABLE;
  844. pdata->use_rx_csum = DEFAULT_RX_CSUM_ENABLE;
  845. /* Init all registers */
  846. ret = smsc95xx_reset(dev);
  847. dev->net->netdev_ops = &smsc95xx_netdev_ops;
  848. dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
  849. dev->net->flags |= IFF_MULTICAST;
  850. dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD;
  851. return 0;
  852. }
  853. static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  854. {
  855. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  856. if (pdata) {
  857. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  858. kfree(pdata);
  859. pdata = NULL;
  860. dev->data[0] = 0;
  861. }
  862. }
  863. static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
  864. {
  865. skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
  866. skb->ip_summed = CHECKSUM_COMPLETE;
  867. skb_trim(skb, skb->len - 2);
  868. }
  869. static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  870. {
  871. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  872. while (skb->len > 0) {
  873. u32 header, align_count;
  874. struct sk_buff *ax_skb;
  875. unsigned char *packet;
  876. u16 size;
  877. memcpy(&header, skb->data, sizeof(header));
  878. le32_to_cpus(&header);
  879. skb_pull(skb, 4 + NET_IP_ALIGN);
  880. packet = skb->data;
  881. /* get the packet length */
  882. size = (u16)((header & RX_STS_FL_) >> 16);
  883. align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
  884. if (unlikely(header & RX_STS_ES_)) {
  885. netif_dbg(dev, rx_err, dev->net,
  886. "Error header=0x%08x\n", header);
  887. dev->net->stats.rx_errors++;
  888. dev->net->stats.rx_dropped++;
  889. if (header & RX_STS_CRC_) {
  890. dev->net->stats.rx_crc_errors++;
  891. } else {
  892. if (header & (RX_STS_TL_ | RX_STS_RF_))
  893. dev->net->stats.rx_frame_errors++;
  894. if ((header & RX_STS_LE_) &&
  895. (!(header & RX_STS_FT_)))
  896. dev->net->stats.rx_length_errors++;
  897. }
  898. } else {
  899. /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
  900. if (unlikely(size > (ETH_FRAME_LEN + 12))) {
  901. netif_dbg(dev, rx_err, dev->net,
  902. "size err header=0x%08x\n", header);
  903. return 0;
  904. }
  905. /* last frame in this batch */
  906. if (skb->len == size) {
  907. if (pdata->use_rx_csum)
  908. smsc95xx_rx_csum_offload(skb);
  909. skb_trim(skb, skb->len - 4); /* remove fcs */
  910. skb->truesize = size + sizeof(struct sk_buff);
  911. return 1;
  912. }
  913. ax_skb = skb_clone(skb, GFP_ATOMIC);
  914. if (unlikely(!ax_skb)) {
  915. netdev_warn(dev->net, "Error allocating skb\n");
  916. return 0;
  917. }
  918. ax_skb->len = size;
  919. ax_skb->data = packet;
  920. skb_set_tail_pointer(ax_skb, size);
  921. if (pdata->use_rx_csum)
  922. smsc95xx_rx_csum_offload(ax_skb);
  923. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  924. ax_skb->truesize = size + sizeof(struct sk_buff);
  925. usbnet_skb_return(dev, ax_skb);
  926. }
  927. skb_pull(skb, size);
  928. /* padding bytes before the next frame starts */
  929. if (skb->len)
  930. skb_pull(skb, align_count);
  931. }
  932. if (unlikely(skb->len < 0)) {
  933. netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
  934. return 0;
  935. }
  936. return 1;
  937. }
  938. static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
  939. {
  940. int len = skb->data - skb->head;
  941. u16 high_16 = (u16)(skb->csum_offset + skb->csum_start - len);
  942. u16 low_16 = (u16)(skb->csum_start - len);
  943. return (high_16 << 16) | low_16;
  944. }
  945. static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
  946. struct sk_buff *skb, gfp_t flags)
  947. {
  948. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  949. bool csum = pdata->use_tx_csum && (skb->ip_summed == CHECKSUM_PARTIAL);
  950. int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
  951. u32 tx_cmd_a, tx_cmd_b;
  952. /* We do not advertise SG, so skbs should be already linearized */
  953. BUG_ON(skb_shinfo(skb)->nr_frags);
  954. if (skb_headroom(skb) < overhead) {
  955. struct sk_buff *skb2 = skb_copy_expand(skb,
  956. overhead, 0, flags);
  957. dev_kfree_skb_any(skb);
  958. skb = skb2;
  959. if (!skb)
  960. return NULL;
  961. }
  962. if (csum) {
  963. if (skb->len <= 45) {
  964. /* workaround - hardware tx checksum does not work
  965. * properly with extremely small packets */
  966. long csstart = skb->csum_start - skb_headroom(skb);
  967. __wsum calc = csum_partial(skb->data + csstart,
  968. skb->len - csstart, 0);
  969. *((__sum16 *)(skb->data + csstart
  970. + skb->csum_offset)) = csum_fold(calc);
  971. csum = false;
  972. } else {
  973. u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
  974. skb_push(skb, 4);
  975. memcpy(skb->data, &csum_preamble, 4);
  976. }
  977. }
  978. skb_push(skb, 4);
  979. tx_cmd_b = (u32)(skb->len - 4);
  980. if (csum)
  981. tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
  982. cpu_to_le32s(&tx_cmd_b);
  983. memcpy(skb->data, &tx_cmd_b, 4);
  984. skb_push(skb, 4);
  985. tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
  986. TX_CMD_A_LAST_SEG_;
  987. cpu_to_le32s(&tx_cmd_a);
  988. memcpy(skb->data, &tx_cmd_a, 4);
  989. return skb;
  990. }
  991. static const struct driver_info smsc95xx_info = {
  992. .description = "smsc95xx USB 2.0 Ethernet",
  993. .bind = smsc95xx_bind,
  994. .unbind = smsc95xx_unbind,
  995. .link_reset = smsc95xx_link_reset,
  996. .reset = smsc95xx_reset,
  997. .rx_fixup = smsc95xx_rx_fixup,
  998. .tx_fixup = smsc95xx_tx_fixup,
  999. .status = smsc95xx_status,
  1000. .flags = FLAG_ETHER | FLAG_SEND_ZLP,
  1001. };
  1002. static const struct usb_device_id products[] = {
  1003. {
  1004. /* SMSC9500 USB Ethernet Device */
  1005. USB_DEVICE(0x0424, 0x9500),
  1006. .driver_info = (unsigned long) &smsc95xx_info,
  1007. },
  1008. {
  1009. /* SMSC9505 USB Ethernet Device */
  1010. USB_DEVICE(0x0424, 0x9505),
  1011. .driver_info = (unsigned long) &smsc95xx_info,
  1012. },
  1013. {
  1014. /* SMSC9500A USB Ethernet Device */
  1015. USB_DEVICE(0x0424, 0x9E00),
  1016. .driver_info = (unsigned long) &smsc95xx_info,
  1017. },
  1018. {
  1019. /* SMSC9505A USB Ethernet Device */
  1020. USB_DEVICE(0x0424, 0x9E01),
  1021. .driver_info = (unsigned long) &smsc95xx_info,
  1022. },
  1023. {
  1024. /* SMSC9512/9514 USB Hub & Ethernet Device */
  1025. USB_DEVICE(0x0424, 0xec00),
  1026. .driver_info = (unsigned long) &smsc95xx_info,
  1027. },
  1028. {
  1029. /* SMSC9500 USB Ethernet Device (SAL10) */
  1030. USB_DEVICE(0x0424, 0x9900),
  1031. .driver_info = (unsigned long) &smsc95xx_info,
  1032. },
  1033. {
  1034. /* SMSC9505 USB Ethernet Device (SAL10) */
  1035. USB_DEVICE(0x0424, 0x9901),
  1036. .driver_info = (unsigned long) &smsc95xx_info,
  1037. },
  1038. {
  1039. /* SMSC9500A USB Ethernet Device (SAL10) */
  1040. USB_DEVICE(0x0424, 0x9902),
  1041. .driver_info = (unsigned long) &smsc95xx_info,
  1042. },
  1043. {
  1044. /* SMSC9505A USB Ethernet Device (SAL10) */
  1045. USB_DEVICE(0x0424, 0x9903),
  1046. .driver_info = (unsigned long) &smsc95xx_info,
  1047. },
  1048. {
  1049. /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */
  1050. USB_DEVICE(0x0424, 0x9904),
  1051. .driver_info = (unsigned long) &smsc95xx_info,
  1052. },
  1053. {
  1054. /* SMSC9500A USB Ethernet Device (HAL) */
  1055. USB_DEVICE(0x0424, 0x9905),
  1056. .driver_info = (unsigned long) &smsc95xx_info,
  1057. },
  1058. {
  1059. /* SMSC9505A USB Ethernet Device (HAL) */
  1060. USB_DEVICE(0x0424, 0x9906),
  1061. .driver_info = (unsigned long) &smsc95xx_info,
  1062. },
  1063. {
  1064. /* SMSC9500 USB Ethernet Device (Alternate ID) */
  1065. USB_DEVICE(0x0424, 0x9907),
  1066. .driver_info = (unsigned long) &smsc95xx_info,
  1067. },
  1068. {
  1069. /* SMSC9500A USB Ethernet Device (Alternate ID) */
  1070. USB_DEVICE(0x0424, 0x9908),
  1071. .driver_info = (unsigned long) &smsc95xx_info,
  1072. },
  1073. {
  1074. /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */
  1075. USB_DEVICE(0x0424, 0x9909),
  1076. .driver_info = (unsigned long) &smsc95xx_info,
  1077. },
  1078. { }, /* END */
  1079. };
  1080. MODULE_DEVICE_TABLE(usb, products);
  1081. static struct usb_driver smsc95xx_driver = {
  1082. .name = "smsc95xx",
  1083. .id_table = products,
  1084. .probe = usbnet_probe,
  1085. .suspend = usbnet_suspend,
  1086. .resume = usbnet_resume,
  1087. .disconnect = usbnet_disconnect,
  1088. };
  1089. static int __init smsc95xx_init(void)
  1090. {
  1091. return usb_register(&smsc95xx_driver);
  1092. }
  1093. module_init(smsc95xx_init);
  1094. static void __exit smsc95xx_exit(void)
  1095. {
  1096. usb_deregister(&smsc95xx_driver);
  1097. }
  1098. module_exit(smsc95xx_exit);
  1099. MODULE_AUTHOR("Nancy Lin");
  1100. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@smsc.com>");
  1101. MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
  1102. MODULE_LICENSE("GPL");