marvell.c 15 KB

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  1. /*
  2. * drivers/net/phy/marvell.c
  3. *
  4. * Driver for Marvell PHYs
  5. *
  6. * Author: Andy Fleming
  7. *
  8. * Copyright (c) 2004 Freescale Semiconductor, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. *
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/string.h>
  18. #include <linux/errno.h>
  19. #include <linux/unistd.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/init.h>
  22. #include <linux/delay.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/skbuff.h>
  26. #include <linux/spinlock.h>
  27. #include <linux/mm.h>
  28. #include <linux/module.h>
  29. #include <linux/mii.h>
  30. #include <linux/ethtool.h>
  31. #include <linux/phy.h>
  32. #include <asm/io.h>
  33. #include <asm/irq.h>
  34. #include <asm/uaccess.h>
  35. #define MII_M1011_IEVENT 0x13
  36. #define MII_M1011_IEVENT_CLEAR 0x0000
  37. #define MII_M1011_IMASK 0x12
  38. #define MII_M1011_IMASK_INIT 0x6400
  39. #define MII_M1011_IMASK_CLEAR 0x0000
  40. #define MII_M1011_PHY_SCR 0x10
  41. #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
  42. #define MII_M1145_PHY_EXT_CR 0x14
  43. #define MII_M1145_RGMII_RX_DELAY 0x0080
  44. #define MII_M1145_RGMII_TX_DELAY 0x0002
  45. #define M1145_DEV_FLAGS_RESISTANCE 0x00000001
  46. #define MII_M1111_PHY_LED_CONTROL 0x18
  47. #define MII_M1111_PHY_LED_DIRECT 0x4100
  48. #define MII_M1111_PHY_LED_COMBINE 0x411c
  49. #define MII_M1111_PHY_EXT_CR 0x14
  50. #define MII_M1111_RX_DELAY 0x80
  51. #define MII_M1111_TX_DELAY 0x2
  52. #define MII_M1111_PHY_EXT_SR 0x1b
  53. #define MII_M1111_HWCFG_MODE_MASK 0xf
  54. #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
  55. #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
  56. #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
  57. #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
  58. #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
  59. #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
  60. #define MII_M1111_COPPER 0
  61. #define MII_M1111_FIBER 1
  62. #define MII_88E1121_PHY_LED_CTRL 16
  63. #define MII_88E1121_PHY_LED_PAGE 3
  64. #define MII_88E1121_PHY_LED_DEF 0x0030
  65. #define MII_88E1121_PHY_PAGE 22
  66. #define MII_M1011_PHY_STATUS 0x11
  67. #define MII_M1011_PHY_STATUS_1000 0x8000
  68. #define MII_M1011_PHY_STATUS_100 0x4000
  69. #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
  70. #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
  71. #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
  72. #define MII_M1011_PHY_STATUS_LINK 0x0400
  73. MODULE_DESCRIPTION("Marvell PHY driver");
  74. MODULE_AUTHOR("Andy Fleming");
  75. MODULE_LICENSE("GPL");
  76. static int marvell_ack_interrupt(struct phy_device *phydev)
  77. {
  78. int err;
  79. /* Clear the interrupts by reading the reg */
  80. err = phy_read(phydev, MII_M1011_IEVENT);
  81. if (err < 0)
  82. return err;
  83. return 0;
  84. }
  85. static int marvell_config_intr(struct phy_device *phydev)
  86. {
  87. int err;
  88. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  89. err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
  90. else
  91. err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
  92. return err;
  93. }
  94. static int marvell_config_aneg(struct phy_device *phydev)
  95. {
  96. int err;
  97. /* The Marvell PHY has an errata which requires
  98. * that certain registers get written in order
  99. * to restart autonegotiation */
  100. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  101. if (err < 0)
  102. return err;
  103. err = phy_write(phydev, 0x1d, 0x1f);
  104. if (err < 0)
  105. return err;
  106. err = phy_write(phydev, 0x1e, 0x200c);
  107. if (err < 0)
  108. return err;
  109. err = phy_write(phydev, 0x1d, 0x5);
  110. if (err < 0)
  111. return err;
  112. err = phy_write(phydev, 0x1e, 0);
  113. if (err < 0)
  114. return err;
  115. err = phy_write(phydev, 0x1e, 0x100);
  116. if (err < 0)
  117. return err;
  118. err = phy_write(phydev, MII_M1011_PHY_SCR,
  119. MII_M1011_PHY_SCR_AUTO_CROSS);
  120. if (err < 0)
  121. return err;
  122. err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
  123. MII_M1111_PHY_LED_DIRECT);
  124. if (err < 0)
  125. return err;
  126. err = genphy_config_aneg(phydev);
  127. if (err < 0)
  128. return err;
  129. if (phydev->autoneg != AUTONEG_ENABLE) {
  130. int bmcr;
  131. /*
  132. * A write to speed/duplex bits (that is performed by
  133. * genphy_config_aneg() call above) must be followed by
  134. * a software reset. Otherwise, the write has no effect.
  135. */
  136. bmcr = phy_read(phydev, MII_BMCR);
  137. if (bmcr < 0)
  138. return bmcr;
  139. err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
  140. if (err < 0)
  141. return err;
  142. }
  143. return 0;
  144. }
  145. static int m88e1121_config_aneg(struct phy_device *phydev)
  146. {
  147. int err, temp;
  148. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  149. if (err < 0)
  150. return err;
  151. err = phy_write(phydev, MII_M1011_PHY_SCR,
  152. MII_M1011_PHY_SCR_AUTO_CROSS);
  153. if (err < 0)
  154. return err;
  155. temp = phy_read(phydev, MII_88E1121_PHY_PAGE);
  156. phy_write(phydev, MII_88E1121_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
  157. phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
  158. phy_write(phydev, MII_88E1121_PHY_PAGE, temp);
  159. err = genphy_config_aneg(phydev);
  160. return err;
  161. }
  162. static int m88e1111_config_init(struct phy_device *phydev)
  163. {
  164. int err;
  165. int temp;
  166. /* Enable Fiber/Copper auto selection */
  167. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  168. temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO;
  169. phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  170. temp = phy_read(phydev, MII_BMCR);
  171. temp |= BMCR_RESET;
  172. phy_write(phydev, MII_BMCR, temp);
  173. if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
  174. (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
  175. (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
  176. (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
  177. temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
  178. if (temp < 0)
  179. return temp;
  180. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
  181. temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
  182. } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
  183. temp &= ~MII_M1111_TX_DELAY;
  184. temp |= MII_M1111_RX_DELAY;
  185. } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
  186. temp &= ~MII_M1111_RX_DELAY;
  187. temp |= MII_M1111_TX_DELAY;
  188. }
  189. err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
  190. if (err < 0)
  191. return err;
  192. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  193. if (temp < 0)
  194. return temp;
  195. temp &= ~(MII_M1111_HWCFG_MODE_MASK);
  196. if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
  197. temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
  198. else
  199. temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
  200. err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  201. if (err < 0)
  202. return err;
  203. }
  204. if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  205. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  206. if (temp < 0)
  207. return temp;
  208. temp &= ~(MII_M1111_HWCFG_MODE_MASK);
  209. temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
  210. temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
  211. err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  212. if (err < 0)
  213. return err;
  214. }
  215. if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
  216. temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
  217. if (temp < 0)
  218. return temp;
  219. temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
  220. err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
  221. if (err < 0)
  222. return err;
  223. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  224. if (temp < 0)
  225. return temp;
  226. temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
  227. temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
  228. err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  229. if (err < 0)
  230. return err;
  231. /* soft reset */
  232. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  233. if (err < 0)
  234. return err;
  235. do
  236. temp = phy_read(phydev, MII_BMCR);
  237. while (temp & BMCR_RESET);
  238. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  239. if (temp < 0)
  240. return temp;
  241. temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
  242. temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
  243. err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  244. if (err < 0)
  245. return err;
  246. }
  247. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  248. if (err < 0)
  249. return err;
  250. return 0;
  251. }
  252. static int m88e1118_config_aneg(struct phy_device *phydev)
  253. {
  254. int err;
  255. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  256. if (err < 0)
  257. return err;
  258. err = phy_write(phydev, MII_M1011_PHY_SCR,
  259. MII_M1011_PHY_SCR_AUTO_CROSS);
  260. if (err < 0)
  261. return err;
  262. err = genphy_config_aneg(phydev);
  263. return 0;
  264. }
  265. static int m88e1118_config_init(struct phy_device *phydev)
  266. {
  267. int err;
  268. /* Change address */
  269. err = phy_write(phydev, 0x16, 0x0002);
  270. if (err < 0)
  271. return err;
  272. /* Enable 1000 Mbit */
  273. err = phy_write(phydev, 0x15, 0x1070);
  274. if (err < 0)
  275. return err;
  276. /* Change address */
  277. err = phy_write(phydev, 0x16, 0x0003);
  278. if (err < 0)
  279. return err;
  280. /* Adjust LED Control */
  281. err = phy_write(phydev, 0x10, 0x021e);
  282. if (err < 0)
  283. return err;
  284. /* Reset address */
  285. err = phy_write(phydev, 0x16, 0x0);
  286. if (err < 0)
  287. return err;
  288. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  289. if (err < 0)
  290. return err;
  291. return 0;
  292. }
  293. static int m88e1145_config_init(struct phy_device *phydev)
  294. {
  295. int err;
  296. /* Take care of errata E0 & E1 */
  297. err = phy_write(phydev, 0x1d, 0x001b);
  298. if (err < 0)
  299. return err;
  300. err = phy_write(phydev, 0x1e, 0x418f);
  301. if (err < 0)
  302. return err;
  303. err = phy_write(phydev, 0x1d, 0x0016);
  304. if (err < 0)
  305. return err;
  306. err = phy_write(phydev, 0x1e, 0xa2da);
  307. if (err < 0)
  308. return err;
  309. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
  310. int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
  311. if (temp < 0)
  312. return temp;
  313. temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
  314. err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
  315. if (err < 0)
  316. return err;
  317. if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
  318. err = phy_write(phydev, 0x1d, 0x0012);
  319. if (err < 0)
  320. return err;
  321. temp = phy_read(phydev, 0x1e);
  322. if (temp < 0)
  323. return temp;
  324. temp &= 0xf03f;
  325. temp |= 2 << 9; /* 36 ohm */
  326. temp |= 2 << 6; /* 39 ohm */
  327. err = phy_write(phydev, 0x1e, temp);
  328. if (err < 0)
  329. return err;
  330. err = phy_write(phydev, 0x1d, 0x3);
  331. if (err < 0)
  332. return err;
  333. err = phy_write(phydev, 0x1e, 0x8000);
  334. if (err < 0)
  335. return err;
  336. }
  337. }
  338. return 0;
  339. }
  340. /* marvell_read_status
  341. *
  342. * Generic status code does not detect Fiber correctly!
  343. * Description:
  344. * Check the link, then figure out the current state
  345. * by comparing what we advertise with what the link partner
  346. * advertises. Start by checking the gigabit possibilities,
  347. * then move on to 10/100.
  348. */
  349. static int marvell_read_status(struct phy_device *phydev)
  350. {
  351. int adv;
  352. int err;
  353. int lpa;
  354. int status = 0;
  355. /* Update the link, but return if there
  356. * was an error */
  357. err = genphy_update_link(phydev);
  358. if (err)
  359. return err;
  360. if (AUTONEG_ENABLE == phydev->autoneg) {
  361. status = phy_read(phydev, MII_M1011_PHY_STATUS);
  362. if (status < 0)
  363. return status;
  364. lpa = phy_read(phydev, MII_LPA);
  365. if (lpa < 0)
  366. return lpa;
  367. adv = phy_read(phydev, MII_ADVERTISE);
  368. if (adv < 0)
  369. return adv;
  370. lpa &= adv;
  371. if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
  372. phydev->duplex = DUPLEX_FULL;
  373. else
  374. phydev->duplex = DUPLEX_HALF;
  375. status = status & MII_M1011_PHY_STATUS_SPD_MASK;
  376. phydev->pause = phydev->asym_pause = 0;
  377. switch (status) {
  378. case MII_M1011_PHY_STATUS_1000:
  379. phydev->speed = SPEED_1000;
  380. break;
  381. case MII_M1011_PHY_STATUS_100:
  382. phydev->speed = SPEED_100;
  383. break;
  384. default:
  385. phydev->speed = SPEED_10;
  386. break;
  387. }
  388. if (phydev->duplex == DUPLEX_FULL) {
  389. phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
  390. phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
  391. }
  392. } else {
  393. int bmcr = phy_read(phydev, MII_BMCR);
  394. if (bmcr < 0)
  395. return bmcr;
  396. if (bmcr & BMCR_FULLDPLX)
  397. phydev->duplex = DUPLEX_FULL;
  398. else
  399. phydev->duplex = DUPLEX_HALF;
  400. if (bmcr & BMCR_SPEED1000)
  401. phydev->speed = SPEED_1000;
  402. else if (bmcr & BMCR_SPEED100)
  403. phydev->speed = SPEED_100;
  404. else
  405. phydev->speed = SPEED_10;
  406. phydev->pause = phydev->asym_pause = 0;
  407. }
  408. return 0;
  409. }
  410. static int m88e1121_did_interrupt(struct phy_device *phydev)
  411. {
  412. int imask;
  413. imask = phy_read(phydev, MII_M1011_IEVENT);
  414. if (imask & MII_M1011_IMASK_INIT)
  415. return 1;
  416. return 0;
  417. }
  418. static struct phy_driver marvell_drivers[] = {
  419. {
  420. .phy_id = 0x01410c60,
  421. .phy_id_mask = 0xfffffff0,
  422. .name = "Marvell 88E1101",
  423. .features = PHY_GBIT_FEATURES,
  424. .flags = PHY_HAS_INTERRUPT,
  425. .config_aneg = &marvell_config_aneg,
  426. .read_status = &genphy_read_status,
  427. .ack_interrupt = &marvell_ack_interrupt,
  428. .config_intr = &marvell_config_intr,
  429. .driver = { .owner = THIS_MODULE },
  430. },
  431. {
  432. .phy_id = 0x01410c90,
  433. .phy_id_mask = 0xfffffff0,
  434. .name = "Marvell 88E1112",
  435. .features = PHY_GBIT_FEATURES,
  436. .flags = PHY_HAS_INTERRUPT,
  437. .config_init = &m88e1111_config_init,
  438. .config_aneg = &marvell_config_aneg,
  439. .read_status = &genphy_read_status,
  440. .ack_interrupt = &marvell_ack_interrupt,
  441. .config_intr = &marvell_config_intr,
  442. .driver = { .owner = THIS_MODULE },
  443. },
  444. {
  445. .phy_id = 0x01410cc0,
  446. .phy_id_mask = 0xfffffff0,
  447. .name = "Marvell 88E1111",
  448. .features = PHY_GBIT_FEATURES,
  449. .flags = PHY_HAS_INTERRUPT,
  450. .config_init = &m88e1111_config_init,
  451. .config_aneg = &marvell_config_aneg,
  452. .read_status = &marvell_read_status,
  453. .ack_interrupt = &marvell_ack_interrupt,
  454. .config_intr = &marvell_config_intr,
  455. .driver = { .owner = THIS_MODULE },
  456. },
  457. {
  458. .phy_id = 0x01410e10,
  459. .phy_id_mask = 0xfffffff0,
  460. .name = "Marvell 88E1118",
  461. .features = PHY_GBIT_FEATURES,
  462. .flags = PHY_HAS_INTERRUPT,
  463. .config_init = &m88e1118_config_init,
  464. .config_aneg = &m88e1118_config_aneg,
  465. .read_status = &genphy_read_status,
  466. .ack_interrupt = &marvell_ack_interrupt,
  467. .config_intr = &marvell_config_intr,
  468. .driver = {.owner = THIS_MODULE,},
  469. },
  470. {
  471. .phy_id = 0x01410cb0,
  472. .phy_id_mask = 0xfffffff0,
  473. .name = "Marvell 88E1121R",
  474. .features = PHY_GBIT_FEATURES,
  475. .flags = PHY_HAS_INTERRUPT,
  476. .config_aneg = &m88e1121_config_aneg,
  477. .read_status = &marvell_read_status,
  478. .ack_interrupt = &marvell_ack_interrupt,
  479. .config_intr = &marvell_config_intr,
  480. .did_interrupt = &m88e1121_did_interrupt,
  481. .driver = { .owner = THIS_MODULE },
  482. },
  483. {
  484. .phy_id = 0x01410cd0,
  485. .phy_id_mask = 0xfffffff0,
  486. .name = "Marvell 88E1145",
  487. .features = PHY_GBIT_FEATURES,
  488. .flags = PHY_HAS_INTERRUPT,
  489. .config_init = &m88e1145_config_init,
  490. .config_aneg = &marvell_config_aneg,
  491. .read_status = &genphy_read_status,
  492. .ack_interrupt = &marvell_ack_interrupt,
  493. .config_intr = &marvell_config_intr,
  494. .driver = { .owner = THIS_MODULE },
  495. },
  496. {
  497. .phy_id = 0x01410e30,
  498. .phy_id_mask = 0xfffffff0,
  499. .name = "Marvell 88E1240",
  500. .features = PHY_GBIT_FEATURES,
  501. .flags = PHY_HAS_INTERRUPT,
  502. .config_init = &m88e1111_config_init,
  503. .config_aneg = &marvell_config_aneg,
  504. .read_status = &genphy_read_status,
  505. .ack_interrupt = &marvell_ack_interrupt,
  506. .config_intr = &marvell_config_intr,
  507. .driver = { .owner = THIS_MODULE },
  508. },
  509. };
  510. static int __init marvell_init(void)
  511. {
  512. int ret;
  513. int i;
  514. for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) {
  515. ret = phy_driver_register(&marvell_drivers[i]);
  516. if (ret) {
  517. while (i-- > 0)
  518. phy_driver_unregister(&marvell_drivers[i]);
  519. return ret;
  520. }
  521. }
  522. return 0;
  523. }
  524. static void __exit marvell_exit(void)
  525. {
  526. int i;
  527. for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++)
  528. phy_driver_unregister(&marvell_drivers[i]);
  529. }
  530. module_init(marvell_init);
  531. module_exit(marvell_exit);