netxen_nic_init.c 42 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * Copyright (C) 2009 - QLogic Corporation.
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  19. * MA 02111-1307, USA.
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called "COPYING".
  23. *
  24. */
  25. #include <linux/netdevice.h>
  26. #include <linux/delay.h>
  27. #include <linux/slab.h>
  28. #include "netxen_nic.h"
  29. #include "netxen_nic_hw.h"
  30. struct crb_addr_pair {
  31. u32 addr;
  32. u32 data;
  33. };
  34. #define NETXEN_MAX_CRB_XFORM 60
  35. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  36. #define NETXEN_ADDR_ERROR (0xffffffff)
  37. #define crb_addr_transform(name) \
  38. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  39. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  40. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  41. static void
  42. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  43. struct nx_host_rds_ring *rds_ring);
  44. static int netxen_p3_has_mn(struct netxen_adapter *adapter);
  45. static void crb_addr_transform_setup(void)
  46. {
  47. crb_addr_transform(XDMA);
  48. crb_addr_transform(TIMR);
  49. crb_addr_transform(SRE);
  50. crb_addr_transform(SQN3);
  51. crb_addr_transform(SQN2);
  52. crb_addr_transform(SQN1);
  53. crb_addr_transform(SQN0);
  54. crb_addr_transform(SQS3);
  55. crb_addr_transform(SQS2);
  56. crb_addr_transform(SQS1);
  57. crb_addr_transform(SQS0);
  58. crb_addr_transform(RPMX7);
  59. crb_addr_transform(RPMX6);
  60. crb_addr_transform(RPMX5);
  61. crb_addr_transform(RPMX4);
  62. crb_addr_transform(RPMX3);
  63. crb_addr_transform(RPMX2);
  64. crb_addr_transform(RPMX1);
  65. crb_addr_transform(RPMX0);
  66. crb_addr_transform(ROMUSB);
  67. crb_addr_transform(SN);
  68. crb_addr_transform(QMN);
  69. crb_addr_transform(QMS);
  70. crb_addr_transform(PGNI);
  71. crb_addr_transform(PGND);
  72. crb_addr_transform(PGN3);
  73. crb_addr_transform(PGN2);
  74. crb_addr_transform(PGN1);
  75. crb_addr_transform(PGN0);
  76. crb_addr_transform(PGSI);
  77. crb_addr_transform(PGSD);
  78. crb_addr_transform(PGS3);
  79. crb_addr_transform(PGS2);
  80. crb_addr_transform(PGS1);
  81. crb_addr_transform(PGS0);
  82. crb_addr_transform(PS);
  83. crb_addr_transform(PH);
  84. crb_addr_transform(NIU);
  85. crb_addr_transform(I2Q);
  86. crb_addr_transform(EG);
  87. crb_addr_transform(MN);
  88. crb_addr_transform(MS);
  89. crb_addr_transform(CAS2);
  90. crb_addr_transform(CAS1);
  91. crb_addr_transform(CAS0);
  92. crb_addr_transform(CAM);
  93. crb_addr_transform(C2C1);
  94. crb_addr_transform(C2C0);
  95. crb_addr_transform(SMB);
  96. crb_addr_transform(OCM0);
  97. crb_addr_transform(I2C0);
  98. }
  99. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  100. {
  101. struct netxen_recv_context *recv_ctx;
  102. struct nx_host_rds_ring *rds_ring;
  103. struct netxen_rx_buffer *rx_buf;
  104. int i, ring;
  105. recv_ctx = &adapter->recv_ctx;
  106. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  107. rds_ring = &recv_ctx->rds_rings[ring];
  108. for (i = 0; i < rds_ring->num_desc; ++i) {
  109. rx_buf = &(rds_ring->rx_buf_arr[i]);
  110. if (rx_buf->state == NETXEN_BUFFER_FREE)
  111. continue;
  112. pci_unmap_single(adapter->pdev,
  113. rx_buf->dma,
  114. rds_ring->dma_size,
  115. PCI_DMA_FROMDEVICE);
  116. if (rx_buf->skb != NULL)
  117. dev_kfree_skb_any(rx_buf->skb);
  118. }
  119. }
  120. }
  121. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  122. {
  123. struct netxen_cmd_buffer *cmd_buf;
  124. struct netxen_skb_frag *buffrag;
  125. int i, j;
  126. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  127. cmd_buf = tx_ring->cmd_buf_arr;
  128. for (i = 0; i < tx_ring->num_desc; i++) {
  129. buffrag = cmd_buf->frag_array;
  130. if (buffrag->dma) {
  131. pci_unmap_single(adapter->pdev, buffrag->dma,
  132. buffrag->length, PCI_DMA_TODEVICE);
  133. buffrag->dma = 0ULL;
  134. }
  135. for (j = 0; j < cmd_buf->frag_count; j++) {
  136. buffrag++;
  137. if (buffrag->dma) {
  138. pci_unmap_page(adapter->pdev, buffrag->dma,
  139. buffrag->length,
  140. PCI_DMA_TODEVICE);
  141. buffrag->dma = 0ULL;
  142. }
  143. }
  144. if (cmd_buf->skb) {
  145. dev_kfree_skb_any(cmd_buf->skb);
  146. cmd_buf->skb = NULL;
  147. }
  148. cmd_buf++;
  149. }
  150. }
  151. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  152. {
  153. struct netxen_recv_context *recv_ctx;
  154. struct nx_host_rds_ring *rds_ring;
  155. struct nx_host_tx_ring *tx_ring;
  156. int ring;
  157. recv_ctx = &adapter->recv_ctx;
  158. if (recv_ctx->rds_rings == NULL)
  159. goto skip_rds;
  160. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  161. rds_ring = &recv_ctx->rds_rings[ring];
  162. vfree(rds_ring->rx_buf_arr);
  163. rds_ring->rx_buf_arr = NULL;
  164. }
  165. kfree(recv_ctx->rds_rings);
  166. skip_rds:
  167. if (adapter->tx_ring == NULL)
  168. return;
  169. tx_ring = adapter->tx_ring;
  170. vfree(tx_ring->cmd_buf_arr);
  171. kfree(tx_ring);
  172. adapter->tx_ring = NULL;
  173. }
  174. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  175. {
  176. struct netxen_recv_context *recv_ctx;
  177. struct nx_host_rds_ring *rds_ring;
  178. struct nx_host_sds_ring *sds_ring;
  179. struct nx_host_tx_ring *tx_ring;
  180. struct netxen_rx_buffer *rx_buf;
  181. int ring, i, size;
  182. struct netxen_cmd_buffer *cmd_buf_arr;
  183. struct net_device *netdev = adapter->netdev;
  184. struct pci_dev *pdev = adapter->pdev;
  185. size = sizeof(struct nx_host_tx_ring);
  186. tx_ring = kzalloc(size, GFP_KERNEL);
  187. if (tx_ring == NULL) {
  188. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  189. netdev->name);
  190. return -ENOMEM;
  191. }
  192. adapter->tx_ring = tx_ring;
  193. tx_ring->num_desc = adapter->num_txd;
  194. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  195. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  196. if (cmd_buf_arr == NULL) {
  197. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  198. netdev->name);
  199. return -ENOMEM;
  200. }
  201. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  202. tx_ring->cmd_buf_arr = cmd_buf_arr;
  203. recv_ctx = &adapter->recv_ctx;
  204. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  205. rds_ring = kzalloc(size, GFP_KERNEL);
  206. if (rds_ring == NULL) {
  207. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  208. netdev->name);
  209. return -ENOMEM;
  210. }
  211. recv_ctx->rds_rings = rds_ring;
  212. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  213. rds_ring = &recv_ctx->rds_rings[ring];
  214. switch (ring) {
  215. case RCV_RING_NORMAL:
  216. rds_ring->num_desc = adapter->num_rxd;
  217. if (adapter->ahw.cut_through) {
  218. rds_ring->dma_size =
  219. NX_CT_DEFAULT_RX_BUF_LEN;
  220. rds_ring->skb_size =
  221. NX_CT_DEFAULT_RX_BUF_LEN;
  222. } else {
  223. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  224. rds_ring->dma_size =
  225. NX_P3_RX_BUF_MAX_LEN;
  226. else
  227. rds_ring->dma_size =
  228. NX_P2_RX_BUF_MAX_LEN;
  229. rds_ring->skb_size =
  230. rds_ring->dma_size + NET_IP_ALIGN;
  231. }
  232. break;
  233. case RCV_RING_JUMBO:
  234. rds_ring->num_desc = adapter->num_jumbo_rxd;
  235. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  236. rds_ring->dma_size =
  237. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  238. else
  239. rds_ring->dma_size =
  240. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  241. if (adapter->capabilities & NX_CAP0_HW_LRO)
  242. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  243. rds_ring->skb_size =
  244. rds_ring->dma_size + NET_IP_ALIGN;
  245. break;
  246. case RCV_RING_LRO:
  247. rds_ring->num_desc = adapter->num_lro_rxd;
  248. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  249. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  250. break;
  251. }
  252. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  253. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  254. if (rds_ring->rx_buf_arr == NULL) {
  255. printk(KERN_ERR "%s: Failed to allocate "
  256. "rx buffer ring %d\n",
  257. netdev->name, ring);
  258. /* free whatever was already allocated */
  259. goto err_out;
  260. }
  261. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  262. INIT_LIST_HEAD(&rds_ring->free_list);
  263. /*
  264. * Now go through all of them, set reference handles
  265. * and put them in the queues.
  266. */
  267. rx_buf = rds_ring->rx_buf_arr;
  268. for (i = 0; i < rds_ring->num_desc; i++) {
  269. list_add_tail(&rx_buf->list,
  270. &rds_ring->free_list);
  271. rx_buf->ref_handle = i;
  272. rx_buf->state = NETXEN_BUFFER_FREE;
  273. rx_buf++;
  274. }
  275. spin_lock_init(&rds_ring->lock);
  276. }
  277. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  278. sds_ring = &recv_ctx->sds_rings[ring];
  279. sds_ring->irq = adapter->msix_entries[ring].vector;
  280. sds_ring->adapter = adapter;
  281. sds_ring->num_desc = adapter->num_rxd;
  282. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  283. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  284. }
  285. return 0;
  286. err_out:
  287. netxen_free_sw_resources(adapter);
  288. return -ENOMEM;
  289. }
  290. /*
  291. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  292. * address to external PCI CRB address.
  293. */
  294. static u32 netxen_decode_crb_addr(u32 addr)
  295. {
  296. int i;
  297. u32 base_addr, offset, pci_base;
  298. crb_addr_transform_setup();
  299. pci_base = NETXEN_ADDR_ERROR;
  300. base_addr = addr & 0xfff00000;
  301. offset = addr & 0x000fffff;
  302. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  303. if (crb_addr_xform[i] == base_addr) {
  304. pci_base = i << 20;
  305. break;
  306. }
  307. }
  308. if (pci_base == NETXEN_ADDR_ERROR)
  309. return pci_base;
  310. else
  311. return (pci_base + offset);
  312. }
  313. #define NETXEN_MAX_ROM_WAIT_USEC 100
  314. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  315. {
  316. long timeout = 0;
  317. long done = 0;
  318. cond_resched();
  319. while (done == 0) {
  320. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  321. done &= 2;
  322. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  323. dev_err(&adapter->pdev->dev,
  324. "Timeout reached waiting for rom done");
  325. return -EIO;
  326. }
  327. udelay(1);
  328. }
  329. return 0;
  330. }
  331. static int do_rom_fast_read(struct netxen_adapter *adapter,
  332. int addr, int *valp)
  333. {
  334. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  335. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  336. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  337. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  338. if (netxen_wait_rom_done(adapter)) {
  339. printk("Error waiting for rom done\n");
  340. return -EIO;
  341. }
  342. /* reset abyte_cnt and dummy_byte_cnt */
  343. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  344. udelay(10);
  345. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  346. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  347. return 0;
  348. }
  349. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  350. u8 *bytes, size_t size)
  351. {
  352. int addridx;
  353. int ret = 0;
  354. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  355. int v;
  356. ret = do_rom_fast_read(adapter, addridx, &v);
  357. if (ret != 0)
  358. break;
  359. *(__le32 *)bytes = cpu_to_le32(v);
  360. bytes += 4;
  361. }
  362. return ret;
  363. }
  364. int
  365. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  366. u8 *bytes, size_t size)
  367. {
  368. int ret;
  369. ret = netxen_rom_lock(adapter);
  370. if (ret < 0)
  371. return ret;
  372. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  373. netxen_rom_unlock(adapter);
  374. return ret;
  375. }
  376. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  377. {
  378. int ret;
  379. if (netxen_rom_lock(adapter) != 0)
  380. return -EIO;
  381. ret = do_rom_fast_read(adapter, addr, valp);
  382. netxen_rom_unlock(adapter);
  383. return ret;
  384. }
  385. #define NETXEN_BOARDTYPE 0x4008
  386. #define NETXEN_BOARDNUM 0x400c
  387. #define NETXEN_CHIPNUM 0x4010
  388. int netxen_pinit_from_rom(struct netxen_adapter *adapter)
  389. {
  390. int addr, val;
  391. int i, n, init_delay = 0;
  392. struct crb_addr_pair *buf;
  393. unsigned offset;
  394. u32 off;
  395. /* resetall */
  396. netxen_rom_lock(adapter);
  397. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  398. netxen_rom_unlock(adapter);
  399. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  400. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  401. (n != 0xcafecafe) ||
  402. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  403. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  404. "n: %08x\n", netxen_nic_driver_name, n);
  405. return -EIO;
  406. }
  407. offset = n & 0xffffU;
  408. n = (n >> 16) & 0xffffU;
  409. } else {
  410. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  411. !(n & 0x80000000)) {
  412. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  413. "n: %08x\n", netxen_nic_driver_name, n);
  414. return -EIO;
  415. }
  416. offset = 1;
  417. n &= ~0x80000000;
  418. }
  419. if (n >= 1024) {
  420. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  421. " initialized.\n", __func__, n);
  422. return -EIO;
  423. }
  424. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  425. if (buf == NULL) {
  426. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  427. netxen_nic_driver_name);
  428. return -ENOMEM;
  429. }
  430. for (i = 0; i < n; i++) {
  431. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  432. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  433. kfree(buf);
  434. return -EIO;
  435. }
  436. buf[i].addr = addr;
  437. buf[i].data = val;
  438. }
  439. for (i = 0; i < n; i++) {
  440. off = netxen_decode_crb_addr(buf[i].addr);
  441. if (off == NETXEN_ADDR_ERROR) {
  442. printk(KERN_ERR"CRB init value out of range %x\n",
  443. buf[i].addr);
  444. continue;
  445. }
  446. off += NETXEN_PCI_CRBSPACE;
  447. if (off & 1)
  448. continue;
  449. /* skipping cold reboot MAGIC */
  450. if (off == NETXEN_CAM_RAM(0x1fc))
  451. continue;
  452. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  453. if (off == (NETXEN_CRB_I2C0 + 0x1c))
  454. continue;
  455. /* do not reset PCI */
  456. if (off == (ROMUSB_GLB + 0xbc))
  457. continue;
  458. if (off == (ROMUSB_GLB + 0xa8))
  459. continue;
  460. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  461. continue;
  462. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  463. continue;
  464. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  465. continue;
  466. if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
  467. continue;
  468. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
  469. !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  470. buf[i].data = 0x1020;
  471. /* skip the function enable register */
  472. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  473. continue;
  474. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  475. continue;
  476. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  477. continue;
  478. }
  479. init_delay = 1;
  480. /* After writing this register, HW needs time for CRB */
  481. /* to quiet down (else crb_window returns 0xffffffff) */
  482. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  483. init_delay = 1000;
  484. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  485. /* hold xdma in reset also */
  486. buf[i].data = NETXEN_NIC_XDMA_RESET;
  487. buf[i].data = 0x8000ff;
  488. }
  489. }
  490. NXWR32(adapter, off, buf[i].data);
  491. msleep(init_delay);
  492. }
  493. kfree(buf);
  494. /* disable_peg_cache_all */
  495. /* unreset_net_cache */
  496. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  497. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  498. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  499. }
  500. /* p2dn replyCount */
  501. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  502. /* disable_peg_cache 0 */
  503. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  504. /* disable_peg_cache 1 */
  505. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  506. /* peg_clr_all */
  507. /* peg_clr 0 */
  508. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  509. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  510. /* peg_clr 1 */
  511. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  512. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  513. /* peg_clr 2 */
  514. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  515. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  516. /* peg_clr 3 */
  517. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  518. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  519. return 0;
  520. }
  521. static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
  522. {
  523. uint32_t i;
  524. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  525. __le32 entries = cpu_to_le32(directory->num_entries);
  526. for (i = 0; i < entries; i++) {
  527. __le32 offs = cpu_to_le32(directory->findex) +
  528. (i * cpu_to_le32(directory->entry_size));
  529. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  530. if (tab_type == section)
  531. return (struct uni_table_desc *) &unirom[offs];
  532. }
  533. return NULL;
  534. }
  535. static int
  536. nx_set_product_offs(struct netxen_adapter *adapter)
  537. {
  538. struct uni_table_desc *ptab_descr;
  539. const u8 *unirom = adapter->fw->data;
  540. uint32_t i;
  541. __le32 entries;
  542. int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
  543. 1 : netxen_p3_has_mn(adapter);
  544. ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
  545. if (ptab_descr == NULL)
  546. return -1;
  547. entries = cpu_to_le32(ptab_descr->num_entries);
  548. nomn:
  549. for (i = 0; i < entries; i++) {
  550. __le32 flags, file_chiprev, offs;
  551. u8 chiprev = adapter->ahw.revision_id;
  552. uint32_t flagbit;
  553. offs = cpu_to_le32(ptab_descr->findex) +
  554. (i * cpu_to_le32(ptab_descr->entry_size));
  555. flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
  556. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  557. NX_UNI_CHIP_REV_OFF));
  558. flagbit = mn_present ? 1 : 2;
  559. if ((chiprev == file_chiprev) &&
  560. ((1ULL << flagbit) & flags)) {
  561. adapter->file_prd_off = offs;
  562. return 0;
  563. }
  564. }
  565. if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  566. mn_present = 0;
  567. goto nomn;
  568. }
  569. return -1;
  570. }
  571. static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
  572. u32 section, u32 idx_offset)
  573. {
  574. const u8 *unirom = adapter->fw->data;
  575. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  576. idx_offset));
  577. struct uni_table_desc *tab_desc;
  578. __le32 offs;
  579. tab_desc = nx_get_table_desc(unirom, section);
  580. if (tab_desc == NULL)
  581. return NULL;
  582. offs = cpu_to_le32(tab_desc->findex) +
  583. (cpu_to_le32(tab_desc->entry_size) * idx);
  584. return (struct uni_data_desc *)&unirom[offs];
  585. }
  586. static u8 *
  587. nx_get_bootld_offs(struct netxen_adapter *adapter)
  588. {
  589. u32 offs = NETXEN_BOOTLD_START;
  590. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  591. offs = cpu_to_le32((nx_get_data_desc(adapter,
  592. NX_UNI_DIR_SECT_BOOTLD,
  593. NX_UNI_BOOTLD_IDX_OFF))->findex);
  594. return (u8 *)&adapter->fw->data[offs];
  595. }
  596. static u8 *
  597. nx_get_fw_offs(struct netxen_adapter *adapter)
  598. {
  599. u32 offs = NETXEN_IMAGE_START;
  600. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  601. offs = cpu_to_le32((nx_get_data_desc(adapter,
  602. NX_UNI_DIR_SECT_FW,
  603. NX_UNI_FIRMWARE_IDX_OFF))->findex);
  604. return (u8 *)&adapter->fw->data[offs];
  605. }
  606. static __le32
  607. nx_get_fw_size(struct netxen_adapter *adapter)
  608. {
  609. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  610. return cpu_to_le32((nx_get_data_desc(adapter,
  611. NX_UNI_DIR_SECT_FW,
  612. NX_UNI_FIRMWARE_IDX_OFF))->size);
  613. else
  614. return cpu_to_le32(
  615. *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
  616. }
  617. static __le32
  618. nx_get_fw_version(struct netxen_adapter *adapter)
  619. {
  620. struct uni_data_desc *fw_data_desc;
  621. const struct firmware *fw = adapter->fw;
  622. __le32 major, minor, sub;
  623. const u8 *ver_str;
  624. int i, ret = 0;
  625. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  626. fw_data_desc = nx_get_data_desc(adapter,
  627. NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
  628. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  629. cpu_to_le32(fw_data_desc->size) - 17;
  630. for (i = 0; i < 12; i++) {
  631. if (!strncmp(&ver_str[i], "REV=", 4)) {
  632. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  633. &major, &minor, &sub);
  634. break;
  635. }
  636. }
  637. if (ret != 3)
  638. return 0;
  639. return major + (minor << 8) + (sub << 16);
  640. } else
  641. return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  642. }
  643. static __le32
  644. nx_get_bios_version(struct netxen_adapter *adapter)
  645. {
  646. const struct firmware *fw = adapter->fw;
  647. __le32 bios_ver, prd_off = adapter->file_prd_off;
  648. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  649. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  650. + NX_UNI_BIOS_VERSION_OFF));
  651. return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) +
  652. (bios_ver >> 24);
  653. } else
  654. return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  655. }
  656. int
  657. netxen_need_fw_reset(struct netxen_adapter *adapter)
  658. {
  659. u32 count, old_count;
  660. u32 val, version, major, minor, build;
  661. int i, timeout;
  662. u8 fw_type;
  663. /* NX2031 firmware doesn't support heartbit */
  664. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  665. return 1;
  666. if (adapter->need_fw_reset)
  667. return 1;
  668. /* last attempt had failed */
  669. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  670. return 1;
  671. old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  672. for (i = 0; i < 10; i++) {
  673. timeout = msleep_interruptible(200);
  674. if (timeout) {
  675. NXWR32(adapter, CRB_CMDPEG_STATE,
  676. PHAN_INITIALIZE_FAILED);
  677. return -EINTR;
  678. }
  679. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  680. if (count != old_count)
  681. break;
  682. }
  683. /* firmware is dead */
  684. if (count == old_count)
  685. return 1;
  686. /* check if we have got newer or different file firmware */
  687. if (adapter->fw) {
  688. val = nx_get_fw_version(adapter);
  689. version = NETXEN_DECODE_VERSION(val);
  690. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  691. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  692. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  693. if (version > NETXEN_VERSION_CODE(major, minor, build))
  694. return 1;
  695. if (version == NETXEN_VERSION_CODE(major, minor, build) &&
  696. adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
  697. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  698. fw_type = (val & 0x4) ?
  699. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  700. if (adapter->fw_type != fw_type)
  701. return 1;
  702. }
  703. }
  704. return 0;
  705. }
  706. static char *fw_name[] = {
  707. NX_P2_MN_ROMIMAGE_NAME,
  708. NX_P3_CT_ROMIMAGE_NAME,
  709. NX_P3_MN_ROMIMAGE_NAME,
  710. NX_UNIFIED_ROMIMAGE_NAME,
  711. NX_FLASH_ROMIMAGE_NAME,
  712. };
  713. int
  714. netxen_load_firmware(struct netxen_adapter *adapter)
  715. {
  716. u64 *ptr64;
  717. u32 i, flashaddr, size;
  718. const struct firmware *fw = adapter->fw;
  719. struct pci_dev *pdev = adapter->pdev;
  720. dev_info(&pdev->dev, "loading firmware from %s\n",
  721. fw_name[adapter->fw_type]);
  722. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  723. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  724. if (fw) {
  725. __le64 data;
  726. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  727. ptr64 = (u64 *)nx_get_bootld_offs(adapter);
  728. flashaddr = NETXEN_BOOTLD_START;
  729. for (i = 0; i < size; i++) {
  730. data = cpu_to_le64(ptr64[i]);
  731. if (adapter->pci_mem_write(adapter, flashaddr, data))
  732. return -EIO;
  733. flashaddr += 8;
  734. }
  735. size = (__force u32)nx_get_fw_size(adapter) / 8;
  736. ptr64 = (u64 *)nx_get_fw_offs(adapter);
  737. flashaddr = NETXEN_IMAGE_START;
  738. for (i = 0; i < size; i++) {
  739. data = cpu_to_le64(ptr64[i]);
  740. if (adapter->pci_mem_write(adapter,
  741. flashaddr, data))
  742. return -EIO;
  743. flashaddr += 8;
  744. }
  745. } else {
  746. u64 data;
  747. u32 hi, lo;
  748. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  749. flashaddr = NETXEN_BOOTLD_START;
  750. for (i = 0; i < size; i++) {
  751. if (netxen_rom_fast_read(adapter,
  752. flashaddr, (int *)&lo) != 0)
  753. return -EIO;
  754. if (netxen_rom_fast_read(adapter,
  755. flashaddr + 4, (int *)&hi) != 0)
  756. return -EIO;
  757. /* hi, lo are already in host endian byteorder */
  758. data = (((u64)hi << 32) | lo);
  759. if (adapter->pci_mem_write(adapter,
  760. flashaddr, data))
  761. return -EIO;
  762. flashaddr += 8;
  763. }
  764. }
  765. msleep(1);
  766. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
  767. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
  768. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
  769. } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  770. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  771. else {
  772. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  773. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  774. }
  775. return 0;
  776. }
  777. static int
  778. netxen_validate_firmware(struct netxen_adapter *adapter)
  779. {
  780. __le32 val;
  781. u32 ver, min_ver, bios, min_size;
  782. struct pci_dev *pdev = adapter->pdev;
  783. const struct firmware *fw = adapter->fw;
  784. u8 fw_type = adapter->fw_type;
  785. if (fw_type == NX_UNIFIED_ROMIMAGE) {
  786. if (nx_set_product_offs(adapter))
  787. return -EINVAL;
  788. min_size = NX_UNI_FW_MIN_SIZE;
  789. } else {
  790. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  791. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  792. return -EINVAL;
  793. min_size = NX_FW_MIN_SIZE;
  794. }
  795. if (fw->size < min_size)
  796. return -EINVAL;
  797. val = nx_get_fw_version(adapter);
  798. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  799. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  800. else
  801. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  802. ver = NETXEN_DECODE_VERSION(val);
  803. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  804. dev_err(&pdev->dev,
  805. "%s: firmware version %d.%d.%d unsupported\n",
  806. fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
  807. return -EINVAL;
  808. }
  809. val = nx_get_bios_version(adapter);
  810. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  811. if ((__force u32)val != bios) {
  812. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  813. fw_name[fw_type]);
  814. return -EINVAL;
  815. }
  816. /* check if flashed firmware is newer */
  817. if (netxen_rom_fast_read(adapter,
  818. NX_FW_VERSION_OFFSET, (int *)&val))
  819. return -EIO;
  820. val = NETXEN_DECODE_VERSION(val);
  821. if (val > ver) {
  822. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  823. fw_name[fw_type]);
  824. return -EINVAL;
  825. }
  826. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  827. return 0;
  828. }
  829. static void
  830. nx_get_next_fwtype(struct netxen_adapter *adapter)
  831. {
  832. u8 fw_type;
  833. switch (adapter->fw_type) {
  834. case NX_UNKNOWN_ROMIMAGE:
  835. fw_type = NX_UNIFIED_ROMIMAGE;
  836. break;
  837. case NX_UNIFIED_ROMIMAGE:
  838. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  839. fw_type = NX_FLASH_ROMIMAGE;
  840. else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  841. fw_type = NX_P2_MN_ROMIMAGE;
  842. else if (netxen_p3_has_mn(adapter))
  843. fw_type = NX_P3_MN_ROMIMAGE;
  844. else
  845. fw_type = NX_P3_CT_ROMIMAGE;
  846. break;
  847. case NX_P3_MN_ROMIMAGE:
  848. fw_type = NX_P3_CT_ROMIMAGE;
  849. break;
  850. case NX_P2_MN_ROMIMAGE:
  851. case NX_P3_CT_ROMIMAGE:
  852. default:
  853. fw_type = NX_FLASH_ROMIMAGE;
  854. break;
  855. }
  856. adapter->fw_type = fw_type;
  857. }
  858. static int
  859. netxen_p3_has_mn(struct netxen_adapter *adapter)
  860. {
  861. u32 capability, flashed_ver;
  862. capability = 0;
  863. /* NX2031 always had MN */
  864. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  865. return 1;
  866. netxen_rom_fast_read(adapter,
  867. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  868. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  869. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  870. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  871. if (capability & NX_PEG_TUNE_MN_PRESENT)
  872. return 1;
  873. }
  874. return 0;
  875. }
  876. void netxen_request_firmware(struct netxen_adapter *adapter)
  877. {
  878. struct pci_dev *pdev = adapter->pdev;
  879. int rc = 0;
  880. adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
  881. next:
  882. nx_get_next_fwtype(adapter);
  883. if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
  884. adapter->fw = NULL;
  885. } else {
  886. rc = request_firmware(&adapter->fw,
  887. fw_name[adapter->fw_type], &pdev->dev);
  888. if (rc != 0)
  889. goto next;
  890. rc = netxen_validate_firmware(adapter);
  891. if (rc != 0) {
  892. release_firmware(adapter->fw);
  893. msleep(1);
  894. goto next;
  895. }
  896. }
  897. }
  898. void
  899. netxen_release_firmware(struct netxen_adapter *adapter)
  900. {
  901. if (adapter->fw)
  902. release_firmware(adapter->fw);
  903. adapter->fw = NULL;
  904. }
  905. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  906. {
  907. u64 addr;
  908. u32 hi, lo;
  909. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  910. return 0;
  911. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  912. NETXEN_HOST_DUMMY_DMA_SIZE,
  913. &adapter->dummy_dma.phys_addr);
  914. if (adapter->dummy_dma.addr == NULL) {
  915. dev_err(&adapter->pdev->dev,
  916. "ERROR: Could not allocate dummy DMA memory\n");
  917. return -ENOMEM;
  918. }
  919. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  920. hi = (addr >> 32) & 0xffffffff;
  921. lo = addr & 0xffffffff;
  922. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  923. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  924. return 0;
  925. }
  926. /*
  927. * NetXen DMA watchdog control:
  928. *
  929. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  930. * Bit 1 : disable_request => 1 req disable dma watchdog
  931. * Bit 2 : enable_request => 1 req enable dma watchdog
  932. * Bit 3-31 : unused
  933. */
  934. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  935. {
  936. int i = 100;
  937. u32 ctrl;
  938. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  939. return;
  940. if (!adapter->dummy_dma.addr)
  941. return;
  942. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  943. if ((ctrl & 0x1) != 0) {
  944. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  945. while ((ctrl & 0x1) != 0) {
  946. msleep(50);
  947. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  948. if (--i == 0)
  949. break;
  950. };
  951. }
  952. if (i) {
  953. pci_free_consistent(adapter->pdev,
  954. NETXEN_HOST_DUMMY_DMA_SIZE,
  955. adapter->dummy_dma.addr,
  956. adapter->dummy_dma.phys_addr);
  957. adapter->dummy_dma.addr = NULL;
  958. } else
  959. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  960. }
  961. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  962. {
  963. u32 val = 0;
  964. int retries = 60;
  965. if (pegtune_val)
  966. return 0;
  967. do {
  968. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  969. switch (val) {
  970. case PHAN_INITIALIZE_COMPLETE:
  971. case PHAN_INITIALIZE_ACK:
  972. return 0;
  973. case PHAN_INITIALIZE_FAILED:
  974. goto out_err;
  975. default:
  976. break;
  977. }
  978. msleep(500);
  979. } while (--retries);
  980. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  981. out_err:
  982. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  983. return -EIO;
  984. }
  985. static int
  986. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  987. {
  988. u32 val = 0;
  989. int retries = 2000;
  990. do {
  991. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  992. if (val == PHAN_PEG_RCV_INITIALIZED)
  993. return 0;
  994. msleep(10);
  995. } while (--retries);
  996. if (!retries) {
  997. printk(KERN_ERR "Receive Peg initialization not "
  998. "complete, state: 0x%x.\n", val);
  999. return -EIO;
  1000. }
  1001. return 0;
  1002. }
  1003. int netxen_init_firmware(struct netxen_adapter *adapter)
  1004. {
  1005. int err;
  1006. err = netxen_receive_peg_ready(adapter);
  1007. if (err)
  1008. return err;
  1009. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  1010. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  1011. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  1012. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  1013. return err;
  1014. }
  1015. static void
  1016. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  1017. {
  1018. u32 cable_OUI;
  1019. u16 cable_len;
  1020. u16 link_speed;
  1021. u8 link_status, module, duplex, autoneg;
  1022. struct net_device *netdev = adapter->netdev;
  1023. adapter->has_link_events = 1;
  1024. cable_OUI = msg->body[1] & 0xffffffff;
  1025. cable_len = (msg->body[1] >> 32) & 0xffff;
  1026. link_speed = (msg->body[1] >> 48) & 0xffff;
  1027. link_status = msg->body[2] & 0xff;
  1028. duplex = (msg->body[2] >> 16) & 0xff;
  1029. autoneg = (msg->body[2] >> 24) & 0xff;
  1030. module = (msg->body[2] >> 8) & 0xff;
  1031. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  1032. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  1033. netdev->name, cable_OUI, cable_len);
  1034. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  1035. printk(KERN_INFO "%s: unsupported cable length %d\n",
  1036. netdev->name, cable_len);
  1037. }
  1038. netxen_advert_link_change(adapter, link_status);
  1039. /* update link parameters */
  1040. if (duplex == LINKEVENT_FULL_DUPLEX)
  1041. adapter->link_duplex = DUPLEX_FULL;
  1042. else
  1043. adapter->link_duplex = DUPLEX_HALF;
  1044. adapter->module_type = module;
  1045. adapter->link_autoneg = autoneg;
  1046. adapter->link_speed = link_speed;
  1047. }
  1048. static void
  1049. netxen_handle_fw_message(int desc_cnt, int index,
  1050. struct nx_host_sds_ring *sds_ring)
  1051. {
  1052. nx_fw_msg_t msg;
  1053. struct status_desc *desc;
  1054. int i = 0, opcode;
  1055. while (desc_cnt > 0 && i < 8) {
  1056. desc = &sds_ring->desc_head[index];
  1057. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1058. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1059. index = get_next_index(index, sds_ring->num_desc);
  1060. desc_cnt--;
  1061. }
  1062. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  1063. switch (opcode) {
  1064. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1065. netxen_handle_linkevent(sds_ring->adapter, &msg);
  1066. break;
  1067. default:
  1068. break;
  1069. }
  1070. }
  1071. static int
  1072. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  1073. struct nx_host_rds_ring *rds_ring,
  1074. struct netxen_rx_buffer *buffer)
  1075. {
  1076. struct sk_buff *skb;
  1077. dma_addr_t dma;
  1078. struct pci_dev *pdev = adapter->pdev;
  1079. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  1080. if (!buffer->skb)
  1081. return 1;
  1082. skb = buffer->skb;
  1083. if (!adapter->ahw.cut_through)
  1084. skb_reserve(skb, 2);
  1085. dma = pci_map_single(pdev, skb->data,
  1086. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1087. if (pci_dma_mapping_error(pdev, dma)) {
  1088. dev_kfree_skb_any(skb);
  1089. buffer->skb = NULL;
  1090. return 1;
  1091. }
  1092. buffer->skb = skb;
  1093. buffer->dma = dma;
  1094. buffer->state = NETXEN_BUFFER_BUSY;
  1095. return 0;
  1096. }
  1097. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1098. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1099. {
  1100. struct netxen_rx_buffer *buffer;
  1101. struct sk_buff *skb;
  1102. buffer = &rds_ring->rx_buf_arr[index];
  1103. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1104. PCI_DMA_FROMDEVICE);
  1105. skb = buffer->skb;
  1106. if (!skb)
  1107. goto no_skb;
  1108. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1109. adapter->stats.csummed++;
  1110. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1111. } else
  1112. skb->ip_summed = CHECKSUM_NONE;
  1113. skb->dev = adapter->netdev;
  1114. buffer->skb = NULL;
  1115. no_skb:
  1116. buffer->state = NETXEN_BUFFER_FREE;
  1117. return skb;
  1118. }
  1119. static struct netxen_rx_buffer *
  1120. netxen_process_rcv(struct netxen_adapter *adapter,
  1121. struct nx_host_sds_ring *sds_ring,
  1122. int ring, u64 sts_data0)
  1123. {
  1124. struct net_device *netdev = adapter->netdev;
  1125. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1126. struct netxen_rx_buffer *buffer;
  1127. struct sk_buff *skb;
  1128. struct nx_host_rds_ring *rds_ring;
  1129. int index, length, cksum, pkt_offset;
  1130. if (unlikely(ring >= adapter->max_rds_rings))
  1131. return NULL;
  1132. rds_ring = &recv_ctx->rds_rings[ring];
  1133. index = netxen_get_sts_refhandle(sts_data0);
  1134. if (unlikely(index >= rds_ring->num_desc))
  1135. return NULL;
  1136. buffer = &rds_ring->rx_buf_arr[index];
  1137. length = netxen_get_sts_totallength(sts_data0);
  1138. cksum = netxen_get_sts_status(sts_data0);
  1139. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1140. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1141. if (!skb)
  1142. return buffer;
  1143. if (length > rds_ring->skb_size)
  1144. skb_put(skb, rds_ring->skb_size);
  1145. else
  1146. skb_put(skb, length);
  1147. if (pkt_offset)
  1148. skb_pull(skb, pkt_offset);
  1149. skb->truesize = skb->len + sizeof(struct sk_buff);
  1150. skb->protocol = eth_type_trans(skb, netdev);
  1151. napi_gro_receive(&sds_ring->napi, skb);
  1152. adapter->stats.rx_pkts++;
  1153. adapter->stats.rxbytes += length;
  1154. return buffer;
  1155. }
  1156. #define TCP_HDR_SIZE 20
  1157. #define TCP_TS_OPTION_SIZE 12
  1158. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1159. static struct netxen_rx_buffer *
  1160. netxen_process_lro(struct netxen_adapter *adapter,
  1161. struct nx_host_sds_ring *sds_ring,
  1162. int ring, u64 sts_data0, u64 sts_data1)
  1163. {
  1164. struct net_device *netdev = adapter->netdev;
  1165. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1166. struct netxen_rx_buffer *buffer;
  1167. struct sk_buff *skb;
  1168. struct nx_host_rds_ring *rds_ring;
  1169. struct iphdr *iph;
  1170. struct tcphdr *th;
  1171. bool push, timestamp;
  1172. int l2_hdr_offset, l4_hdr_offset;
  1173. int index;
  1174. u16 lro_length, length, data_offset;
  1175. u32 seq_number;
  1176. if (unlikely(ring > adapter->max_rds_rings))
  1177. return NULL;
  1178. rds_ring = &recv_ctx->rds_rings[ring];
  1179. index = netxen_get_lro_sts_refhandle(sts_data0);
  1180. if (unlikely(index > rds_ring->num_desc))
  1181. return NULL;
  1182. buffer = &rds_ring->rx_buf_arr[index];
  1183. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1184. lro_length = netxen_get_lro_sts_length(sts_data0);
  1185. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1186. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1187. push = netxen_get_lro_sts_push_flag(sts_data0);
  1188. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1189. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1190. if (!skb)
  1191. return buffer;
  1192. if (timestamp)
  1193. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1194. else
  1195. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1196. skb_put(skb, lro_length + data_offset);
  1197. skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
  1198. skb_pull(skb, l2_hdr_offset);
  1199. skb->protocol = eth_type_trans(skb, netdev);
  1200. iph = (struct iphdr *)skb->data;
  1201. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1202. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1203. iph->tot_len = htons(length);
  1204. iph->check = 0;
  1205. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1206. th->psh = push;
  1207. th->seq = htonl(seq_number);
  1208. length = skb->len;
  1209. netif_receive_skb(skb);
  1210. adapter->stats.lro_pkts++;
  1211. adapter->stats.rxbytes += length;
  1212. return buffer;
  1213. }
  1214. #define netxen_merge_rx_buffers(list, head) \
  1215. do { list_splice_tail_init(list, head); } while (0);
  1216. int
  1217. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1218. {
  1219. struct netxen_adapter *adapter = sds_ring->adapter;
  1220. struct list_head *cur;
  1221. struct status_desc *desc;
  1222. struct netxen_rx_buffer *rxbuf;
  1223. u32 consumer = sds_ring->consumer;
  1224. int count = 0;
  1225. u64 sts_data0, sts_data1;
  1226. int opcode, ring = 0, desc_cnt;
  1227. while (count < max) {
  1228. desc = &sds_ring->desc_head[consumer];
  1229. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1230. if (!(sts_data0 & STATUS_OWNER_HOST))
  1231. break;
  1232. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1233. opcode = netxen_get_sts_opcode(sts_data0);
  1234. switch (opcode) {
  1235. case NETXEN_NIC_RXPKT_DESC:
  1236. case NETXEN_OLD_RXPKT_DESC:
  1237. case NETXEN_NIC_SYN_OFFLOAD:
  1238. ring = netxen_get_sts_type(sts_data0);
  1239. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1240. ring, sts_data0);
  1241. break;
  1242. case NETXEN_NIC_LRO_DESC:
  1243. ring = netxen_get_lro_sts_type(sts_data0);
  1244. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1245. rxbuf = netxen_process_lro(adapter, sds_ring,
  1246. ring, sts_data0, sts_data1);
  1247. break;
  1248. case NETXEN_NIC_RESPONSE_DESC:
  1249. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1250. default:
  1251. goto skip;
  1252. }
  1253. WARN_ON(desc_cnt > 1);
  1254. if (rxbuf)
  1255. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1256. skip:
  1257. for (; desc_cnt > 0; desc_cnt--) {
  1258. desc = &sds_ring->desc_head[consumer];
  1259. desc->status_desc_data[0] =
  1260. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1261. consumer = get_next_index(consumer, sds_ring->num_desc);
  1262. }
  1263. count++;
  1264. }
  1265. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1266. struct nx_host_rds_ring *rds_ring =
  1267. &adapter->recv_ctx.rds_rings[ring];
  1268. if (!list_empty(&sds_ring->free_list[ring])) {
  1269. list_for_each(cur, &sds_ring->free_list[ring]) {
  1270. rxbuf = list_entry(cur,
  1271. struct netxen_rx_buffer, list);
  1272. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1273. }
  1274. spin_lock(&rds_ring->lock);
  1275. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1276. &rds_ring->free_list);
  1277. spin_unlock(&rds_ring->lock);
  1278. }
  1279. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1280. }
  1281. if (count) {
  1282. sds_ring->consumer = consumer;
  1283. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1284. }
  1285. return count;
  1286. }
  1287. /* Process Command status ring */
  1288. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1289. {
  1290. u32 sw_consumer, hw_consumer;
  1291. int count = 0, i;
  1292. struct netxen_cmd_buffer *buffer;
  1293. struct pci_dev *pdev = adapter->pdev;
  1294. struct net_device *netdev = adapter->netdev;
  1295. struct netxen_skb_frag *frag;
  1296. int done = 0;
  1297. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1298. if (!spin_trylock(&adapter->tx_clean_lock))
  1299. return 1;
  1300. sw_consumer = tx_ring->sw_consumer;
  1301. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1302. while (sw_consumer != hw_consumer) {
  1303. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1304. if (buffer->skb) {
  1305. frag = &buffer->frag_array[0];
  1306. pci_unmap_single(pdev, frag->dma, frag->length,
  1307. PCI_DMA_TODEVICE);
  1308. frag->dma = 0ULL;
  1309. for (i = 1; i < buffer->frag_count; i++) {
  1310. frag++; /* Get the next frag */
  1311. pci_unmap_page(pdev, frag->dma, frag->length,
  1312. PCI_DMA_TODEVICE);
  1313. frag->dma = 0ULL;
  1314. }
  1315. adapter->stats.xmitfinished++;
  1316. dev_kfree_skb_any(buffer->skb);
  1317. buffer->skb = NULL;
  1318. }
  1319. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1320. if (++count >= MAX_STATUS_HANDLE)
  1321. break;
  1322. }
  1323. if (count && netif_running(netdev)) {
  1324. tx_ring->sw_consumer = sw_consumer;
  1325. smp_mb();
  1326. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1327. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1328. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) {
  1329. netif_wake_queue(netdev);
  1330. adapter->tx_timeo_cnt = 0;
  1331. }
  1332. __netif_tx_unlock(tx_ring->txq);
  1333. }
  1334. }
  1335. /*
  1336. * If everything is freed up to consumer then check if the ring is full
  1337. * If the ring is full then check if more needs to be freed and
  1338. * schedule the call back again.
  1339. *
  1340. * This happens when there are 2 CPUs. One could be freeing and the
  1341. * other filling it. If the ring is full when we get out of here and
  1342. * the card has already interrupted the host then the host can miss the
  1343. * interrupt.
  1344. *
  1345. * There is still a possible race condition and the host could miss an
  1346. * interrupt. The card has to take care of this.
  1347. */
  1348. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1349. done = (sw_consumer == hw_consumer);
  1350. spin_unlock(&adapter->tx_clean_lock);
  1351. return (done);
  1352. }
  1353. void
  1354. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1355. struct nx_host_rds_ring *rds_ring)
  1356. {
  1357. struct rcv_desc *pdesc;
  1358. struct netxen_rx_buffer *buffer;
  1359. int producer, count = 0;
  1360. netxen_ctx_msg msg = 0;
  1361. struct list_head *head;
  1362. producer = rds_ring->producer;
  1363. spin_lock(&rds_ring->lock);
  1364. head = &rds_ring->free_list;
  1365. while (!list_empty(head)) {
  1366. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1367. if (!buffer->skb) {
  1368. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1369. break;
  1370. }
  1371. count++;
  1372. list_del(&buffer->list);
  1373. /* make a rcv descriptor */
  1374. pdesc = &rds_ring->desc_head[producer];
  1375. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1376. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1377. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1378. producer = get_next_index(producer, rds_ring->num_desc);
  1379. }
  1380. spin_unlock(&rds_ring->lock);
  1381. if (count) {
  1382. rds_ring->producer = producer;
  1383. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1384. (producer-1) & (rds_ring->num_desc-1));
  1385. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1386. /*
  1387. * Write a doorbell msg to tell phanmon of change in
  1388. * receive ring producer
  1389. * Only for firmware version < 4.0.0
  1390. */
  1391. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1392. netxen_set_msg_privid(msg);
  1393. netxen_set_msg_count(msg,
  1394. ((producer - 1) &
  1395. (rds_ring->num_desc - 1)));
  1396. netxen_set_msg_ctxid(msg, adapter->portnum);
  1397. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1398. NXWRIO(adapter, DB_NORMALIZE(adapter,
  1399. NETXEN_RCV_PRODUCER_OFFSET), msg);
  1400. }
  1401. }
  1402. }
  1403. static void
  1404. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1405. struct nx_host_rds_ring *rds_ring)
  1406. {
  1407. struct rcv_desc *pdesc;
  1408. struct netxen_rx_buffer *buffer;
  1409. int producer, count = 0;
  1410. struct list_head *head;
  1411. producer = rds_ring->producer;
  1412. if (!spin_trylock(&rds_ring->lock))
  1413. return;
  1414. head = &rds_ring->free_list;
  1415. while (!list_empty(head)) {
  1416. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1417. if (!buffer->skb) {
  1418. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1419. break;
  1420. }
  1421. count++;
  1422. list_del(&buffer->list);
  1423. /* make a rcv descriptor */
  1424. pdesc = &rds_ring->desc_head[producer];
  1425. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1426. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1427. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1428. producer = get_next_index(producer, rds_ring->num_desc);
  1429. }
  1430. if (count) {
  1431. rds_ring->producer = producer;
  1432. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1433. (producer - 1) & (rds_ring->num_desc - 1));
  1434. }
  1435. spin_unlock(&rds_ring->lock);
  1436. }
  1437. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1438. {
  1439. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1440. return;
  1441. }