pxaficp_ir.c 23 KB

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  1. /*
  2. * linux/drivers/net/irda/pxaficp_ir.c
  3. *
  4. * Based on sa1100_ir.c by Russell King
  5. *
  6. * Changes copyright (C) 2003-2005 MontaVista Software, Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * Infra-red driver (SIR/FIR) for the PXA2xx embedded microprocessor
  13. *
  14. */
  15. #include <linux/module.h>
  16. #include <linux/netdevice.h>
  17. #include <linux/etherdevice.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/clk.h>
  20. #include <linux/gpio.h>
  21. #include <linux/slab.h>
  22. #include <net/irda/irda.h>
  23. #include <net/irda/irmod.h>
  24. #include <net/irda/wrapper.h>
  25. #include <net/irda/irda_device.h>
  26. #include <mach/dma.h>
  27. #include <mach/irda.h>
  28. #include <mach/regs-uart.h>
  29. #include <mach/regs-ost.h>
  30. #define FICP __REG(0x40800000) /* Start of FICP area */
  31. #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
  32. #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
  33. #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
  34. #define ICDR __REG(0x4080000c) /* ICP Data Register */
  35. #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
  36. #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
  37. #define ICCR0_AME (1 << 7) /* Address match enable */
  38. #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
  39. #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
  40. #define ICCR0_RXE (1 << 4) /* Receive enable */
  41. #define ICCR0_TXE (1 << 3) /* Transmit enable */
  42. #define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
  43. #define ICCR0_LBM (1 << 1) /* Loopback mode */
  44. #define ICCR0_ITR (1 << 0) /* IrDA transmission */
  45. #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
  46. #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
  47. #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
  48. #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
  49. #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
  50. #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
  51. #ifdef CONFIG_PXA27x
  52. #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
  53. #endif
  54. #define ICSR0_FRE (1 << 5) /* Framing error */
  55. #define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
  56. #define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
  57. #define ICSR0_RAB (1 << 2) /* Receiver abort */
  58. #define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
  59. #define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
  60. #define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
  61. #define ICSR1_CRE (1 << 5) /* CRC error */
  62. #define ICSR1_EOF (1 << 4) /* End of frame */
  63. #define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
  64. #define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
  65. #define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
  66. #define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
  67. #define IrSR_RXPL_NEG_IS_ZERO (1<<4)
  68. #define IrSR_RXPL_POS_IS_ZERO 0x0
  69. #define IrSR_TXPL_NEG_IS_ZERO (1<<3)
  70. #define IrSR_TXPL_POS_IS_ZERO 0x0
  71. #define IrSR_XMODE_PULSE_1_6 (1<<2)
  72. #define IrSR_XMODE_PULSE_3_16 0x0
  73. #define IrSR_RCVEIR_IR_MODE (1<<1)
  74. #define IrSR_RCVEIR_UART_MODE 0x0
  75. #define IrSR_XMITIR_IR_MODE (1<<0)
  76. #define IrSR_XMITIR_UART_MODE 0x0
  77. #define IrSR_IR_RECEIVE_ON (\
  78. IrSR_RXPL_NEG_IS_ZERO | \
  79. IrSR_TXPL_POS_IS_ZERO | \
  80. IrSR_XMODE_PULSE_3_16 | \
  81. IrSR_RCVEIR_IR_MODE | \
  82. IrSR_XMITIR_UART_MODE)
  83. #define IrSR_IR_TRANSMIT_ON (\
  84. IrSR_RXPL_NEG_IS_ZERO | \
  85. IrSR_TXPL_POS_IS_ZERO | \
  86. IrSR_XMODE_PULSE_3_16 | \
  87. IrSR_RCVEIR_UART_MODE | \
  88. IrSR_XMITIR_IR_MODE)
  89. struct pxa_irda {
  90. int speed;
  91. int newspeed;
  92. unsigned long last_oscr;
  93. unsigned char *dma_rx_buff;
  94. unsigned char *dma_tx_buff;
  95. dma_addr_t dma_rx_buff_phy;
  96. dma_addr_t dma_tx_buff_phy;
  97. unsigned int dma_tx_buff_len;
  98. int txdma;
  99. int rxdma;
  100. struct irlap_cb *irlap;
  101. struct qos_info qos;
  102. iobuff_t tx_buff;
  103. iobuff_t rx_buff;
  104. struct device *dev;
  105. struct pxaficp_platform_data *pdata;
  106. struct clk *fir_clk;
  107. struct clk *sir_clk;
  108. struct clk *cur_clk;
  109. };
  110. static inline void pxa_irda_disable_clk(struct pxa_irda *si)
  111. {
  112. if (si->cur_clk)
  113. clk_disable(si->cur_clk);
  114. si->cur_clk = NULL;
  115. }
  116. static inline void pxa_irda_enable_firclk(struct pxa_irda *si)
  117. {
  118. si->cur_clk = si->fir_clk;
  119. clk_enable(si->fir_clk);
  120. }
  121. static inline void pxa_irda_enable_sirclk(struct pxa_irda *si)
  122. {
  123. si->cur_clk = si->sir_clk;
  124. clk_enable(si->sir_clk);
  125. }
  126. #define IS_FIR(si) ((si)->speed >= 4000000)
  127. #define IRDA_FRAME_SIZE_LIMIT 2047
  128. inline static void pxa_irda_fir_dma_rx_start(struct pxa_irda *si)
  129. {
  130. DCSR(si->rxdma) = DCSR_NODESC;
  131. DSADR(si->rxdma) = __PREG(ICDR);
  132. DTADR(si->rxdma) = si->dma_rx_buff_phy;
  133. DCMD(si->rxdma) = DCMD_INCTRGADDR | DCMD_FLOWSRC | DCMD_WIDTH1 | DCMD_BURST32 | IRDA_FRAME_SIZE_LIMIT;
  134. DCSR(si->rxdma) |= DCSR_RUN;
  135. }
  136. inline static void pxa_irda_fir_dma_tx_start(struct pxa_irda *si)
  137. {
  138. DCSR(si->txdma) = DCSR_NODESC;
  139. DSADR(si->txdma) = si->dma_tx_buff_phy;
  140. DTADR(si->txdma) = __PREG(ICDR);
  141. DCMD(si->txdma) = DCMD_INCSRCADDR | DCMD_FLOWTRG | DCMD_ENDIRQEN | DCMD_WIDTH1 | DCMD_BURST32 | si->dma_tx_buff_len;
  142. DCSR(si->txdma) |= DCSR_RUN;
  143. }
  144. /*
  145. * Set the IrDA communications mode.
  146. */
  147. static void pxa_irda_set_mode(struct pxa_irda *si, int mode)
  148. {
  149. if (si->pdata->transceiver_mode)
  150. si->pdata->transceiver_mode(si->dev, mode);
  151. else {
  152. if (gpio_is_valid(si->pdata->gpio_pwdown))
  153. gpio_set_value(si->pdata->gpio_pwdown,
  154. !(mode & IR_OFF) ^
  155. !si->pdata->gpio_pwdown_inverted);
  156. pxa2xx_transceiver_mode(si->dev, mode);
  157. }
  158. }
  159. /*
  160. * Set the IrDA communications speed.
  161. */
  162. static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
  163. {
  164. unsigned long flags;
  165. unsigned int divisor;
  166. switch (speed) {
  167. case 9600: case 19200: case 38400:
  168. case 57600: case 115200:
  169. /* refer to PXA250/210 Developer's Manual 10-7 */
  170. /* BaudRate = 14.7456 MHz / (16*Divisor) */
  171. divisor = 14745600 / (16 * speed);
  172. local_irq_save(flags);
  173. if (IS_FIR(si)) {
  174. /* stop RX DMA */
  175. DCSR(si->rxdma) &= ~DCSR_RUN;
  176. /* disable FICP */
  177. ICCR0 = 0;
  178. pxa_irda_disable_clk(si);
  179. /* set board transceiver to SIR mode */
  180. pxa_irda_set_mode(si, IR_SIRMODE);
  181. /* enable the STUART clock */
  182. pxa_irda_enable_sirclk(si);
  183. }
  184. /* disable STUART first */
  185. STIER = 0;
  186. /* access DLL & DLH */
  187. STLCR |= LCR_DLAB;
  188. STDLL = divisor & 0xff;
  189. STDLH = divisor >> 8;
  190. STLCR &= ~LCR_DLAB;
  191. si->speed = speed;
  192. STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6;
  193. STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE;
  194. local_irq_restore(flags);
  195. break;
  196. case 4000000:
  197. local_irq_save(flags);
  198. /* disable STUART */
  199. STIER = 0;
  200. STISR = 0;
  201. pxa_irda_disable_clk(si);
  202. /* disable FICP first */
  203. ICCR0 = 0;
  204. /* set board transceiver to FIR mode */
  205. pxa_irda_set_mode(si, IR_FIRMODE);
  206. /* enable the FICP clock */
  207. pxa_irda_enable_firclk(si);
  208. si->speed = speed;
  209. pxa_irda_fir_dma_rx_start(si);
  210. ICCR0 = ICCR0_ITR | ICCR0_RXE;
  211. local_irq_restore(flags);
  212. break;
  213. default:
  214. return -EINVAL;
  215. }
  216. return 0;
  217. }
  218. /* SIR interrupt service routine. */
  219. static irqreturn_t pxa_irda_sir_irq(int irq, void *dev_id)
  220. {
  221. struct net_device *dev = dev_id;
  222. struct pxa_irda *si = netdev_priv(dev);
  223. int iir, lsr, data;
  224. iir = STIIR;
  225. switch (iir & 0x0F) {
  226. case 0x06: /* Receiver Line Status */
  227. lsr = STLSR;
  228. while (lsr & LSR_FIFOE) {
  229. data = STRBR;
  230. if (lsr & (LSR_OE | LSR_PE | LSR_FE | LSR_BI)) {
  231. printk(KERN_DEBUG "pxa_ir: sir receiving error\n");
  232. dev->stats.rx_errors++;
  233. if (lsr & LSR_FE)
  234. dev->stats.rx_frame_errors++;
  235. if (lsr & LSR_OE)
  236. dev->stats.rx_fifo_errors++;
  237. } else {
  238. dev->stats.rx_bytes++;
  239. async_unwrap_char(dev, &dev->stats,
  240. &si->rx_buff, data);
  241. }
  242. lsr = STLSR;
  243. }
  244. si->last_oscr = OSCR;
  245. break;
  246. case 0x04: /* Received Data Available */
  247. /* forth through */
  248. case 0x0C: /* Character Timeout Indication */
  249. do {
  250. dev->stats.rx_bytes++;
  251. async_unwrap_char(dev, &dev->stats, &si->rx_buff, STRBR);
  252. } while (STLSR & LSR_DR);
  253. si->last_oscr = OSCR;
  254. break;
  255. case 0x02: /* Transmit FIFO Data Request */
  256. while ((si->tx_buff.len) && (STLSR & LSR_TDRQ)) {
  257. STTHR = *si->tx_buff.data++;
  258. si->tx_buff.len -= 1;
  259. }
  260. if (si->tx_buff.len == 0) {
  261. dev->stats.tx_packets++;
  262. dev->stats.tx_bytes += si->tx_buff.data - si->tx_buff.head;
  263. /* We need to ensure that the transmitter has finished. */
  264. while ((STLSR & LSR_TEMT) == 0)
  265. cpu_relax();
  266. si->last_oscr = OSCR;
  267. /*
  268. * Ok, we've finished transmitting. Now enable
  269. * the receiver. Sometimes we get a receive IRQ
  270. * immediately after a transmit...
  271. */
  272. if (si->newspeed) {
  273. pxa_irda_set_speed(si, si->newspeed);
  274. si->newspeed = 0;
  275. } else {
  276. /* enable IR Receiver, disable IR Transmitter */
  277. STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6;
  278. /* enable STUART and receive interrupts */
  279. STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE;
  280. }
  281. /* I'm hungry! */
  282. netif_wake_queue(dev);
  283. }
  284. break;
  285. }
  286. return IRQ_HANDLED;
  287. }
  288. /* FIR Receive DMA interrupt handler */
  289. static void pxa_irda_fir_dma_rx_irq(int channel, void *data)
  290. {
  291. int dcsr = DCSR(channel);
  292. DCSR(channel) = dcsr & ~DCSR_RUN;
  293. printk(KERN_DEBUG "pxa_ir: fir rx dma bus error %#x\n", dcsr);
  294. }
  295. /* FIR Transmit DMA interrupt handler */
  296. static void pxa_irda_fir_dma_tx_irq(int channel, void *data)
  297. {
  298. struct net_device *dev = data;
  299. struct pxa_irda *si = netdev_priv(dev);
  300. int dcsr;
  301. dcsr = DCSR(channel);
  302. DCSR(channel) = dcsr & ~DCSR_RUN;
  303. if (dcsr & DCSR_ENDINTR) {
  304. dev->stats.tx_packets++;
  305. dev->stats.tx_bytes += si->dma_tx_buff_len;
  306. } else {
  307. dev->stats.tx_errors++;
  308. }
  309. while (ICSR1 & ICSR1_TBY)
  310. cpu_relax();
  311. si->last_oscr = OSCR;
  312. /*
  313. * HACK: It looks like the TBY bit is dropped too soon.
  314. * Without this delay things break.
  315. */
  316. udelay(120);
  317. if (si->newspeed) {
  318. pxa_irda_set_speed(si, si->newspeed);
  319. si->newspeed = 0;
  320. } else {
  321. int i = 64;
  322. ICCR0 = 0;
  323. pxa_irda_fir_dma_rx_start(si);
  324. while ((ICSR1 & ICSR1_RNE) && i--)
  325. (void)ICDR;
  326. ICCR0 = ICCR0_ITR | ICCR0_RXE;
  327. if (i < 0)
  328. printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n");
  329. }
  330. netif_wake_queue(dev);
  331. }
  332. /* EIF(Error in FIFO/End in Frame) handler for FIR */
  333. static void pxa_irda_fir_irq_eif(struct pxa_irda *si, struct net_device *dev, int icsr0)
  334. {
  335. unsigned int len, stat, data;
  336. /* Get the current data position. */
  337. len = DTADR(si->rxdma) - si->dma_rx_buff_phy;
  338. do {
  339. /* Read Status, and then Data. */
  340. stat = ICSR1;
  341. rmb();
  342. data = ICDR;
  343. if (stat & (ICSR1_CRE | ICSR1_ROR)) {
  344. dev->stats.rx_errors++;
  345. if (stat & ICSR1_CRE) {
  346. printk(KERN_DEBUG "pxa_ir: fir receive CRC error\n");
  347. dev->stats.rx_crc_errors++;
  348. }
  349. if (stat & ICSR1_ROR) {
  350. printk(KERN_DEBUG "pxa_ir: fir receive overrun\n");
  351. dev->stats.rx_over_errors++;
  352. }
  353. } else {
  354. si->dma_rx_buff[len++] = data;
  355. }
  356. /* If we hit the end of frame, there's no point in continuing. */
  357. if (stat & ICSR1_EOF)
  358. break;
  359. } while (ICSR0 & ICSR0_EIF);
  360. if (stat & ICSR1_EOF) {
  361. /* end of frame. */
  362. struct sk_buff *skb;
  363. if (icsr0 & ICSR0_FRE) {
  364. printk(KERN_ERR "pxa_ir: dropping erroneous frame\n");
  365. dev->stats.rx_dropped++;
  366. return;
  367. }
  368. skb = alloc_skb(len+1,GFP_ATOMIC);
  369. if (!skb) {
  370. printk(KERN_ERR "pxa_ir: fir out of memory for receive skb\n");
  371. dev->stats.rx_dropped++;
  372. return;
  373. }
  374. /* Align IP header to 20 bytes */
  375. skb_reserve(skb, 1);
  376. skb_copy_to_linear_data(skb, si->dma_rx_buff, len);
  377. skb_put(skb, len);
  378. /* Feed it to IrLAP */
  379. skb->dev = dev;
  380. skb_reset_mac_header(skb);
  381. skb->protocol = htons(ETH_P_IRDA);
  382. netif_rx(skb);
  383. dev->stats.rx_packets++;
  384. dev->stats.rx_bytes += len;
  385. }
  386. }
  387. /* FIR interrupt handler */
  388. static irqreturn_t pxa_irda_fir_irq(int irq, void *dev_id)
  389. {
  390. struct net_device *dev = dev_id;
  391. struct pxa_irda *si = netdev_priv(dev);
  392. int icsr0, i = 64;
  393. /* stop RX DMA */
  394. DCSR(si->rxdma) &= ~DCSR_RUN;
  395. si->last_oscr = OSCR;
  396. icsr0 = ICSR0;
  397. if (icsr0 & (ICSR0_FRE | ICSR0_RAB)) {
  398. if (icsr0 & ICSR0_FRE) {
  399. printk(KERN_DEBUG "pxa_ir: fir receive frame error\n");
  400. dev->stats.rx_frame_errors++;
  401. } else {
  402. printk(KERN_DEBUG "pxa_ir: fir receive abort\n");
  403. dev->stats.rx_errors++;
  404. }
  405. ICSR0 = icsr0 & (ICSR0_FRE | ICSR0_RAB);
  406. }
  407. if (icsr0 & ICSR0_EIF) {
  408. /* An error in FIFO occured, or there is a end of frame */
  409. pxa_irda_fir_irq_eif(si, dev, icsr0);
  410. }
  411. ICCR0 = 0;
  412. pxa_irda_fir_dma_rx_start(si);
  413. while ((ICSR1 & ICSR1_RNE) && i--)
  414. (void)ICDR;
  415. ICCR0 = ICCR0_ITR | ICCR0_RXE;
  416. if (i < 0)
  417. printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n");
  418. return IRQ_HANDLED;
  419. }
  420. /* hard_xmit interface of irda device */
  421. static int pxa_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
  422. {
  423. struct pxa_irda *si = netdev_priv(dev);
  424. int speed = irda_get_next_speed(skb);
  425. /*
  426. * Does this packet contain a request to change the interface
  427. * speed? If so, remember it until we complete the transmission
  428. * of this frame.
  429. */
  430. if (speed != si->speed && speed != -1)
  431. si->newspeed = speed;
  432. /*
  433. * If this is an empty frame, we can bypass a lot.
  434. */
  435. if (skb->len == 0) {
  436. if (si->newspeed) {
  437. si->newspeed = 0;
  438. pxa_irda_set_speed(si, speed);
  439. }
  440. dev_kfree_skb(skb);
  441. return NETDEV_TX_OK;
  442. }
  443. netif_stop_queue(dev);
  444. if (!IS_FIR(si)) {
  445. si->tx_buff.data = si->tx_buff.head;
  446. si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data, si->tx_buff.truesize);
  447. /* Disable STUART interrupts and switch to transmit mode. */
  448. STIER = 0;
  449. STISR = IrSR_IR_TRANSMIT_ON | IrSR_XMODE_PULSE_1_6;
  450. /* enable STUART and transmit interrupts */
  451. STIER = IER_UUE | IER_TIE;
  452. } else {
  453. unsigned long mtt = irda_get_mtt(skb);
  454. si->dma_tx_buff_len = skb->len;
  455. skb_copy_from_linear_data(skb, si->dma_tx_buff, skb->len);
  456. if (mtt)
  457. while ((unsigned)(OSCR - si->last_oscr)/4 < mtt)
  458. cpu_relax();
  459. /* stop RX DMA, disable FICP */
  460. DCSR(si->rxdma) &= ~DCSR_RUN;
  461. ICCR0 = 0;
  462. pxa_irda_fir_dma_tx_start(si);
  463. ICCR0 = ICCR0_ITR | ICCR0_TXE;
  464. }
  465. dev_kfree_skb(skb);
  466. dev->trans_start = jiffies;
  467. return NETDEV_TX_OK;
  468. }
  469. static int pxa_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
  470. {
  471. struct if_irda_req *rq = (struct if_irda_req *)ifreq;
  472. struct pxa_irda *si = netdev_priv(dev);
  473. int ret;
  474. switch (cmd) {
  475. case SIOCSBANDWIDTH:
  476. ret = -EPERM;
  477. if (capable(CAP_NET_ADMIN)) {
  478. /*
  479. * We are unable to set the speed if the
  480. * device is not running.
  481. */
  482. if (netif_running(dev)) {
  483. ret = pxa_irda_set_speed(si,
  484. rq->ifr_baudrate);
  485. } else {
  486. printk(KERN_INFO "pxa_ir: SIOCSBANDWIDTH: !netif_running\n");
  487. ret = 0;
  488. }
  489. }
  490. break;
  491. case SIOCSMEDIABUSY:
  492. ret = -EPERM;
  493. if (capable(CAP_NET_ADMIN)) {
  494. irda_device_set_media_busy(dev, TRUE);
  495. ret = 0;
  496. }
  497. break;
  498. case SIOCGRECEIVING:
  499. ret = 0;
  500. rq->ifr_receiving = IS_FIR(si) ? 0
  501. : si->rx_buff.state != OUTSIDE_FRAME;
  502. break;
  503. default:
  504. ret = -EOPNOTSUPP;
  505. break;
  506. }
  507. return ret;
  508. }
  509. static void pxa_irda_startup(struct pxa_irda *si)
  510. {
  511. /* Disable STUART interrupts */
  512. STIER = 0;
  513. /* enable STUART interrupt to the processor */
  514. STMCR = MCR_OUT2;
  515. /* configure SIR frame format: StartBit - Data 7 ... Data 0 - Stop Bit */
  516. STLCR = LCR_WLS0 | LCR_WLS1;
  517. /* enable FIFO, we use FIFO to improve performance */
  518. STFCR = FCR_TRFIFOE | FCR_ITL_32;
  519. /* disable FICP */
  520. ICCR0 = 0;
  521. /* configure FICP ICCR2 */
  522. ICCR2 = ICCR2_TXP | ICCR2_TRIG_32;
  523. /* configure DMAC */
  524. DRCMR(17) = si->rxdma | DRCMR_MAPVLD;
  525. DRCMR(18) = si->txdma | DRCMR_MAPVLD;
  526. /* force SIR reinitialization */
  527. si->speed = 4000000;
  528. pxa_irda_set_speed(si, 9600);
  529. printk(KERN_DEBUG "pxa_ir: irda startup\n");
  530. }
  531. static void pxa_irda_shutdown(struct pxa_irda *si)
  532. {
  533. unsigned long flags;
  534. local_irq_save(flags);
  535. /* disable STUART and interrupt */
  536. STIER = 0;
  537. /* disable STUART SIR mode */
  538. STISR = 0;
  539. /* disable DMA */
  540. DCSR(si->txdma) &= ~DCSR_RUN;
  541. DCSR(si->rxdma) &= ~DCSR_RUN;
  542. /* disable FICP */
  543. ICCR0 = 0;
  544. /* disable the STUART or FICP clocks */
  545. pxa_irda_disable_clk(si);
  546. DRCMR(17) = 0;
  547. DRCMR(18) = 0;
  548. local_irq_restore(flags);
  549. /* power off board transceiver */
  550. pxa_irda_set_mode(si, IR_OFF);
  551. printk(KERN_DEBUG "pxa_ir: irda shutdown\n");
  552. }
  553. static int pxa_irda_start(struct net_device *dev)
  554. {
  555. struct pxa_irda *si = netdev_priv(dev);
  556. int err;
  557. si->speed = 9600;
  558. err = request_irq(IRQ_STUART, pxa_irda_sir_irq, 0, dev->name, dev);
  559. if (err)
  560. goto err_irq1;
  561. err = request_irq(IRQ_ICP, pxa_irda_fir_irq, 0, dev->name, dev);
  562. if (err)
  563. goto err_irq2;
  564. /*
  565. * The interrupt must remain disabled for now.
  566. */
  567. disable_irq(IRQ_STUART);
  568. disable_irq(IRQ_ICP);
  569. err = -EBUSY;
  570. si->rxdma = pxa_request_dma("FICP_RX",DMA_PRIO_LOW, pxa_irda_fir_dma_rx_irq, dev);
  571. if (si->rxdma < 0)
  572. goto err_rx_dma;
  573. si->txdma = pxa_request_dma("FICP_TX",DMA_PRIO_LOW, pxa_irda_fir_dma_tx_irq, dev);
  574. if (si->txdma < 0)
  575. goto err_tx_dma;
  576. err = -ENOMEM;
  577. si->dma_rx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT,
  578. &si->dma_rx_buff_phy, GFP_KERNEL );
  579. if (!si->dma_rx_buff)
  580. goto err_dma_rx_buff;
  581. si->dma_tx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT,
  582. &si->dma_tx_buff_phy, GFP_KERNEL );
  583. if (!si->dma_tx_buff)
  584. goto err_dma_tx_buff;
  585. /* Setup the serial port for the initial speed. */
  586. pxa_irda_startup(si);
  587. /*
  588. * Open a new IrLAP layer instance.
  589. */
  590. si->irlap = irlap_open(dev, &si->qos, "pxa");
  591. err = -ENOMEM;
  592. if (!si->irlap)
  593. goto err_irlap;
  594. /*
  595. * Now enable the interrupt and start the queue
  596. */
  597. enable_irq(IRQ_STUART);
  598. enable_irq(IRQ_ICP);
  599. netif_start_queue(dev);
  600. printk(KERN_DEBUG "pxa_ir: irda driver opened\n");
  601. return 0;
  602. err_irlap:
  603. pxa_irda_shutdown(si);
  604. dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy);
  605. err_dma_tx_buff:
  606. dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy);
  607. err_dma_rx_buff:
  608. pxa_free_dma(si->txdma);
  609. err_tx_dma:
  610. pxa_free_dma(si->rxdma);
  611. err_rx_dma:
  612. free_irq(IRQ_ICP, dev);
  613. err_irq2:
  614. free_irq(IRQ_STUART, dev);
  615. err_irq1:
  616. return err;
  617. }
  618. static int pxa_irda_stop(struct net_device *dev)
  619. {
  620. struct pxa_irda *si = netdev_priv(dev);
  621. netif_stop_queue(dev);
  622. pxa_irda_shutdown(si);
  623. /* Stop IrLAP */
  624. if (si->irlap) {
  625. irlap_close(si->irlap);
  626. si->irlap = NULL;
  627. }
  628. free_irq(IRQ_STUART, dev);
  629. free_irq(IRQ_ICP, dev);
  630. pxa_free_dma(si->rxdma);
  631. pxa_free_dma(si->txdma);
  632. if (si->dma_rx_buff)
  633. dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy);
  634. if (si->dma_tx_buff)
  635. dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy);
  636. printk(KERN_DEBUG "pxa_ir: irda driver closed\n");
  637. return 0;
  638. }
  639. static int pxa_irda_suspend(struct platform_device *_dev, pm_message_t state)
  640. {
  641. struct net_device *dev = platform_get_drvdata(_dev);
  642. struct pxa_irda *si;
  643. if (dev && netif_running(dev)) {
  644. si = netdev_priv(dev);
  645. netif_device_detach(dev);
  646. pxa_irda_shutdown(si);
  647. }
  648. return 0;
  649. }
  650. static int pxa_irda_resume(struct platform_device *_dev)
  651. {
  652. struct net_device *dev = platform_get_drvdata(_dev);
  653. struct pxa_irda *si;
  654. if (dev && netif_running(dev)) {
  655. si = netdev_priv(dev);
  656. pxa_irda_startup(si);
  657. netif_device_attach(dev);
  658. netif_wake_queue(dev);
  659. }
  660. return 0;
  661. }
  662. static int pxa_irda_init_iobuf(iobuff_t *io, int size)
  663. {
  664. io->head = kmalloc(size, GFP_KERNEL | GFP_DMA);
  665. if (io->head != NULL) {
  666. io->truesize = size;
  667. io->in_frame = FALSE;
  668. io->state = OUTSIDE_FRAME;
  669. io->data = io->head;
  670. }
  671. return io->head ? 0 : -ENOMEM;
  672. }
  673. static const struct net_device_ops pxa_irda_netdev_ops = {
  674. .ndo_open = pxa_irda_start,
  675. .ndo_stop = pxa_irda_stop,
  676. .ndo_start_xmit = pxa_irda_hard_xmit,
  677. .ndo_do_ioctl = pxa_irda_ioctl,
  678. };
  679. static int pxa_irda_probe(struct platform_device *pdev)
  680. {
  681. struct net_device *dev;
  682. struct pxa_irda *si;
  683. unsigned int baudrate_mask;
  684. int err;
  685. if (!pdev->dev.platform_data)
  686. return -ENODEV;
  687. err = request_mem_region(__PREG(STUART), 0x24, "IrDA") ? 0 : -EBUSY;
  688. if (err)
  689. goto err_mem_1;
  690. err = request_mem_region(__PREG(FICP), 0x1c, "IrDA") ? 0 : -EBUSY;
  691. if (err)
  692. goto err_mem_2;
  693. dev = alloc_irdadev(sizeof(struct pxa_irda));
  694. if (!dev)
  695. goto err_mem_3;
  696. SET_NETDEV_DEV(dev, &pdev->dev);
  697. si = netdev_priv(dev);
  698. si->dev = &pdev->dev;
  699. si->pdata = pdev->dev.platform_data;
  700. si->sir_clk = clk_get(&pdev->dev, "UARTCLK");
  701. si->fir_clk = clk_get(&pdev->dev, "FICPCLK");
  702. if (IS_ERR(si->sir_clk) || IS_ERR(si->fir_clk)) {
  703. err = PTR_ERR(IS_ERR(si->sir_clk) ? si->sir_clk : si->fir_clk);
  704. goto err_mem_4;
  705. }
  706. /*
  707. * Initialise the SIR buffers
  708. */
  709. err = pxa_irda_init_iobuf(&si->rx_buff, 14384);
  710. if (err)
  711. goto err_mem_4;
  712. err = pxa_irda_init_iobuf(&si->tx_buff, 4000);
  713. if (err)
  714. goto err_mem_5;
  715. if (gpio_is_valid(si->pdata->gpio_pwdown)) {
  716. err = gpio_request(si->pdata->gpio_pwdown, "IrDA switch");
  717. if (err)
  718. goto err_startup;
  719. err = gpio_direction_output(si->pdata->gpio_pwdown,
  720. !si->pdata->gpio_pwdown_inverted);
  721. if (err) {
  722. gpio_free(si->pdata->gpio_pwdown);
  723. goto err_startup;
  724. }
  725. }
  726. if (si->pdata->startup) {
  727. err = si->pdata->startup(si->dev);
  728. if (err)
  729. goto err_startup;
  730. }
  731. if (gpio_is_valid(si->pdata->gpio_pwdown) && si->pdata->startup)
  732. dev_warn(si->dev, "gpio_pwdown and startup() both defined!\n");
  733. dev->netdev_ops = &pxa_irda_netdev_ops;
  734. irda_init_max_qos_capabilies(&si->qos);
  735. baudrate_mask = 0;
  736. if (si->pdata->transceiver_cap & IR_SIRMODE)
  737. baudrate_mask |= IR_9600|IR_19200|IR_38400|IR_57600|IR_115200;
  738. if (si->pdata->transceiver_cap & IR_FIRMODE)
  739. baudrate_mask |= IR_4000000 << 8;
  740. si->qos.baud_rate.bits &= baudrate_mask;
  741. si->qos.min_turn_time.bits = 7; /* 1ms or more */
  742. irda_qos_bits_to_value(&si->qos);
  743. err = register_netdev(dev);
  744. if (err == 0)
  745. dev_set_drvdata(&pdev->dev, dev);
  746. if (err) {
  747. if (si->pdata->shutdown)
  748. si->pdata->shutdown(si->dev);
  749. err_startup:
  750. kfree(si->tx_buff.head);
  751. err_mem_5:
  752. kfree(si->rx_buff.head);
  753. err_mem_4:
  754. if (si->sir_clk && !IS_ERR(si->sir_clk))
  755. clk_put(si->sir_clk);
  756. if (si->fir_clk && !IS_ERR(si->fir_clk))
  757. clk_put(si->fir_clk);
  758. free_netdev(dev);
  759. err_mem_3:
  760. release_mem_region(__PREG(FICP), 0x1c);
  761. err_mem_2:
  762. release_mem_region(__PREG(STUART), 0x24);
  763. }
  764. err_mem_1:
  765. return err;
  766. }
  767. static int pxa_irda_remove(struct platform_device *_dev)
  768. {
  769. struct net_device *dev = platform_get_drvdata(_dev);
  770. if (dev) {
  771. struct pxa_irda *si = netdev_priv(dev);
  772. unregister_netdev(dev);
  773. if (gpio_is_valid(si->pdata->gpio_pwdown))
  774. gpio_free(si->pdata->gpio_pwdown);
  775. if (si->pdata->shutdown)
  776. si->pdata->shutdown(si->dev);
  777. kfree(si->tx_buff.head);
  778. kfree(si->rx_buff.head);
  779. clk_put(si->fir_clk);
  780. clk_put(si->sir_clk);
  781. free_netdev(dev);
  782. }
  783. release_mem_region(__PREG(STUART), 0x24);
  784. release_mem_region(__PREG(FICP), 0x1c);
  785. return 0;
  786. }
  787. static struct platform_driver pxa_ir_driver = {
  788. .driver = {
  789. .name = "pxa2xx-ir",
  790. .owner = THIS_MODULE,
  791. },
  792. .probe = pxa_irda_probe,
  793. .remove = pxa_irda_remove,
  794. .suspend = pxa_irda_suspend,
  795. .resume = pxa_irda_resume,
  796. };
  797. static int __init pxa_irda_init(void)
  798. {
  799. return platform_driver_register(&pxa_ir_driver);
  800. }
  801. static void __exit pxa_irda_exit(void)
  802. {
  803. platform_driver_unregister(&pxa_ir_driver);
  804. }
  805. module_init(pxa_irda_init);
  806. module_exit(pxa_irda_exit);
  807. MODULE_LICENSE("GPL");
  808. MODULE_ALIAS("platform:pxa2xx-ir");