ems_pci.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387
  1. /*
  2. * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
  3. * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
  4. * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the version 2 of the GNU General Public License
  8. * as published by the Free Software Foundation
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software Foundation,
  17. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/netdevice.h>
  23. #include <linux/delay.h>
  24. #include <linux/slab.h>
  25. #include <linux/pci.h>
  26. #include <linux/can.h>
  27. #include <linux/can/dev.h>
  28. #include <linux/io.h>
  29. #include "sja1000.h"
  30. #define DRV_NAME "ems_pci"
  31. MODULE_AUTHOR("Sebastian Haas <haas@ems-wuenche.com>");
  32. MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
  33. MODULE_SUPPORTED_DEVICE("EMS CPC-PCI/PCIe/104P CAN card");
  34. MODULE_LICENSE("GPL v2");
  35. #define EMS_PCI_V1_MAX_CHAN 2
  36. #define EMS_PCI_V2_MAX_CHAN 4
  37. #define EMS_PCI_MAX_CHAN EMS_PCI_V2_MAX_CHAN
  38. struct ems_pci_card {
  39. int version;
  40. int channels;
  41. struct pci_dev *pci_dev;
  42. struct net_device *net_dev[EMS_PCI_MAX_CHAN];
  43. void __iomem *conf_addr;
  44. void __iomem *base_addr;
  45. };
  46. #define EMS_PCI_CAN_CLOCK (16000000 / 2)
  47. /*
  48. * Register definitions and descriptions are from LinCAN 0.3.3.
  49. *
  50. * PSB4610 PITA-2 bridge control registers
  51. */
  52. #define PITA2_ICR 0x00 /* Interrupt Control Register */
  53. #define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
  54. #define PITA2_ICR_INT0_EN 0x00020000 /* [RW] Enable INT0 */
  55. #define PITA2_MISC 0x1c /* Miscellaneous Register */
  56. #define PITA2_MISC_CONFIG 0x04000000 /* Multiplexed parallel interface */
  57. /*
  58. * Register definitions for the PLX 9030
  59. */
  60. #define PLX_ICSR 0x4c /* Interrupt Control/Status register */
  61. #define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
  62. #define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
  63. #define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
  64. #define PLX_ICSR_ENA_CLR (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \
  65. PLX_ICSR_LINTI1_CLR)
  66. /*
  67. * The board configuration is probably following:
  68. * RX1 is connected to ground.
  69. * TX1 is not connected.
  70. * CLKO is not connected.
  71. * Setting the OCR register to 0xDA is a good idea.
  72. * This means normal output mode, push-pull and the correct polarity.
  73. */
  74. #define EMS_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
  75. /*
  76. * In the CDR register, you should set CBP to 1.
  77. * You will probably also want to set the clock divider value to 7
  78. * (meaning direct oscillator output) because the second SJA1000 chip
  79. * is driven by the first one CLKOUT output.
  80. */
  81. #define EMS_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
  82. #define EMS_PCI_V1_BASE_BAR 1
  83. #define EMS_PCI_V1_CONF_SIZE 4096 /* size of PITA control area */
  84. #define EMS_PCI_V2_BASE_BAR 2
  85. #define EMS_PCI_V2_CONF_SIZE 128 /* size of PLX control area */
  86. #define EMS_PCI_CAN_BASE_OFFSET 0x400 /* offset where the controllers starts */
  87. #define EMS_PCI_CAN_CTRL_SIZE 0x200 /* memory size for each controller */
  88. #define EMS_PCI_BASE_SIZE 4096 /* size of controller area */
  89. static DEFINE_PCI_DEVICE_TABLE(ems_pci_tbl) = {
  90. /* CPC-PCI v1 */
  91. {PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
  92. /* CPC-PCI v2 */
  93. {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
  94. /* CPC-104P v2 */
  95. {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
  96. {0,}
  97. };
  98. MODULE_DEVICE_TABLE(pci, ems_pci_tbl);
  99. /*
  100. * Helper to read internal registers from card logic (not CAN)
  101. */
  102. static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port)
  103. {
  104. return readb(card->base_addr + (port * 4));
  105. }
  106. static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port)
  107. {
  108. return readb(priv->reg_base + (port * 4));
  109. }
  110. static void ems_pci_v1_write_reg(const struct sja1000_priv *priv,
  111. int port, u8 val)
  112. {
  113. writeb(val, priv->reg_base + (port * 4));
  114. }
  115. static void ems_pci_v1_post_irq(const struct sja1000_priv *priv)
  116. {
  117. struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
  118. /* reset int flag of pita */
  119. writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
  120. card->conf_addr + PITA2_ICR);
  121. }
  122. static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port)
  123. {
  124. return readb(priv->reg_base + port);
  125. }
  126. static void ems_pci_v2_write_reg(const struct sja1000_priv *priv,
  127. int port, u8 val)
  128. {
  129. writeb(val, priv->reg_base + port);
  130. }
  131. static void ems_pci_v2_post_irq(const struct sja1000_priv *priv)
  132. {
  133. struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
  134. writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
  135. }
  136. /*
  137. * Check if a CAN controller is present at the specified location
  138. * by trying to set 'em into the PeliCAN mode
  139. */
  140. static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
  141. {
  142. unsigned char res;
  143. /* Make sure SJA1000 is in reset mode */
  144. priv->write_reg(priv, REG_MOD, 1);
  145. priv->write_reg(priv, REG_CDR, CDR_PELICAN);
  146. /* read reset-values */
  147. res = priv->read_reg(priv, REG_CDR);
  148. if (res == CDR_PELICAN)
  149. return 1;
  150. return 0;
  151. }
  152. static void ems_pci_del_card(struct pci_dev *pdev)
  153. {
  154. struct ems_pci_card *card = pci_get_drvdata(pdev);
  155. struct net_device *dev;
  156. int i = 0;
  157. for (i = 0; i < card->channels; i++) {
  158. dev = card->net_dev[i];
  159. if (!dev)
  160. continue;
  161. dev_info(&pdev->dev, "Removing %s.\n", dev->name);
  162. unregister_sja1000dev(dev);
  163. free_sja1000dev(dev);
  164. }
  165. if (card->base_addr != NULL)
  166. pci_iounmap(card->pci_dev, card->base_addr);
  167. if (card->conf_addr != NULL)
  168. pci_iounmap(card->pci_dev, card->conf_addr);
  169. kfree(card);
  170. pci_disable_device(pdev);
  171. pci_set_drvdata(pdev, NULL);
  172. }
  173. static void ems_pci_card_reset(struct ems_pci_card *card)
  174. {
  175. /* Request board reset */
  176. writeb(0, card->base_addr);
  177. }
  178. /*
  179. * Probe PCI device for EMS CAN signature and register each available
  180. * CAN channel to SJA1000 Socket-CAN subsystem.
  181. */
  182. static int __devinit ems_pci_add_card(struct pci_dev *pdev,
  183. const struct pci_device_id *ent)
  184. {
  185. struct sja1000_priv *priv;
  186. struct net_device *dev;
  187. struct ems_pci_card *card;
  188. int max_chan, conf_size, base_bar;
  189. int err, i;
  190. /* Enabling PCI device */
  191. if (pci_enable_device(pdev) < 0) {
  192. dev_err(&pdev->dev, "Enabling PCI device failed\n");
  193. return -ENODEV;
  194. }
  195. /* Allocating card structures to hold addresses, ... */
  196. card = kzalloc(sizeof(struct ems_pci_card), GFP_KERNEL);
  197. if (card == NULL) {
  198. dev_err(&pdev->dev, "Unable to allocate memory\n");
  199. pci_disable_device(pdev);
  200. return -ENOMEM;
  201. }
  202. pci_set_drvdata(pdev, card);
  203. card->pci_dev = pdev;
  204. card->channels = 0;
  205. if (pdev->vendor == PCI_VENDOR_ID_PLX) {
  206. card->version = 2; /* CPC-PCI v2 */
  207. max_chan = EMS_PCI_V2_MAX_CHAN;
  208. base_bar = EMS_PCI_V2_BASE_BAR;
  209. conf_size = EMS_PCI_V2_CONF_SIZE;
  210. } else {
  211. card->version = 1; /* CPC-PCI v1 */
  212. max_chan = EMS_PCI_V1_MAX_CHAN;
  213. base_bar = EMS_PCI_V1_BASE_BAR;
  214. conf_size = EMS_PCI_V1_CONF_SIZE;
  215. }
  216. /* Remap configuration space and controller memory area */
  217. card->conf_addr = pci_iomap(pdev, 0, conf_size);
  218. if (card->conf_addr == NULL) {
  219. err = -ENOMEM;
  220. goto failure_cleanup;
  221. }
  222. card->base_addr = pci_iomap(pdev, base_bar, EMS_PCI_BASE_SIZE);
  223. if (card->base_addr == NULL) {
  224. err = -ENOMEM;
  225. goto failure_cleanup;
  226. }
  227. if (card->version == 1) {
  228. /* Configure PITA-2 parallel interface (enable MUX) */
  229. writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);
  230. /* Check for unique EMS CAN signature */
  231. if (ems_pci_v1_readb(card, 0) != 0x55 ||
  232. ems_pci_v1_readb(card, 1) != 0xAA ||
  233. ems_pci_v1_readb(card, 2) != 0x01 ||
  234. ems_pci_v1_readb(card, 3) != 0xCB ||
  235. ems_pci_v1_readb(card, 4) != 0x11) {
  236. dev_err(&pdev->dev,
  237. "Not EMS Dr. Thomas Wuensche interface\n");
  238. err = -ENODEV;
  239. goto failure_cleanup;
  240. }
  241. }
  242. ems_pci_card_reset(card);
  243. /* Detect available channels */
  244. for (i = 0; i < max_chan; i++) {
  245. dev = alloc_sja1000dev(0);
  246. if (dev == NULL) {
  247. err = -ENOMEM;
  248. goto failure_cleanup;
  249. }
  250. card->net_dev[i] = dev;
  251. priv = netdev_priv(dev);
  252. priv->priv = card;
  253. priv->irq_flags = IRQF_SHARED;
  254. dev->irq = pdev->irq;
  255. priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET
  256. + (i * EMS_PCI_CAN_CTRL_SIZE);
  257. if (card->version == 1) {
  258. priv->read_reg = ems_pci_v1_read_reg;
  259. priv->write_reg = ems_pci_v1_write_reg;
  260. priv->post_irq = ems_pci_v1_post_irq;
  261. } else {
  262. priv->read_reg = ems_pci_v2_read_reg;
  263. priv->write_reg = ems_pci_v2_write_reg;
  264. priv->post_irq = ems_pci_v2_post_irq;
  265. }
  266. /* Check if channel is present */
  267. if (ems_pci_check_chan(priv)) {
  268. priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
  269. priv->ocr = EMS_PCI_OCR;
  270. priv->cdr = EMS_PCI_CDR;
  271. SET_NETDEV_DEV(dev, &pdev->dev);
  272. if (card->version == 1)
  273. /* reset int flag of pita */
  274. writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
  275. card->conf_addr + PITA2_ICR);
  276. else
  277. /* enable IRQ in PLX 9030 */
  278. writel(PLX_ICSR_ENA_CLR,
  279. card->conf_addr + PLX_ICSR);
  280. /* Register SJA1000 device */
  281. err = register_sja1000dev(dev);
  282. if (err) {
  283. dev_err(&pdev->dev, "Registering device failed "
  284. "(err=%d)\n", err);
  285. free_sja1000dev(dev);
  286. goto failure_cleanup;
  287. }
  288. card->channels++;
  289. dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d\n",
  290. i + 1, priv->reg_base, dev->irq);
  291. } else {
  292. free_sja1000dev(dev);
  293. }
  294. }
  295. return 0;
  296. failure_cleanup:
  297. dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
  298. ems_pci_del_card(pdev);
  299. return err;
  300. }
  301. static struct pci_driver ems_pci_driver = {
  302. .name = DRV_NAME,
  303. .id_table = ems_pci_tbl,
  304. .probe = ems_pci_add_card,
  305. .remove = ems_pci_del_card,
  306. };
  307. static int __init ems_pci_init(void)
  308. {
  309. return pci_register_driver(&ems_pci_driver);
  310. }
  311. static void __exit ems_pci_exit(void)
  312. {
  313. pci_unregister_driver(&ems_pci_driver);
  314. }
  315. module_init(ems_pci_init);
  316. module_exit(ems_pci_exit);