bfin_can.c 17 KB

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  1. /*
  2. * Blackfin On-Chip CAN Driver
  3. *
  4. * Copyright 2004-2009 Analog Devices Inc.
  5. *
  6. * Enter bugs at http://blackfin.uclinux.org/
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/init.h>
  12. #include <linux/kernel.h>
  13. #include <linux/bitops.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/errno.h>
  16. #include <linux/netdevice.h>
  17. #include <linux/skbuff.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/can.h>
  20. #include <linux/can/dev.h>
  21. #include <linux/can/error.h>
  22. #include <asm/bfin_can.h>
  23. #include <asm/portmux.h>
  24. #define DRV_NAME "bfin_can"
  25. #define BFIN_CAN_TIMEOUT 100
  26. #define TX_ECHO_SKB_MAX 1
  27. /*
  28. * bfin can private data
  29. */
  30. struct bfin_can_priv {
  31. struct can_priv can; /* must be the first member */
  32. struct net_device *dev;
  33. void __iomem *membase;
  34. int rx_irq;
  35. int tx_irq;
  36. int err_irq;
  37. unsigned short *pin_list;
  38. };
  39. /*
  40. * bfin can timing parameters
  41. */
  42. static struct can_bittiming_const bfin_can_bittiming_const = {
  43. .name = DRV_NAME,
  44. .tseg1_min = 1,
  45. .tseg1_max = 16,
  46. .tseg2_min = 1,
  47. .tseg2_max = 8,
  48. .sjw_max = 4,
  49. /*
  50. * Although the BRP field can be set to any value, it is recommended
  51. * that the value be greater than or equal to 4, as restrictions
  52. * apply to the bit timing configuration when BRP is less than 4.
  53. */
  54. .brp_min = 4,
  55. .brp_max = 1024,
  56. .brp_inc = 1,
  57. };
  58. static int bfin_can_set_bittiming(struct net_device *dev)
  59. {
  60. struct bfin_can_priv *priv = netdev_priv(dev);
  61. struct bfin_can_regs __iomem *reg = priv->membase;
  62. struct can_bittiming *bt = &priv->can.bittiming;
  63. u16 clk, timing;
  64. clk = bt->brp - 1;
  65. timing = ((bt->sjw - 1) << 8) | (bt->prop_seg + bt->phase_seg1 - 1) |
  66. ((bt->phase_seg2 - 1) << 4);
  67. /*
  68. * If the SAM bit is set, the input signal is oversampled three times
  69. * at the SCLK rate.
  70. */
  71. if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
  72. timing |= SAM;
  73. bfin_write16(&reg->clock, clk);
  74. bfin_write16(&reg->timing, timing);
  75. dev_info(dev->dev.parent, "setting CLOCK=0x%04x TIMING=0x%04x\n",
  76. clk, timing);
  77. return 0;
  78. }
  79. static void bfin_can_set_reset_mode(struct net_device *dev)
  80. {
  81. struct bfin_can_priv *priv = netdev_priv(dev);
  82. struct bfin_can_regs __iomem *reg = priv->membase;
  83. int timeout = BFIN_CAN_TIMEOUT;
  84. int i;
  85. /* disable interrupts */
  86. bfin_write16(&reg->mbim1, 0);
  87. bfin_write16(&reg->mbim2, 0);
  88. bfin_write16(&reg->gim, 0);
  89. /* reset can and enter configuration mode */
  90. bfin_write16(&reg->control, SRS | CCR);
  91. SSYNC();
  92. bfin_write16(&reg->control, CCR);
  93. SSYNC();
  94. while (!(bfin_read16(&reg->control) & CCA)) {
  95. udelay(10);
  96. if (--timeout == 0) {
  97. dev_err(dev->dev.parent,
  98. "fail to enter configuration mode\n");
  99. BUG();
  100. }
  101. }
  102. /*
  103. * All mailbox configurations are marked as inactive
  104. * by writing to CAN Mailbox Configuration Registers 1 and 2
  105. * For all bits: 0 - Mailbox disabled, 1 - Mailbox enabled
  106. */
  107. bfin_write16(&reg->mc1, 0);
  108. bfin_write16(&reg->mc2, 0);
  109. /* Set Mailbox Direction */
  110. bfin_write16(&reg->md1, 0xFFFF); /* mailbox 1-16 are RX */
  111. bfin_write16(&reg->md2, 0); /* mailbox 17-32 are TX */
  112. /* RECEIVE_STD_CHL */
  113. for (i = 0; i < 2; i++) {
  114. bfin_write16(&reg->chl[RECEIVE_STD_CHL + i].id0, 0);
  115. bfin_write16(&reg->chl[RECEIVE_STD_CHL + i].id1, AME);
  116. bfin_write16(&reg->chl[RECEIVE_STD_CHL + i].dlc, 0);
  117. bfin_write16(&reg->msk[RECEIVE_STD_CHL + i].amh, 0x1FFF);
  118. bfin_write16(&reg->msk[RECEIVE_STD_CHL + i].aml, 0xFFFF);
  119. }
  120. /* RECEIVE_EXT_CHL */
  121. for (i = 0; i < 2; i++) {
  122. bfin_write16(&reg->chl[RECEIVE_EXT_CHL + i].id0, 0);
  123. bfin_write16(&reg->chl[RECEIVE_EXT_CHL + i].id1, AME | IDE);
  124. bfin_write16(&reg->chl[RECEIVE_EXT_CHL + i].dlc, 0);
  125. bfin_write16(&reg->msk[RECEIVE_EXT_CHL + i].amh, 0x1FFF);
  126. bfin_write16(&reg->msk[RECEIVE_EXT_CHL + i].aml, 0xFFFF);
  127. }
  128. bfin_write16(&reg->mc2, BIT(TRANSMIT_CHL - 16));
  129. bfin_write16(&reg->mc1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL));
  130. SSYNC();
  131. priv->can.state = CAN_STATE_STOPPED;
  132. }
  133. static void bfin_can_set_normal_mode(struct net_device *dev)
  134. {
  135. struct bfin_can_priv *priv = netdev_priv(dev);
  136. struct bfin_can_regs __iomem *reg = priv->membase;
  137. int timeout = BFIN_CAN_TIMEOUT;
  138. /*
  139. * leave configuration mode
  140. */
  141. bfin_write16(&reg->control, bfin_read16(&reg->control) & ~CCR);
  142. while (bfin_read16(&reg->status) & CCA) {
  143. udelay(10);
  144. if (--timeout == 0) {
  145. dev_err(dev->dev.parent,
  146. "fail to leave configuration mode\n");
  147. BUG();
  148. }
  149. }
  150. /*
  151. * clear _All_ tx and rx interrupts
  152. */
  153. bfin_write16(&reg->mbtif1, 0xFFFF);
  154. bfin_write16(&reg->mbtif2, 0xFFFF);
  155. bfin_write16(&reg->mbrif1, 0xFFFF);
  156. bfin_write16(&reg->mbrif2, 0xFFFF);
  157. /*
  158. * clear global interrupt status register
  159. */
  160. bfin_write16(&reg->gis, 0x7FF); /* overwrites with '1' */
  161. /*
  162. * Initialize Interrupts
  163. * - set bits in the mailbox interrupt mask register
  164. * - global interrupt mask
  165. */
  166. bfin_write16(&reg->mbim1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL));
  167. bfin_write16(&reg->mbim2, BIT(TRANSMIT_CHL - 16));
  168. bfin_write16(&reg->gim, EPIM | BOIM | RMLIM);
  169. SSYNC();
  170. }
  171. static void bfin_can_start(struct net_device *dev)
  172. {
  173. struct bfin_can_priv *priv = netdev_priv(dev);
  174. /* enter reset mode */
  175. if (priv->can.state != CAN_STATE_STOPPED)
  176. bfin_can_set_reset_mode(dev);
  177. /* leave reset mode */
  178. bfin_can_set_normal_mode(dev);
  179. }
  180. static int bfin_can_set_mode(struct net_device *dev, enum can_mode mode)
  181. {
  182. switch (mode) {
  183. case CAN_MODE_START:
  184. bfin_can_start(dev);
  185. if (netif_queue_stopped(dev))
  186. netif_wake_queue(dev);
  187. break;
  188. default:
  189. return -EOPNOTSUPP;
  190. }
  191. return 0;
  192. }
  193. static int bfin_can_start_xmit(struct sk_buff *skb, struct net_device *dev)
  194. {
  195. struct bfin_can_priv *priv = netdev_priv(dev);
  196. struct bfin_can_regs __iomem *reg = priv->membase;
  197. struct can_frame *cf = (struct can_frame *)skb->data;
  198. u8 dlc = cf->can_dlc;
  199. canid_t id = cf->can_id;
  200. u8 *data = cf->data;
  201. u16 val;
  202. int i;
  203. if (can_dropped_invalid_skb(dev, skb))
  204. return NETDEV_TX_OK;
  205. netif_stop_queue(dev);
  206. /* fill id */
  207. if (id & CAN_EFF_FLAG) {
  208. bfin_write16(&reg->chl[TRANSMIT_CHL].id0, id);
  209. if (id & CAN_RTR_FLAG)
  210. writew(((id & 0x1FFF0000) >> 16) | IDE | AME | RTR,
  211. &reg->chl[TRANSMIT_CHL].id1);
  212. else
  213. writew(((id & 0x1FFF0000) >> 16) | IDE | AME,
  214. &reg->chl[TRANSMIT_CHL].id1);
  215. } else {
  216. if (id & CAN_RTR_FLAG)
  217. writew((id << 2) | AME | RTR,
  218. &reg->chl[TRANSMIT_CHL].id1);
  219. else
  220. bfin_write16(&reg->chl[TRANSMIT_CHL].id1,
  221. (id << 2) | AME);
  222. }
  223. /* fill payload */
  224. for (i = 0; i < 8; i += 2) {
  225. val = ((7 - i) < dlc ? (data[7 - i]) : 0) +
  226. ((6 - i) < dlc ? (data[6 - i] << 8) : 0);
  227. bfin_write16(&reg->chl[TRANSMIT_CHL].data[i], val);
  228. }
  229. /* fill data length code */
  230. bfin_write16(&reg->chl[TRANSMIT_CHL].dlc, dlc);
  231. dev->trans_start = jiffies;
  232. can_put_echo_skb(skb, dev, 0);
  233. /* set transmit request */
  234. bfin_write16(&reg->trs2, BIT(TRANSMIT_CHL - 16));
  235. return 0;
  236. }
  237. static void bfin_can_rx(struct net_device *dev, u16 isrc)
  238. {
  239. struct bfin_can_priv *priv = netdev_priv(dev);
  240. struct net_device_stats *stats = &dev->stats;
  241. struct bfin_can_regs __iomem *reg = priv->membase;
  242. struct can_frame *cf;
  243. struct sk_buff *skb;
  244. int obj;
  245. int i;
  246. u16 val;
  247. skb = alloc_can_skb(dev, &cf);
  248. if (skb == NULL)
  249. return;
  250. /* get id */
  251. if (isrc & BIT(RECEIVE_EXT_CHL)) {
  252. /* extended frame format (EFF) */
  253. cf->can_id = ((bfin_read16(&reg->chl[RECEIVE_EXT_CHL].id1)
  254. & 0x1FFF) << 16)
  255. + bfin_read16(&reg->chl[RECEIVE_EXT_CHL].id0);
  256. cf->can_id |= CAN_EFF_FLAG;
  257. obj = RECEIVE_EXT_CHL;
  258. } else {
  259. /* standard frame format (SFF) */
  260. cf->can_id = (bfin_read16(&reg->chl[RECEIVE_STD_CHL].id1)
  261. & 0x1ffc) >> 2;
  262. obj = RECEIVE_STD_CHL;
  263. }
  264. if (bfin_read16(&reg->chl[obj].id1) & RTR)
  265. cf->can_id |= CAN_RTR_FLAG;
  266. /* get data length code */
  267. cf->can_dlc = get_can_dlc(bfin_read16(&reg->chl[obj].dlc) & 0xF);
  268. /* get payload */
  269. for (i = 0; i < 8; i += 2) {
  270. val = bfin_read16(&reg->chl[obj].data[i]);
  271. cf->data[7 - i] = (7 - i) < cf->can_dlc ? val : 0;
  272. cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0;
  273. }
  274. netif_rx(skb);
  275. stats->rx_packets++;
  276. stats->rx_bytes += cf->can_dlc;
  277. }
  278. static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status)
  279. {
  280. struct bfin_can_priv *priv = netdev_priv(dev);
  281. struct bfin_can_regs __iomem *reg = priv->membase;
  282. struct net_device_stats *stats = &dev->stats;
  283. struct can_frame *cf;
  284. struct sk_buff *skb;
  285. enum can_state state = priv->can.state;
  286. skb = alloc_can_err_skb(dev, &cf);
  287. if (skb == NULL)
  288. return -ENOMEM;
  289. if (isrc & RMLIS) {
  290. /* data overrun interrupt */
  291. dev_dbg(dev->dev.parent, "data overrun interrupt\n");
  292. cf->can_id |= CAN_ERR_CRTL;
  293. cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
  294. stats->rx_over_errors++;
  295. stats->rx_errors++;
  296. }
  297. if (isrc & BOIS) {
  298. dev_dbg(dev->dev.parent, "bus-off mode interrupt\n");
  299. state = CAN_STATE_BUS_OFF;
  300. cf->can_id |= CAN_ERR_BUSOFF;
  301. can_bus_off(dev);
  302. }
  303. if (isrc & EPIS) {
  304. /* error passive interrupt */
  305. dev_dbg(dev->dev.parent, "error passive interrupt\n");
  306. state = CAN_STATE_ERROR_PASSIVE;
  307. }
  308. if ((isrc & EWTIS) || (isrc & EWRIS)) {
  309. dev_dbg(dev->dev.parent,
  310. "Error Warning Transmit/Receive Interrupt\n");
  311. state = CAN_STATE_ERROR_WARNING;
  312. }
  313. if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING ||
  314. state == CAN_STATE_ERROR_PASSIVE)) {
  315. u16 cec = bfin_read16(&reg->cec);
  316. u8 rxerr = cec;
  317. u8 txerr = cec >> 8;
  318. cf->can_id |= CAN_ERR_CRTL;
  319. if (state == CAN_STATE_ERROR_WARNING) {
  320. priv->can.can_stats.error_warning++;
  321. cf->data[1] = (txerr > rxerr) ?
  322. CAN_ERR_CRTL_TX_WARNING :
  323. CAN_ERR_CRTL_RX_WARNING;
  324. } else {
  325. priv->can.can_stats.error_passive++;
  326. cf->data[1] = (txerr > rxerr) ?
  327. CAN_ERR_CRTL_TX_PASSIVE :
  328. CAN_ERR_CRTL_RX_PASSIVE;
  329. }
  330. }
  331. if (status) {
  332. priv->can.can_stats.bus_error++;
  333. cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
  334. if (status & BEF)
  335. cf->data[2] |= CAN_ERR_PROT_BIT;
  336. else if (status & FER)
  337. cf->data[2] |= CAN_ERR_PROT_FORM;
  338. else if (status & SER)
  339. cf->data[2] |= CAN_ERR_PROT_STUFF;
  340. else
  341. cf->data[2] |= CAN_ERR_PROT_UNSPEC;
  342. }
  343. priv->can.state = state;
  344. netif_rx(skb);
  345. stats->rx_packets++;
  346. stats->rx_bytes += cf->can_dlc;
  347. return 0;
  348. }
  349. irqreturn_t bfin_can_interrupt(int irq, void *dev_id)
  350. {
  351. struct net_device *dev = dev_id;
  352. struct bfin_can_priv *priv = netdev_priv(dev);
  353. struct bfin_can_regs __iomem *reg = priv->membase;
  354. struct net_device_stats *stats = &dev->stats;
  355. u16 status, isrc;
  356. if ((irq == priv->tx_irq) && bfin_read16(&reg->mbtif2)) {
  357. /* transmission complete interrupt */
  358. bfin_write16(&reg->mbtif2, 0xFFFF);
  359. stats->tx_packets++;
  360. stats->tx_bytes += bfin_read16(&reg->chl[TRANSMIT_CHL].dlc);
  361. can_get_echo_skb(dev, 0);
  362. netif_wake_queue(dev);
  363. } else if ((irq == priv->rx_irq) && bfin_read16(&reg->mbrif1)) {
  364. /* receive interrupt */
  365. isrc = bfin_read16(&reg->mbrif1);
  366. bfin_write16(&reg->mbrif1, 0xFFFF);
  367. bfin_can_rx(dev, isrc);
  368. } else if ((irq == priv->err_irq) && bfin_read16(&reg->gis)) {
  369. /* error interrupt */
  370. isrc = bfin_read16(&reg->gis);
  371. status = bfin_read16(&reg->esr);
  372. bfin_write16(&reg->gis, 0x7FF);
  373. bfin_can_err(dev, isrc, status);
  374. } else {
  375. return IRQ_NONE;
  376. }
  377. return IRQ_HANDLED;
  378. }
  379. static int bfin_can_open(struct net_device *dev)
  380. {
  381. struct bfin_can_priv *priv = netdev_priv(dev);
  382. int err;
  383. /* set chip into reset mode */
  384. bfin_can_set_reset_mode(dev);
  385. /* common open */
  386. err = open_candev(dev);
  387. if (err)
  388. goto exit_open;
  389. /* register interrupt handler */
  390. err = request_irq(priv->rx_irq, &bfin_can_interrupt, 0,
  391. "bfin-can-rx", dev);
  392. if (err)
  393. goto exit_rx_irq;
  394. err = request_irq(priv->tx_irq, &bfin_can_interrupt, 0,
  395. "bfin-can-tx", dev);
  396. if (err)
  397. goto exit_tx_irq;
  398. err = request_irq(priv->err_irq, &bfin_can_interrupt, 0,
  399. "bfin-can-err", dev);
  400. if (err)
  401. goto exit_err_irq;
  402. bfin_can_start(dev);
  403. netif_start_queue(dev);
  404. return 0;
  405. exit_err_irq:
  406. free_irq(priv->tx_irq, dev);
  407. exit_tx_irq:
  408. free_irq(priv->rx_irq, dev);
  409. exit_rx_irq:
  410. close_candev(dev);
  411. exit_open:
  412. return err;
  413. }
  414. static int bfin_can_close(struct net_device *dev)
  415. {
  416. struct bfin_can_priv *priv = netdev_priv(dev);
  417. netif_stop_queue(dev);
  418. bfin_can_set_reset_mode(dev);
  419. close_candev(dev);
  420. free_irq(priv->rx_irq, dev);
  421. free_irq(priv->tx_irq, dev);
  422. free_irq(priv->err_irq, dev);
  423. return 0;
  424. }
  425. struct net_device *alloc_bfin_candev(void)
  426. {
  427. struct net_device *dev;
  428. struct bfin_can_priv *priv;
  429. dev = alloc_candev(sizeof(*priv), TX_ECHO_SKB_MAX);
  430. if (!dev)
  431. return NULL;
  432. priv = netdev_priv(dev);
  433. priv->dev = dev;
  434. priv->can.bittiming_const = &bfin_can_bittiming_const;
  435. priv->can.do_set_bittiming = bfin_can_set_bittiming;
  436. priv->can.do_set_mode = bfin_can_set_mode;
  437. priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
  438. return dev;
  439. }
  440. static const struct net_device_ops bfin_can_netdev_ops = {
  441. .ndo_open = bfin_can_open,
  442. .ndo_stop = bfin_can_close,
  443. .ndo_start_xmit = bfin_can_start_xmit,
  444. };
  445. static int __devinit bfin_can_probe(struct platform_device *pdev)
  446. {
  447. int err;
  448. struct net_device *dev;
  449. struct bfin_can_priv *priv;
  450. struct resource *res_mem, *rx_irq, *tx_irq, *err_irq;
  451. unsigned short *pdata;
  452. pdata = pdev->dev.platform_data;
  453. if (!pdata) {
  454. dev_err(&pdev->dev, "No platform data provided!\n");
  455. err = -EINVAL;
  456. goto exit;
  457. }
  458. res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  459. rx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  460. tx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
  461. err_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
  462. if (!res_mem || !rx_irq || !tx_irq || !err_irq) {
  463. err = -EINVAL;
  464. goto exit;
  465. }
  466. if (!request_mem_region(res_mem->start, resource_size(res_mem),
  467. dev_name(&pdev->dev))) {
  468. err = -EBUSY;
  469. goto exit;
  470. }
  471. /* request peripheral pins */
  472. err = peripheral_request_list(pdata, dev_name(&pdev->dev));
  473. if (err)
  474. goto exit_mem_release;
  475. dev = alloc_bfin_candev();
  476. if (!dev) {
  477. err = -ENOMEM;
  478. goto exit_peri_pin_free;
  479. }
  480. priv = netdev_priv(dev);
  481. priv->membase = (void __iomem *)res_mem->start;
  482. priv->rx_irq = rx_irq->start;
  483. priv->tx_irq = tx_irq->start;
  484. priv->err_irq = err_irq->start;
  485. priv->pin_list = pdata;
  486. priv->can.clock.freq = get_sclk();
  487. dev_set_drvdata(&pdev->dev, dev);
  488. SET_NETDEV_DEV(dev, &pdev->dev);
  489. dev->flags |= IFF_ECHO; /* we support local echo */
  490. dev->netdev_ops = &bfin_can_netdev_ops;
  491. bfin_can_set_reset_mode(dev);
  492. err = register_candev(dev);
  493. if (err) {
  494. dev_err(&pdev->dev, "registering failed (err=%d)\n", err);
  495. goto exit_candev_free;
  496. }
  497. dev_info(&pdev->dev,
  498. "%s device registered"
  499. "(&reg_base=%p, rx_irq=%d, tx_irq=%d, err_irq=%d, sclk=%d)\n",
  500. DRV_NAME, (void *)priv->membase, priv->rx_irq,
  501. priv->tx_irq, priv->err_irq, priv->can.clock.freq);
  502. return 0;
  503. exit_candev_free:
  504. free_candev(dev);
  505. exit_peri_pin_free:
  506. peripheral_free_list(pdata);
  507. exit_mem_release:
  508. release_mem_region(res_mem->start, resource_size(res_mem));
  509. exit:
  510. return err;
  511. }
  512. static int __devexit bfin_can_remove(struct platform_device *pdev)
  513. {
  514. struct net_device *dev = dev_get_drvdata(&pdev->dev);
  515. struct bfin_can_priv *priv = netdev_priv(dev);
  516. struct resource *res;
  517. bfin_can_set_reset_mode(dev);
  518. unregister_candev(dev);
  519. dev_set_drvdata(&pdev->dev, NULL);
  520. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  521. release_mem_region(res->start, resource_size(res));
  522. peripheral_free_list(priv->pin_list);
  523. free_candev(dev);
  524. return 0;
  525. }
  526. #ifdef CONFIG_PM
  527. static int bfin_can_suspend(struct platform_device *pdev, pm_message_t mesg)
  528. {
  529. struct net_device *dev = dev_get_drvdata(&pdev->dev);
  530. struct bfin_can_priv *priv = netdev_priv(dev);
  531. struct bfin_can_regs __iomem *reg = priv->membase;
  532. int timeout = BFIN_CAN_TIMEOUT;
  533. if (netif_running(dev)) {
  534. /* enter sleep mode */
  535. bfin_write16(&reg->control, bfin_read16(&reg->control) | SMR);
  536. SSYNC();
  537. while (!(bfin_read16(&reg->intr) & SMACK)) {
  538. udelay(10);
  539. if (--timeout == 0) {
  540. dev_err(dev->dev.parent,
  541. "fail to enter sleep mode\n");
  542. BUG();
  543. }
  544. }
  545. }
  546. return 0;
  547. }
  548. static int bfin_can_resume(struct platform_device *pdev)
  549. {
  550. struct net_device *dev = dev_get_drvdata(&pdev->dev);
  551. struct bfin_can_priv *priv = netdev_priv(dev);
  552. struct bfin_can_regs __iomem *reg = priv->membase;
  553. if (netif_running(dev)) {
  554. /* leave sleep mode */
  555. bfin_write16(&reg->intr, 0);
  556. SSYNC();
  557. }
  558. return 0;
  559. }
  560. #else
  561. #define bfin_can_suspend NULL
  562. #define bfin_can_resume NULL
  563. #endif /* CONFIG_PM */
  564. static struct platform_driver bfin_can_driver = {
  565. .probe = bfin_can_probe,
  566. .remove = __devexit_p(bfin_can_remove),
  567. .suspend = bfin_can_suspend,
  568. .resume = bfin_can_resume,
  569. .driver = {
  570. .name = DRV_NAME,
  571. .owner = THIS_MODULE,
  572. },
  573. };
  574. static int __init bfin_can_init(void)
  575. {
  576. return platform_driver_register(&bfin_can_driver);
  577. }
  578. module_init(bfin_can_init);
  579. static void __exit bfin_can_exit(void)
  580. {
  581. platform_driver_unregister(&bfin_can_driver);
  582. }
  583. module_exit(bfin_can_exit);
  584. MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
  585. MODULE_LICENSE("GPL");
  586. MODULE_DESCRIPTION("Blackfin on-chip CAN netdevice driver");