pcf50633-core.c 16 KB

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  1. /* NXP PCF50633 Power Management Unit (PMU) driver
  2. *
  3. * (C) 2006-2008 by Openmoko, Inc.
  4. * Author: Harald Welte <laforge@openmoko.org>
  5. * Balaji Rao <balajirrao@openmoko.org>
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/device.h>
  16. #include <linux/sysfs.h>
  17. #include <linux/module.h>
  18. #include <linux/types.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/workqueue.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/i2c.h>
  23. #include <linux/irq.h>
  24. #include <linux/slab.h>
  25. #include <linux/mfd/pcf50633/core.h>
  26. /* Two MBCS registers used during cold start */
  27. #define PCF50633_REG_MBCS1 0x4b
  28. #define PCF50633_REG_MBCS2 0x4c
  29. #define PCF50633_MBCS1_USBPRES 0x01
  30. #define PCF50633_MBCS1_ADAPTPRES 0x01
  31. static int __pcf50633_read(struct pcf50633 *pcf, u8 reg, int num, u8 *data)
  32. {
  33. int ret;
  34. ret = i2c_smbus_read_i2c_block_data(pcf->i2c_client, reg,
  35. num, data);
  36. if (ret < 0)
  37. dev_err(pcf->dev, "Error reading %d regs at %d\n", num, reg);
  38. return ret;
  39. }
  40. static int __pcf50633_write(struct pcf50633 *pcf, u8 reg, int num, u8 *data)
  41. {
  42. int ret;
  43. ret = i2c_smbus_write_i2c_block_data(pcf->i2c_client, reg,
  44. num, data);
  45. if (ret < 0)
  46. dev_err(pcf->dev, "Error writing %d regs at %d\n", num, reg);
  47. return ret;
  48. }
  49. /* Read a block of upto 32 regs */
  50. int pcf50633_read_block(struct pcf50633 *pcf, u8 reg,
  51. int nr_regs, u8 *data)
  52. {
  53. int ret;
  54. mutex_lock(&pcf->lock);
  55. ret = __pcf50633_read(pcf, reg, nr_regs, data);
  56. mutex_unlock(&pcf->lock);
  57. return ret;
  58. }
  59. EXPORT_SYMBOL_GPL(pcf50633_read_block);
  60. /* Write a block of upto 32 regs */
  61. int pcf50633_write_block(struct pcf50633 *pcf , u8 reg,
  62. int nr_regs, u8 *data)
  63. {
  64. int ret;
  65. mutex_lock(&pcf->lock);
  66. ret = __pcf50633_write(pcf, reg, nr_regs, data);
  67. mutex_unlock(&pcf->lock);
  68. return ret;
  69. }
  70. EXPORT_SYMBOL_GPL(pcf50633_write_block);
  71. u8 pcf50633_reg_read(struct pcf50633 *pcf, u8 reg)
  72. {
  73. u8 val;
  74. mutex_lock(&pcf->lock);
  75. __pcf50633_read(pcf, reg, 1, &val);
  76. mutex_unlock(&pcf->lock);
  77. return val;
  78. }
  79. EXPORT_SYMBOL_GPL(pcf50633_reg_read);
  80. int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val)
  81. {
  82. int ret;
  83. mutex_lock(&pcf->lock);
  84. ret = __pcf50633_write(pcf, reg, 1, &val);
  85. mutex_unlock(&pcf->lock);
  86. return ret;
  87. }
  88. EXPORT_SYMBOL_GPL(pcf50633_reg_write);
  89. int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val)
  90. {
  91. int ret;
  92. u8 tmp;
  93. val &= mask;
  94. mutex_lock(&pcf->lock);
  95. ret = __pcf50633_read(pcf, reg, 1, &tmp);
  96. if (ret < 0)
  97. goto out;
  98. tmp &= ~mask;
  99. tmp |= val;
  100. ret = __pcf50633_write(pcf, reg, 1, &tmp);
  101. out:
  102. mutex_unlock(&pcf->lock);
  103. return ret;
  104. }
  105. EXPORT_SYMBOL_GPL(pcf50633_reg_set_bit_mask);
  106. int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 val)
  107. {
  108. int ret;
  109. u8 tmp;
  110. mutex_lock(&pcf->lock);
  111. ret = __pcf50633_read(pcf, reg, 1, &tmp);
  112. if (ret < 0)
  113. goto out;
  114. tmp &= ~val;
  115. ret = __pcf50633_write(pcf, reg, 1, &tmp);
  116. out:
  117. mutex_unlock(&pcf->lock);
  118. return ret;
  119. }
  120. EXPORT_SYMBOL_GPL(pcf50633_reg_clear_bits);
  121. /* sysfs attributes */
  122. static ssize_t show_dump_regs(struct device *dev, struct device_attribute *attr,
  123. char *buf)
  124. {
  125. struct pcf50633 *pcf = dev_get_drvdata(dev);
  126. u8 dump[16];
  127. int n, n1, idx = 0;
  128. char *buf1 = buf;
  129. static u8 address_no_read[] = { /* must be ascending */
  130. PCF50633_REG_INT1,
  131. PCF50633_REG_INT2,
  132. PCF50633_REG_INT3,
  133. PCF50633_REG_INT4,
  134. PCF50633_REG_INT5,
  135. 0 /* terminator */
  136. };
  137. for (n = 0; n < 256; n += sizeof(dump)) {
  138. for (n1 = 0; n1 < sizeof(dump); n1++)
  139. if (n == address_no_read[idx]) {
  140. idx++;
  141. dump[n1] = 0x00;
  142. } else
  143. dump[n1] = pcf50633_reg_read(pcf, n + n1);
  144. hex_dump_to_buffer(dump, sizeof(dump), 16, 1, buf1, 128, 0);
  145. buf1 += strlen(buf1);
  146. *buf1++ = '\n';
  147. *buf1 = '\0';
  148. }
  149. return buf1 - buf;
  150. }
  151. static DEVICE_ATTR(dump_regs, 0400, show_dump_regs, NULL);
  152. static ssize_t show_resume_reason(struct device *dev,
  153. struct device_attribute *attr, char *buf)
  154. {
  155. struct pcf50633 *pcf = dev_get_drvdata(dev);
  156. int n;
  157. n = sprintf(buf, "%02x%02x%02x%02x%02x\n",
  158. pcf->resume_reason[0],
  159. pcf->resume_reason[1],
  160. pcf->resume_reason[2],
  161. pcf->resume_reason[3],
  162. pcf->resume_reason[4]);
  163. return n;
  164. }
  165. static DEVICE_ATTR(resume_reason, 0400, show_resume_reason, NULL);
  166. static struct attribute *pcf_sysfs_entries[] = {
  167. &dev_attr_dump_regs.attr,
  168. &dev_attr_resume_reason.attr,
  169. NULL,
  170. };
  171. static struct attribute_group pcf_attr_group = {
  172. .name = NULL, /* put in device directory */
  173. .attrs = pcf_sysfs_entries,
  174. };
  175. int pcf50633_register_irq(struct pcf50633 *pcf, int irq,
  176. void (*handler) (int, void *), void *data)
  177. {
  178. if (irq < 0 || irq > PCF50633_NUM_IRQ || !handler)
  179. return -EINVAL;
  180. if (WARN_ON(pcf->irq_handler[irq].handler))
  181. return -EBUSY;
  182. mutex_lock(&pcf->lock);
  183. pcf->irq_handler[irq].handler = handler;
  184. pcf->irq_handler[irq].data = data;
  185. mutex_unlock(&pcf->lock);
  186. return 0;
  187. }
  188. EXPORT_SYMBOL_GPL(pcf50633_register_irq);
  189. int pcf50633_free_irq(struct pcf50633 *pcf, int irq)
  190. {
  191. if (irq < 0 || irq > PCF50633_NUM_IRQ)
  192. return -EINVAL;
  193. mutex_lock(&pcf->lock);
  194. pcf->irq_handler[irq].handler = NULL;
  195. mutex_unlock(&pcf->lock);
  196. return 0;
  197. }
  198. EXPORT_SYMBOL_GPL(pcf50633_free_irq);
  199. static int __pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, u8 mask)
  200. {
  201. u8 reg, bits, tmp;
  202. int ret = 0, idx;
  203. idx = irq >> 3;
  204. reg = PCF50633_REG_INT1M + idx;
  205. bits = 1 << (irq & 0x07);
  206. mutex_lock(&pcf->lock);
  207. if (mask) {
  208. ret = __pcf50633_read(pcf, reg, 1, &tmp);
  209. if (ret < 0)
  210. goto out;
  211. tmp |= bits;
  212. ret = __pcf50633_write(pcf, reg, 1, &tmp);
  213. if (ret < 0)
  214. goto out;
  215. pcf->mask_regs[idx] &= ~bits;
  216. pcf->mask_regs[idx] |= bits;
  217. } else {
  218. ret = __pcf50633_read(pcf, reg, 1, &tmp);
  219. if (ret < 0)
  220. goto out;
  221. tmp &= ~bits;
  222. ret = __pcf50633_write(pcf, reg, 1, &tmp);
  223. if (ret < 0)
  224. goto out;
  225. pcf->mask_regs[idx] &= ~bits;
  226. }
  227. out:
  228. mutex_unlock(&pcf->lock);
  229. return ret;
  230. }
  231. int pcf50633_irq_mask(struct pcf50633 *pcf, int irq)
  232. {
  233. dev_dbg(pcf->dev, "Masking IRQ %d\n", irq);
  234. return __pcf50633_irq_mask_set(pcf, irq, 1);
  235. }
  236. EXPORT_SYMBOL_GPL(pcf50633_irq_mask);
  237. int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq)
  238. {
  239. dev_dbg(pcf->dev, "Unmasking IRQ %d\n", irq);
  240. return __pcf50633_irq_mask_set(pcf, irq, 0);
  241. }
  242. EXPORT_SYMBOL_GPL(pcf50633_irq_unmask);
  243. int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq)
  244. {
  245. u8 reg, bits;
  246. reg = irq >> 3;
  247. bits = 1 << (irq & 0x07);
  248. return pcf->mask_regs[reg] & bits;
  249. }
  250. EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get);
  251. static void pcf50633_irq_call_handler(struct pcf50633 *pcf, int irq)
  252. {
  253. if (pcf->irq_handler[irq].handler)
  254. pcf->irq_handler[irq].handler(irq, pcf->irq_handler[irq].data);
  255. }
  256. /* Maximum amount of time ONKEY is held before emergency action is taken */
  257. #define PCF50633_ONKEY1S_TIMEOUT 8
  258. static void pcf50633_irq_worker(struct work_struct *work)
  259. {
  260. struct pcf50633 *pcf;
  261. int ret, i, j;
  262. u8 pcf_int[5], chgstat;
  263. pcf = container_of(work, struct pcf50633, irq_work);
  264. /* Read the 5 INT regs in one transaction */
  265. ret = pcf50633_read_block(pcf, PCF50633_REG_INT1,
  266. ARRAY_SIZE(pcf_int), pcf_int);
  267. if (ret != ARRAY_SIZE(pcf_int)) {
  268. dev_err(pcf->dev, "Error reading INT registers\n");
  269. /*
  270. * If this doesn't ACK the interrupt to the chip, we'll be
  271. * called once again as we're level triggered.
  272. */
  273. goto out;
  274. }
  275. /* defeat 8s death from lowsys on A5 */
  276. pcf50633_reg_write(pcf, PCF50633_REG_OOCSHDWN, 0x04);
  277. /* We immediately read the usb and adapter status. We thus make sure
  278. * only of USBINS/USBREM IRQ handlers are called */
  279. if (pcf_int[0] & (PCF50633_INT1_USBINS | PCF50633_INT1_USBREM)) {
  280. chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
  281. if (chgstat & (0x3 << 4))
  282. pcf_int[0] &= ~(1 << PCF50633_INT1_USBREM);
  283. else
  284. pcf_int[0] &= ~(1 << PCF50633_INT1_USBINS);
  285. }
  286. /* Make sure only one of ADPINS or ADPREM is set */
  287. if (pcf_int[0] & (PCF50633_INT1_ADPINS | PCF50633_INT1_ADPREM)) {
  288. chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
  289. if (chgstat & (0x3 << 4))
  290. pcf_int[0] &= ~(1 << PCF50633_INT1_ADPREM);
  291. else
  292. pcf_int[0] &= ~(1 << PCF50633_INT1_ADPINS);
  293. }
  294. dev_dbg(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x "
  295. "INT4=0x%02x INT5=0x%02x\n", pcf_int[0],
  296. pcf_int[1], pcf_int[2], pcf_int[3], pcf_int[4]);
  297. /* Some revisions of the chip don't have a 8s standby mode on
  298. * ONKEY1S press. We try to manually do it in such cases. */
  299. if ((pcf_int[0] & PCF50633_INT1_SECOND) && pcf->onkey1s_held) {
  300. dev_info(pcf->dev, "ONKEY1S held for %d secs\n",
  301. pcf->onkey1s_held);
  302. if (pcf->onkey1s_held++ == PCF50633_ONKEY1S_TIMEOUT)
  303. if (pcf->pdata->force_shutdown)
  304. pcf->pdata->force_shutdown(pcf);
  305. }
  306. if (pcf_int[2] & PCF50633_INT3_ONKEY1S) {
  307. dev_info(pcf->dev, "ONKEY1S held\n");
  308. pcf->onkey1s_held = 1 ;
  309. /* Unmask IRQ_SECOND */
  310. pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M,
  311. PCF50633_INT1_SECOND);
  312. /* Unmask IRQ_ONKEYR */
  313. pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT2M,
  314. PCF50633_INT2_ONKEYR);
  315. }
  316. if ((pcf_int[1] & PCF50633_INT2_ONKEYR) && pcf->onkey1s_held) {
  317. pcf->onkey1s_held = 0;
  318. /* Mask SECOND and ONKEYR interrupts */
  319. if (pcf->mask_regs[0] & PCF50633_INT1_SECOND)
  320. pcf50633_reg_set_bit_mask(pcf,
  321. PCF50633_REG_INT1M,
  322. PCF50633_INT1_SECOND,
  323. PCF50633_INT1_SECOND);
  324. if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR)
  325. pcf50633_reg_set_bit_mask(pcf,
  326. PCF50633_REG_INT2M,
  327. PCF50633_INT2_ONKEYR,
  328. PCF50633_INT2_ONKEYR);
  329. }
  330. /* Have we just resumed ? */
  331. if (pcf->is_suspended) {
  332. pcf->is_suspended = 0;
  333. /* Set the resume reason filtering out non resumers */
  334. for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
  335. pcf->resume_reason[i] = pcf_int[i] &
  336. pcf->pdata->resumers[i];
  337. /* Make sure we don't pass on any ONKEY events to
  338. * userspace now */
  339. pcf_int[1] &= ~(PCF50633_INT2_ONKEYR | PCF50633_INT2_ONKEYF);
  340. }
  341. for (i = 0; i < ARRAY_SIZE(pcf_int); i++) {
  342. /* Unset masked interrupts */
  343. pcf_int[i] &= ~pcf->mask_regs[i];
  344. for (j = 0; j < 8 ; j++)
  345. if (pcf_int[i] & (1 << j))
  346. pcf50633_irq_call_handler(pcf, (i * 8) + j);
  347. }
  348. out:
  349. put_device(pcf->dev);
  350. enable_irq(pcf->irq);
  351. }
  352. static irqreturn_t pcf50633_irq(int irq, void *data)
  353. {
  354. struct pcf50633 *pcf = data;
  355. dev_dbg(pcf->dev, "pcf50633_irq\n");
  356. get_device(pcf->dev);
  357. disable_irq_nosync(pcf->irq);
  358. queue_work(pcf->work_queue, &pcf->irq_work);
  359. return IRQ_HANDLED;
  360. }
  361. static void
  362. pcf50633_client_dev_register(struct pcf50633 *pcf, const char *name,
  363. struct platform_device **pdev)
  364. {
  365. int ret;
  366. *pdev = platform_device_alloc(name, -1);
  367. if (!*pdev) {
  368. dev_err(pcf->dev, "Falied to allocate %s\n", name);
  369. return;
  370. }
  371. (*pdev)->dev.parent = pcf->dev;
  372. ret = platform_device_add(*pdev);
  373. if (ret) {
  374. dev_err(pcf->dev, "Failed to register %s: %d\n", name, ret);
  375. platform_device_put(*pdev);
  376. *pdev = NULL;
  377. }
  378. }
  379. #ifdef CONFIG_PM
  380. static int pcf50633_suspend(struct i2c_client *client, pm_message_t state)
  381. {
  382. struct pcf50633 *pcf;
  383. int ret = 0, i;
  384. u8 res[5];
  385. pcf = i2c_get_clientdata(client);
  386. /* Make sure our interrupt handlers are not called
  387. * henceforth */
  388. disable_irq(pcf->irq);
  389. /* Make sure that any running IRQ worker has quit */
  390. cancel_work_sync(&pcf->irq_work);
  391. /* Save the masks */
  392. ret = pcf50633_read_block(pcf, PCF50633_REG_INT1M,
  393. ARRAY_SIZE(pcf->suspend_irq_masks),
  394. pcf->suspend_irq_masks);
  395. if (ret < 0) {
  396. dev_err(pcf->dev, "error saving irq masks\n");
  397. goto out;
  398. }
  399. /* Write wakeup irq masks */
  400. for (i = 0; i < ARRAY_SIZE(res); i++)
  401. res[i] = ~pcf->pdata->resumers[i];
  402. ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M,
  403. ARRAY_SIZE(res), &res[0]);
  404. if (ret < 0) {
  405. dev_err(pcf->dev, "error writing wakeup irq masks\n");
  406. goto out;
  407. }
  408. pcf->is_suspended = 1;
  409. out:
  410. return ret;
  411. }
  412. static int pcf50633_resume(struct i2c_client *client)
  413. {
  414. struct pcf50633 *pcf;
  415. int ret;
  416. pcf = i2c_get_clientdata(client);
  417. /* Write the saved mask registers */
  418. ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M,
  419. ARRAY_SIZE(pcf->suspend_irq_masks),
  420. pcf->suspend_irq_masks);
  421. if (ret < 0)
  422. dev_err(pcf->dev, "Error restoring saved suspend masks\n");
  423. /* Restore regulators' state */
  424. get_device(pcf->dev);
  425. /*
  426. * Clear any pending interrupts and set resume reason if any.
  427. * This will leave with enable_irq()
  428. */
  429. pcf50633_irq_worker(&pcf->irq_work);
  430. return 0;
  431. }
  432. #else
  433. #define pcf50633_suspend NULL
  434. #define pcf50633_resume NULL
  435. #endif
  436. static int __devinit pcf50633_probe(struct i2c_client *client,
  437. const struct i2c_device_id *ids)
  438. {
  439. struct pcf50633 *pcf;
  440. struct pcf50633_platform_data *pdata = client->dev.platform_data;
  441. int i, ret;
  442. int version, variant;
  443. if (!client->irq) {
  444. dev_err(&client->dev, "Missing IRQ\n");
  445. return -ENOENT;
  446. }
  447. pcf = kzalloc(sizeof(*pcf), GFP_KERNEL);
  448. if (!pcf)
  449. return -ENOMEM;
  450. pcf->pdata = pdata;
  451. mutex_init(&pcf->lock);
  452. i2c_set_clientdata(client, pcf);
  453. pcf->dev = &client->dev;
  454. pcf->i2c_client = client;
  455. pcf->irq = client->irq;
  456. pcf->work_queue = create_singlethread_workqueue("pcf50633");
  457. if (!pcf->work_queue) {
  458. dev_err(&client->dev, "Failed to alloc workqueue\n");
  459. ret = -ENOMEM;
  460. goto err_free;
  461. }
  462. INIT_WORK(&pcf->irq_work, pcf50633_irq_worker);
  463. version = pcf50633_reg_read(pcf, 0);
  464. variant = pcf50633_reg_read(pcf, 1);
  465. if (version < 0 || variant < 0) {
  466. dev_err(pcf->dev, "Unable to probe pcf50633\n");
  467. ret = -ENODEV;
  468. goto err_destroy_workqueue;
  469. }
  470. dev_info(pcf->dev, "Probed device version %d variant %d\n",
  471. version, variant);
  472. /* Enable all interrupts except RTC SECOND */
  473. pcf->mask_regs[0] = 0x80;
  474. pcf50633_reg_write(pcf, PCF50633_REG_INT1M, pcf->mask_regs[0]);
  475. pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00);
  476. pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00);
  477. pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00);
  478. pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00);
  479. ret = request_irq(client->irq, pcf50633_irq,
  480. IRQF_TRIGGER_LOW, "pcf50633", pcf);
  481. if (ret) {
  482. dev_err(pcf->dev, "Failed to request IRQ %d\n", ret);
  483. goto err_destroy_workqueue;
  484. }
  485. /* Create sub devices */
  486. pcf50633_client_dev_register(pcf, "pcf50633-input",
  487. &pcf->input_pdev);
  488. pcf50633_client_dev_register(pcf, "pcf50633-rtc",
  489. &pcf->rtc_pdev);
  490. pcf50633_client_dev_register(pcf, "pcf50633-mbc",
  491. &pcf->mbc_pdev);
  492. pcf50633_client_dev_register(pcf, "pcf50633-adc",
  493. &pcf->adc_pdev);
  494. for (i = 0; i < PCF50633_NUM_REGULATORS; i++) {
  495. struct platform_device *pdev;
  496. pdev = platform_device_alloc("pcf50633-regltr", i);
  497. if (!pdev) {
  498. dev_err(pcf->dev, "Cannot create regulator %d\n", i);
  499. continue;
  500. }
  501. pdev->dev.parent = pcf->dev;
  502. platform_device_add_data(pdev, &pdata->reg_init_data[i],
  503. sizeof(pdata->reg_init_data[i]));
  504. pcf->regulator_pdev[i] = pdev;
  505. platform_device_add(pdev);
  506. }
  507. if (enable_irq_wake(client->irq) < 0)
  508. dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up source"
  509. "in this hardware revision", client->irq);
  510. ret = sysfs_create_group(&client->dev.kobj, &pcf_attr_group);
  511. if (ret)
  512. dev_err(pcf->dev, "error creating sysfs entries\n");
  513. if (pdata->probe_done)
  514. pdata->probe_done(pcf);
  515. return 0;
  516. err_destroy_workqueue:
  517. destroy_workqueue(pcf->work_queue);
  518. err_free:
  519. i2c_set_clientdata(client, NULL);
  520. kfree(pcf);
  521. return ret;
  522. }
  523. static int __devexit pcf50633_remove(struct i2c_client *client)
  524. {
  525. struct pcf50633 *pcf = i2c_get_clientdata(client);
  526. int i;
  527. free_irq(pcf->irq, pcf);
  528. destroy_workqueue(pcf->work_queue);
  529. platform_device_unregister(pcf->input_pdev);
  530. platform_device_unregister(pcf->rtc_pdev);
  531. platform_device_unregister(pcf->mbc_pdev);
  532. platform_device_unregister(pcf->adc_pdev);
  533. for (i = 0; i < PCF50633_NUM_REGULATORS; i++)
  534. platform_device_unregister(pcf->regulator_pdev[i]);
  535. kfree(pcf);
  536. return 0;
  537. }
  538. static struct i2c_device_id pcf50633_id_table[] = {
  539. {"pcf50633", 0x73},
  540. {/* end of list */}
  541. };
  542. static struct i2c_driver pcf50633_driver = {
  543. .driver = {
  544. .name = "pcf50633",
  545. },
  546. .id_table = pcf50633_id_table,
  547. .probe = pcf50633_probe,
  548. .remove = __devexit_p(pcf50633_remove),
  549. .suspend = pcf50633_suspend,
  550. .resume = pcf50633_resume,
  551. };
  552. static int __init pcf50633_init(void)
  553. {
  554. return i2c_add_driver(&pcf50633_driver);
  555. }
  556. static void __exit pcf50633_exit(void)
  557. {
  558. i2c_del_driver(&pcf50633_driver);
  559. }
  560. MODULE_DESCRIPTION("I2C chip driver for NXP PCF50633 PMU");
  561. MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
  562. MODULE_LICENSE("GPL");
  563. subsys_initcall(pcf50633_init);
  564. module_exit(pcf50633_exit);