ov7670.c 34 KB

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  1. /*
  2. * A V4L2 driver for OmniVision OV7670 cameras.
  3. *
  4. * Copyright 2006 One Laptop Per Child Association, Inc. Written
  5. * by Jonathan Corbet with substantial inspiration from Mark
  6. * McClelland's ovcamchip code.
  7. *
  8. * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  9. *
  10. * This file may be distributed under the terms of the GNU General
  11. * Public License, version 2.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <linux/slab.h>
  16. #include <linux/i2c.h>
  17. #include <linux/delay.h>
  18. #include <linux/videodev2.h>
  19. #include <media/v4l2-device.h>
  20. #include <media/v4l2-chip-ident.h>
  21. #include <media/v4l2-i2c-drv.h>
  22. MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
  23. MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors");
  24. MODULE_LICENSE("GPL");
  25. static int debug;
  26. module_param(debug, bool, 0644);
  27. MODULE_PARM_DESC(debug, "Debug level (0-1)");
  28. /*
  29. * Basic window sizes. These probably belong somewhere more globally
  30. * useful.
  31. */
  32. #define VGA_WIDTH 640
  33. #define VGA_HEIGHT 480
  34. #define QVGA_WIDTH 320
  35. #define QVGA_HEIGHT 240
  36. #define CIF_WIDTH 352
  37. #define CIF_HEIGHT 288
  38. #define QCIF_WIDTH 176
  39. #define QCIF_HEIGHT 144
  40. /*
  41. * Our nominal (default) frame rate.
  42. */
  43. #define OV7670_FRAME_RATE 30
  44. /*
  45. * The 7670 sits on i2c with ID 0x42
  46. */
  47. #define OV7670_I2C_ADDR 0x42
  48. /* Registers */
  49. #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
  50. #define REG_BLUE 0x01 /* blue gain */
  51. #define REG_RED 0x02 /* red gain */
  52. #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
  53. #define REG_COM1 0x04 /* Control 1 */
  54. #define COM1_CCIR656 0x40 /* CCIR656 enable */
  55. #define REG_BAVE 0x05 /* U/B Average level */
  56. #define REG_GbAVE 0x06 /* Y/Gb Average level */
  57. #define REG_AECHH 0x07 /* AEC MS 5 bits */
  58. #define REG_RAVE 0x08 /* V/R Average level */
  59. #define REG_COM2 0x09 /* Control 2 */
  60. #define COM2_SSLEEP 0x10 /* Soft sleep mode */
  61. #define REG_PID 0x0a /* Product ID MSB */
  62. #define REG_VER 0x0b /* Product ID LSB */
  63. #define REG_COM3 0x0c /* Control 3 */
  64. #define COM3_SWAP 0x40 /* Byte swap */
  65. #define COM3_SCALEEN 0x08 /* Enable scaling */
  66. #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
  67. #define REG_COM4 0x0d /* Control 4 */
  68. #define REG_COM5 0x0e /* All "reserved" */
  69. #define REG_COM6 0x0f /* Control 6 */
  70. #define REG_AECH 0x10 /* More bits of AEC value */
  71. #define REG_CLKRC 0x11 /* Clocl control */
  72. #define CLK_EXT 0x40 /* Use external clock directly */
  73. #define CLK_SCALE 0x3f /* Mask for internal clock scale */
  74. #define REG_COM7 0x12 /* Control 7 */
  75. #define COM7_RESET 0x80 /* Register reset */
  76. #define COM7_FMT_MASK 0x38
  77. #define COM7_FMT_VGA 0x00
  78. #define COM7_FMT_CIF 0x20 /* CIF format */
  79. #define COM7_FMT_QVGA 0x10 /* QVGA format */
  80. #define COM7_FMT_QCIF 0x08 /* QCIF format */
  81. #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
  82. #define COM7_YUV 0x00 /* YUV */
  83. #define COM7_BAYER 0x01 /* Bayer format */
  84. #define COM7_PBAYER 0x05 /* "Processed bayer" */
  85. #define REG_COM8 0x13 /* Control 8 */
  86. #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
  87. #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
  88. #define COM8_BFILT 0x20 /* Band filter enable */
  89. #define COM8_AGC 0x04 /* Auto gain enable */
  90. #define COM8_AWB 0x02 /* White balance enable */
  91. #define COM8_AEC 0x01 /* Auto exposure enable */
  92. #define REG_COM9 0x14 /* Control 9 - gain ceiling */
  93. #define REG_COM10 0x15 /* Control 10 */
  94. #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
  95. #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
  96. #define COM10_HREF_REV 0x08 /* Reverse HREF */
  97. #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
  98. #define COM10_VS_NEG 0x02 /* VSYNC negative */
  99. #define COM10_HS_NEG 0x01 /* HSYNC negative */
  100. #define REG_HSTART 0x17 /* Horiz start high bits */
  101. #define REG_HSTOP 0x18 /* Horiz stop high bits */
  102. #define REG_VSTART 0x19 /* Vert start high bits */
  103. #define REG_VSTOP 0x1a /* Vert stop high bits */
  104. #define REG_PSHFT 0x1b /* Pixel delay after HREF */
  105. #define REG_MIDH 0x1c /* Manuf. ID high */
  106. #define REG_MIDL 0x1d /* Manuf. ID low */
  107. #define REG_MVFP 0x1e /* Mirror / vflip */
  108. #define MVFP_MIRROR 0x20 /* Mirror image */
  109. #define MVFP_FLIP 0x10 /* Vertical flip */
  110. #define REG_AEW 0x24 /* AGC upper limit */
  111. #define REG_AEB 0x25 /* AGC lower limit */
  112. #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
  113. #define REG_HSYST 0x30 /* HSYNC rising edge delay */
  114. #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
  115. #define REG_HREF 0x32 /* HREF pieces */
  116. #define REG_TSLB 0x3a /* lots of stuff */
  117. #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
  118. #define REG_COM11 0x3b /* Control 11 */
  119. #define COM11_NIGHT 0x80 /* NIght mode enable */
  120. #define COM11_NMFR 0x60 /* Two bit NM frame rate */
  121. #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
  122. #define COM11_50HZ 0x08 /* Manual 50Hz select */
  123. #define COM11_EXP 0x02
  124. #define REG_COM12 0x3c /* Control 12 */
  125. #define COM12_HREF 0x80 /* HREF always */
  126. #define REG_COM13 0x3d /* Control 13 */
  127. #define COM13_GAMMA 0x80 /* Gamma enable */
  128. #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
  129. #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
  130. #define REG_COM14 0x3e /* Control 14 */
  131. #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
  132. #define REG_EDGE 0x3f /* Edge enhancement factor */
  133. #define REG_COM15 0x40 /* Control 15 */
  134. #define COM15_R10F0 0x00 /* Data range 10 to F0 */
  135. #define COM15_R01FE 0x80 /* 01 to FE */
  136. #define COM15_R00FF 0xc0 /* 00 to FF */
  137. #define COM15_RGB565 0x10 /* RGB565 output */
  138. #define COM15_RGB555 0x30 /* RGB555 output */
  139. #define REG_COM16 0x41 /* Control 16 */
  140. #define COM16_AWBGAIN 0x08 /* AWB gain enable */
  141. #define REG_COM17 0x42 /* Control 17 */
  142. #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
  143. #define COM17_CBAR 0x08 /* DSP Color bar */
  144. /*
  145. * This matrix defines how the colors are generated, must be
  146. * tweaked to adjust hue and saturation.
  147. *
  148. * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
  149. *
  150. * They are nine-bit signed quantities, with the sign bit
  151. * stored in 0x58. Sign for v-red is bit 0, and up from there.
  152. */
  153. #define REG_CMATRIX_BASE 0x4f
  154. #define CMATRIX_LEN 6
  155. #define REG_CMATRIX_SIGN 0x58
  156. #define REG_BRIGHT 0x55 /* Brightness */
  157. #define REG_CONTRAS 0x56 /* Contrast control */
  158. #define REG_GFIX 0x69 /* Fix gain control */
  159. #define REG_REG76 0x76 /* OV's name */
  160. #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
  161. #define R76_WHTPCOR 0x40 /* White pixel correction enable */
  162. #define REG_RGB444 0x8c /* RGB 444 control */
  163. #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
  164. #define R444_RGBX 0x01 /* Empty nibble at end */
  165. #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
  166. #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
  167. #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
  168. #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
  169. #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
  170. #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
  171. #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
  172. #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
  173. #define REG_BD60MAX 0xab /* 60hz banding step limit */
  174. /*
  175. * Information we maintain about a known sensor.
  176. */
  177. struct ov7670_format_struct; /* coming later */
  178. struct ov7670_info {
  179. struct v4l2_subdev sd;
  180. struct ov7670_format_struct *fmt; /* Current format */
  181. unsigned char sat; /* Saturation value */
  182. int hue; /* Hue value */
  183. };
  184. static inline struct ov7670_info *to_state(struct v4l2_subdev *sd)
  185. {
  186. return container_of(sd, struct ov7670_info, sd);
  187. }
  188. /*
  189. * The default register settings, as obtained from OmniVision. There
  190. * is really no making sense of most of these - lots of "reserved" values
  191. * and such.
  192. *
  193. * These settings give VGA YUYV.
  194. */
  195. struct regval_list {
  196. unsigned char reg_num;
  197. unsigned char value;
  198. };
  199. static struct regval_list ov7670_default_regs[] = {
  200. { REG_COM7, COM7_RESET },
  201. /*
  202. * Clock scale: 3 = 15fps
  203. * 2 = 20fps
  204. * 1 = 30fps
  205. */
  206. { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */
  207. { REG_TSLB, 0x04 }, /* OV */
  208. { REG_COM7, 0 }, /* VGA */
  209. /*
  210. * Set the hardware window. These values from OV don't entirely
  211. * make sense - hstop is less than hstart. But they work...
  212. */
  213. { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
  214. { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
  215. { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
  216. { REG_COM3, 0 }, { REG_COM14, 0 },
  217. /* Mystery scaling numbers */
  218. { 0x70, 0x3a }, { 0x71, 0x35 },
  219. { 0x72, 0x11 }, { 0x73, 0xf0 },
  220. { 0xa2, 0x02 }, { REG_COM10, 0x0 },
  221. /* Gamma curve values */
  222. { 0x7a, 0x20 }, { 0x7b, 0x10 },
  223. { 0x7c, 0x1e }, { 0x7d, 0x35 },
  224. { 0x7e, 0x5a }, { 0x7f, 0x69 },
  225. { 0x80, 0x76 }, { 0x81, 0x80 },
  226. { 0x82, 0x88 }, { 0x83, 0x8f },
  227. { 0x84, 0x96 }, { 0x85, 0xa3 },
  228. { 0x86, 0xaf }, { 0x87, 0xc4 },
  229. { 0x88, 0xd7 }, { 0x89, 0xe8 },
  230. /* AGC and AEC parameters. Note we start by disabling those features,
  231. then turn them only after tweaking the values. */
  232. { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT },
  233. { REG_GAIN, 0 }, { REG_AECH, 0 },
  234. { REG_COM4, 0x40 }, /* magic reserved bit */
  235. { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
  236. { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
  237. { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
  238. { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
  239. { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
  240. { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
  241. { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
  242. { REG_HAECC7, 0x94 },
  243. { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC },
  244. /* Almost all of these are magic "reserved" values. */
  245. { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
  246. { 0x16, 0x02 }, { REG_MVFP, 0x07 },
  247. { 0x21, 0x02 }, { 0x22, 0x91 },
  248. { 0x29, 0x07 }, { 0x33, 0x0b },
  249. { 0x35, 0x0b }, { 0x37, 0x1d },
  250. { 0x38, 0x71 }, { 0x39, 0x2a },
  251. { REG_COM12, 0x78 }, { 0x4d, 0x40 },
  252. { 0x4e, 0x20 }, { REG_GFIX, 0 },
  253. { 0x6b, 0x4a }, { 0x74, 0x10 },
  254. { 0x8d, 0x4f }, { 0x8e, 0 },
  255. { 0x8f, 0 }, { 0x90, 0 },
  256. { 0x91, 0 }, { 0x96, 0 },
  257. { 0x9a, 0 }, { 0xb0, 0x84 },
  258. { 0xb1, 0x0c }, { 0xb2, 0x0e },
  259. { 0xb3, 0x82 }, { 0xb8, 0x0a },
  260. /* More reserved magic, some of which tweaks white balance */
  261. { 0x43, 0x0a }, { 0x44, 0xf0 },
  262. { 0x45, 0x34 }, { 0x46, 0x58 },
  263. { 0x47, 0x28 }, { 0x48, 0x3a },
  264. { 0x59, 0x88 }, { 0x5a, 0x88 },
  265. { 0x5b, 0x44 }, { 0x5c, 0x67 },
  266. { 0x5d, 0x49 }, { 0x5e, 0x0e },
  267. { 0x6c, 0x0a }, { 0x6d, 0x55 },
  268. { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */
  269. { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
  270. { REG_RED, 0x60 },
  271. { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB },
  272. /* Matrix coefficients */
  273. { 0x4f, 0x80 }, { 0x50, 0x80 },
  274. { 0x51, 0 }, { 0x52, 0x22 },
  275. { 0x53, 0x5e }, { 0x54, 0x80 },
  276. { 0x58, 0x9e },
  277. { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
  278. { 0x75, 0x05 }, { 0x76, 0xe1 },
  279. { 0x4c, 0 }, { 0x77, 0x01 },
  280. { REG_COM13, 0xc3 }, { 0x4b, 0x09 },
  281. { 0xc9, 0x60 }, { REG_COM16, 0x38 },
  282. { 0x56, 0x40 },
  283. { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO },
  284. { 0xa4, 0x88 }, { 0x96, 0 },
  285. { 0x97, 0x30 }, { 0x98, 0x20 },
  286. { 0x99, 0x30 }, { 0x9a, 0x84 },
  287. { 0x9b, 0x29 }, { 0x9c, 0x03 },
  288. { 0x9d, 0x4c }, { 0x9e, 0x3f },
  289. { 0x78, 0x04 },
  290. /* Extra-weird stuff. Some sort of multiplexor register */
  291. { 0x79, 0x01 }, { 0xc8, 0xf0 },
  292. { 0x79, 0x0f }, { 0xc8, 0x00 },
  293. { 0x79, 0x10 }, { 0xc8, 0x7e },
  294. { 0x79, 0x0a }, { 0xc8, 0x80 },
  295. { 0x79, 0x0b }, { 0xc8, 0x01 },
  296. { 0x79, 0x0c }, { 0xc8, 0x0f },
  297. { 0x79, 0x0d }, { 0xc8, 0x20 },
  298. { 0x79, 0x09 }, { 0xc8, 0x80 },
  299. { 0x79, 0x02 }, { 0xc8, 0xc0 },
  300. { 0x79, 0x03 }, { 0xc8, 0x40 },
  301. { 0x79, 0x05 }, { 0xc8, 0x30 },
  302. { 0x79, 0x26 },
  303. { 0xff, 0xff }, /* END MARKER */
  304. };
  305. /*
  306. * Here we'll try to encapsulate the changes for just the output
  307. * video format.
  308. *
  309. * RGB656 and YUV422 come from OV; RGB444 is homebrewed.
  310. *
  311. * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why.
  312. */
  313. static struct regval_list ov7670_fmt_yuv422[] = {
  314. { REG_COM7, 0x0 }, /* Selects YUV mode */
  315. { REG_RGB444, 0 }, /* No RGB444 please */
  316. { REG_COM1, 0 },
  317. { REG_COM15, COM15_R00FF },
  318. { REG_COM9, 0x18 }, /* 4x gain ceiling; 0x8 is reserved bit */
  319. { 0x4f, 0x80 }, /* "matrix coefficient 1" */
  320. { 0x50, 0x80 }, /* "matrix coefficient 2" */
  321. { 0x51, 0 }, /* vb */
  322. { 0x52, 0x22 }, /* "matrix coefficient 4" */
  323. { 0x53, 0x5e }, /* "matrix coefficient 5" */
  324. { 0x54, 0x80 }, /* "matrix coefficient 6" */
  325. { REG_COM13, COM13_GAMMA|COM13_UVSAT },
  326. { 0xff, 0xff },
  327. };
  328. static struct regval_list ov7670_fmt_rgb565[] = {
  329. { REG_COM7, COM7_RGB }, /* Selects RGB mode */
  330. { REG_RGB444, 0 }, /* No RGB444 please */
  331. { REG_COM1, 0x0 },
  332. { REG_COM15, COM15_RGB565 },
  333. { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
  334. { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
  335. { 0x50, 0xb3 }, /* "matrix coefficient 2" */
  336. { 0x51, 0 }, /* vb */
  337. { 0x52, 0x3d }, /* "matrix coefficient 4" */
  338. { 0x53, 0xa7 }, /* "matrix coefficient 5" */
  339. { 0x54, 0xe4 }, /* "matrix coefficient 6" */
  340. { REG_COM13, COM13_GAMMA|COM13_UVSAT },
  341. { 0xff, 0xff },
  342. };
  343. static struct regval_list ov7670_fmt_rgb444[] = {
  344. { REG_COM7, COM7_RGB }, /* Selects RGB mode */
  345. { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */
  346. { REG_COM1, 0x40 }, /* Magic reserved bit */
  347. { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
  348. { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
  349. { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
  350. { 0x50, 0xb3 }, /* "matrix coefficient 2" */
  351. { 0x51, 0 }, /* vb */
  352. { 0x52, 0x3d }, /* "matrix coefficient 4" */
  353. { 0x53, 0xa7 }, /* "matrix coefficient 5" */
  354. { 0x54, 0xe4 }, /* "matrix coefficient 6" */
  355. { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */
  356. { 0xff, 0xff },
  357. };
  358. static struct regval_list ov7670_fmt_raw[] = {
  359. { REG_COM7, COM7_BAYER },
  360. { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
  361. { REG_COM16, 0x3d }, /* Edge enhancement, denoise */
  362. { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
  363. { 0xff, 0xff },
  364. };
  365. /*
  366. * Low-level register I/O.
  367. */
  368. static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
  369. unsigned char *value)
  370. {
  371. struct i2c_client *client = v4l2_get_subdevdata(sd);
  372. int ret;
  373. ret = i2c_smbus_read_byte_data(client, reg);
  374. if (ret >= 0) {
  375. *value = (unsigned char)ret;
  376. ret = 0;
  377. }
  378. return ret;
  379. }
  380. static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
  381. unsigned char value)
  382. {
  383. struct i2c_client *client = v4l2_get_subdevdata(sd);
  384. int ret = i2c_smbus_write_byte_data(client, reg, value);
  385. if (reg == REG_COM7 && (value & COM7_RESET))
  386. msleep(2); /* Wait for reset to run */
  387. return ret;
  388. }
  389. /*
  390. * Write a list of register settings; ff/ff stops the process.
  391. */
  392. static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
  393. {
  394. while (vals->reg_num != 0xff || vals->value != 0xff) {
  395. int ret = ov7670_write(sd, vals->reg_num, vals->value);
  396. if (ret < 0)
  397. return ret;
  398. vals++;
  399. }
  400. return 0;
  401. }
  402. /*
  403. * Stuff that knows about the sensor.
  404. */
  405. static int ov7670_reset(struct v4l2_subdev *sd, u32 val)
  406. {
  407. ov7670_write(sd, REG_COM7, COM7_RESET);
  408. msleep(1);
  409. return 0;
  410. }
  411. static int ov7670_init(struct v4l2_subdev *sd, u32 val)
  412. {
  413. return ov7670_write_array(sd, ov7670_default_regs);
  414. }
  415. static int ov7670_detect(struct v4l2_subdev *sd)
  416. {
  417. unsigned char v;
  418. int ret;
  419. ret = ov7670_init(sd, 0);
  420. if (ret < 0)
  421. return ret;
  422. ret = ov7670_read(sd, REG_MIDH, &v);
  423. if (ret < 0)
  424. return ret;
  425. if (v != 0x7f) /* OV manuf. id. */
  426. return -ENODEV;
  427. ret = ov7670_read(sd, REG_MIDL, &v);
  428. if (ret < 0)
  429. return ret;
  430. if (v != 0xa2)
  431. return -ENODEV;
  432. /*
  433. * OK, we know we have an OmniVision chip...but which one?
  434. */
  435. ret = ov7670_read(sd, REG_PID, &v);
  436. if (ret < 0)
  437. return ret;
  438. if (v != 0x76) /* PID + VER = 0x76 / 0x73 */
  439. return -ENODEV;
  440. ret = ov7670_read(sd, REG_VER, &v);
  441. if (ret < 0)
  442. return ret;
  443. if (v != 0x73) /* PID + VER = 0x76 / 0x73 */
  444. return -ENODEV;
  445. return 0;
  446. }
  447. /*
  448. * Store information about the video data format. The color matrix
  449. * is deeply tied into the format, so keep the relevant values here.
  450. * The magic matrix nubmers come from OmniVision.
  451. */
  452. static struct ov7670_format_struct {
  453. __u8 *desc;
  454. __u32 pixelformat;
  455. struct regval_list *regs;
  456. int cmatrix[CMATRIX_LEN];
  457. int bpp; /* Bytes per pixel */
  458. } ov7670_formats[] = {
  459. {
  460. .desc = "YUYV 4:2:2",
  461. .pixelformat = V4L2_PIX_FMT_YUYV,
  462. .regs = ov7670_fmt_yuv422,
  463. .cmatrix = { 128, -128, 0, -34, -94, 128 },
  464. .bpp = 2,
  465. },
  466. {
  467. .desc = "RGB 444",
  468. .pixelformat = V4L2_PIX_FMT_RGB444,
  469. .regs = ov7670_fmt_rgb444,
  470. .cmatrix = { 179, -179, 0, -61, -176, 228 },
  471. .bpp = 2,
  472. },
  473. {
  474. .desc = "RGB 565",
  475. .pixelformat = V4L2_PIX_FMT_RGB565,
  476. .regs = ov7670_fmt_rgb565,
  477. .cmatrix = { 179, -179, 0, -61, -176, 228 },
  478. .bpp = 2,
  479. },
  480. {
  481. .desc = "Raw RGB Bayer",
  482. .pixelformat = V4L2_PIX_FMT_SBGGR8,
  483. .regs = ov7670_fmt_raw,
  484. .cmatrix = { 0, 0, 0, 0, 0, 0 },
  485. .bpp = 1
  486. },
  487. };
  488. #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats)
  489. /*
  490. * Then there is the issue of window sizes. Try to capture the info here.
  491. */
  492. /*
  493. * QCIF mode is done (by OV) in a very strange way - it actually looks like
  494. * VGA with weird scaling options - they do *not* use the canned QCIF mode
  495. * which is allegedly provided by the sensor. So here's the weird register
  496. * settings.
  497. */
  498. static struct regval_list ov7670_qcif_regs[] = {
  499. { REG_COM3, COM3_SCALEEN|COM3_DCWEN },
  500. { REG_COM3, COM3_DCWEN },
  501. { REG_COM14, COM14_DCWEN | 0x01},
  502. { 0x73, 0xf1 },
  503. { 0xa2, 0x52 },
  504. { 0x7b, 0x1c },
  505. { 0x7c, 0x28 },
  506. { 0x7d, 0x3c },
  507. { 0x7f, 0x69 },
  508. { REG_COM9, 0x38 },
  509. { 0xa1, 0x0b },
  510. { 0x74, 0x19 },
  511. { 0x9a, 0x80 },
  512. { 0x43, 0x14 },
  513. { REG_COM13, 0xc0 },
  514. { 0xff, 0xff },
  515. };
  516. static struct ov7670_win_size {
  517. int width;
  518. int height;
  519. unsigned char com7_bit;
  520. int hstart; /* Start/stop values for the camera. Note */
  521. int hstop; /* that they do not always make complete */
  522. int vstart; /* sense to humans, but evidently the sensor */
  523. int vstop; /* will do the right thing... */
  524. struct regval_list *regs; /* Regs to tweak */
  525. /* h/vref stuff */
  526. } ov7670_win_sizes[] = {
  527. /* VGA */
  528. {
  529. .width = VGA_WIDTH,
  530. .height = VGA_HEIGHT,
  531. .com7_bit = COM7_FMT_VGA,
  532. .hstart = 158, /* These values from */
  533. .hstop = 14, /* Omnivision */
  534. .vstart = 10,
  535. .vstop = 490,
  536. .regs = NULL,
  537. },
  538. /* CIF */
  539. {
  540. .width = CIF_WIDTH,
  541. .height = CIF_HEIGHT,
  542. .com7_bit = COM7_FMT_CIF,
  543. .hstart = 170, /* Empirically determined */
  544. .hstop = 90,
  545. .vstart = 14,
  546. .vstop = 494,
  547. .regs = NULL,
  548. },
  549. /* QVGA */
  550. {
  551. .width = QVGA_WIDTH,
  552. .height = QVGA_HEIGHT,
  553. .com7_bit = COM7_FMT_QVGA,
  554. .hstart = 164, /* Empirically determined */
  555. .hstop = 20,
  556. .vstart = 14,
  557. .vstop = 494,
  558. .regs = NULL,
  559. },
  560. /* QCIF */
  561. {
  562. .width = QCIF_WIDTH,
  563. .height = QCIF_HEIGHT,
  564. .com7_bit = COM7_FMT_VGA, /* see comment above */
  565. .hstart = 456, /* Empirically determined */
  566. .hstop = 24,
  567. .vstart = 14,
  568. .vstop = 494,
  569. .regs = ov7670_qcif_regs,
  570. },
  571. };
  572. #define N_WIN_SIZES (ARRAY_SIZE(ov7670_win_sizes))
  573. /*
  574. * Store a set of start/stop values into the camera.
  575. */
  576. static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
  577. int vstart, int vstop)
  578. {
  579. int ret;
  580. unsigned char v;
  581. /*
  582. * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
  583. * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
  584. * a mystery "edge offset" value in the top two bits of href.
  585. */
  586. ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
  587. ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
  588. ret += ov7670_read(sd, REG_HREF, &v);
  589. v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
  590. msleep(10);
  591. ret += ov7670_write(sd, REG_HREF, v);
  592. /*
  593. * Vertical: similar arrangement, but only 10 bits.
  594. */
  595. ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
  596. ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
  597. ret += ov7670_read(sd, REG_VREF, &v);
  598. v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
  599. msleep(10);
  600. ret += ov7670_write(sd, REG_VREF, v);
  601. return ret;
  602. }
  603. static int ov7670_enum_fmt(struct v4l2_subdev *sd, struct v4l2_fmtdesc *fmt)
  604. {
  605. struct ov7670_format_struct *ofmt;
  606. if (fmt->index >= N_OV7670_FMTS)
  607. return -EINVAL;
  608. ofmt = ov7670_formats + fmt->index;
  609. fmt->flags = 0;
  610. strcpy(fmt->description, ofmt->desc);
  611. fmt->pixelformat = ofmt->pixelformat;
  612. return 0;
  613. }
  614. static int ov7670_try_fmt_internal(struct v4l2_subdev *sd,
  615. struct v4l2_format *fmt,
  616. struct ov7670_format_struct **ret_fmt,
  617. struct ov7670_win_size **ret_wsize)
  618. {
  619. int index;
  620. struct ov7670_win_size *wsize;
  621. struct v4l2_pix_format *pix = &fmt->fmt.pix;
  622. for (index = 0; index < N_OV7670_FMTS; index++)
  623. if (ov7670_formats[index].pixelformat == pix->pixelformat)
  624. break;
  625. if (index >= N_OV7670_FMTS) {
  626. /* default to first format */
  627. index = 0;
  628. pix->pixelformat = ov7670_formats[0].pixelformat;
  629. }
  630. if (ret_fmt != NULL)
  631. *ret_fmt = ov7670_formats + index;
  632. /*
  633. * Fields: the OV devices claim to be progressive.
  634. */
  635. pix->field = V4L2_FIELD_NONE;
  636. /*
  637. * Round requested image size down to the nearest
  638. * we support, but not below the smallest.
  639. */
  640. for (wsize = ov7670_win_sizes; wsize < ov7670_win_sizes + N_WIN_SIZES;
  641. wsize++)
  642. if (pix->width >= wsize->width && pix->height >= wsize->height)
  643. break;
  644. if (wsize >= ov7670_win_sizes + N_WIN_SIZES)
  645. wsize--; /* Take the smallest one */
  646. if (ret_wsize != NULL)
  647. *ret_wsize = wsize;
  648. /*
  649. * Note the size we'll actually handle.
  650. */
  651. pix->width = wsize->width;
  652. pix->height = wsize->height;
  653. pix->bytesperline = pix->width*ov7670_formats[index].bpp;
  654. pix->sizeimage = pix->height*pix->bytesperline;
  655. return 0;
  656. }
  657. static int ov7670_try_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
  658. {
  659. return ov7670_try_fmt_internal(sd, fmt, NULL, NULL);
  660. }
  661. /*
  662. * Set a format.
  663. */
  664. static int ov7670_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
  665. {
  666. int ret;
  667. struct ov7670_format_struct *ovfmt;
  668. struct ov7670_win_size *wsize;
  669. struct ov7670_info *info = to_state(sd);
  670. unsigned char com7, clkrc = 0;
  671. ret = ov7670_try_fmt_internal(sd, fmt, &ovfmt, &wsize);
  672. if (ret)
  673. return ret;
  674. /*
  675. * HACK: if we're running rgb565 we need to grab then rewrite
  676. * CLKRC. If we're *not*, however, then rewriting clkrc hoses
  677. * the colors.
  678. */
  679. if (fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565) {
  680. ret = ov7670_read(sd, REG_CLKRC, &clkrc);
  681. if (ret)
  682. return ret;
  683. }
  684. /*
  685. * COM7 is a pain in the ass, it doesn't like to be read then
  686. * quickly written afterward. But we have everything we need
  687. * to set it absolutely here, as long as the format-specific
  688. * register sets list it first.
  689. */
  690. com7 = ovfmt->regs[0].value;
  691. com7 |= wsize->com7_bit;
  692. ov7670_write(sd, REG_COM7, com7);
  693. /*
  694. * Now write the rest of the array. Also store start/stops
  695. */
  696. ov7670_write_array(sd, ovfmt->regs + 1);
  697. ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart,
  698. wsize->vstop);
  699. ret = 0;
  700. if (wsize->regs)
  701. ret = ov7670_write_array(sd, wsize->regs);
  702. info->fmt = ovfmt;
  703. if (fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565 && ret == 0)
  704. ret = ov7670_write(sd, REG_CLKRC, clkrc);
  705. return ret;
  706. }
  707. /*
  708. * Implement G/S_PARM. There is a "high quality" mode we could try
  709. * to do someday; for now, we just do the frame rate tweak.
  710. */
  711. static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
  712. {
  713. struct v4l2_captureparm *cp = &parms->parm.capture;
  714. unsigned char clkrc;
  715. int ret;
  716. if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
  717. return -EINVAL;
  718. ret = ov7670_read(sd, REG_CLKRC, &clkrc);
  719. if (ret < 0)
  720. return ret;
  721. memset(cp, 0, sizeof(struct v4l2_captureparm));
  722. cp->capability = V4L2_CAP_TIMEPERFRAME;
  723. cp->timeperframe.numerator = 1;
  724. cp->timeperframe.denominator = OV7670_FRAME_RATE;
  725. if ((clkrc & CLK_EXT) == 0 && (clkrc & CLK_SCALE) > 1)
  726. cp->timeperframe.denominator /= (clkrc & CLK_SCALE);
  727. return 0;
  728. }
  729. static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
  730. {
  731. struct v4l2_captureparm *cp = &parms->parm.capture;
  732. struct v4l2_fract *tpf = &cp->timeperframe;
  733. unsigned char clkrc;
  734. int ret, div;
  735. if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
  736. return -EINVAL;
  737. if (cp->extendedmode != 0)
  738. return -EINVAL;
  739. /*
  740. * CLKRC has a reserved bit, so let's preserve it.
  741. */
  742. ret = ov7670_read(sd, REG_CLKRC, &clkrc);
  743. if (ret < 0)
  744. return ret;
  745. if (tpf->numerator == 0 || tpf->denominator == 0)
  746. div = 1; /* Reset to full rate */
  747. else
  748. div = (tpf->numerator*OV7670_FRAME_RATE)/tpf->denominator;
  749. if (div == 0)
  750. div = 1;
  751. else if (div > CLK_SCALE)
  752. div = CLK_SCALE;
  753. clkrc = (clkrc & 0x80) | div;
  754. tpf->numerator = 1;
  755. tpf->denominator = OV7670_FRAME_RATE/div;
  756. return ov7670_write(sd, REG_CLKRC, clkrc);
  757. }
  758. /*
  759. * Code for dealing with controls.
  760. */
  761. static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
  762. int matrix[CMATRIX_LEN])
  763. {
  764. int i, ret;
  765. unsigned char signbits = 0;
  766. /*
  767. * Weird crap seems to exist in the upper part of
  768. * the sign bits register, so let's preserve it.
  769. */
  770. ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits);
  771. signbits &= 0xc0;
  772. for (i = 0; i < CMATRIX_LEN; i++) {
  773. unsigned char raw;
  774. if (matrix[i] < 0) {
  775. signbits |= (1 << i);
  776. if (matrix[i] < -255)
  777. raw = 0xff;
  778. else
  779. raw = (-1 * matrix[i]) & 0xff;
  780. }
  781. else {
  782. if (matrix[i] > 255)
  783. raw = 0xff;
  784. else
  785. raw = matrix[i] & 0xff;
  786. }
  787. ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
  788. }
  789. ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
  790. return ret;
  791. }
  792. /*
  793. * Hue also requires messing with the color matrix. It also requires
  794. * trig functions, which tend not to be well supported in the kernel.
  795. * So here is a simple table of sine values, 0-90 degrees, in steps
  796. * of five degrees. Values are multiplied by 1000.
  797. *
  798. * The following naive approximate trig functions require an argument
  799. * carefully limited to -180 <= theta <= 180.
  800. */
  801. #define SIN_STEP 5
  802. static const int ov7670_sin_table[] = {
  803. 0, 87, 173, 258, 342, 422,
  804. 499, 573, 642, 707, 766, 819,
  805. 866, 906, 939, 965, 984, 996,
  806. 1000
  807. };
  808. static int ov7670_sine(int theta)
  809. {
  810. int chs = 1;
  811. int sine;
  812. if (theta < 0) {
  813. theta = -theta;
  814. chs = -1;
  815. }
  816. if (theta <= 90)
  817. sine = ov7670_sin_table[theta/SIN_STEP];
  818. else {
  819. theta -= 90;
  820. sine = 1000 - ov7670_sin_table[theta/SIN_STEP];
  821. }
  822. return sine*chs;
  823. }
  824. static int ov7670_cosine(int theta)
  825. {
  826. theta = 90 - theta;
  827. if (theta > 180)
  828. theta -= 360;
  829. else if (theta < -180)
  830. theta += 360;
  831. return ov7670_sine(theta);
  832. }
  833. static void ov7670_calc_cmatrix(struct ov7670_info *info,
  834. int matrix[CMATRIX_LEN])
  835. {
  836. int i;
  837. /*
  838. * Apply the current saturation setting first.
  839. */
  840. for (i = 0; i < CMATRIX_LEN; i++)
  841. matrix[i] = (info->fmt->cmatrix[i]*info->sat) >> 7;
  842. /*
  843. * Then, if need be, rotate the hue value.
  844. */
  845. if (info->hue != 0) {
  846. int sinth, costh, tmpmatrix[CMATRIX_LEN];
  847. memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int));
  848. sinth = ov7670_sine(info->hue);
  849. costh = ov7670_cosine(info->hue);
  850. matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000;
  851. matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000;
  852. matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000;
  853. matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000;
  854. matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000;
  855. matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000;
  856. }
  857. }
  858. static int ov7670_s_sat(struct v4l2_subdev *sd, int value)
  859. {
  860. struct ov7670_info *info = to_state(sd);
  861. int matrix[CMATRIX_LEN];
  862. int ret;
  863. info->sat = value;
  864. ov7670_calc_cmatrix(info, matrix);
  865. ret = ov7670_store_cmatrix(sd, matrix);
  866. return ret;
  867. }
  868. static int ov7670_g_sat(struct v4l2_subdev *sd, __s32 *value)
  869. {
  870. struct ov7670_info *info = to_state(sd);
  871. *value = info->sat;
  872. return 0;
  873. }
  874. static int ov7670_s_hue(struct v4l2_subdev *sd, int value)
  875. {
  876. struct ov7670_info *info = to_state(sd);
  877. int matrix[CMATRIX_LEN];
  878. int ret;
  879. if (value < -180 || value > 180)
  880. return -EINVAL;
  881. info->hue = value;
  882. ov7670_calc_cmatrix(info, matrix);
  883. ret = ov7670_store_cmatrix(sd, matrix);
  884. return ret;
  885. }
  886. static int ov7670_g_hue(struct v4l2_subdev *sd, __s32 *value)
  887. {
  888. struct ov7670_info *info = to_state(sd);
  889. *value = info->hue;
  890. return 0;
  891. }
  892. /*
  893. * Some weird registers seem to store values in a sign/magnitude format!
  894. */
  895. static unsigned char ov7670_sm_to_abs(unsigned char v)
  896. {
  897. if ((v & 0x80) == 0)
  898. return v + 128;
  899. return 128 - (v & 0x7f);
  900. }
  901. static unsigned char ov7670_abs_to_sm(unsigned char v)
  902. {
  903. if (v > 127)
  904. return v & 0x7f;
  905. return (128 - v) | 0x80;
  906. }
  907. static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
  908. {
  909. unsigned char com8 = 0, v;
  910. int ret;
  911. ov7670_read(sd, REG_COM8, &com8);
  912. com8 &= ~COM8_AEC;
  913. ov7670_write(sd, REG_COM8, com8);
  914. v = ov7670_abs_to_sm(value);
  915. ret = ov7670_write(sd, REG_BRIGHT, v);
  916. return ret;
  917. }
  918. static int ov7670_g_brightness(struct v4l2_subdev *sd, __s32 *value)
  919. {
  920. unsigned char v = 0;
  921. int ret = ov7670_read(sd, REG_BRIGHT, &v);
  922. *value = ov7670_sm_to_abs(v);
  923. return ret;
  924. }
  925. static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
  926. {
  927. return ov7670_write(sd, REG_CONTRAS, (unsigned char) value);
  928. }
  929. static int ov7670_g_contrast(struct v4l2_subdev *sd, __s32 *value)
  930. {
  931. unsigned char v = 0;
  932. int ret = ov7670_read(sd, REG_CONTRAS, &v);
  933. *value = v;
  934. return ret;
  935. }
  936. static int ov7670_g_hflip(struct v4l2_subdev *sd, __s32 *value)
  937. {
  938. int ret;
  939. unsigned char v = 0;
  940. ret = ov7670_read(sd, REG_MVFP, &v);
  941. *value = (v & MVFP_MIRROR) == MVFP_MIRROR;
  942. return ret;
  943. }
  944. static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
  945. {
  946. unsigned char v = 0;
  947. int ret;
  948. ret = ov7670_read(sd, REG_MVFP, &v);
  949. if (value)
  950. v |= MVFP_MIRROR;
  951. else
  952. v &= ~MVFP_MIRROR;
  953. msleep(10); /* FIXME */
  954. ret += ov7670_write(sd, REG_MVFP, v);
  955. return ret;
  956. }
  957. static int ov7670_g_vflip(struct v4l2_subdev *sd, __s32 *value)
  958. {
  959. int ret;
  960. unsigned char v = 0;
  961. ret = ov7670_read(sd, REG_MVFP, &v);
  962. *value = (v & MVFP_FLIP) == MVFP_FLIP;
  963. return ret;
  964. }
  965. static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
  966. {
  967. unsigned char v = 0;
  968. int ret;
  969. ret = ov7670_read(sd, REG_MVFP, &v);
  970. if (value)
  971. v |= MVFP_FLIP;
  972. else
  973. v &= ~MVFP_FLIP;
  974. msleep(10); /* FIXME */
  975. ret += ov7670_write(sd, REG_MVFP, v);
  976. return ret;
  977. }
  978. static int ov7670_queryctrl(struct v4l2_subdev *sd,
  979. struct v4l2_queryctrl *qc)
  980. {
  981. /* Fill in min, max, step and default value for these controls. */
  982. switch (qc->id) {
  983. case V4L2_CID_BRIGHTNESS:
  984. return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
  985. case V4L2_CID_CONTRAST:
  986. return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64);
  987. case V4L2_CID_VFLIP:
  988. case V4L2_CID_HFLIP:
  989. return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
  990. case V4L2_CID_SATURATION:
  991. return v4l2_ctrl_query_fill(qc, 0, 256, 1, 128);
  992. case V4L2_CID_HUE:
  993. return v4l2_ctrl_query_fill(qc, -180, 180, 5, 0);
  994. }
  995. return -EINVAL;
  996. }
  997. static int ov7670_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
  998. {
  999. switch (ctrl->id) {
  1000. case V4L2_CID_BRIGHTNESS:
  1001. return ov7670_g_brightness(sd, &ctrl->value);
  1002. case V4L2_CID_CONTRAST:
  1003. return ov7670_g_contrast(sd, &ctrl->value);
  1004. case V4L2_CID_SATURATION:
  1005. return ov7670_g_sat(sd, &ctrl->value);
  1006. case V4L2_CID_HUE:
  1007. return ov7670_g_hue(sd, &ctrl->value);
  1008. case V4L2_CID_VFLIP:
  1009. return ov7670_g_vflip(sd, &ctrl->value);
  1010. case V4L2_CID_HFLIP:
  1011. return ov7670_g_hflip(sd, &ctrl->value);
  1012. }
  1013. return -EINVAL;
  1014. }
  1015. static int ov7670_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
  1016. {
  1017. switch (ctrl->id) {
  1018. case V4L2_CID_BRIGHTNESS:
  1019. return ov7670_s_brightness(sd, ctrl->value);
  1020. case V4L2_CID_CONTRAST:
  1021. return ov7670_s_contrast(sd, ctrl->value);
  1022. case V4L2_CID_SATURATION:
  1023. return ov7670_s_sat(sd, ctrl->value);
  1024. case V4L2_CID_HUE:
  1025. return ov7670_s_hue(sd, ctrl->value);
  1026. case V4L2_CID_VFLIP:
  1027. return ov7670_s_vflip(sd, ctrl->value);
  1028. case V4L2_CID_HFLIP:
  1029. return ov7670_s_hflip(sd, ctrl->value);
  1030. }
  1031. return -EINVAL;
  1032. }
  1033. static int ov7670_g_chip_ident(struct v4l2_subdev *sd,
  1034. struct v4l2_dbg_chip_ident *chip)
  1035. {
  1036. struct i2c_client *client = v4l2_get_subdevdata(sd);
  1037. return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_OV7670, 0);
  1038. }
  1039. #ifdef CONFIG_VIDEO_ADV_DEBUG
  1040. static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
  1041. {
  1042. struct i2c_client *client = v4l2_get_subdevdata(sd);
  1043. unsigned char val = 0;
  1044. int ret;
  1045. if (!v4l2_chip_match_i2c_client(client, &reg->match))
  1046. return -EINVAL;
  1047. if (!capable(CAP_SYS_ADMIN))
  1048. return -EPERM;
  1049. ret = ov7670_read(sd, reg->reg & 0xff, &val);
  1050. reg->val = val;
  1051. reg->size = 1;
  1052. return ret;
  1053. }
  1054. static int ov7670_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
  1055. {
  1056. struct i2c_client *client = v4l2_get_subdevdata(sd);
  1057. if (!v4l2_chip_match_i2c_client(client, &reg->match))
  1058. return -EINVAL;
  1059. if (!capable(CAP_SYS_ADMIN))
  1060. return -EPERM;
  1061. ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff);
  1062. return 0;
  1063. }
  1064. #endif
  1065. /* ----------------------------------------------------------------------- */
  1066. static const struct v4l2_subdev_core_ops ov7670_core_ops = {
  1067. .g_chip_ident = ov7670_g_chip_ident,
  1068. .g_ctrl = ov7670_g_ctrl,
  1069. .s_ctrl = ov7670_s_ctrl,
  1070. .queryctrl = ov7670_queryctrl,
  1071. .reset = ov7670_reset,
  1072. .init = ov7670_init,
  1073. #ifdef CONFIG_VIDEO_ADV_DEBUG
  1074. .g_register = ov7670_g_register,
  1075. .s_register = ov7670_s_register,
  1076. #endif
  1077. };
  1078. static const struct v4l2_subdev_video_ops ov7670_video_ops = {
  1079. .enum_fmt = ov7670_enum_fmt,
  1080. .try_fmt = ov7670_try_fmt,
  1081. .s_fmt = ov7670_s_fmt,
  1082. .s_parm = ov7670_s_parm,
  1083. .g_parm = ov7670_g_parm,
  1084. };
  1085. static const struct v4l2_subdev_ops ov7670_ops = {
  1086. .core = &ov7670_core_ops,
  1087. .video = &ov7670_video_ops,
  1088. };
  1089. /* ----------------------------------------------------------------------- */
  1090. static int ov7670_probe(struct i2c_client *client,
  1091. const struct i2c_device_id *id)
  1092. {
  1093. struct v4l2_subdev *sd;
  1094. struct ov7670_info *info;
  1095. int ret;
  1096. info = kzalloc(sizeof(struct ov7670_info), GFP_KERNEL);
  1097. if (info == NULL)
  1098. return -ENOMEM;
  1099. sd = &info->sd;
  1100. v4l2_i2c_subdev_init(sd, client, &ov7670_ops);
  1101. /* Make sure it's an ov7670 */
  1102. ret = ov7670_detect(sd);
  1103. if (ret) {
  1104. v4l_dbg(1, debug, client,
  1105. "chip found @ 0x%x (%s) is not an ov7670 chip.\n",
  1106. client->addr << 1, client->adapter->name);
  1107. kfree(info);
  1108. return ret;
  1109. }
  1110. v4l_info(client, "chip found @ 0x%02x (%s)\n",
  1111. client->addr << 1, client->adapter->name);
  1112. info->fmt = &ov7670_formats[0];
  1113. info->sat = 128; /* Review this */
  1114. return 0;
  1115. }
  1116. static int ov7670_remove(struct i2c_client *client)
  1117. {
  1118. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1119. v4l2_device_unregister_subdev(sd);
  1120. kfree(to_state(sd));
  1121. return 0;
  1122. }
  1123. static const struct i2c_device_id ov7670_id[] = {
  1124. { "ov7670", 0 },
  1125. { }
  1126. };
  1127. MODULE_DEVICE_TABLE(i2c, ov7670_id);
  1128. static struct v4l2_i2c_driver_data v4l2_i2c_data = {
  1129. .name = "ov7670",
  1130. .probe = ov7670_probe,
  1131. .remove = ov7670_remove,
  1132. .id_table = ov7670_id,
  1133. };