stv090x.c 124 KB

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  1. /*
  2. STV0900/0903 Multistandard Broadcast Frontend driver
  3. Copyright (C) Manu Abraham <abraham.manu@gmail.com>
  4. Copyright (C) ST Microelectronics
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. */
  17. #include <linux/init.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/string.h>
  21. #include <linux/slab.h>
  22. #include <linux/mutex.h>
  23. #include <linux/dvb/frontend.h>
  24. #include "dvb_frontend.h"
  25. #include "stv6110x.h" /* for demodulator internal modes */
  26. #include "stv090x_reg.h"
  27. #include "stv090x.h"
  28. #include "stv090x_priv.h"
  29. static unsigned int verbose;
  30. module_param(verbose, int, 0644);
  31. /* internal params node */
  32. struct stv090x_dev {
  33. /* pointer for internal params, one for each pair of demods */
  34. struct stv090x_internal *internal;
  35. struct stv090x_dev *next_dev;
  36. };
  37. /* first internal params */
  38. static struct stv090x_dev *stv090x_first_dev;
  39. /* find chip by i2c adapter and i2c address */
  40. static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap,
  41. u8 i2c_addr)
  42. {
  43. struct stv090x_dev *temp_dev = stv090x_first_dev;
  44. /*
  45. Search of the last stv0900 chip or
  46. find it by i2c adapter and i2c address */
  47. while ((temp_dev != NULL) &&
  48. ((temp_dev->internal->i2c_adap != i2c_adap) ||
  49. (temp_dev->internal->i2c_addr != i2c_addr))) {
  50. temp_dev = temp_dev->next_dev;
  51. }
  52. return temp_dev;
  53. }
  54. /* deallocating chip */
  55. static void remove_dev(struct stv090x_internal *internal)
  56. {
  57. struct stv090x_dev *prev_dev = stv090x_first_dev;
  58. struct stv090x_dev *del_dev = find_dev(internal->i2c_adap,
  59. internal->i2c_addr);
  60. if (del_dev != NULL) {
  61. if (del_dev == stv090x_first_dev) {
  62. stv090x_first_dev = del_dev->next_dev;
  63. } else {
  64. while (prev_dev->next_dev != del_dev)
  65. prev_dev = prev_dev->next_dev;
  66. prev_dev->next_dev = del_dev->next_dev;
  67. }
  68. kfree(del_dev);
  69. }
  70. }
  71. /* allocating new chip */
  72. static struct stv090x_dev *append_internal(struct stv090x_internal *internal)
  73. {
  74. struct stv090x_dev *new_dev;
  75. struct stv090x_dev *temp_dev;
  76. new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL);
  77. if (new_dev != NULL) {
  78. new_dev->internal = internal;
  79. new_dev->next_dev = NULL;
  80. /* append to list */
  81. if (stv090x_first_dev == NULL) {
  82. stv090x_first_dev = new_dev;
  83. } else {
  84. temp_dev = stv090x_first_dev;
  85. while (temp_dev->next_dev != NULL)
  86. temp_dev = temp_dev->next_dev;
  87. temp_dev->next_dev = new_dev;
  88. }
  89. }
  90. return new_dev;
  91. }
  92. /* DVBS1 and DSS C/N Lookup table */
  93. static const struct stv090x_tab stv090x_s1cn_tab[] = {
  94. { 0, 8917 }, /* 0.0dB */
  95. { 5, 8801 }, /* 0.5dB */
  96. { 10, 8667 }, /* 1.0dB */
  97. { 15, 8522 }, /* 1.5dB */
  98. { 20, 8355 }, /* 2.0dB */
  99. { 25, 8175 }, /* 2.5dB */
  100. { 30, 7979 }, /* 3.0dB */
  101. { 35, 7763 }, /* 3.5dB */
  102. { 40, 7530 }, /* 4.0dB */
  103. { 45, 7282 }, /* 4.5dB */
  104. { 50, 7026 }, /* 5.0dB */
  105. { 55, 6781 }, /* 5.5dB */
  106. { 60, 6514 }, /* 6.0dB */
  107. { 65, 6241 }, /* 6.5dB */
  108. { 70, 5965 }, /* 7.0dB */
  109. { 75, 5690 }, /* 7.5dB */
  110. { 80, 5424 }, /* 8.0dB */
  111. { 85, 5161 }, /* 8.5dB */
  112. { 90, 4902 }, /* 9.0dB */
  113. { 95, 4654 }, /* 9.5dB */
  114. { 100, 4417 }, /* 10.0dB */
  115. { 105, 4186 }, /* 10.5dB */
  116. { 110, 3968 }, /* 11.0dB */
  117. { 115, 3757 }, /* 11.5dB */
  118. { 120, 3558 }, /* 12.0dB */
  119. { 125, 3366 }, /* 12.5dB */
  120. { 130, 3185 }, /* 13.0dB */
  121. { 135, 3012 }, /* 13.5dB */
  122. { 140, 2850 }, /* 14.0dB */
  123. { 145, 2698 }, /* 14.5dB */
  124. { 150, 2550 }, /* 15.0dB */
  125. { 160, 2283 }, /* 16.0dB */
  126. { 170, 2042 }, /* 17.0dB */
  127. { 180, 1827 }, /* 18.0dB */
  128. { 190, 1636 }, /* 19.0dB */
  129. { 200, 1466 }, /* 20.0dB */
  130. { 210, 1315 }, /* 21.0dB */
  131. { 220, 1181 }, /* 22.0dB */
  132. { 230, 1064 }, /* 23.0dB */
  133. { 240, 960 }, /* 24.0dB */
  134. { 250, 869 }, /* 25.0dB */
  135. { 260, 792 }, /* 26.0dB */
  136. { 270, 724 }, /* 27.0dB */
  137. { 280, 665 }, /* 28.0dB */
  138. { 290, 616 }, /* 29.0dB */
  139. { 300, 573 }, /* 30.0dB */
  140. { 310, 537 }, /* 31.0dB */
  141. { 320, 507 }, /* 32.0dB */
  142. { 330, 483 }, /* 33.0dB */
  143. { 400, 398 }, /* 40.0dB */
  144. { 450, 381 }, /* 45.0dB */
  145. { 500, 377 } /* 50.0dB */
  146. };
  147. /* DVBS2 C/N Lookup table */
  148. static const struct stv090x_tab stv090x_s2cn_tab[] = {
  149. { -30, 13348 }, /* -3.0dB */
  150. { -20, 12640 }, /* -2d.0B */
  151. { -10, 11883 }, /* -1.0dB */
  152. { 0, 11101 }, /* -0.0dB */
  153. { 5, 10718 }, /* 0.5dB */
  154. { 10, 10339 }, /* 1.0dB */
  155. { 15, 9947 }, /* 1.5dB */
  156. { 20, 9552 }, /* 2.0dB */
  157. { 25, 9183 }, /* 2.5dB */
  158. { 30, 8799 }, /* 3.0dB */
  159. { 35, 8422 }, /* 3.5dB */
  160. { 40, 8062 }, /* 4.0dB */
  161. { 45, 7707 }, /* 4.5dB */
  162. { 50, 7353 }, /* 5.0dB */
  163. { 55, 7025 }, /* 5.5dB */
  164. { 60, 6684 }, /* 6.0dB */
  165. { 65, 6331 }, /* 6.5dB */
  166. { 70, 6036 }, /* 7.0dB */
  167. { 75, 5727 }, /* 7.5dB */
  168. { 80, 5437 }, /* 8.0dB */
  169. { 85, 5164 }, /* 8.5dB */
  170. { 90, 4902 }, /* 9.0dB */
  171. { 95, 4653 }, /* 9.5dB */
  172. { 100, 4408 }, /* 10.0dB */
  173. { 105, 4187 }, /* 10.5dB */
  174. { 110, 3961 }, /* 11.0dB */
  175. { 115, 3751 }, /* 11.5dB */
  176. { 120, 3558 }, /* 12.0dB */
  177. { 125, 3368 }, /* 12.5dB */
  178. { 130, 3191 }, /* 13.0dB */
  179. { 135, 3017 }, /* 13.5dB */
  180. { 140, 2862 }, /* 14.0dB */
  181. { 145, 2710 }, /* 14.5dB */
  182. { 150, 2565 }, /* 15.0dB */
  183. { 160, 2300 }, /* 16.0dB */
  184. { 170, 2058 }, /* 17.0dB */
  185. { 180, 1849 }, /* 18.0dB */
  186. { 190, 1663 }, /* 19.0dB */
  187. { 200, 1495 }, /* 20.0dB */
  188. { 210, 1349 }, /* 21.0dB */
  189. { 220, 1222 }, /* 22.0dB */
  190. { 230, 1110 }, /* 23.0dB */
  191. { 240, 1011 }, /* 24.0dB */
  192. { 250, 925 }, /* 25.0dB */
  193. { 260, 853 }, /* 26.0dB */
  194. { 270, 789 }, /* 27.0dB */
  195. { 280, 734 }, /* 28.0dB */
  196. { 290, 690 }, /* 29.0dB */
  197. { 300, 650 }, /* 30.0dB */
  198. { 310, 619 }, /* 31.0dB */
  199. { 320, 593 }, /* 32.0dB */
  200. { 330, 571 }, /* 33.0dB */
  201. { 400, 498 }, /* 40.0dB */
  202. { 450, 484 }, /* 45.0dB */
  203. { 500, 481 } /* 50.0dB */
  204. };
  205. /* RF level C/N lookup table */
  206. static const struct stv090x_tab stv090x_rf_tab[] = {
  207. { -5, 0xcaa1 }, /* -5dBm */
  208. { -10, 0xc229 }, /* -10dBm */
  209. { -15, 0xbb08 }, /* -15dBm */
  210. { -20, 0xb4bc }, /* -20dBm */
  211. { -25, 0xad5a }, /* -25dBm */
  212. { -30, 0xa298 }, /* -30dBm */
  213. { -35, 0x98a8 }, /* -35dBm */
  214. { -40, 0x8389 }, /* -40dBm */
  215. { -45, 0x59be }, /* -45dBm */
  216. { -50, 0x3a14 }, /* -50dBm */
  217. { -55, 0x2d11 }, /* -55dBm */
  218. { -60, 0x210d }, /* -60dBm */
  219. { -65, 0xa14f }, /* -65dBm */
  220. { -70, 0x07aa } /* -70dBm */
  221. };
  222. static struct stv090x_reg stv0900_initval[] = {
  223. { STV090x_OUTCFG, 0x00 },
  224. { STV090x_MODECFG, 0xff },
  225. { STV090x_AGCRF1CFG, 0x11 },
  226. { STV090x_AGCRF2CFG, 0x13 },
  227. { STV090x_TSGENERAL1X, 0x14 },
  228. { STV090x_TSTTNR2, 0x21 },
  229. { STV090x_TSTTNR4, 0x21 },
  230. { STV090x_P2_DISTXCTL, 0x22 },
  231. { STV090x_P2_F22TX, 0xc0 },
  232. { STV090x_P2_F22RX, 0xc0 },
  233. { STV090x_P2_DISRXCTL, 0x00 },
  234. { STV090x_P2_DMDCFGMD, 0xF9 },
  235. { STV090x_P2_DEMOD, 0x08 },
  236. { STV090x_P2_DMDCFG3, 0xc4 },
  237. { STV090x_P2_CARFREQ, 0xed },
  238. { STV090x_P2_LDT, 0xd0 },
  239. { STV090x_P2_LDT2, 0xb8 },
  240. { STV090x_P2_TMGCFG, 0xd2 },
  241. { STV090x_P2_TMGTHRISE, 0x20 },
  242. { STV090x_P1_TMGCFG, 0xd2 },
  243. { STV090x_P2_TMGTHFALL, 0x00 },
  244. { STV090x_P2_FECSPY, 0x88 },
  245. { STV090x_P2_FSPYDATA, 0x3a },
  246. { STV090x_P2_FBERCPT4, 0x00 },
  247. { STV090x_P2_FSPYBER, 0x10 },
  248. { STV090x_P2_ERRCTRL1, 0x35 },
  249. { STV090x_P2_ERRCTRL2, 0xc1 },
  250. { STV090x_P2_CFRICFG, 0xf8 },
  251. { STV090x_P2_NOSCFG, 0x1c },
  252. { STV090x_P2_DMDTOM, 0x20 },
  253. { STV090x_P2_CORRELMANT, 0x70 },
  254. { STV090x_P2_CORRELABS, 0x88 },
  255. { STV090x_P2_AGC2O, 0x5b },
  256. { STV090x_P2_AGC2REF, 0x38 },
  257. { STV090x_P2_CARCFG, 0xe4 },
  258. { STV090x_P2_ACLC, 0x1A },
  259. { STV090x_P2_BCLC, 0x09 },
  260. { STV090x_P2_CARHDR, 0x08 },
  261. { STV090x_P2_KREFTMG, 0xc1 },
  262. { STV090x_P2_SFRUPRATIO, 0xf0 },
  263. { STV090x_P2_SFRLOWRATIO, 0x70 },
  264. { STV090x_P2_SFRSTEP, 0x58 },
  265. { STV090x_P2_TMGCFG2, 0x01 },
  266. { STV090x_P2_CAR2CFG, 0x26 },
  267. { STV090x_P2_BCLC2S2Q, 0x86 },
  268. { STV090x_P2_BCLC2S28, 0x86 },
  269. { STV090x_P2_SMAPCOEF7, 0x77 },
  270. { STV090x_P2_SMAPCOEF6, 0x85 },
  271. { STV090x_P2_SMAPCOEF5, 0x77 },
  272. { STV090x_P2_TSCFGL, 0x20 },
  273. { STV090x_P2_DMDCFG2, 0x3b },
  274. { STV090x_P2_MODCODLST0, 0xff },
  275. { STV090x_P2_MODCODLST1, 0xff },
  276. { STV090x_P2_MODCODLST2, 0xff },
  277. { STV090x_P2_MODCODLST3, 0xff },
  278. { STV090x_P2_MODCODLST4, 0xff },
  279. { STV090x_P2_MODCODLST5, 0xff },
  280. { STV090x_P2_MODCODLST6, 0xff },
  281. { STV090x_P2_MODCODLST7, 0xcc },
  282. { STV090x_P2_MODCODLST8, 0xcc },
  283. { STV090x_P2_MODCODLST9, 0xcc },
  284. { STV090x_P2_MODCODLSTA, 0xcc },
  285. { STV090x_P2_MODCODLSTB, 0xcc },
  286. { STV090x_P2_MODCODLSTC, 0xcc },
  287. { STV090x_P2_MODCODLSTD, 0xcc },
  288. { STV090x_P2_MODCODLSTE, 0xcc },
  289. { STV090x_P2_MODCODLSTF, 0xcf },
  290. { STV090x_P1_DISTXCTL, 0x22 },
  291. { STV090x_P1_F22TX, 0xc0 },
  292. { STV090x_P1_F22RX, 0xc0 },
  293. { STV090x_P1_DISRXCTL, 0x00 },
  294. { STV090x_P1_DMDCFGMD, 0xf9 },
  295. { STV090x_P1_DEMOD, 0x08 },
  296. { STV090x_P1_DMDCFG3, 0xc4 },
  297. { STV090x_P1_DMDTOM, 0x20 },
  298. { STV090x_P1_CARFREQ, 0xed },
  299. { STV090x_P1_LDT, 0xd0 },
  300. { STV090x_P1_LDT2, 0xb8 },
  301. { STV090x_P1_TMGCFG, 0xd2 },
  302. { STV090x_P1_TMGTHRISE, 0x20 },
  303. { STV090x_P1_TMGTHFALL, 0x00 },
  304. { STV090x_P1_SFRUPRATIO, 0xf0 },
  305. { STV090x_P1_SFRLOWRATIO, 0x70 },
  306. { STV090x_P1_TSCFGL, 0x20 },
  307. { STV090x_P1_FECSPY, 0x88 },
  308. { STV090x_P1_FSPYDATA, 0x3a },
  309. { STV090x_P1_FBERCPT4, 0x00 },
  310. { STV090x_P1_FSPYBER, 0x10 },
  311. { STV090x_P1_ERRCTRL1, 0x35 },
  312. { STV090x_P1_ERRCTRL2, 0xc1 },
  313. { STV090x_P1_CFRICFG, 0xf8 },
  314. { STV090x_P1_NOSCFG, 0x1c },
  315. { STV090x_P1_CORRELMANT, 0x70 },
  316. { STV090x_P1_CORRELABS, 0x88 },
  317. { STV090x_P1_AGC2O, 0x5b },
  318. { STV090x_P1_AGC2REF, 0x38 },
  319. { STV090x_P1_CARCFG, 0xe4 },
  320. { STV090x_P1_ACLC, 0x1A },
  321. { STV090x_P1_BCLC, 0x09 },
  322. { STV090x_P1_CARHDR, 0x08 },
  323. { STV090x_P1_KREFTMG, 0xc1 },
  324. { STV090x_P1_SFRSTEP, 0x58 },
  325. { STV090x_P1_TMGCFG2, 0x01 },
  326. { STV090x_P1_CAR2CFG, 0x26 },
  327. { STV090x_P1_BCLC2S2Q, 0x86 },
  328. { STV090x_P1_BCLC2S28, 0x86 },
  329. { STV090x_P1_SMAPCOEF7, 0x77 },
  330. { STV090x_P1_SMAPCOEF6, 0x85 },
  331. { STV090x_P1_SMAPCOEF5, 0x77 },
  332. { STV090x_P1_DMDCFG2, 0x3b },
  333. { STV090x_P1_MODCODLST0, 0xff },
  334. { STV090x_P1_MODCODLST1, 0xff },
  335. { STV090x_P1_MODCODLST2, 0xff },
  336. { STV090x_P1_MODCODLST3, 0xff },
  337. { STV090x_P1_MODCODLST4, 0xff },
  338. { STV090x_P1_MODCODLST5, 0xff },
  339. { STV090x_P1_MODCODLST6, 0xff },
  340. { STV090x_P1_MODCODLST7, 0xcc },
  341. { STV090x_P1_MODCODLST8, 0xcc },
  342. { STV090x_P1_MODCODLST9, 0xcc },
  343. { STV090x_P1_MODCODLSTA, 0xcc },
  344. { STV090x_P1_MODCODLSTB, 0xcc },
  345. { STV090x_P1_MODCODLSTC, 0xcc },
  346. { STV090x_P1_MODCODLSTD, 0xcc },
  347. { STV090x_P1_MODCODLSTE, 0xcc },
  348. { STV090x_P1_MODCODLSTF, 0xcf },
  349. { STV090x_GENCFG, 0x1d },
  350. { STV090x_NBITER_NF4, 0x37 },
  351. { STV090x_NBITER_NF5, 0x29 },
  352. { STV090x_NBITER_NF6, 0x37 },
  353. { STV090x_NBITER_NF7, 0x33 },
  354. { STV090x_NBITER_NF8, 0x31 },
  355. { STV090x_NBITER_NF9, 0x2f },
  356. { STV090x_NBITER_NF10, 0x39 },
  357. { STV090x_NBITER_NF11, 0x3a },
  358. { STV090x_NBITER_NF12, 0x29 },
  359. { STV090x_NBITER_NF13, 0x37 },
  360. { STV090x_NBITER_NF14, 0x33 },
  361. { STV090x_NBITER_NF15, 0x2f },
  362. { STV090x_NBITER_NF16, 0x39 },
  363. { STV090x_NBITER_NF17, 0x3a },
  364. { STV090x_NBITERNOERR, 0x04 },
  365. { STV090x_GAINLLR_NF4, 0x0C },
  366. { STV090x_GAINLLR_NF5, 0x0F },
  367. { STV090x_GAINLLR_NF6, 0x11 },
  368. { STV090x_GAINLLR_NF7, 0x14 },
  369. { STV090x_GAINLLR_NF8, 0x17 },
  370. { STV090x_GAINLLR_NF9, 0x19 },
  371. { STV090x_GAINLLR_NF10, 0x20 },
  372. { STV090x_GAINLLR_NF11, 0x21 },
  373. { STV090x_GAINLLR_NF12, 0x0D },
  374. { STV090x_GAINLLR_NF13, 0x0F },
  375. { STV090x_GAINLLR_NF14, 0x13 },
  376. { STV090x_GAINLLR_NF15, 0x1A },
  377. { STV090x_GAINLLR_NF16, 0x1F },
  378. { STV090x_GAINLLR_NF17, 0x21 },
  379. { STV090x_RCCFGH, 0x20 },
  380. { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
  381. { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
  382. { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
  383. { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
  384. };
  385. static struct stv090x_reg stv0903_initval[] = {
  386. { STV090x_OUTCFG, 0x00 },
  387. { STV090x_AGCRF1CFG, 0x11 },
  388. { STV090x_STOPCLK1, 0x48 },
  389. { STV090x_STOPCLK2, 0x14 },
  390. { STV090x_TSTTNR1, 0x27 },
  391. { STV090x_TSTTNR2, 0x21 },
  392. { STV090x_P1_DISTXCTL, 0x22 },
  393. { STV090x_P1_F22TX, 0xc0 },
  394. { STV090x_P1_F22RX, 0xc0 },
  395. { STV090x_P1_DISRXCTL, 0x00 },
  396. { STV090x_P1_DMDCFGMD, 0xF9 },
  397. { STV090x_P1_DEMOD, 0x08 },
  398. { STV090x_P1_DMDCFG3, 0xc4 },
  399. { STV090x_P1_CARFREQ, 0xed },
  400. { STV090x_P1_TNRCFG2, 0x82 },
  401. { STV090x_P1_LDT, 0xd0 },
  402. { STV090x_P1_LDT2, 0xb8 },
  403. { STV090x_P1_TMGCFG, 0xd2 },
  404. { STV090x_P1_TMGTHRISE, 0x20 },
  405. { STV090x_P1_TMGTHFALL, 0x00 },
  406. { STV090x_P1_SFRUPRATIO, 0xf0 },
  407. { STV090x_P1_SFRLOWRATIO, 0x70 },
  408. { STV090x_P1_TSCFGL, 0x20 },
  409. { STV090x_P1_FECSPY, 0x88 },
  410. { STV090x_P1_FSPYDATA, 0x3a },
  411. { STV090x_P1_FBERCPT4, 0x00 },
  412. { STV090x_P1_FSPYBER, 0x10 },
  413. { STV090x_P1_ERRCTRL1, 0x35 },
  414. { STV090x_P1_ERRCTRL2, 0xc1 },
  415. { STV090x_P1_CFRICFG, 0xf8 },
  416. { STV090x_P1_NOSCFG, 0x1c },
  417. { STV090x_P1_DMDTOM, 0x20 },
  418. { STV090x_P1_CORRELMANT, 0x70 },
  419. { STV090x_P1_CORRELABS, 0x88 },
  420. { STV090x_P1_AGC2O, 0x5b },
  421. { STV090x_P1_AGC2REF, 0x38 },
  422. { STV090x_P1_CARCFG, 0xe4 },
  423. { STV090x_P1_ACLC, 0x1A },
  424. { STV090x_P1_BCLC, 0x09 },
  425. { STV090x_P1_CARHDR, 0x08 },
  426. { STV090x_P1_KREFTMG, 0xc1 },
  427. { STV090x_P1_SFRSTEP, 0x58 },
  428. { STV090x_P1_TMGCFG2, 0x01 },
  429. { STV090x_P1_CAR2CFG, 0x26 },
  430. { STV090x_P1_BCLC2S2Q, 0x86 },
  431. { STV090x_P1_BCLC2S28, 0x86 },
  432. { STV090x_P1_SMAPCOEF7, 0x77 },
  433. { STV090x_P1_SMAPCOEF6, 0x85 },
  434. { STV090x_P1_SMAPCOEF5, 0x77 },
  435. { STV090x_P1_DMDCFG2, 0x3b },
  436. { STV090x_P1_MODCODLST0, 0xff },
  437. { STV090x_P1_MODCODLST1, 0xff },
  438. { STV090x_P1_MODCODLST2, 0xff },
  439. { STV090x_P1_MODCODLST3, 0xff },
  440. { STV090x_P1_MODCODLST4, 0xff },
  441. { STV090x_P1_MODCODLST5, 0xff },
  442. { STV090x_P1_MODCODLST6, 0xff },
  443. { STV090x_P1_MODCODLST7, 0xcc },
  444. { STV090x_P1_MODCODLST8, 0xcc },
  445. { STV090x_P1_MODCODLST9, 0xcc },
  446. { STV090x_P1_MODCODLSTA, 0xcc },
  447. { STV090x_P1_MODCODLSTB, 0xcc },
  448. { STV090x_P1_MODCODLSTC, 0xcc },
  449. { STV090x_P1_MODCODLSTD, 0xcc },
  450. { STV090x_P1_MODCODLSTE, 0xcc },
  451. { STV090x_P1_MODCODLSTF, 0xcf },
  452. { STV090x_GENCFG, 0x1c },
  453. { STV090x_NBITER_NF4, 0x37 },
  454. { STV090x_NBITER_NF5, 0x29 },
  455. { STV090x_NBITER_NF6, 0x37 },
  456. { STV090x_NBITER_NF7, 0x33 },
  457. { STV090x_NBITER_NF8, 0x31 },
  458. { STV090x_NBITER_NF9, 0x2f },
  459. { STV090x_NBITER_NF10, 0x39 },
  460. { STV090x_NBITER_NF11, 0x3a },
  461. { STV090x_NBITER_NF12, 0x29 },
  462. { STV090x_NBITER_NF13, 0x37 },
  463. { STV090x_NBITER_NF14, 0x33 },
  464. { STV090x_NBITER_NF15, 0x2f },
  465. { STV090x_NBITER_NF16, 0x39 },
  466. { STV090x_NBITER_NF17, 0x3a },
  467. { STV090x_NBITERNOERR, 0x04 },
  468. { STV090x_GAINLLR_NF4, 0x0C },
  469. { STV090x_GAINLLR_NF5, 0x0F },
  470. { STV090x_GAINLLR_NF6, 0x11 },
  471. { STV090x_GAINLLR_NF7, 0x14 },
  472. { STV090x_GAINLLR_NF8, 0x17 },
  473. { STV090x_GAINLLR_NF9, 0x19 },
  474. { STV090x_GAINLLR_NF10, 0x20 },
  475. { STV090x_GAINLLR_NF11, 0x21 },
  476. { STV090x_GAINLLR_NF12, 0x0D },
  477. { STV090x_GAINLLR_NF13, 0x0F },
  478. { STV090x_GAINLLR_NF14, 0x13 },
  479. { STV090x_GAINLLR_NF15, 0x1A },
  480. { STV090x_GAINLLR_NF16, 0x1F },
  481. { STV090x_GAINLLR_NF17, 0x21 },
  482. { STV090x_RCCFGH, 0x20 },
  483. { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
  484. { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
  485. };
  486. static struct stv090x_reg stv0900_cut20_val[] = {
  487. { STV090x_P2_DMDCFG3, 0xe8 },
  488. { STV090x_P2_DMDCFG4, 0x10 },
  489. { STV090x_P2_CARFREQ, 0x38 },
  490. { STV090x_P2_CARHDR, 0x20 },
  491. { STV090x_P2_KREFTMG, 0x5a },
  492. { STV090x_P2_SMAPCOEF7, 0x06 },
  493. { STV090x_P2_SMAPCOEF6, 0x00 },
  494. { STV090x_P2_SMAPCOEF5, 0x04 },
  495. { STV090x_P2_NOSCFG, 0x0c },
  496. { STV090x_P1_DMDCFG3, 0xe8 },
  497. { STV090x_P1_DMDCFG4, 0x10 },
  498. { STV090x_P1_CARFREQ, 0x38 },
  499. { STV090x_P1_CARHDR, 0x20 },
  500. { STV090x_P1_KREFTMG, 0x5a },
  501. { STV090x_P1_SMAPCOEF7, 0x06 },
  502. { STV090x_P1_SMAPCOEF6, 0x00 },
  503. { STV090x_P1_SMAPCOEF5, 0x04 },
  504. { STV090x_P1_NOSCFG, 0x0c },
  505. { STV090x_GAINLLR_NF4, 0x21 },
  506. { STV090x_GAINLLR_NF5, 0x21 },
  507. { STV090x_GAINLLR_NF6, 0x20 },
  508. { STV090x_GAINLLR_NF7, 0x1F },
  509. { STV090x_GAINLLR_NF8, 0x1E },
  510. { STV090x_GAINLLR_NF9, 0x1E },
  511. { STV090x_GAINLLR_NF10, 0x1D },
  512. { STV090x_GAINLLR_NF11, 0x1B },
  513. { STV090x_GAINLLR_NF12, 0x20 },
  514. { STV090x_GAINLLR_NF13, 0x20 },
  515. { STV090x_GAINLLR_NF14, 0x20 },
  516. { STV090x_GAINLLR_NF15, 0x20 },
  517. { STV090x_GAINLLR_NF16, 0x20 },
  518. { STV090x_GAINLLR_NF17, 0x21 },
  519. };
  520. static struct stv090x_reg stv0903_cut20_val[] = {
  521. { STV090x_P1_DMDCFG3, 0xe8 },
  522. { STV090x_P1_DMDCFG4, 0x10 },
  523. { STV090x_P1_CARFREQ, 0x38 },
  524. { STV090x_P1_CARHDR, 0x20 },
  525. { STV090x_P1_KREFTMG, 0x5a },
  526. { STV090x_P1_SMAPCOEF7, 0x06 },
  527. { STV090x_P1_SMAPCOEF6, 0x00 },
  528. { STV090x_P1_SMAPCOEF5, 0x04 },
  529. { STV090x_P1_NOSCFG, 0x0c },
  530. { STV090x_GAINLLR_NF4, 0x21 },
  531. { STV090x_GAINLLR_NF5, 0x21 },
  532. { STV090x_GAINLLR_NF6, 0x20 },
  533. { STV090x_GAINLLR_NF7, 0x1F },
  534. { STV090x_GAINLLR_NF8, 0x1E },
  535. { STV090x_GAINLLR_NF9, 0x1E },
  536. { STV090x_GAINLLR_NF10, 0x1D },
  537. { STV090x_GAINLLR_NF11, 0x1B },
  538. { STV090x_GAINLLR_NF12, 0x20 },
  539. { STV090x_GAINLLR_NF13, 0x20 },
  540. { STV090x_GAINLLR_NF14, 0x20 },
  541. { STV090x_GAINLLR_NF15, 0x20 },
  542. { STV090x_GAINLLR_NF16, 0x20 },
  543. { STV090x_GAINLLR_NF17, 0x21 }
  544. };
  545. /* Cut 2.0 Long Frame Tracking CR loop */
  546. static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
  547. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  548. { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
  549. { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
  550. { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
  551. { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  552. { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  553. { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  554. { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  555. { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  556. { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
  557. { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
  558. { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
  559. { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
  560. { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
  561. { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
  562. };
  563. /* Cut 3.0 Long Frame Tracking CR loop */
  564. static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
  565. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  566. { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
  567. { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  568. { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  569. { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
  570. { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  571. { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  572. { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  573. { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
  574. { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
  575. { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
  576. { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
  577. { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
  578. { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
  579. { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
  580. };
  581. /* Cut 2.0 Long Frame Tracking CR Loop */
  582. static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
  583. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  584. { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
  585. { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
  586. { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
  587. { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
  588. { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
  589. { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
  590. { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  591. { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  592. { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  593. { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  594. { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
  595. };
  596. /* Cut 3.0 Long Frame Tracking CR Loop */
  597. static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
  598. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  599. { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
  600. { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
  601. { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
  602. { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
  603. { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
  604. { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
  605. { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  606. { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  607. { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  608. { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
  609. { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
  610. };
  611. static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
  612. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  613. { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
  614. { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
  615. { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
  616. };
  617. static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
  618. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  619. { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
  620. { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
  621. { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
  622. };
  623. /* Cut 2.0 Short Frame Tracking CR Loop */
  624. static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
  625. /* MODCOD 2M 5M 10M 20M 30M */
  626. { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
  627. { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
  628. { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
  629. { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
  630. };
  631. /* Cut 3.0 Short Frame Tracking CR Loop */
  632. static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
  633. /* MODCOD 2M 5M 10M 20M 30M */
  634. { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
  635. { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
  636. { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
  637. { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
  638. };
  639. static inline s32 comp2(s32 __x, s32 __width)
  640. {
  641. if (__width == 32)
  642. return __x;
  643. else
  644. return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
  645. }
  646. static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
  647. {
  648. const struct stv090x_config *config = state->config;
  649. int ret;
  650. u8 b0[] = { reg >> 8, reg & 0xff };
  651. u8 buf;
  652. struct i2c_msg msg[] = {
  653. { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
  654. { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
  655. };
  656. ret = i2c_transfer(state->i2c, msg, 2);
  657. if (ret != 2) {
  658. if (ret != -ERESTARTSYS)
  659. dprintk(FE_ERROR, 1,
  660. "Read error, Reg=[0x%02x], Status=%d",
  661. reg, ret);
  662. return ret < 0 ? ret : -EREMOTEIO;
  663. }
  664. if (unlikely(*state->verbose >= FE_DEBUGREG))
  665. dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
  666. reg, buf);
  667. return (unsigned int) buf;
  668. }
  669. static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
  670. {
  671. const struct stv090x_config *config = state->config;
  672. int ret;
  673. u8 buf[2 + count];
  674. struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
  675. buf[0] = reg >> 8;
  676. buf[1] = reg & 0xff;
  677. memcpy(&buf[2], data, count);
  678. if (unlikely(*state->verbose >= FE_DEBUGREG)) {
  679. int i;
  680. printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
  681. for (i = 0; i < count; i++)
  682. printk(" %02x", data[i]);
  683. printk("\n");
  684. }
  685. ret = i2c_transfer(state->i2c, &i2c_msg, 1);
  686. if (ret != 1) {
  687. if (ret != -ERESTARTSYS)
  688. dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
  689. reg, data[0], count, ret);
  690. return ret < 0 ? ret : -EREMOTEIO;
  691. }
  692. return 0;
  693. }
  694. static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
  695. {
  696. return stv090x_write_regs(state, reg, &data, 1);
  697. }
  698. static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  699. {
  700. struct stv090x_state *state = fe->demodulator_priv;
  701. u32 reg;
  702. if (enable)
  703. mutex_lock(&state->internal->tuner_lock);
  704. reg = STV090x_READ_DEMOD(state, I2CRPT);
  705. if (enable) {
  706. dprintk(FE_DEBUG, 1, "Enable Gate");
  707. STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
  708. if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
  709. goto err;
  710. } else {
  711. dprintk(FE_DEBUG, 1, "Disable Gate");
  712. STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
  713. if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
  714. goto err;
  715. }
  716. if (!enable)
  717. mutex_unlock(&state->internal->tuner_lock);
  718. return 0;
  719. err:
  720. dprintk(FE_ERROR, 1, "I/O error");
  721. mutex_unlock(&state->internal->tuner_lock);
  722. return -1;
  723. }
  724. static void stv090x_get_lock_tmg(struct stv090x_state *state)
  725. {
  726. switch (state->algo) {
  727. case STV090x_BLIND_SEARCH:
  728. dprintk(FE_DEBUG, 1, "Blind Search");
  729. if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
  730. state->DemodTimeout = 1500;
  731. state->FecTimeout = 400;
  732. } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
  733. state->DemodTimeout = 1000;
  734. state->FecTimeout = 300;
  735. } else { /*SR >20Msps*/
  736. state->DemodTimeout = 700;
  737. state->FecTimeout = 100;
  738. }
  739. break;
  740. case STV090x_COLD_SEARCH:
  741. case STV090x_WARM_SEARCH:
  742. default:
  743. dprintk(FE_DEBUG, 1, "Normal Search");
  744. if (state->srate <= 1000000) { /*SR <=1Msps*/
  745. state->DemodTimeout = 4500;
  746. state->FecTimeout = 1700;
  747. } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
  748. state->DemodTimeout = 2500;
  749. state->FecTimeout = 1100;
  750. } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
  751. state->DemodTimeout = 1000;
  752. state->FecTimeout = 550;
  753. } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
  754. state->DemodTimeout = 700;
  755. state->FecTimeout = 250;
  756. } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
  757. state->DemodTimeout = 400;
  758. state->FecTimeout = 130;
  759. } else { /*SR >20Msps*/
  760. state->DemodTimeout = 300;
  761. state->FecTimeout = 100;
  762. }
  763. break;
  764. }
  765. if (state->algo == STV090x_WARM_SEARCH)
  766. state->DemodTimeout /= 2;
  767. }
  768. static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
  769. {
  770. u32 sym;
  771. if (srate > 60000000) {
  772. sym = (srate << 4); /* SR * 2^16 / master_clk */
  773. sym /= (state->internal->mclk >> 12);
  774. } else if (srate > 6000000) {
  775. sym = (srate << 6);
  776. sym /= (state->internal->mclk >> 10);
  777. } else {
  778. sym = (srate << 9);
  779. sym /= (state->internal->mclk >> 7);
  780. }
  781. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
  782. goto err;
  783. if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
  784. goto err;
  785. return 0;
  786. err:
  787. dprintk(FE_ERROR, 1, "I/O error");
  788. return -1;
  789. }
  790. static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
  791. {
  792. u32 sym;
  793. srate = 105 * (srate / 100);
  794. if (srate > 60000000) {
  795. sym = (srate << 4); /* SR * 2^16 / master_clk */
  796. sym /= (state->internal->mclk >> 12);
  797. } else if (srate > 6000000) {
  798. sym = (srate << 6);
  799. sym /= (state->internal->mclk >> 10);
  800. } else {
  801. sym = (srate << 9);
  802. sym /= (state->internal->mclk >> 7);
  803. }
  804. if (sym < 0x7fff) {
  805. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
  806. goto err;
  807. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
  808. goto err;
  809. } else {
  810. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
  811. goto err;
  812. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
  813. goto err;
  814. }
  815. return 0;
  816. err:
  817. dprintk(FE_ERROR, 1, "I/O error");
  818. return -1;
  819. }
  820. static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
  821. {
  822. u32 sym;
  823. srate = 95 * (srate / 100);
  824. if (srate > 60000000) {
  825. sym = (srate << 4); /* SR * 2^16 / master_clk */
  826. sym /= (state->internal->mclk >> 12);
  827. } else if (srate > 6000000) {
  828. sym = (srate << 6);
  829. sym /= (state->internal->mclk >> 10);
  830. } else {
  831. sym = (srate << 9);
  832. sym /= (state->internal->mclk >> 7);
  833. }
  834. if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
  835. goto err;
  836. if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
  837. goto err;
  838. return 0;
  839. err:
  840. dprintk(FE_ERROR, 1, "I/O error");
  841. return -1;
  842. }
  843. static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
  844. {
  845. u32 ro;
  846. switch (rolloff) {
  847. case STV090x_RO_20:
  848. ro = 20;
  849. break;
  850. case STV090x_RO_25:
  851. ro = 25;
  852. break;
  853. case STV090x_RO_35:
  854. default:
  855. ro = 35;
  856. break;
  857. }
  858. return srate + (srate * ro) / 100;
  859. }
  860. static int stv090x_set_vit_thacq(struct stv090x_state *state)
  861. {
  862. if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
  863. goto err;
  864. if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
  865. goto err;
  866. if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
  867. goto err;
  868. if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
  869. goto err;
  870. if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
  871. goto err;
  872. if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
  873. goto err;
  874. return 0;
  875. err:
  876. dprintk(FE_ERROR, 1, "I/O error");
  877. return -1;
  878. }
  879. static int stv090x_set_vit_thtracq(struct stv090x_state *state)
  880. {
  881. if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
  882. goto err;
  883. if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
  884. goto err;
  885. if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
  886. goto err;
  887. if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
  888. goto err;
  889. if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
  890. goto err;
  891. if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
  892. goto err;
  893. return 0;
  894. err:
  895. dprintk(FE_ERROR, 1, "I/O error");
  896. return -1;
  897. }
  898. static int stv090x_set_viterbi(struct stv090x_state *state)
  899. {
  900. switch (state->search_mode) {
  901. case STV090x_SEARCH_AUTO:
  902. if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
  903. goto err;
  904. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
  905. goto err;
  906. break;
  907. case STV090x_SEARCH_DVBS1:
  908. if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
  909. goto err;
  910. switch (state->fec) {
  911. case STV090x_PR12:
  912. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
  913. goto err;
  914. break;
  915. case STV090x_PR23:
  916. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
  917. goto err;
  918. break;
  919. case STV090x_PR34:
  920. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
  921. goto err;
  922. break;
  923. case STV090x_PR56:
  924. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
  925. goto err;
  926. break;
  927. case STV090x_PR78:
  928. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
  929. goto err;
  930. break;
  931. default:
  932. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
  933. goto err;
  934. break;
  935. }
  936. break;
  937. case STV090x_SEARCH_DSS:
  938. if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
  939. goto err;
  940. switch (state->fec) {
  941. case STV090x_PR12:
  942. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
  943. goto err;
  944. break;
  945. case STV090x_PR23:
  946. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
  947. goto err;
  948. break;
  949. case STV090x_PR67:
  950. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
  951. goto err;
  952. break;
  953. default:
  954. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
  955. goto err;
  956. break;
  957. }
  958. break;
  959. default:
  960. break;
  961. }
  962. return 0;
  963. err:
  964. dprintk(FE_ERROR, 1, "I/O error");
  965. return -1;
  966. }
  967. static int stv090x_stop_modcod(struct stv090x_state *state)
  968. {
  969. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  970. goto err;
  971. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
  972. goto err;
  973. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
  974. goto err;
  975. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
  976. goto err;
  977. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
  978. goto err;
  979. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
  980. goto err;
  981. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
  982. goto err;
  983. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
  984. goto err;
  985. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
  986. goto err;
  987. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
  988. goto err;
  989. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
  990. goto err;
  991. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
  992. goto err;
  993. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
  994. goto err;
  995. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
  996. goto err;
  997. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
  998. goto err;
  999. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
  1000. goto err;
  1001. return 0;
  1002. err:
  1003. dprintk(FE_ERROR, 1, "I/O error");
  1004. return -1;
  1005. }
  1006. static int stv090x_activate_modcod(struct stv090x_state *state)
  1007. {
  1008. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  1009. goto err;
  1010. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
  1011. goto err;
  1012. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
  1013. goto err;
  1014. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
  1015. goto err;
  1016. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
  1017. goto err;
  1018. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
  1019. goto err;
  1020. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
  1021. goto err;
  1022. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
  1023. goto err;
  1024. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
  1025. goto err;
  1026. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
  1027. goto err;
  1028. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
  1029. goto err;
  1030. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
  1031. goto err;
  1032. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
  1033. goto err;
  1034. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
  1035. goto err;
  1036. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
  1037. goto err;
  1038. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
  1039. goto err;
  1040. return 0;
  1041. err:
  1042. dprintk(FE_ERROR, 1, "I/O error");
  1043. return -1;
  1044. }
  1045. static int stv090x_activate_modcod_single(struct stv090x_state *state)
  1046. {
  1047. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  1048. goto err;
  1049. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
  1050. goto err;
  1051. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
  1052. goto err;
  1053. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
  1054. goto err;
  1055. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
  1056. goto err;
  1057. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
  1058. goto err;
  1059. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
  1060. goto err;
  1061. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
  1062. goto err;
  1063. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
  1064. goto err;
  1065. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
  1066. goto err;
  1067. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
  1068. goto err;
  1069. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
  1070. goto err;
  1071. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
  1072. goto err;
  1073. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
  1074. goto err;
  1075. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
  1076. goto err;
  1077. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
  1078. goto err;
  1079. return 0;
  1080. err:
  1081. dprintk(FE_ERROR, 1, "I/O error");
  1082. return -1;
  1083. }
  1084. static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
  1085. {
  1086. u32 reg;
  1087. switch (state->demod) {
  1088. case STV090x_DEMODULATOR_0:
  1089. mutex_lock(&state->internal->demod_lock);
  1090. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  1091. STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
  1092. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  1093. goto err;
  1094. mutex_unlock(&state->internal->demod_lock);
  1095. break;
  1096. case STV090x_DEMODULATOR_1:
  1097. mutex_lock(&state->internal->demod_lock);
  1098. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  1099. STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
  1100. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  1101. goto err;
  1102. mutex_unlock(&state->internal->demod_lock);
  1103. break;
  1104. default:
  1105. dprintk(FE_ERROR, 1, "Wrong demodulator!");
  1106. break;
  1107. }
  1108. return 0;
  1109. err:
  1110. mutex_unlock(&state->internal->demod_lock);
  1111. dprintk(FE_ERROR, 1, "I/O error");
  1112. return -1;
  1113. }
  1114. static int stv090x_dvbs_track_crl(struct stv090x_state *state)
  1115. {
  1116. if (state->internal->dev_ver >= 0x30) {
  1117. /* Set ACLC BCLC optimised value vs SR */
  1118. if (state->srate >= 15000000) {
  1119. if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
  1120. goto err;
  1121. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
  1122. goto err;
  1123. } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
  1124. if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
  1125. goto err;
  1126. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
  1127. goto err;
  1128. } else if (state->srate < 7000000) {
  1129. if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
  1130. goto err;
  1131. if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
  1132. goto err;
  1133. }
  1134. } else {
  1135. /* Cut 2.0 */
  1136. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
  1137. goto err;
  1138. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  1139. goto err;
  1140. }
  1141. return 0;
  1142. err:
  1143. dprintk(FE_ERROR, 1, "I/O error");
  1144. return -1;
  1145. }
  1146. static int stv090x_delivery_search(struct stv090x_state *state)
  1147. {
  1148. u32 reg;
  1149. switch (state->search_mode) {
  1150. case STV090x_SEARCH_DVBS1:
  1151. case STV090x_SEARCH_DSS:
  1152. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1153. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1154. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1155. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1156. goto err;
  1157. /* Activate Viterbi decoder in legacy search,
  1158. * do not use FRESVIT1, might impact VITERBI2
  1159. */
  1160. if (stv090x_vitclk_ctl(state, 0) < 0)
  1161. goto err;
  1162. if (stv090x_dvbs_track_crl(state) < 0)
  1163. goto err;
  1164. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
  1165. goto err;
  1166. if (stv090x_set_vit_thacq(state) < 0)
  1167. goto err;
  1168. if (stv090x_set_viterbi(state) < 0)
  1169. goto err;
  1170. break;
  1171. case STV090x_SEARCH_DVBS2:
  1172. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1173. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  1174. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1175. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1176. goto err;
  1177. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1178. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1179. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1180. goto err;
  1181. if (stv090x_vitclk_ctl(state, 1) < 0)
  1182. goto err;
  1183. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
  1184. goto err;
  1185. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  1186. goto err;
  1187. if (state->internal->dev_ver <= 0x20) {
  1188. /* enable S2 carrier loop */
  1189. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
  1190. goto err;
  1191. } else {
  1192. /* > Cut 3: Stop carrier 3 */
  1193. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
  1194. goto err;
  1195. }
  1196. if (state->demod_mode != STV090x_SINGLE) {
  1197. /* Cut 2: enable link during search */
  1198. if (stv090x_activate_modcod(state) < 0)
  1199. goto err;
  1200. } else {
  1201. /* Single demodulator
  1202. * Authorize SHORT and LONG frames,
  1203. * QPSK, 8PSK, 16APSK and 32APSK
  1204. */
  1205. if (stv090x_activate_modcod_single(state) < 0)
  1206. goto err;
  1207. }
  1208. if (stv090x_set_vit_thtracq(state) < 0)
  1209. goto err;
  1210. break;
  1211. case STV090x_SEARCH_AUTO:
  1212. default:
  1213. /* enable DVB-S2 and DVB-S2 in Auto MODE */
  1214. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1215. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  1216. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1217. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1218. goto err;
  1219. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1220. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1221. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1222. goto err;
  1223. if (stv090x_vitclk_ctl(state, 0) < 0)
  1224. goto err;
  1225. if (stv090x_dvbs_track_crl(state) < 0)
  1226. goto err;
  1227. if (state->internal->dev_ver <= 0x20) {
  1228. /* enable S2 carrier loop */
  1229. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
  1230. goto err;
  1231. } else {
  1232. /* > Cut 3: Stop carrier 3 */
  1233. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
  1234. goto err;
  1235. }
  1236. if (state->demod_mode != STV090x_SINGLE) {
  1237. /* Cut 2: enable link during search */
  1238. if (stv090x_activate_modcod(state) < 0)
  1239. goto err;
  1240. } else {
  1241. /* Single demodulator
  1242. * Authorize SHORT and LONG frames,
  1243. * QPSK, 8PSK, 16APSK and 32APSK
  1244. */
  1245. if (stv090x_activate_modcod_single(state) < 0)
  1246. goto err;
  1247. }
  1248. if (stv090x_set_vit_thacq(state) < 0)
  1249. goto err;
  1250. if (stv090x_set_viterbi(state) < 0)
  1251. goto err;
  1252. break;
  1253. }
  1254. return 0;
  1255. err:
  1256. dprintk(FE_ERROR, 1, "I/O error");
  1257. return -1;
  1258. }
  1259. static int stv090x_start_search(struct stv090x_state *state)
  1260. {
  1261. u32 reg, freq_abs;
  1262. s16 freq;
  1263. /* Reset demodulator */
  1264. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1265. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
  1266. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1267. goto err;
  1268. if (state->internal->dev_ver <= 0x20) {
  1269. if (state->srate <= 5000000) {
  1270. if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
  1271. goto err;
  1272. if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
  1273. goto err;
  1274. if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
  1275. goto err;
  1276. if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
  1277. goto err;
  1278. if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
  1279. goto err;
  1280. /*enlarge the timing bandwith for Low SR*/
  1281. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
  1282. goto err;
  1283. } else {
  1284. /* If the symbol rate is >5 Msps
  1285. Set The carrier search up and low to auto mode */
  1286. if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
  1287. goto err;
  1288. /*reduce the timing bandwith for high SR*/
  1289. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
  1290. goto err;
  1291. }
  1292. } else {
  1293. /* >= Cut 3 */
  1294. if (state->srate <= 5000000) {
  1295. /* enlarge the timing bandwith for Low SR */
  1296. STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
  1297. } else {
  1298. /* reduce timing bandwith for high SR */
  1299. STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
  1300. }
  1301. /* Set CFR min and max to manual mode */
  1302. STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
  1303. if (state->algo == STV090x_WARM_SEARCH) {
  1304. /* WARM Start
  1305. * CFR min = -1MHz,
  1306. * CFR max = +1MHz
  1307. */
  1308. freq_abs = 1000 << 16;
  1309. freq_abs /= (state->internal->mclk / 1000);
  1310. freq = (s16) freq_abs;
  1311. } else {
  1312. /* COLD Start
  1313. * CFR min =- (SearchRange / 2 + 600KHz)
  1314. * CFR max = +(SearchRange / 2 + 600KHz)
  1315. * (600KHz for the tuner step size)
  1316. */
  1317. freq_abs = (state->search_range / 2000) + 600;
  1318. freq_abs = freq_abs << 16;
  1319. freq_abs /= (state->internal->mclk / 1000);
  1320. freq = (s16) freq_abs;
  1321. }
  1322. if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
  1323. goto err;
  1324. if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
  1325. goto err;
  1326. freq *= -1;
  1327. if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
  1328. goto err;
  1329. if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
  1330. goto err;
  1331. }
  1332. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
  1333. goto err;
  1334. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
  1335. goto err;
  1336. if (state->internal->dev_ver >= 0x20) {
  1337. if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
  1338. goto err;
  1339. if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
  1340. goto err;
  1341. if ((state->search_mode == STV090x_DVBS1) ||
  1342. (state->search_mode == STV090x_DSS) ||
  1343. (state->search_mode == STV090x_SEARCH_AUTO)) {
  1344. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
  1345. goto err;
  1346. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
  1347. goto err;
  1348. }
  1349. }
  1350. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
  1351. goto err;
  1352. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
  1353. goto err;
  1354. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
  1355. goto err;
  1356. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1357. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
  1358. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1359. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1360. goto err;
  1361. reg = STV090x_READ_DEMOD(state, DMDCFG2);
  1362. STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
  1363. if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
  1364. goto err;
  1365. if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
  1366. goto err;
  1367. if (state->internal->dev_ver >= 0x20) {
  1368. /*Frequency offset detector setting*/
  1369. if (state->srate < 2000000) {
  1370. if (state->internal->dev_ver <= 0x20) {
  1371. /* Cut 2 */
  1372. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
  1373. goto err;
  1374. } else {
  1375. /* Cut 3 */
  1376. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
  1377. goto err;
  1378. }
  1379. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
  1380. goto err;
  1381. } else if (state->srate < 10000000) {
  1382. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
  1383. goto err;
  1384. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
  1385. goto err;
  1386. } else {
  1387. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
  1388. goto err;
  1389. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
  1390. goto err;
  1391. }
  1392. } else {
  1393. if (state->srate < 10000000) {
  1394. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
  1395. goto err;
  1396. } else {
  1397. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
  1398. goto err;
  1399. }
  1400. }
  1401. switch (state->algo) {
  1402. case STV090x_WARM_SEARCH:
  1403. /* The symbol rate and the exact
  1404. * carrier Frequency are known
  1405. */
  1406. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1407. goto err;
  1408. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  1409. goto err;
  1410. break;
  1411. case STV090x_COLD_SEARCH:
  1412. /* The symbol rate is known */
  1413. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1414. goto err;
  1415. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1416. goto err;
  1417. break;
  1418. default:
  1419. break;
  1420. }
  1421. return 0;
  1422. err:
  1423. dprintk(FE_ERROR, 1, "I/O error");
  1424. return -1;
  1425. }
  1426. static int stv090x_get_agc2_min_level(struct stv090x_state *state)
  1427. {
  1428. u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
  1429. s32 i, j, steps, dir;
  1430. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1431. goto err;
  1432. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1433. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
  1434. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1435. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1436. goto err;
  1437. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
  1438. goto err;
  1439. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
  1440. goto err;
  1441. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
  1442. goto err;
  1443. if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
  1444. goto err;
  1445. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
  1446. goto err;
  1447. if (stv090x_set_srate(state, 1000000) < 0)
  1448. goto err;
  1449. steps = state->search_range / 1000000;
  1450. if (steps <= 0)
  1451. steps = 1;
  1452. dir = 1;
  1453. freq_step = (1000000 * 256) / (state->internal->mclk / 256);
  1454. freq_init = 0;
  1455. for (i = 0; i < steps; i++) {
  1456. if (dir > 0)
  1457. freq_init = freq_init + (freq_step * i);
  1458. else
  1459. freq_init = freq_init - (freq_step * i);
  1460. dir *= -1;
  1461. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
  1462. goto err;
  1463. if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
  1464. goto err;
  1465. if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
  1466. goto err;
  1467. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
  1468. goto err;
  1469. msleep(10);
  1470. agc2 = 0;
  1471. for (j = 0; j < 10; j++) {
  1472. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1473. STV090x_READ_DEMOD(state, AGC2I0);
  1474. }
  1475. agc2 /= 10;
  1476. if (agc2 < agc2_min)
  1477. agc2_min = agc2;
  1478. }
  1479. return agc2_min;
  1480. err:
  1481. dprintk(FE_ERROR, 1, "I/O error");
  1482. return -1;
  1483. }
  1484. static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
  1485. {
  1486. u8 r3, r2, r1, r0;
  1487. s32 srate, int_1, int_2, tmp_1, tmp_2;
  1488. r3 = STV090x_READ_DEMOD(state, SFR3);
  1489. r2 = STV090x_READ_DEMOD(state, SFR2);
  1490. r1 = STV090x_READ_DEMOD(state, SFR1);
  1491. r0 = STV090x_READ_DEMOD(state, SFR0);
  1492. srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
  1493. int_1 = clk >> 16;
  1494. int_2 = srate >> 16;
  1495. tmp_1 = clk % 0x10000;
  1496. tmp_2 = srate % 0x10000;
  1497. srate = (int_1 * int_2) +
  1498. ((int_1 * tmp_2) >> 16) +
  1499. ((int_2 * tmp_1) >> 16);
  1500. return srate;
  1501. }
  1502. static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
  1503. {
  1504. struct dvb_frontend *fe = &state->frontend;
  1505. int tmg_lock = 0, i;
  1506. s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
  1507. u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
  1508. u32 agc2th;
  1509. if (state->internal->dev_ver >= 0x30)
  1510. agc2th = 0x2e00;
  1511. else
  1512. agc2th = 0x1f00;
  1513. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1514. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
  1515. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1516. goto err;
  1517. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
  1518. goto err;
  1519. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
  1520. goto err;
  1521. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
  1522. goto err;
  1523. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
  1524. goto err;
  1525. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1526. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
  1527. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1528. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1529. goto err;
  1530. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
  1531. goto err;
  1532. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
  1533. goto err;
  1534. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
  1535. goto err;
  1536. if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
  1537. goto err;
  1538. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
  1539. goto err;
  1540. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
  1541. goto err;
  1542. if (state->internal->dev_ver >= 0x30) {
  1543. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
  1544. goto err;
  1545. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
  1546. goto err;
  1547. } else if (state->internal->dev_ver >= 0x20) {
  1548. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
  1549. goto err;
  1550. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
  1551. goto err;
  1552. }
  1553. if (state->srate <= 2000000)
  1554. car_step = 1000;
  1555. else if (state->srate <= 5000000)
  1556. car_step = 2000;
  1557. else if (state->srate <= 12000000)
  1558. car_step = 3000;
  1559. else
  1560. car_step = 5000;
  1561. steps = -1 + ((state->search_range / 1000) / car_step);
  1562. steps /= 2;
  1563. steps = (2 * steps) + 1;
  1564. if (steps < 0)
  1565. steps = 1;
  1566. else if (steps > 10) {
  1567. steps = 11;
  1568. car_step = (state->search_range / 1000) / 10;
  1569. }
  1570. cur_step = 0;
  1571. dir = 1;
  1572. freq = state->frequency;
  1573. while ((!tmg_lock) && (cur_step < steps)) {
  1574. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
  1575. goto err;
  1576. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
  1577. goto err;
  1578. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1579. goto err;
  1580. if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
  1581. goto err;
  1582. if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
  1583. goto err;
  1584. /* trigger acquisition */
  1585. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
  1586. goto err;
  1587. msleep(50);
  1588. for (i = 0; i < 10; i++) {
  1589. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1590. if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
  1591. tmg_cpt++;
  1592. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1593. STV090x_READ_DEMOD(state, AGC2I0);
  1594. }
  1595. agc2 /= 10;
  1596. srate_coarse = stv090x_get_srate(state, state->internal->mclk);
  1597. cur_step++;
  1598. dir *= -1;
  1599. if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
  1600. (srate_coarse < 50000000) && (srate_coarse > 850000))
  1601. tmg_lock = 1;
  1602. else if (cur_step < steps) {
  1603. if (dir > 0)
  1604. freq += cur_step * car_step;
  1605. else
  1606. freq -= cur_step * car_step;
  1607. /* Setup tuner */
  1608. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1609. goto err;
  1610. if (state->config->tuner_set_frequency) {
  1611. if (state->config->tuner_set_frequency(fe, freq) < 0)
  1612. goto err_gateoff;
  1613. }
  1614. if (state->config->tuner_set_bandwidth) {
  1615. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  1616. goto err_gateoff;
  1617. }
  1618. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1619. goto err;
  1620. msleep(50);
  1621. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1622. goto err;
  1623. if (state->config->tuner_get_status) {
  1624. if (state->config->tuner_get_status(fe, &reg) < 0)
  1625. goto err_gateoff;
  1626. }
  1627. if (reg)
  1628. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  1629. else
  1630. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  1631. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1632. goto err;
  1633. }
  1634. }
  1635. if (!tmg_lock)
  1636. srate_coarse = 0;
  1637. else
  1638. srate_coarse = stv090x_get_srate(state, state->internal->mclk);
  1639. return srate_coarse;
  1640. err_gateoff:
  1641. stv090x_i2c_gate_ctrl(fe, 0);
  1642. err:
  1643. dprintk(FE_ERROR, 1, "I/O error");
  1644. return -1;
  1645. }
  1646. static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
  1647. {
  1648. u32 srate_coarse, freq_coarse, sym, reg;
  1649. srate_coarse = stv090x_get_srate(state, state->internal->mclk);
  1650. freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
  1651. freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
  1652. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1653. if (sym < state->srate)
  1654. srate_coarse = 0;
  1655. else {
  1656. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
  1657. goto err;
  1658. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
  1659. goto err;
  1660. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
  1661. goto err;
  1662. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
  1663. goto err;
  1664. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
  1665. goto err;
  1666. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1667. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
  1668. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1669. goto err;
  1670. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1671. goto err;
  1672. if (state->internal->dev_ver >= 0x30) {
  1673. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
  1674. goto err;
  1675. } else if (state->internal->dev_ver >= 0x20) {
  1676. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  1677. goto err;
  1678. }
  1679. if (srate_coarse > 3000000) {
  1680. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1681. sym = (sym / 1000) * 65536;
  1682. sym /= (state->internal->mclk / 1000);
  1683. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
  1684. goto err;
  1685. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
  1686. goto err;
  1687. sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
  1688. sym = (sym / 1000) * 65536;
  1689. sym /= (state->internal->mclk / 1000);
  1690. if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
  1691. goto err;
  1692. if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
  1693. goto err;
  1694. sym = (srate_coarse / 1000) * 65536;
  1695. sym /= (state->internal->mclk / 1000);
  1696. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
  1697. goto err;
  1698. if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
  1699. goto err;
  1700. } else {
  1701. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1702. sym = (sym / 100) * 65536;
  1703. sym /= (state->internal->mclk / 100);
  1704. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
  1705. goto err;
  1706. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
  1707. goto err;
  1708. sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
  1709. sym = (sym / 100) * 65536;
  1710. sym /= (state->internal->mclk / 100);
  1711. if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
  1712. goto err;
  1713. if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
  1714. goto err;
  1715. sym = (srate_coarse / 100) * 65536;
  1716. sym /= (state->internal->mclk / 100);
  1717. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
  1718. goto err;
  1719. if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
  1720. goto err;
  1721. }
  1722. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
  1723. goto err;
  1724. if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
  1725. goto err;
  1726. if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
  1727. goto err;
  1728. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
  1729. goto err;
  1730. }
  1731. return srate_coarse;
  1732. err:
  1733. dprintk(FE_ERROR, 1, "I/O error");
  1734. return -1;
  1735. }
  1736. static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
  1737. {
  1738. s32 timer = 0, lock = 0;
  1739. u32 reg;
  1740. u8 stat;
  1741. while ((timer < timeout) && (!lock)) {
  1742. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  1743. stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  1744. switch (stat) {
  1745. case 0: /* searching */
  1746. case 1: /* first PLH detected */
  1747. default:
  1748. dprintk(FE_DEBUG, 1, "Demodulator searching ..");
  1749. lock = 0;
  1750. break;
  1751. case 2: /* DVB-S2 mode */
  1752. case 3: /* DVB-S1/legacy mode */
  1753. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1754. lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  1755. break;
  1756. }
  1757. if (!lock)
  1758. msleep(10);
  1759. else
  1760. dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
  1761. timer += 10;
  1762. }
  1763. return lock;
  1764. }
  1765. static int stv090x_blind_search(struct stv090x_state *state)
  1766. {
  1767. u32 agc2, reg, srate_coarse;
  1768. s32 cpt_fail, agc2_ovflw, i;
  1769. u8 k_ref, k_max, k_min;
  1770. int coarse_fail = 0;
  1771. int lock;
  1772. k_max = 110;
  1773. k_min = 10;
  1774. agc2 = stv090x_get_agc2_min_level(state);
  1775. if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
  1776. lock = 0;
  1777. } else {
  1778. if (state->internal->dev_ver <= 0x20) {
  1779. if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
  1780. goto err;
  1781. } else {
  1782. /* > Cut 3 */
  1783. if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
  1784. goto err;
  1785. }
  1786. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
  1787. goto err;
  1788. if (state->internal->dev_ver >= 0x20) {
  1789. if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
  1790. goto err;
  1791. if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
  1792. goto err;
  1793. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
  1794. goto err;
  1795. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
  1796. goto err;
  1797. }
  1798. k_ref = k_max;
  1799. do {
  1800. if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
  1801. goto err;
  1802. if (stv090x_srate_srch_coarse(state) != 0) {
  1803. srate_coarse = stv090x_srate_srch_fine(state);
  1804. if (srate_coarse != 0) {
  1805. stv090x_get_lock_tmg(state);
  1806. lock = stv090x_get_dmdlock(state,
  1807. state->DemodTimeout);
  1808. } else {
  1809. lock = 0;
  1810. }
  1811. } else {
  1812. cpt_fail = 0;
  1813. agc2_ovflw = 0;
  1814. for (i = 0; i < 10; i++) {
  1815. agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
  1816. STV090x_READ_DEMOD(state, AGC2I0);
  1817. if (agc2 >= 0xff00)
  1818. agc2_ovflw++;
  1819. reg = STV090x_READ_DEMOD(state, DSTATUS2);
  1820. if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
  1821. (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
  1822. cpt_fail++;
  1823. }
  1824. if ((cpt_fail > 7) || (agc2_ovflw > 7))
  1825. coarse_fail = 1;
  1826. lock = 0;
  1827. }
  1828. k_ref -= 20;
  1829. } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
  1830. }
  1831. return lock;
  1832. err:
  1833. dprintk(FE_ERROR, 1, "I/O error");
  1834. return -1;
  1835. }
  1836. static int stv090x_chk_tmg(struct stv090x_state *state)
  1837. {
  1838. u32 reg;
  1839. s32 tmg_cpt = 0, i;
  1840. u8 freq, tmg_thh, tmg_thl;
  1841. int tmg_lock = 0;
  1842. freq = STV090x_READ_DEMOD(state, CARFREQ);
  1843. tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
  1844. tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
  1845. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
  1846. goto err;
  1847. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
  1848. goto err;
  1849. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1850. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
  1851. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1852. goto err;
  1853. if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
  1854. goto err;
  1855. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
  1856. goto err;
  1857. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
  1858. goto err;
  1859. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
  1860. goto err;
  1861. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1862. goto err;
  1863. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
  1864. goto err;
  1865. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
  1866. goto err;
  1867. msleep(10);
  1868. for (i = 0; i < 10; i++) {
  1869. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1870. if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
  1871. tmg_cpt++;
  1872. msleep(1);
  1873. }
  1874. if (tmg_cpt >= 3)
  1875. tmg_lock = 1;
  1876. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1877. goto err;
  1878. if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
  1879. goto err;
  1880. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
  1881. goto err;
  1882. if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
  1883. goto err;
  1884. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
  1885. goto err;
  1886. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
  1887. goto err;
  1888. return tmg_lock;
  1889. err:
  1890. dprintk(FE_ERROR, 1, "I/O error");
  1891. return -1;
  1892. }
  1893. static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
  1894. {
  1895. struct dvb_frontend *fe = &state->frontend;
  1896. u32 reg;
  1897. s32 car_step, steps, cur_step, dir, freq, timeout_lock;
  1898. int lock = 0;
  1899. if (state->srate >= 10000000)
  1900. timeout_lock = timeout_dmd / 3;
  1901. else
  1902. timeout_lock = timeout_dmd / 2;
  1903. lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
  1904. if (!lock) {
  1905. if (state->srate >= 10000000) {
  1906. if (stv090x_chk_tmg(state)) {
  1907. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1908. goto err;
  1909. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1910. goto err;
  1911. lock = stv090x_get_dmdlock(state, timeout_dmd);
  1912. } else {
  1913. lock = 0;
  1914. }
  1915. } else {
  1916. if (state->srate <= 4000000)
  1917. car_step = 1000;
  1918. else if (state->srate <= 7000000)
  1919. car_step = 2000;
  1920. else if (state->srate <= 10000000)
  1921. car_step = 3000;
  1922. else
  1923. car_step = 5000;
  1924. steps = (state->search_range / 1000) / car_step;
  1925. steps /= 2;
  1926. steps = 2 * (steps + 1);
  1927. if (steps < 0)
  1928. steps = 2;
  1929. else if (steps > 12)
  1930. steps = 12;
  1931. cur_step = 1;
  1932. dir = 1;
  1933. if (!lock) {
  1934. freq = state->frequency;
  1935. state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
  1936. while ((cur_step <= steps) && (!lock)) {
  1937. if (dir > 0)
  1938. freq += cur_step * car_step;
  1939. else
  1940. freq -= cur_step * car_step;
  1941. /* Setup tuner */
  1942. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1943. goto err;
  1944. if (state->config->tuner_set_frequency) {
  1945. if (state->config->tuner_set_frequency(fe, freq) < 0)
  1946. goto err_gateoff;
  1947. }
  1948. if (state->config->tuner_set_bandwidth) {
  1949. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  1950. goto err_gateoff;
  1951. }
  1952. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1953. goto err;
  1954. msleep(50);
  1955. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  1956. goto err;
  1957. if (state->config->tuner_get_status) {
  1958. if (state->config->tuner_get_status(fe, &reg) < 0)
  1959. goto err_gateoff;
  1960. }
  1961. if (reg)
  1962. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  1963. else
  1964. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  1965. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  1966. goto err;
  1967. STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
  1968. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
  1969. goto err;
  1970. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1971. goto err;
  1972. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1973. goto err;
  1974. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1975. goto err;
  1976. lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
  1977. dir *= -1;
  1978. cur_step++;
  1979. }
  1980. }
  1981. }
  1982. }
  1983. return lock;
  1984. err_gateoff:
  1985. stv090x_i2c_gate_ctrl(fe, 0);
  1986. err:
  1987. dprintk(FE_ERROR, 1, "I/O error");
  1988. return -1;
  1989. }
  1990. static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
  1991. {
  1992. s32 timeout, inc, steps_max, srate, car_max;
  1993. srate = state->srate;
  1994. car_max = state->search_range / 1000;
  1995. car_max += car_max / 10;
  1996. car_max = 65536 * (car_max / 2);
  1997. car_max /= (state->internal->mclk / 1000);
  1998. if (car_max > 0x4000)
  1999. car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
  2000. inc = srate;
  2001. inc /= state->internal->mclk / 1000;
  2002. inc *= 256;
  2003. inc *= 256;
  2004. inc /= 1000;
  2005. switch (state->search_mode) {
  2006. case STV090x_SEARCH_DVBS1:
  2007. case STV090x_SEARCH_DSS:
  2008. inc *= 3; /* freq step = 3% of srate */
  2009. timeout = 20;
  2010. break;
  2011. case STV090x_SEARCH_DVBS2:
  2012. inc *= 4;
  2013. timeout = 25;
  2014. break;
  2015. case STV090x_SEARCH_AUTO:
  2016. default:
  2017. inc *= 3;
  2018. timeout = 25;
  2019. break;
  2020. }
  2021. inc /= 100;
  2022. if ((inc > car_max) || (inc < 0))
  2023. inc = car_max / 2; /* increment <= 1/8 Mclk */
  2024. timeout *= 27500; /* 27.5 Msps reference */
  2025. if (srate > 0)
  2026. timeout /= (srate / 1000);
  2027. if ((timeout > 100) || (timeout < 0))
  2028. timeout = 100;
  2029. steps_max = (car_max / inc) + 1; /* min steps = 3 */
  2030. if ((steps_max > 100) || (steps_max < 0)) {
  2031. steps_max = 100; /* max steps <= 100 */
  2032. inc = car_max / steps_max;
  2033. }
  2034. *freq_inc = inc;
  2035. *timeout_sw = timeout;
  2036. *steps = steps_max;
  2037. return 0;
  2038. }
  2039. static int stv090x_chk_signal(struct stv090x_state *state)
  2040. {
  2041. s32 offst_car, agc2, car_max;
  2042. int no_signal;
  2043. offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
  2044. offst_car |= STV090x_READ_DEMOD(state, CFR1);
  2045. offst_car = comp2(offst_car, 16);
  2046. agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
  2047. agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
  2048. car_max = state->search_range / 1000;
  2049. car_max += (car_max / 10); /* 10% margin */
  2050. car_max = (65536 * car_max / 2);
  2051. car_max /= state->internal->mclk / 1000;
  2052. if (car_max > 0x4000)
  2053. car_max = 0x4000;
  2054. if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
  2055. no_signal = 1;
  2056. dprintk(FE_DEBUG, 1, "No Signal");
  2057. } else {
  2058. no_signal = 0;
  2059. dprintk(FE_DEBUG, 1, "Found Signal");
  2060. }
  2061. return no_signal;
  2062. }
  2063. static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
  2064. {
  2065. int no_signal, lock = 0;
  2066. s32 cpt_step = 0, offst_freq, car_max;
  2067. u32 reg;
  2068. car_max = state->search_range / 1000;
  2069. car_max += (car_max / 10);
  2070. car_max = (65536 * car_max / 2);
  2071. car_max /= (state->internal->mclk / 1000);
  2072. if (car_max > 0x4000)
  2073. car_max = 0x4000;
  2074. if (zigzag)
  2075. offst_freq = 0;
  2076. else
  2077. offst_freq = -car_max + inc;
  2078. do {
  2079. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
  2080. goto err;
  2081. if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
  2082. goto err;
  2083. if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
  2084. goto err;
  2085. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2086. goto err;
  2087. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  2088. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
  2089. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  2090. goto err;
  2091. if (zigzag) {
  2092. if (offst_freq >= 0)
  2093. offst_freq = -offst_freq - 2 * inc;
  2094. else
  2095. offst_freq = -offst_freq;
  2096. } else {
  2097. offst_freq += 2 * inc;
  2098. }
  2099. cpt_step++;
  2100. lock = stv090x_get_dmdlock(state, timeout);
  2101. no_signal = stv090x_chk_signal(state);
  2102. } while ((!lock) &&
  2103. (!no_signal) &&
  2104. ((offst_freq - inc) < car_max) &&
  2105. ((offst_freq + inc) > -car_max) &&
  2106. (cpt_step < steps_max));
  2107. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  2108. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
  2109. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  2110. goto err;
  2111. return lock;
  2112. err:
  2113. dprintk(FE_ERROR, 1, "I/O error");
  2114. return -1;
  2115. }
  2116. static int stv090x_sw_algo(struct stv090x_state *state)
  2117. {
  2118. int no_signal, zigzag, lock = 0;
  2119. u32 reg;
  2120. s32 dvbs2_fly_wheel;
  2121. s32 inc, timeout_step, trials, steps_max;
  2122. /* get params */
  2123. stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
  2124. switch (state->search_mode) {
  2125. case STV090x_SEARCH_DVBS1:
  2126. case STV090x_SEARCH_DSS:
  2127. /* accelerate the frequency detector */
  2128. if (state->internal->dev_ver >= 0x20) {
  2129. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
  2130. goto err;
  2131. }
  2132. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
  2133. goto err;
  2134. zigzag = 0;
  2135. break;
  2136. case STV090x_SEARCH_DVBS2:
  2137. if (state->internal->dev_ver >= 0x20) {
  2138. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2139. goto err;
  2140. }
  2141. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
  2142. goto err;
  2143. zigzag = 1;
  2144. break;
  2145. case STV090x_SEARCH_AUTO:
  2146. default:
  2147. /* accelerate the frequency detector */
  2148. if (state->internal->dev_ver >= 0x20) {
  2149. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
  2150. goto err;
  2151. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2152. goto err;
  2153. }
  2154. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
  2155. goto err;
  2156. zigzag = 0;
  2157. break;
  2158. }
  2159. trials = 0;
  2160. do {
  2161. lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
  2162. no_signal = stv090x_chk_signal(state);
  2163. trials++;
  2164. /*run the SW search 2 times maximum*/
  2165. if (lock || no_signal || (trials == 2)) {
  2166. /*Check if the demod is not losing lock in DVBS2*/
  2167. if (state->internal->dev_ver >= 0x20) {
  2168. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  2169. goto err;
  2170. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
  2171. goto err;
  2172. }
  2173. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2174. if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
  2175. /*Check if the demod is not losing lock in DVBS2*/
  2176. msleep(timeout_step);
  2177. reg = STV090x_READ_DEMOD(state, DMDFLYW);
  2178. dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
  2179. if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
  2180. msleep(timeout_step);
  2181. reg = STV090x_READ_DEMOD(state, DMDFLYW);
  2182. dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
  2183. }
  2184. if (dvbs2_fly_wheel < 0xd) {
  2185. /*FALSE lock, The demod is loosing lock */
  2186. lock = 0;
  2187. if (trials < 2) {
  2188. if (state->internal->dev_ver >= 0x20) {
  2189. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  2190. goto err;
  2191. }
  2192. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
  2193. goto err;
  2194. }
  2195. }
  2196. }
  2197. }
  2198. } while ((!lock) && (trials < 2) && (!no_signal));
  2199. return lock;
  2200. err:
  2201. dprintk(FE_ERROR, 1, "I/O error");
  2202. return -1;
  2203. }
  2204. static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
  2205. {
  2206. u32 reg;
  2207. enum stv090x_delsys delsys;
  2208. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2209. if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
  2210. delsys = STV090x_DVBS2;
  2211. else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
  2212. reg = STV090x_READ_DEMOD(state, FECM);
  2213. if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
  2214. delsys = STV090x_DSS;
  2215. else
  2216. delsys = STV090x_DVBS1;
  2217. } else {
  2218. delsys = STV090x_ERROR;
  2219. }
  2220. return delsys;
  2221. }
  2222. /* in Hz */
  2223. static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
  2224. {
  2225. s32 derot, int_1, int_2, tmp_1, tmp_2;
  2226. derot = STV090x_READ_DEMOD(state, CFR2) << 16;
  2227. derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
  2228. derot |= STV090x_READ_DEMOD(state, CFR0);
  2229. derot = comp2(derot, 24);
  2230. int_1 = mclk >> 12;
  2231. int_2 = derot >> 12;
  2232. /* carrier_frequency = MasterClock * Reg / 2^24 */
  2233. tmp_1 = mclk % 0x1000;
  2234. tmp_2 = derot % 0x1000;
  2235. derot = (int_1 * int_2) +
  2236. ((int_1 * tmp_2) >> 12) +
  2237. ((int_2 * tmp_1) >> 12);
  2238. return derot;
  2239. }
  2240. static int stv090x_get_viterbi(struct stv090x_state *state)
  2241. {
  2242. u32 reg, rate;
  2243. reg = STV090x_READ_DEMOD(state, VITCURPUN);
  2244. rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
  2245. switch (rate) {
  2246. case 13:
  2247. state->fec = STV090x_PR12;
  2248. break;
  2249. case 18:
  2250. state->fec = STV090x_PR23;
  2251. break;
  2252. case 21:
  2253. state->fec = STV090x_PR34;
  2254. break;
  2255. case 24:
  2256. state->fec = STV090x_PR56;
  2257. break;
  2258. case 25:
  2259. state->fec = STV090x_PR67;
  2260. break;
  2261. case 26:
  2262. state->fec = STV090x_PR78;
  2263. break;
  2264. default:
  2265. state->fec = STV090x_PRERR;
  2266. break;
  2267. }
  2268. return 0;
  2269. }
  2270. static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
  2271. {
  2272. struct dvb_frontend *fe = &state->frontend;
  2273. u8 tmg;
  2274. u32 reg;
  2275. s32 i = 0, offst_freq;
  2276. msleep(5);
  2277. if (state->algo == STV090x_BLIND_SEARCH) {
  2278. tmg = STV090x_READ_DEMOD(state, TMGREG2);
  2279. STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
  2280. while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
  2281. tmg = STV090x_READ_DEMOD(state, TMGREG2);
  2282. msleep(5);
  2283. i += 5;
  2284. }
  2285. }
  2286. state->delsys = stv090x_get_std(state);
  2287. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2288. goto err;
  2289. if (state->config->tuner_get_frequency) {
  2290. if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
  2291. goto err_gateoff;
  2292. }
  2293. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2294. goto err;
  2295. offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
  2296. state->frequency += offst_freq;
  2297. if (stv090x_get_viterbi(state) < 0)
  2298. goto err;
  2299. reg = STV090x_READ_DEMOD(state, DMDMODCOD);
  2300. state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
  2301. state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
  2302. state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
  2303. reg = STV090x_READ_DEMOD(state, TMGOBS);
  2304. state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
  2305. reg = STV090x_READ_DEMOD(state, FECM);
  2306. state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
  2307. if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
  2308. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2309. goto err;
  2310. if (state->config->tuner_get_frequency) {
  2311. if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
  2312. goto err_gateoff;
  2313. }
  2314. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2315. goto err;
  2316. if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
  2317. return STV090x_RANGEOK;
  2318. else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
  2319. return STV090x_RANGEOK;
  2320. else
  2321. return STV090x_OUTOFRANGE; /* Out of Range */
  2322. } else {
  2323. if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
  2324. return STV090x_RANGEOK;
  2325. else
  2326. return STV090x_OUTOFRANGE;
  2327. }
  2328. return STV090x_OUTOFRANGE;
  2329. err_gateoff:
  2330. stv090x_i2c_gate_ctrl(fe, 0);
  2331. err:
  2332. dprintk(FE_ERROR, 1, "I/O error");
  2333. return -1;
  2334. }
  2335. static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
  2336. {
  2337. s32 offst_tmg;
  2338. offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
  2339. offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
  2340. offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
  2341. offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
  2342. if (!offst_tmg)
  2343. offst_tmg = 1;
  2344. offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
  2345. offst_tmg /= 320;
  2346. return offst_tmg;
  2347. }
  2348. static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
  2349. {
  2350. u8 aclc = 0x29;
  2351. s32 i;
  2352. struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
  2353. if (state->internal->dev_ver == 0x20) {
  2354. car_loop = stv090x_s2_crl_cut20;
  2355. car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
  2356. car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
  2357. } else {
  2358. /* >= Cut 3 */
  2359. car_loop = stv090x_s2_crl_cut30;
  2360. car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
  2361. car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
  2362. }
  2363. if (modcod < STV090x_QPSK_12) {
  2364. i = 0;
  2365. while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
  2366. i++;
  2367. if (i >= 3)
  2368. i = 2;
  2369. } else {
  2370. i = 0;
  2371. while ((i < 14) && (modcod != car_loop[i].modcod))
  2372. i++;
  2373. if (i >= 14) {
  2374. i = 0;
  2375. while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
  2376. i++;
  2377. if (i >= 11)
  2378. i = 10;
  2379. }
  2380. }
  2381. if (modcod <= STV090x_QPSK_25) {
  2382. if (pilots) {
  2383. if (state->srate <= 3000000)
  2384. aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
  2385. else if (state->srate <= 7000000)
  2386. aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
  2387. else if (state->srate <= 15000000)
  2388. aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
  2389. else if (state->srate <= 25000000)
  2390. aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
  2391. else
  2392. aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
  2393. } else {
  2394. if (state->srate <= 3000000)
  2395. aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
  2396. else if (state->srate <= 7000000)
  2397. aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
  2398. else if (state->srate <= 15000000)
  2399. aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
  2400. else if (state->srate <= 25000000)
  2401. aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
  2402. else
  2403. aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
  2404. }
  2405. } else if (modcod <= STV090x_8PSK_910) {
  2406. if (pilots) {
  2407. if (state->srate <= 3000000)
  2408. aclc = car_loop[i].crl_pilots_on_2;
  2409. else if (state->srate <= 7000000)
  2410. aclc = car_loop[i].crl_pilots_on_5;
  2411. else if (state->srate <= 15000000)
  2412. aclc = car_loop[i].crl_pilots_on_10;
  2413. else if (state->srate <= 25000000)
  2414. aclc = car_loop[i].crl_pilots_on_20;
  2415. else
  2416. aclc = car_loop[i].crl_pilots_on_30;
  2417. } else {
  2418. if (state->srate <= 3000000)
  2419. aclc = car_loop[i].crl_pilots_off_2;
  2420. else if (state->srate <= 7000000)
  2421. aclc = car_loop[i].crl_pilots_off_5;
  2422. else if (state->srate <= 15000000)
  2423. aclc = car_loop[i].crl_pilots_off_10;
  2424. else if (state->srate <= 25000000)
  2425. aclc = car_loop[i].crl_pilots_off_20;
  2426. else
  2427. aclc = car_loop[i].crl_pilots_off_30;
  2428. }
  2429. } else { /* 16APSK and 32APSK */
  2430. if (state->srate <= 3000000)
  2431. aclc = car_loop_apsk_low[i].crl_pilots_on_2;
  2432. else if (state->srate <= 7000000)
  2433. aclc = car_loop_apsk_low[i].crl_pilots_on_5;
  2434. else if (state->srate <= 15000000)
  2435. aclc = car_loop_apsk_low[i].crl_pilots_on_10;
  2436. else if (state->srate <= 25000000)
  2437. aclc = car_loop_apsk_low[i].crl_pilots_on_20;
  2438. else
  2439. aclc = car_loop_apsk_low[i].crl_pilots_on_30;
  2440. }
  2441. return aclc;
  2442. }
  2443. static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
  2444. {
  2445. struct stv090x_short_frame_crloop *short_crl = NULL;
  2446. s32 index = 0;
  2447. u8 aclc = 0x0b;
  2448. switch (state->modulation) {
  2449. case STV090x_QPSK:
  2450. default:
  2451. index = 0;
  2452. break;
  2453. case STV090x_8PSK:
  2454. index = 1;
  2455. break;
  2456. case STV090x_16APSK:
  2457. index = 2;
  2458. break;
  2459. case STV090x_32APSK:
  2460. index = 3;
  2461. break;
  2462. }
  2463. if (state->internal->dev_ver >= 0x30) {
  2464. /* Cut 3.0 and up */
  2465. short_crl = stv090x_s2_short_crl_cut30;
  2466. } else {
  2467. /* Cut 2.0 and up: we don't support cuts older than 2.0 */
  2468. short_crl = stv090x_s2_short_crl_cut20;
  2469. }
  2470. if (state->srate <= 3000000)
  2471. aclc = short_crl[index].crl_2;
  2472. else if (state->srate <= 7000000)
  2473. aclc = short_crl[index].crl_5;
  2474. else if (state->srate <= 15000000)
  2475. aclc = short_crl[index].crl_10;
  2476. else if (state->srate <= 25000000)
  2477. aclc = short_crl[index].crl_20;
  2478. else
  2479. aclc = short_crl[index].crl_30;
  2480. return aclc;
  2481. }
  2482. static int stv090x_optimize_track(struct stv090x_state *state)
  2483. {
  2484. struct dvb_frontend *fe = &state->frontend;
  2485. enum stv090x_rolloff rolloff;
  2486. enum stv090x_modcod modcod;
  2487. s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
  2488. u32 reg;
  2489. srate = stv090x_get_srate(state, state->internal->mclk);
  2490. srate += stv090x_get_tmgoffst(state, srate);
  2491. switch (state->delsys) {
  2492. case STV090x_DVBS1:
  2493. case STV090x_DSS:
  2494. if (state->search_mode == STV090x_SEARCH_AUTO) {
  2495. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2496. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2497. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  2498. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2499. goto err;
  2500. }
  2501. reg = STV090x_READ_DEMOD(state, DEMOD);
  2502. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
  2503. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
  2504. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2505. goto err;
  2506. if (state->internal->dev_ver >= 0x30) {
  2507. if (stv090x_get_viterbi(state) < 0)
  2508. goto err;
  2509. if (state->fec == STV090x_PR12) {
  2510. if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
  2511. goto err;
  2512. if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
  2513. goto err;
  2514. } else {
  2515. if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
  2516. goto err;
  2517. if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
  2518. goto err;
  2519. }
  2520. }
  2521. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
  2522. goto err;
  2523. break;
  2524. case STV090x_DVBS2:
  2525. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2526. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  2527. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  2528. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2529. goto err;
  2530. if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
  2531. goto err;
  2532. if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
  2533. goto err;
  2534. if (state->frame_len == STV090x_LONG_FRAME) {
  2535. reg = STV090x_READ_DEMOD(state, DMDMODCOD);
  2536. modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
  2537. pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
  2538. aclc = stv090x_optimize_carloop(state, modcod, pilots);
  2539. if (modcod <= STV090x_QPSK_910) {
  2540. STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
  2541. } else if (modcod <= STV090x_8PSK_910) {
  2542. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2543. goto err;
  2544. if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
  2545. goto err;
  2546. }
  2547. if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
  2548. if (modcod <= STV090x_16APSK_910) {
  2549. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2550. goto err;
  2551. if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
  2552. goto err;
  2553. } else {
  2554. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2555. goto err;
  2556. if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
  2557. goto err;
  2558. }
  2559. }
  2560. } else {
  2561. /*Carrier loop setting for short frame*/
  2562. aclc = stv090x_optimize_carloop_short(state);
  2563. if (state->modulation == STV090x_QPSK) {
  2564. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
  2565. goto err;
  2566. } else if (state->modulation == STV090x_8PSK) {
  2567. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2568. goto err;
  2569. if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
  2570. goto err;
  2571. } else if (state->modulation == STV090x_16APSK) {
  2572. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2573. goto err;
  2574. if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
  2575. goto err;
  2576. } else if (state->modulation == STV090x_32APSK) {
  2577. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2578. goto err;
  2579. if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
  2580. goto err;
  2581. }
  2582. }
  2583. STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
  2584. break;
  2585. case STV090x_UNKNOWN:
  2586. default:
  2587. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2588. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2589. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  2590. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2591. goto err;
  2592. break;
  2593. }
  2594. f_1 = STV090x_READ_DEMOD(state, CFR2);
  2595. f_0 = STV090x_READ_DEMOD(state, CFR1);
  2596. reg = STV090x_READ_DEMOD(state, TMGOBS);
  2597. rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
  2598. if (state->algo == STV090x_BLIND_SEARCH) {
  2599. STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
  2600. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2601. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
  2602. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
  2603. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2604. goto err;
  2605. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
  2606. goto err;
  2607. if (stv090x_set_srate(state, srate) < 0)
  2608. goto err;
  2609. blind_tune = 1;
  2610. if (stv090x_dvbs_track_crl(state) < 0)
  2611. goto err;
  2612. }
  2613. if (state->internal->dev_ver >= 0x20) {
  2614. if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
  2615. (state->search_mode == STV090x_SEARCH_DSS) ||
  2616. (state->search_mode == STV090x_SEARCH_AUTO)) {
  2617. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
  2618. goto err;
  2619. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
  2620. goto err;
  2621. }
  2622. }
  2623. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  2624. goto err;
  2625. /* AUTO tracking MODE */
  2626. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
  2627. goto err;
  2628. /* AUTO tracking MODE */
  2629. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
  2630. goto err;
  2631. if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
  2632. (state->srate < 10000000)) {
  2633. /* update initial carrier freq with the found freq offset */
  2634. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2635. goto err;
  2636. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2637. goto err;
  2638. state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
  2639. if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
  2640. if (state->algo != STV090x_WARM_SEARCH) {
  2641. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2642. goto err;
  2643. if (state->config->tuner_set_bandwidth) {
  2644. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  2645. goto err_gateoff;
  2646. }
  2647. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2648. goto err;
  2649. }
  2650. }
  2651. if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
  2652. msleep(50); /* blind search: wait 50ms for SR stabilization */
  2653. else
  2654. msleep(5);
  2655. stv090x_get_lock_tmg(state);
  2656. if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
  2657. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  2658. goto err;
  2659. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2660. goto err;
  2661. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2662. goto err;
  2663. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2664. goto err;
  2665. i = 0;
  2666. while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
  2667. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  2668. goto err;
  2669. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2670. goto err;
  2671. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2672. goto err;
  2673. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2674. goto err;
  2675. i++;
  2676. }
  2677. }
  2678. }
  2679. if (state->internal->dev_ver >= 0x20) {
  2680. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  2681. goto err;
  2682. }
  2683. if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
  2684. stv090x_set_vit_thtracq(state);
  2685. return 0;
  2686. err_gateoff:
  2687. stv090x_i2c_gate_ctrl(fe, 0);
  2688. err:
  2689. dprintk(FE_ERROR, 1, "I/O error");
  2690. return -1;
  2691. }
  2692. static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
  2693. {
  2694. s32 timer = 0, lock = 0, stat;
  2695. u32 reg;
  2696. while ((timer < timeout) && (!lock)) {
  2697. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2698. stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  2699. switch (stat) {
  2700. case 0: /* searching */
  2701. case 1: /* first PLH detected */
  2702. default:
  2703. lock = 0;
  2704. break;
  2705. case 2: /* DVB-S2 mode */
  2706. reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
  2707. lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
  2708. break;
  2709. case 3: /* DVB-S1/legacy mode */
  2710. reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
  2711. lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
  2712. break;
  2713. }
  2714. if (!lock) {
  2715. msleep(10);
  2716. timer += 10;
  2717. }
  2718. }
  2719. return lock;
  2720. }
  2721. static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
  2722. {
  2723. u32 reg;
  2724. s32 timer = 0;
  2725. int lock;
  2726. lock = stv090x_get_dmdlock(state, timeout_dmd);
  2727. if (lock)
  2728. lock = stv090x_get_feclock(state, timeout_fec);
  2729. if (lock) {
  2730. lock = 0;
  2731. while ((timer < timeout_fec) && (!lock)) {
  2732. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  2733. lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
  2734. msleep(1);
  2735. timer++;
  2736. }
  2737. }
  2738. return lock;
  2739. }
  2740. static int stv090x_set_s2rolloff(struct stv090x_state *state)
  2741. {
  2742. u32 reg;
  2743. if (state->internal->dev_ver <= 0x20) {
  2744. /* rolloff to auto mode if DVBS2 */
  2745. reg = STV090x_READ_DEMOD(state, DEMOD);
  2746. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
  2747. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2748. goto err;
  2749. } else {
  2750. /* DVB-S2 rolloff to auto mode if DVBS2 */
  2751. reg = STV090x_READ_DEMOD(state, DEMOD);
  2752. STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
  2753. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2754. goto err;
  2755. }
  2756. return 0;
  2757. err:
  2758. dprintk(FE_ERROR, 1, "I/O error");
  2759. return -1;
  2760. }
  2761. static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
  2762. {
  2763. struct dvb_frontend *fe = &state->frontend;
  2764. enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
  2765. u32 reg;
  2766. s32 agc1_power, power_iq = 0, i;
  2767. int lock = 0, low_sr = 0, no_signal = 0;
  2768. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2769. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
  2770. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2771. goto err;
  2772. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
  2773. goto err;
  2774. if (state->internal->dev_ver >= 0x20) {
  2775. if (state->srate > 5000000) {
  2776. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
  2777. goto err;
  2778. } else {
  2779. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
  2780. goto err;
  2781. }
  2782. }
  2783. stv090x_get_lock_tmg(state);
  2784. if (state->algo == STV090x_BLIND_SEARCH) {
  2785. state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
  2786. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
  2787. goto err;
  2788. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
  2789. goto err;
  2790. if (stv090x_set_srate(state, 1000000) < 0) /* inital srate = 1Msps */
  2791. goto err;
  2792. } else {
  2793. /* known srate */
  2794. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
  2795. goto err;
  2796. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
  2797. goto err;
  2798. if (state->srate < 2000000) {
  2799. /* SR < 2MSPS */
  2800. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
  2801. goto err;
  2802. } else {
  2803. /* SR >= 2Msps */
  2804. if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
  2805. goto err;
  2806. }
  2807. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  2808. goto err;
  2809. if (state->internal->dev_ver >= 0x20) {
  2810. if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
  2811. goto err;
  2812. if (state->algo == STV090x_COLD_SEARCH)
  2813. state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
  2814. else if (state->algo == STV090x_WARM_SEARCH)
  2815. state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
  2816. }
  2817. /* if cold start or warm (Symbolrate is known)
  2818. * use a Narrow symbol rate scan range
  2819. */
  2820. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
  2821. goto err;
  2822. if (stv090x_set_srate(state, state->srate) < 0)
  2823. goto err;
  2824. if (stv090x_set_max_srate(state, state->internal->mclk,
  2825. state->srate) < 0)
  2826. goto err;
  2827. if (stv090x_set_min_srate(state, state->internal->mclk,
  2828. state->srate) < 0)
  2829. goto err;
  2830. if (state->srate >= 10000000)
  2831. low_sr = 0;
  2832. else
  2833. low_sr = 1;
  2834. }
  2835. /* Setup tuner */
  2836. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2837. goto err;
  2838. if (state->config->tuner_set_bbgain) {
  2839. reg = state->config->tuner_bbgain;
  2840. if (reg == 0)
  2841. reg = 10; /* default: 10dB */
  2842. if (state->config->tuner_set_bbgain(fe, reg) < 0)
  2843. goto err_gateoff;
  2844. }
  2845. if (state->config->tuner_set_frequency) {
  2846. if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
  2847. goto err_gateoff;
  2848. }
  2849. if (state->config->tuner_set_bandwidth) {
  2850. if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
  2851. goto err_gateoff;
  2852. }
  2853. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2854. goto err;
  2855. msleep(50);
  2856. if (state->config->tuner_get_status) {
  2857. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  2858. goto err;
  2859. if (state->config->tuner_get_status(fe, &reg) < 0)
  2860. goto err_gateoff;
  2861. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  2862. goto err;
  2863. if (reg)
  2864. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  2865. else {
  2866. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  2867. return STV090x_NOCARRIER;
  2868. }
  2869. }
  2870. msleep(10);
  2871. agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
  2872. STV090x_READ_DEMOD(state, AGCIQIN0));
  2873. if (agc1_power == 0) {
  2874. /* If AGC1 integrator value is 0
  2875. * then read POWERI, POWERQ
  2876. */
  2877. for (i = 0; i < 5; i++) {
  2878. power_iq += (STV090x_READ_DEMOD(state, POWERI) +
  2879. STV090x_READ_DEMOD(state, POWERQ)) >> 1;
  2880. }
  2881. power_iq /= 5;
  2882. }
  2883. if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
  2884. dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
  2885. lock = 0;
  2886. signal_state = STV090x_NOAGC1;
  2887. } else {
  2888. reg = STV090x_READ_DEMOD(state, DEMOD);
  2889. STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
  2890. if (state->internal->dev_ver <= 0x20) {
  2891. /* rolloff to auto mode if DVBS2 */
  2892. STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
  2893. } else {
  2894. /* DVB-S2 rolloff to auto mode if DVBS2 */
  2895. STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
  2896. }
  2897. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2898. goto err;
  2899. if (stv090x_delivery_search(state) < 0)
  2900. goto err;
  2901. if (state->algo != STV090x_BLIND_SEARCH) {
  2902. if (stv090x_start_search(state) < 0)
  2903. goto err;
  2904. }
  2905. }
  2906. if (signal_state == STV090x_NOAGC1)
  2907. return signal_state;
  2908. if (state->algo == STV090x_BLIND_SEARCH)
  2909. lock = stv090x_blind_search(state);
  2910. else if (state->algo == STV090x_COLD_SEARCH)
  2911. lock = stv090x_get_coldlock(state, state->DemodTimeout);
  2912. else if (state->algo == STV090x_WARM_SEARCH)
  2913. lock = stv090x_get_dmdlock(state, state->DemodTimeout);
  2914. if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
  2915. if (!low_sr) {
  2916. if (stv090x_chk_tmg(state))
  2917. lock = stv090x_sw_algo(state);
  2918. }
  2919. }
  2920. if (lock)
  2921. signal_state = stv090x_get_sig_params(state);
  2922. if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
  2923. stv090x_optimize_track(state);
  2924. if (state->internal->dev_ver >= 0x20) {
  2925. /* >= Cut 2.0 :release TS reset after
  2926. * demod lock and optimized Tracking
  2927. */
  2928. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2929. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2930. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2931. goto err;
  2932. msleep(3);
  2933. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
  2934. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2935. goto err;
  2936. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2937. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2938. goto err;
  2939. }
  2940. lock = stv090x_get_lock(state, state->FecTimeout,
  2941. state->FecTimeout);
  2942. if (lock) {
  2943. if (state->delsys == STV090x_DVBS2) {
  2944. stv090x_set_s2rolloff(state);
  2945. reg = STV090x_READ_DEMOD(state, PDELCTRL2);
  2946. STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
  2947. if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
  2948. goto err;
  2949. /* Reset DVBS2 packet delinator error counter */
  2950. reg = STV090x_READ_DEMOD(state, PDELCTRL2);
  2951. STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
  2952. if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
  2953. goto err;
  2954. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
  2955. goto err;
  2956. } else {
  2957. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
  2958. goto err;
  2959. }
  2960. /* Reset the Total packet counter */
  2961. if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
  2962. goto err;
  2963. /* Reset the packet Error counter2 */
  2964. if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
  2965. goto err;
  2966. } else {
  2967. signal_state = STV090x_NODATA;
  2968. no_signal = stv090x_chk_signal(state);
  2969. }
  2970. }
  2971. return signal_state;
  2972. err_gateoff:
  2973. stv090x_i2c_gate_ctrl(fe, 0);
  2974. err:
  2975. dprintk(FE_ERROR, 1, "I/O error");
  2976. return -1;
  2977. }
  2978. static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
  2979. {
  2980. struct stv090x_state *state = fe->demodulator_priv;
  2981. struct dtv_frontend_properties *props = &fe->dtv_property_cache;
  2982. if (p->frequency == 0)
  2983. return DVBFE_ALGO_SEARCH_INVALID;
  2984. state->delsys = props->delivery_system;
  2985. state->frequency = p->frequency;
  2986. state->srate = p->u.qpsk.symbol_rate;
  2987. state->search_mode = STV090x_SEARCH_AUTO;
  2988. state->algo = STV090x_COLD_SEARCH;
  2989. state->fec = STV090x_PRERR;
  2990. if (state->srate > 10000000) {
  2991. dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
  2992. state->search_range = 10000000;
  2993. } else {
  2994. dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
  2995. state->search_range = 5000000;
  2996. }
  2997. if (stv090x_algo(state) == STV090x_RANGEOK) {
  2998. dprintk(FE_DEBUG, 1, "Search success!");
  2999. return DVBFE_ALGO_SEARCH_SUCCESS;
  3000. } else {
  3001. dprintk(FE_DEBUG, 1, "Search failed!");
  3002. return DVBFE_ALGO_SEARCH_FAILED;
  3003. }
  3004. return DVBFE_ALGO_SEARCH_ERROR;
  3005. }
  3006. static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
  3007. {
  3008. struct stv090x_state *state = fe->demodulator_priv;
  3009. u32 reg;
  3010. u8 search_state;
  3011. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  3012. search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  3013. switch (search_state) {
  3014. case 0: /* searching */
  3015. case 1: /* first PLH detected */
  3016. default:
  3017. dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
  3018. *status = 0;
  3019. break;
  3020. case 2: /* DVB-S2 mode */
  3021. dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
  3022. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3023. if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
  3024. reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
  3025. if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
  3026. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  3027. if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
  3028. *status = FE_HAS_SIGNAL |
  3029. FE_HAS_CARRIER |
  3030. FE_HAS_VITERBI |
  3031. FE_HAS_SYNC |
  3032. FE_HAS_LOCK;
  3033. }
  3034. }
  3035. }
  3036. break;
  3037. case 3: /* DVB-S1/legacy mode */
  3038. dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
  3039. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3040. if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
  3041. reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
  3042. if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
  3043. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  3044. if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
  3045. *status = FE_HAS_SIGNAL |
  3046. FE_HAS_CARRIER |
  3047. FE_HAS_VITERBI |
  3048. FE_HAS_SYNC |
  3049. FE_HAS_LOCK;
  3050. }
  3051. }
  3052. }
  3053. break;
  3054. }
  3055. return 0;
  3056. }
  3057. static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
  3058. {
  3059. struct stv090x_state *state = fe->demodulator_priv;
  3060. s32 count_4, count_3, count_2, count_1, count_0, count;
  3061. u32 reg, h, m, l;
  3062. enum fe_status status;
  3063. stv090x_read_status(fe, &status);
  3064. if (!(status & FE_HAS_LOCK)) {
  3065. *per = 1 << 23; /* Max PER */
  3066. } else {
  3067. /* Counter 2 */
  3068. reg = STV090x_READ_DEMOD(state, ERRCNT22);
  3069. h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
  3070. reg = STV090x_READ_DEMOD(state, ERRCNT21);
  3071. m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
  3072. reg = STV090x_READ_DEMOD(state, ERRCNT20);
  3073. l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
  3074. *per = ((h << 16) | (m << 8) | l);
  3075. count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
  3076. count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
  3077. count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
  3078. count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
  3079. count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
  3080. if ((!count_4) && (!count_3)) {
  3081. count = (count_2 & 0xff) << 16;
  3082. count |= (count_1 & 0xff) << 8;
  3083. count |= count_0 & 0xff;
  3084. } else {
  3085. count = 1 << 24;
  3086. }
  3087. if (count == 0)
  3088. *per = 1;
  3089. }
  3090. if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
  3091. goto err;
  3092. if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
  3093. goto err;
  3094. return 0;
  3095. err:
  3096. dprintk(FE_ERROR, 1, "I/O error");
  3097. return -1;
  3098. }
  3099. static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
  3100. {
  3101. int res = 0;
  3102. int min = 0, med;
  3103. if ((val >= tab[min].read && val < tab[max].read) ||
  3104. (val >= tab[max].read && val < tab[min].read)) {
  3105. while ((max - min) > 1) {
  3106. med = (max + min) / 2;
  3107. if ((val >= tab[min].read && val < tab[med].read) ||
  3108. (val >= tab[med].read && val < tab[min].read))
  3109. max = med;
  3110. else
  3111. min = med;
  3112. }
  3113. res = ((val - tab[min].read) *
  3114. (tab[max].real - tab[min].real) /
  3115. (tab[max].read - tab[min].read)) +
  3116. tab[min].real;
  3117. } else {
  3118. if (tab[min].read < tab[max].read) {
  3119. if (val < tab[min].read)
  3120. res = tab[min].real;
  3121. else if (val >= tab[max].read)
  3122. res = tab[max].real;
  3123. } else {
  3124. if (val >= tab[min].read)
  3125. res = tab[min].real;
  3126. else if (val < tab[max].read)
  3127. res = tab[max].real;
  3128. }
  3129. }
  3130. return res;
  3131. }
  3132. static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
  3133. {
  3134. struct stv090x_state *state = fe->demodulator_priv;
  3135. u32 reg;
  3136. s32 agc_0, agc_1, agc;
  3137. s32 str;
  3138. reg = STV090x_READ_DEMOD(state, AGCIQIN1);
  3139. agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
  3140. reg = STV090x_READ_DEMOD(state, AGCIQIN0);
  3141. agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
  3142. agc = MAKEWORD16(agc_1, agc_0);
  3143. str = stv090x_table_lookup(stv090x_rf_tab,
  3144. ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
  3145. if (agc > stv090x_rf_tab[0].read)
  3146. str = 0;
  3147. else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
  3148. str = -100;
  3149. *strength = (str + 100) * 0xFFFF / 100;
  3150. return 0;
  3151. }
  3152. static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
  3153. {
  3154. struct stv090x_state *state = fe->demodulator_priv;
  3155. u32 reg_0, reg_1, reg, i;
  3156. s32 val_0, val_1, val = 0;
  3157. u8 lock_f;
  3158. s32 div;
  3159. u32 last;
  3160. switch (state->delsys) {
  3161. case STV090x_DVBS2:
  3162. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3163. lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  3164. if (lock_f) {
  3165. msleep(5);
  3166. for (i = 0; i < 16; i++) {
  3167. reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
  3168. val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
  3169. reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
  3170. val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
  3171. val += MAKEWORD16(val_1, val_0);
  3172. msleep(1);
  3173. }
  3174. val /= 16;
  3175. last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
  3176. div = stv090x_s2cn_tab[0].read -
  3177. stv090x_s2cn_tab[last].read;
  3178. *cnr = 0xFFFF - ((val * 0xFFFF) / div);
  3179. }
  3180. break;
  3181. case STV090x_DVBS1:
  3182. case STV090x_DSS:
  3183. reg = STV090x_READ_DEMOD(state, DSTATUS);
  3184. lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  3185. if (lock_f) {
  3186. msleep(5);
  3187. for (i = 0; i < 16; i++) {
  3188. reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
  3189. val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
  3190. reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
  3191. val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
  3192. val += MAKEWORD16(val_1, val_0);
  3193. msleep(1);
  3194. }
  3195. val /= 16;
  3196. last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
  3197. div = stv090x_s1cn_tab[0].read -
  3198. stv090x_s1cn_tab[last].read;
  3199. *cnr = 0xFFFF - ((val * 0xFFFF) / div);
  3200. }
  3201. break;
  3202. default:
  3203. break;
  3204. }
  3205. return 0;
  3206. }
  3207. static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
  3208. {
  3209. struct stv090x_state *state = fe->demodulator_priv;
  3210. u32 reg;
  3211. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3212. switch (tone) {
  3213. case SEC_TONE_ON:
  3214. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
  3215. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3216. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3217. goto err;
  3218. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3219. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3220. goto err;
  3221. break;
  3222. case SEC_TONE_OFF:
  3223. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
  3224. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3225. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3226. goto err;
  3227. break;
  3228. default:
  3229. return -EINVAL;
  3230. }
  3231. return 0;
  3232. err:
  3233. dprintk(FE_ERROR, 1, "I/O error");
  3234. return -1;
  3235. }
  3236. static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
  3237. {
  3238. return DVBFE_ALGO_CUSTOM;
  3239. }
  3240. static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
  3241. {
  3242. struct stv090x_state *state = fe->demodulator_priv;
  3243. u32 reg, idle = 0, fifo_full = 1;
  3244. int i;
  3245. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3246. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
  3247. (state->config->diseqc_envelope_mode) ? 4 : 2);
  3248. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3249. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3250. goto err;
  3251. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3252. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3253. goto err;
  3254. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
  3255. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3256. goto err;
  3257. for (i = 0; i < cmd->msg_len; i++) {
  3258. while (fifo_full) {
  3259. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3260. fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
  3261. }
  3262. if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
  3263. goto err;
  3264. }
  3265. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3266. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
  3267. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3268. goto err;
  3269. i = 0;
  3270. while ((!idle) && (i < 10)) {
  3271. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3272. idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
  3273. msleep(10);
  3274. i++;
  3275. }
  3276. return 0;
  3277. err:
  3278. dprintk(FE_ERROR, 1, "I/O error");
  3279. return -1;
  3280. }
  3281. static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
  3282. {
  3283. struct stv090x_state *state = fe->demodulator_priv;
  3284. u32 reg, idle = 0, fifo_full = 1;
  3285. u8 mode, value;
  3286. int i;
  3287. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3288. if (burst == SEC_MINI_A) {
  3289. mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
  3290. value = 0x00;
  3291. } else {
  3292. mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
  3293. value = 0xFF;
  3294. }
  3295. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
  3296. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3297. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3298. goto err;
  3299. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3300. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3301. goto err;
  3302. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
  3303. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3304. goto err;
  3305. while (fifo_full) {
  3306. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3307. fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
  3308. }
  3309. if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
  3310. goto err;
  3311. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3312. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
  3313. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3314. goto err;
  3315. i = 0;
  3316. while ((!idle) && (i < 10)) {
  3317. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3318. idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
  3319. msleep(10);
  3320. i++;
  3321. }
  3322. return 0;
  3323. err:
  3324. dprintk(FE_ERROR, 1, "I/O error");
  3325. return -1;
  3326. }
  3327. static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
  3328. {
  3329. struct stv090x_state *state = fe->demodulator_priv;
  3330. u32 reg = 0, i = 0, rx_end = 0;
  3331. while ((rx_end != 1) && (i < 10)) {
  3332. msleep(10);
  3333. i++;
  3334. reg = STV090x_READ_DEMOD(state, DISRX_ST0);
  3335. rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
  3336. }
  3337. if (rx_end) {
  3338. reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
  3339. for (i = 0; i < reply->msg_len; i++)
  3340. reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
  3341. }
  3342. return 0;
  3343. }
  3344. static int stv090x_sleep(struct dvb_frontend *fe)
  3345. {
  3346. struct stv090x_state *state = fe->demodulator_priv;
  3347. u32 reg;
  3348. dprintk(FE_DEBUG, 1, "Set %s to sleep",
  3349. state->device == STV0900 ? "STV0900" : "STV0903");
  3350. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3351. STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
  3352. if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
  3353. goto err;
  3354. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3355. STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
  3356. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3357. goto err;
  3358. return 0;
  3359. err:
  3360. dprintk(FE_ERROR, 1, "I/O error");
  3361. return -1;
  3362. }
  3363. static int stv090x_wakeup(struct dvb_frontend *fe)
  3364. {
  3365. struct stv090x_state *state = fe->demodulator_priv;
  3366. u32 reg;
  3367. dprintk(FE_DEBUG, 1, "Wake %s from standby",
  3368. state->device == STV0900 ? "STV0900" : "STV0903");
  3369. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3370. STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
  3371. if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
  3372. goto err;
  3373. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3374. STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
  3375. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3376. goto err;
  3377. return 0;
  3378. err:
  3379. dprintk(FE_ERROR, 1, "I/O error");
  3380. return -1;
  3381. }
  3382. static void stv090x_release(struct dvb_frontend *fe)
  3383. {
  3384. struct stv090x_state *state = fe->demodulator_priv;
  3385. state->internal->num_used--;
  3386. if (state->internal->num_used <= 0) {
  3387. dprintk(FE_ERROR, 1, "Actually removing");
  3388. remove_dev(state->internal);
  3389. kfree(state->internal);
  3390. }
  3391. kfree(state);
  3392. }
  3393. static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
  3394. {
  3395. u32 reg = 0;
  3396. reg = stv090x_read_reg(state, STV090x_GENCFG);
  3397. switch (ldpc_mode) {
  3398. case STV090x_DUAL:
  3399. default:
  3400. if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
  3401. /* set LDPC to dual mode */
  3402. if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
  3403. goto err;
  3404. state->demod_mode = STV090x_DUAL;
  3405. reg = stv090x_read_reg(state, STV090x_TSTRES0);
  3406. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
  3407. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3408. goto err;
  3409. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
  3410. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3411. goto err;
  3412. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  3413. goto err;
  3414. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
  3415. goto err;
  3416. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
  3417. goto err;
  3418. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
  3419. goto err;
  3420. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
  3421. goto err;
  3422. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
  3423. goto err;
  3424. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
  3425. goto err;
  3426. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
  3427. goto err;
  3428. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
  3429. goto err;
  3430. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
  3431. goto err;
  3432. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
  3433. goto err;
  3434. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
  3435. goto err;
  3436. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
  3437. goto err;
  3438. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
  3439. goto err;
  3440. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
  3441. goto err;
  3442. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
  3443. goto err;
  3444. }
  3445. break;
  3446. case STV090x_SINGLE:
  3447. if (stv090x_stop_modcod(state) < 0)
  3448. goto err;
  3449. if (stv090x_activate_modcod_single(state) < 0)
  3450. goto err;
  3451. if (state->demod == STV090x_DEMODULATOR_1) {
  3452. if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
  3453. goto err;
  3454. } else {
  3455. if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
  3456. goto err;
  3457. }
  3458. reg = stv090x_read_reg(state, STV090x_TSTRES0);
  3459. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
  3460. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3461. goto err;
  3462. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
  3463. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3464. goto err;
  3465. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  3466. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
  3467. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3468. goto err;
  3469. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
  3470. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3471. goto err;
  3472. break;
  3473. }
  3474. return 0;
  3475. err:
  3476. dprintk(FE_ERROR, 1, "I/O error");
  3477. return -1;
  3478. }
  3479. /* return (Hz), clk in Hz*/
  3480. static u32 stv090x_get_mclk(struct stv090x_state *state)
  3481. {
  3482. const struct stv090x_config *config = state->config;
  3483. u32 div, reg;
  3484. u8 ratio;
  3485. div = stv090x_read_reg(state, STV090x_NCOARSE);
  3486. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3487. ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
  3488. return (div + 1) * config->xtal / ratio; /* kHz */
  3489. }
  3490. static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
  3491. {
  3492. const struct stv090x_config *config = state->config;
  3493. u32 reg, div, clk_sel;
  3494. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3495. clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
  3496. div = ((clk_sel * mclk) / config->xtal) - 1;
  3497. reg = stv090x_read_reg(state, STV090x_NCOARSE);
  3498. STV090x_SETFIELD(reg, M_DIV_FIELD, div);
  3499. if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
  3500. goto err;
  3501. state->internal->mclk = stv090x_get_mclk(state);
  3502. /*Set the DiseqC frequency to 22KHz */
  3503. div = state->internal->mclk / 704000;
  3504. if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
  3505. goto err;
  3506. if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
  3507. goto err;
  3508. return 0;
  3509. err:
  3510. dprintk(FE_ERROR, 1, "I/O error");
  3511. return -1;
  3512. }
  3513. static int stv090x_set_tspath(struct stv090x_state *state)
  3514. {
  3515. u32 reg;
  3516. if (state->internal->dev_ver >= 0x20) {
  3517. switch (state->config->ts1_mode) {
  3518. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3519. case STV090x_TSMODE_DVBCI:
  3520. switch (state->config->ts2_mode) {
  3521. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3522. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3523. default:
  3524. stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
  3525. break;
  3526. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3527. case STV090x_TSMODE_DVBCI:
  3528. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
  3529. goto err;
  3530. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3531. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3532. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3533. goto err;
  3534. reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
  3535. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3536. if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
  3537. goto err;
  3538. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
  3539. goto err;
  3540. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
  3541. goto err;
  3542. break;
  3543. }
  3544. break;
  3545. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3546. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3547. default:
  3548. switch (state->config->ts2_mode) {
  3549. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3550. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3551. default:
  3552. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
  3553. goto err;
  3554. break;
  3555. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3556. case STV090x_TSMODE_DVBCI:
  3557. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
  3558. goto err;
  3559. break;
  3560. }
  3561. break;
  3562. }
  3563. } else {
  3564. switch (state->config->ts1_mode) {
  3565. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3566. case STV090x_TSMODE_DVBCI:
  3567. switch (state->config->ts2_mode) {
  3568. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3569. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3570. default:
  3571. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
  3572. break;
  3573. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3574. case STV090x_TSMODE_DVBCI:
  3575. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
  3576. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3577. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3578. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3579. goto err;
  3580. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3581. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
  3582. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3583. goto err;
  3584. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
  3585. goto err;
  3586. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
  3587. goto err;
  3588. break;
  3589. }
  3590. break;
  3591. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3592. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3593. default:
  3594. switch (state->config->ts2_mode) {
  3595. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3596. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3597. default:
  3598. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
  3599. break;
  3600. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3601. case STV090x_TSMODE_DVBCI:
  3602. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
  3603. break;
  3604. }
  3605. break;
  3606. }
  3607. }
  3608. switch (state->config->ts1_mode) {
  3609. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3610. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3611. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3612. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3613. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3614. goto err;
  3615. break;
  3616. case STV090x_TSMODE_DVBCI:
  3617. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3618. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3619. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3620. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3621. goto err;
  3622. break;
  3623. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3624. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3625. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3626. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3627. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3628. goto err;
  3629. break;
  3630. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3631. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3632. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3633. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3634. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3635. goto err;
  3636. break;
  3637. default:
  3638. break;
  3639. }
  3640. switch (state->config->ts2_mode) {
  3641. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3642. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3643. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3644. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3645. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3646. goto err;
  3647. break;
  3648. case STV090x_TSMODE_DVBCI:
  3649. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3650. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3651. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3652. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3653. goto err;
  3654. break;
  3655. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3656. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3657. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3658. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3659. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3660. goto err;
  3661. break;
  3662. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3663. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3664. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3665. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3666. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3667. goto err;
  3668. break;
  3669. default:
  3670. break;
  3671. }
  3672. if (state->config->ts1_clk > 0) {
  3673. u32 speed;
  3674. switch (state->config->ts1_mode) {
  3675. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3676. case STV090x_TSMODE_DVBCI:
  3677. default:
  3678. speed = state->internal->mclk /
  3679. (state->config->ts1_clk / 4);
  3680. if (speed < 0x08)
  3681. speed = 0x08;
  3682. if (speed > 0xFF)
  3683. speed = 0xFF;
  3684. break;
  3685. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3686. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3687. speed = state->internal->mclk /
  3688. (state->config->ts1_clk / 32);
  3689. if (speed < 0x20)
  3690. speed = 0x20;
  3691. if (speed > 0xFF)
  3692. speed = 0xFF;
  3693. break;
  3694. }
  3695. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3696. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3697. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3698. goto err;
  3699. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
  3700. goto err;
  3701. }
  3702. if (state->config->ts2_clk > 0) {
  3703. u32 speed;
  3704. switch (state->config->ts2_mode) {
  3705. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3706. case STV090x_TSMODE_DVBCI:
  3707. default:
  3708. speed = state->internal->mclk /
  3709. (state->config->ts2_clk / 4);
  3710. if (speed < 0x08)
  3711. speed = 0x08;
  3712. if (speed > 0xFF)
  3713. speed = 0xFF;
  3714. break;
  3715. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3716. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3717. speed = state->internal->mclk /
  3718. (state->config->ts2_clk / 32);
  3719. if (speed < 0x20)
  3720. speed = 0x20;
  3721. if (speed > 0xFF)
  3722. speed = 0xFF;
  3723. break;
  3724. }
  3725. reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
  3726. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3727. if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
  3728. goto err;
  3729. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
  3730. goto err;
  3731. }
  3732. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3733. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  3734. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3735. goto err;
  3736. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  3737. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3738. goto err;
  3739. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3740. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  3741. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3742. goto err;
  3743. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  3744. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3745. goto err;
  3746. return 0;
  3747. err:
  3748. dprintk(FE_ERROR, 1, "I/O error");
  3749. return -1;
  3750. }
  3751. static int stv090x_init(struct dvb_frontend *fe)
  3752. {
  3753. struct stv090x_state *state = fe->demodulator_priv;
  3754. const struct stv090x_config *config = state->config;
  3755. u32 reg;
  3756. if (state->internal->mclk == 0) {
  3757. stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
  3758. msleep(5);
  3759. if (stv090x_write_reg(state, STV090x_SYNTCTRL,
  3760. 0x20 | config->clk_mode) < 0)
  3761. goto err;
  3762. stv090x_get_mclk(state);
  3763. }
  3764. if (stv090x_wakeup(fe) < 0) {
  3765. dprintk(FE_ERROR, 1, "Error waking device");
  3766. goto err;
  3767. }
  3768. if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
  3769. goto err;
  3770. reg = STV090x_READ_DEMOD(state, TNRCFG2);
  3771. STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
  3772. if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
  3773. goto err;
  3774. reg = STV090x_READ_DEMOD(state, DEMOD);
  3775. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
  3776. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  3777. goto err;
  3778. if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
  3779. goto err;
  3780. if (config->tuner_set_mode) {
  3781. if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
  3782. goto err_gateoff;
  3783. }
  3784. if (config->tuner_init) {
  3785. if (config->tuner_init(fe) < 0)
  3786. goto err_gateoff;
  3787. }
  3788. if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
  3789. goto err;
  3790. if (stv090x_set_tspath(state) < 0)
  3791. goto err;
  3792. return 0;
  3793. err_gateoff:
  3794. stv090x_i2c_gate_ctrl(fe, 0);
  3795. err:
  3796. dprintk(FE_ERROR, 1, "I/O error");
  3797. return -1;
  3798. }
  3799. static int stv090x_setup(struct dvb_frontend *fe)
  3800. {
  3801. struct stv090x_state *state = fe->demodulator_priv;
  3802. const struct stv090x_config *config = state->config;
  3803. const struct stv090x_reg *stv090x_initval = NULL;
  3804. const struct stv090x_reg *stv090x_cut20_val = NULL;
  3805. unsigned long t1_size = 0, t2_size = 0;
  3806. u32 reg = 0;
  3807. int i;
  3808. if (state->device == STV0900) {
  3809. dprintk(FE_DEBUG, 1, "Initializing STV0900");
  3810. stv090x_initval = stv0900_initval;
  3811. t1_size = ARRAY_SIZE(stv0900_initval);
  3812. stv090x_cut20_val = stv0900_cut20_val;
  3813. t2_size = ARRAY_SIZE(stv0900_cut20_val);
  3814. } else if (state->device == STV0903) {
  3815. dprintk(FE_DEBUG, 1, "Initializing STV0903");
  3816. stv090x_initval = stv0903_initval;
  3817. t1_size = ARRAY_SIZE(stv0903_initval);
  3818. stv090x_cut20_val = stv0903_cut20_val;
  3819. t2_size = ARRAY_SIZE(stv0903_cut20_val);
  3820. }
  3821. /* STV090x init */
  3822. /* Stop Demod */
  3823. if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
  3824. goto err;
  3825. if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
  3826. goto err;
  3827. msleep(5);
  3828. /* Set No Tuner Mode */
  3829. if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
  3830. goto err;
  3831. if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
  3832. goto err;
  3833. /* I2C repeater OFF */
  3834. STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
  3835. if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
  3836. goto err;
  3837. if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
  3838. goto err;
  3839. if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
  3840. goto err;
  3841. msleep(5);
  3842. if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
  3843. goto err;
  3844. if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
  3845. goto err;
  3846. msleep(5);
  3847. /* write initval */
  3848. dprintk(FE_DEBUG, 1, "Setting up initial values");
  3849. for (i = 0; i < t1_size; i++) {
  3850. if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
  3851. goto err;
  3852. }
  3853. state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
  3854. if (state->internal->dev_ver >= 0x20) {
  3855. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
  3856. goto err;
  3857. /* write cut20_val*/
  3858. dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
  3859. for (i = 0; i < t2_size; i++) {
  3860. if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
  3861. goto err;
  3862. }
  3863. } else if (state->internal->dev_ver < 0x20) {
  3864. dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
  3865. state->internal->dev_ver);
  3866. goto err;
  3867. } else if (state->internal->dev_ver > 0x30) {
  3868. /* we shouldn't bail out from here */
  3869. dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
  3870. state->internal->dev_ver);
  3871. }
  3872. /* ADC1 range */
  3873. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3874. STV090x_SETFIELD(reg, ADC1_INMODE_FIELD,
  3875. (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1);
  3876. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3877. goto err;
  3878. /* ADC2 range */
  3879. reg = stv090x_read_reg(state, STV090x_TSTTNR3);
  3880. STV090x_SETFIELD(reg, ADC2_INMODE_FIELD,
  3881. (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1);
  3882. if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
  3883. goto err;
  3884. if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
  3885. goto err;
  3886. if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
  3887. goto err;
  3888. return 0;
  3889. err:
  3890. dprintk(FE_ERROR, 1, "I/O error");
  3891. return -1;
  3892. }
  3893. static struct dvb_frontend_ops stv090x_ops = {
  3894. .info = {
  3895. .name = "STV090x Multistandard",
  3896. .type = FE_QPSK,
  3897. .frequency_min = 950000,
  3898. .frequency_max = 2150000,
  3899. .frequency_stepsize = 0,
  3900. .frequency_tolerance = 0,
  3901. .symbol_rate_min = 1000000,
  3902. .symbol_rate_max = 45000000,
  3903. .caps = FE_CAN_INVERSION_AUTO |
  3904. FE_CAN_FEC_AUTO |
  3905. FE_CAN_QPSK |
  3906. FE_CAN_2G_MODULATION
  3907. },
  3908. .release = stv090x_release,
  3909. .init = stv090x_init,
  3910. .sleep = stv090x_sleep,
  3911. .get_frontend_algo = stv090x_frontend_algo,
  3912. .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
  3913. .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
  3914. .diseqc_send_burst = stv090x_send_diseqc_burst,
  3915. .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
  3916. .set_tone = stv090x_set_tone,
  3917. .search = stv090x_search,
  3918. .read_status = stv090x_read_status,
  3919. .read_ber = stv090x_read_per,
  3920. .read_signal_strength = stv090x_read_signal_strength,
  3921. .read_snr = stv090x_read_cnr
  3922. };
  3923. struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
  3924. struct i2c_adapter *i2c,
  3925. enum stv090x_demodulator demod)
  3926. {
  3927. struct stv090x_state *state = NULL;
  3928. struct stv090x_dev *temp_int;
  3929. state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
  3930. if (state == NULL)
  3931. goto error;
  3932. state->verbose = &verbose;
  3933. state->config = config;
  3934. state->i2c = i2c;
  3935. state->frontend.ops = stv090x_ops;
  3936. state->frontend.demodulator_priv = state;
  3937. state->demod = demod;
  3938. state->demod_mode = config->demod_mode; /* Single or Dual mode */
  3939. state->device = config->device;
  3940. state->rolloff = STV090x_RO_35; /* default */
  3941. temp_int = find_dev(state->i2c,
  3942. state->config->address);
  3943. if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) {
  3944. state->internal = temp_int->internal;
  3945. state->internal->num_used++;
  3946. dprintk(FE_INFO, 1, "Found Internal Structure!");
  3947. dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
  3948. state->device == STV0900 ? "STV0900" : "STV0903",
  3949. demod,
  3950. state->internal->dev_ver);
  3951. return &state->frontend;
  3952. } else {
  3953. state->internal = kmalloc(sizeof(struct stv090x_internal),
  3954. GFP_KERNEL);
  3955. temp_int = append_internal(state->internal);
  3956. state->internal->num_used = 1;
  3957. state->internal->mclk = 0;
  3958. state->internal->dev_ver = 0;
  3959. state->internal->i2c_adap = state->i2c;
  3960. state->internal->i2c_addr = state->config->address;
  3961. dprintk(FE_INFO, 1, "Create New Internal Structure!");
  3962. }
  3963. mutex_init(&state->internal->demod_lock);
  3964. mutex_init(&state->internal->tuner_lock);
  3965. if (stv090x_sleep(&state->frontend) < 0) {
  3966. dprintk(FE_ERROR, 1, "Error putting device to sleep");
  3967. goto error;
  3968. }
  3969. if (stv090x_setup(&state->frontend) < 0) {
  3970. dprintk(FE_ERROR, 1, "Error setting up device");
  3971. goto error;
  3972. }
  3973. if (stv090x_wakeup(&state->frontend) < 0) {
  3974. dprintk(FE_ERROR, 1, "Error waking device");
  3975. goto error;
  3976. }
  3977. dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
  3978. state->device == STV0900 ? "STV0900" : "STV0903",
  3979. demod,
  3980. state->internal->dev_ver);
  3981. return &state->frontend;
  3982. error:
  3983. kfree(state);
  3984. return NULL;
  3985. }
  3986. EXPORT_SYMBOL(stv090x_attach);
  3987. MODULE_PARM_DESC(verbose, "Set Verbosity level");
  3988. MODULE_AUTHOR("Manu Abraham");
  3989. MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
  3990. MODULE_LICENSE("GPL");