isar.c 51 KB

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  1. /* $Id: isar.c,v 1.22.2.6 2004/02/11 13:21:34 keil Exp $
  2. *
  3. * isar.c ISAR (Siemens PSB 7110) specific routines
  4. *
  5. * Author Karsten Keil (keil@isdn4linux.de)
  6. *
  7. * This file is (c) under GNU General Public License
  8. *
  9. */
  10. #include <linux/init.h>
  11. #include "hisax.h"
  12. #include "isar.h"
  13. #include "isdnl1.h"
  14. #include <linux/interrupt.h>
  15. #include <linux/slab.h>
  16. #define DBG_LOADFIRM 0
  17. #define DUMP_MBOXFRAME 2
  18. #define DLE 0x10
  19. #define ETX 0x03
  20. #define FAXMODCNT 13
  21. static const u_char faxmodulation[] = {3,24,48,72,73,74,96,97,98,121,122,145,146};
  22. static u_int modmask = 0x1fff;
  23. static int frm_extra_delay = 2;
  24. static int para_TOA = 6;
  25. static const u_char *FC1_CMD[] = {"FAE", "FTS", "FRS", "FTM", "FRM", "FTH", "FRH", "CTRL" };
  26. static void isar_setup(struct IsdnCardState *cs);
  27. static void isar_pump_cmd(struct BCState *bcs, u_char cmd, u_char para);
  28. static void ll_deliver_faxstat(struct BCState *bcs, u_char status);
  29. static inline int
  30. waitforHIA(struct IsdnCardState *cs, int timeout)
  31. {
  32. while ((cs->BC_Read_Reg(cs, 0, ISAR_HIA) & 1) && timeout) {
  33. udelay(1);
  34. timeout--;
  35. }
  36. if (!timeout)
  37. printk(KERN_WARNING "HiSax: ISAR waitforHIA timeout\n");
  38. return(timeout);
  39. }
  40. static int
  41. sendmsg(struct IsdnCardState *cs, u_char his, u_char creg, u_char len,
  42. u_char *msg)
  43. {
  44. int i;
  45. if (!waitforHIA(cs, 4000))
  46. return(0);
  47. #if DUMP_MBOXFRAME
  48. if (cs->debug & L1_DEB_HSCX)
  49. debugl1(cs, "sendmsg(%02x,%02x,%d)", his, creg, len);
  50. #endif
  51. cs->BC_Write_Reg(cs, 0, ISAR_CTRL_H, creg);
  52. cs->BC_Write_Reg(cs, 0, ISAR_CTRL_L, len);
  53. cs->BC_Write_Reg(cs, 0, ISAR_WADR, 0);
  54. if (msg && len) {
  55. cs->BC_Write_Reg(cs, 1, ISAR_MBOX, msg[0]);
  56. for (i=1; i<len; i++)
  57. cs->BC_Write_Reg(cs, 2, ISAR_MBOX, msg[i]);
  58. #if DUMP_MBOXFRAME>1
  59. if (cs->debug & L1_DEB_HSCX_FIFO) {
  60. char tmp[256], *t;
  61. i = len;
  62. while (i>0) {
  63. t = tmp;
  64. t += sprintf(t, "sendmbox cnt %d", len);
  65. QuickHex(t, &msg[len-i], (i>64) ? 64:i);
  66. debugl1(cs, tmp);
  67. i -= 64;
  68. }
  69. }
  70. #endif
  71. }
  72. cs->BC_Write_Reg(cs, 1, ISAR_HIS, his);
  73. waitforHIA(cs, 10000);
  74. return(1);
  75. }
  76. /* Call only with IRQ disabled !!! */
  77. static inline void
  78. rcv_mbox(struct IsdnCardState *cs, struct isar_reg *ireg, u_char *msg)
  79. {
  80. int i;
  81. cs->BC_Write_Reg(cs, 1, ISAR_RADR, 0);
  82. if (msg && ireg->clsb) {
  83. msg[0] = cs->BC_Read_Reg(cs, 1, ISAR_MBOX);
  84. for (i=1; i < ireg->clsb; i++)
  85. msg[i] = cs->BC_Read_Reg(cs, 2, ISAR_MBOX);
  86. #if DUMP_MBOXFRAME>1
  87. if (cs->debug & L1_DEB_HSCX_FIFO) {
  88. char tmp[256], *t;
  89. i = ireg->clsb;
  90. while (i>0) {
  91. t = tmp;
  92. t += sprintf(t, "rcv_mbox cnt %d", ireg->clsb);
  93. QuickHex(t, &msg[ireg->clsb-i], (i>64) ? 64:i);
  94. debugl1(cs, tmp);
  95. i -= 64;
  96. }
  97. }
  98. #endif
  99. }
  100. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  101. }
  102. /* Call only with IRQ disabled !!! */
  103. static inline void
  104. get_irq_infos(struct IsdnCardState *cs, struct isar_reg *ireg)
  105. {
  106. ireg->iis = cs->BC_Read_Reg(cs, 1, ISAR_IIS);
  107. ireg->cmsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_H);
  108. ireg->clsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_L);
  109. #if DUMP_MBOXFRAME
  110. if (cs->debug & L1_DEB_HSCX)
  111. debugl1(cs, "irq_stat(%02x,%02x,%d)", ireg->iis, ireg->cmsb,
  112. ireg->clsb);
  113. #endif
  114. }
  115. static int
  116. waitrecmsg(struct IsdnCardState *cs, u_char *len,
  117. u_char *msg, int maxdelay)
  118. {
  119. int timeout = 0;
  120. struct isar_reg *ir = cs->bcs[0].hw.isar.reg;
  121. while((!(cs->BC_Read_Reg(cs, 0, ISAR_IRQBIT) & ISAR_IRQSTA)) &&
  122. (timeout++ < maxdelay))
  123. udelay(1);
  124. if (timeout > maxdelay) {
  125. printk(KERN_WARNING"isar recmsg IRQSTA timeout\n");
  126. return(0);
  127. }
  128. get_irq_infos(cs, ir);
  129. rcv_mbox(cs, ir, msg);
  130. *len = ir->clsb;
  131. return(1);
  132. }
  133. int
  134. ISARVersion(struct IsdnCardState *cs, char *s)
  135. {
  136. int ver;
  137. u_char msg[] = ISAR_MSG_HWVER;
  138. u_char tmp[64];
  139. u_char len;
  140. u_long flags;
  141. int debug;
  142. cs->cardmsg(cs, CARD_RESET, NULL);
  143. spin_lock_irqsave(&cs->lock, flags);
  144. /* disable ISAR IRQ */
  145. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
  146. debug = cs->debug;
  147. cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
  148. if (!sendmsg(cs, ISAR_HIS_VNR, 0, 3, msg)) {
  149. spin_unlock_irqrestore(&cs->lock, flags);
  150. return(-1);
  151. }
  152. if (!waitrecmsg(cs, &len, tmp, 100000)) {
  153. spin_unlock_irqrestore(&cs->lock, flags);
  154. return(-2);
  155. }
  156. cs->debug = debug;
  157. if (cs->bcs[0].hw.isar.reg->iis == ISAR_IIS_VNR) {
  158. if (len == 1) {
  159. ver = tmp[0] & 0xf;
  160. printk(KERN_INFO "%s ISAR version %d\n", s, ver);
  161. } else
  162. ver = -3;
  163. } else
  164. ver = -4;
  165. spin_unlock_irqrestore(&cs->lock, flags);
  166. return(ver);
  167. }
  168. static int
  169. isar_load_firmware(struct IsdnCardState *cs, u_char __user *buf)
  170. {
  171. int ret, size, cnt, debug;
  172. u_char len, nom, noc;
  173. u_short sadr, left, *sp;
  174. u_char __user *p = buf;
  175. u_char *msg, *tmpmsg, *mp, tmp[64];
  176. u_long flags;
  177. struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
  178. struct {u_short sadr;
  179. u_short len;
  180. u_short d_key;
  181. } blk_head;
  182. #define BLK_HEAD_SIZE 6
  183. if (1 != (ret = ISARVersion(cs, "Testing"))) {
  184. printk(KERN_ERR"isar_load_firmware wrong isar version %d\n", ret);
  185. return(1);
  186. }
  187. debug = cs->debug;
  188. #if DBG_LOADFIRM<2
  189. cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
  190. #endif
  191. if ((ret = copy_from_user(&size, p, sizeof(int)))) {
  192. printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
  193. return ret;
  194. }
  195. p += sizeof(int);
  196. printk(KERN_DEBUG"isar_load_firmware size: %d\n", size);
  197. cnt = 0;
  198. /* disable ISAR IRQ */
  199. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
  200. if (!(msg = kmalloc(256, GFP_KERNEL))) {
  201. printk(KERN_ERR"isar_load_firmware no buffer\n");
  202. return (1);
  203. }
  204. if (!(tmpmsg = kmalloc(256, GFP_KERNEL))) {
  205. printk(KERN_ERR"isar_load_firmware no tmp buffer\n");
  206. kfree(msg);
  207. return (1);
  208. }
  209. spin_lock_irqsave(&cs->lock, flags);
  210. /* disable ISAR IRQ */
  211. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
  212. spin_unlock_irqrestore(&cs->lock, flags);
  213. while (cnt < size) {
  214. if ((ret = copy_from_user(&blk_head, p, BLK_HEAD_SIZE))) {
  215. printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
  216. goto reterror;
  217. }
  218. #ifdef __BIG_ENDIAN
  219. sadr = (blk_head.sadr & 0xff)*256 + blk_head.sadr/256;
  220. blk_head.sadr = sadr;
  221. sadr = (blk_head.len & 0xff)*256 + blk_head.len/256;
  222. blk_head.len = sadr;
  223. sadr = (blk_head.d_key & 0xff)*256 + blk_head.d_key/256;
  224. blk_head.d_key = sadr;
  225. #endif /* __BIG_ENDIAN */
  226. cnt += BLK_HEAD_SIZE;
  227. p += BLK_HEAD_SIZE;
  228. printk(KERN_DEBUG"isar firmware block (%#x,%5d,%#x)\n",
  229. blk_head.sadr, blk_head.len, blk_head.d_key & 0xff);
  230. sadr = blk_head.sadr;
  231. left = blk_head.len;
  232. spin_lock_irqsave(&cs->lock, flags);
  233. if (!sendmsg(cs, ISAR_HIS_DKEY, blk_head.d_key & 0xff, 0, NULL)) {
  234. printk(KERN_ERR"isar sendmsg dkey failed\n");
  235. ret = 1;goto reterr_unlock;
  236. }
  237. if (!waitrecmsg(cs, &len, tmp, 100000)) {
  238. printk(KERN_ERR"isar waitrecmsg dkey failed\n");
  239. ret = 1;goto reterr_unlock;
  240. }
  241. if ((ireg->iis != ISAR_IIS_DKEY) || ireg->cmsb || len) {
  242. printk(KERN_ERR"isar wrong dkey response (%x,%x,%x)\n",
  243. ireg->iis, ireg->cmsb, len);
  244. ret = 1;goto reterr_unlock;
  245. }
  246. spin_unlock_irqrestore(&cs->lock, flags);
  247. while (left>0) {
  248. if (left > 126)
  249. noc = 126;
  250. else
  251. noc = left;
  252. nom = 2*noc;
  253. mp = msg;
  254. *mp++ = sadr / 256;
  255. *mp++ = sadr % 256;
  256. left -= noc;
  257. *mp++ = noc;
  258. if ((ret = copy_from_user(tmpmsg, p, nom))) {
  259. printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
  260. goto reterror;
  261. }
  262. p += nom;
  263. cnt += nom;
  264. nom += 3;
  265. sp = (u_short *)tmpmsg;
  266. #if DBG_LOADFIRM
  267. printk(KERN_DEBUG"isar: load %3d words at %04x left %d\n",
  268. noc, sadr, left);
  269. #endif
  270. sadr += noc;
  271. while(noc) {
  272. #ifdef __BIG_ENDIAN
  273. *mp++ = *sp % 256;
  274. *mp++ = *sp / 256;
  275. #else
  276. *mp++ = *sp / 256;
  277. *mp++ = *sp % 256;
  278. #endif /* __BIG_ENDIAN */
  279. sp++;
  280. noc--;
  281. }
  282. spin_lock_irqsave(&cs->lock, flags);
  283. if (!sendmsg(cs, ISAR_HIS_FIRM, 0, nom, msg)) {
  284. printk(KERN_ERR"isar sendmsg prog failed\n");
  285. ret = 1;goto reterr_unlock;
  286. }
  287. if (!waitrecmsg(cs, &len, tmp, 100000)) {
  288. printk(KERN_ERR"isar waitrecmsg prog failed\n");
  289. ret = 1;goto reterr_unlock;
  290. }
  291. if ((ireg->iis != ISAR_IIS_FIRM) || ireg->cmsb || len) {
  292. printk(KERN_ERR"isar wrong prog response (%x,%x,%x)\n",
  293. ireg->iis, ireg->cmsb, len);
  294. ret = 1;goto reterr_unlock;
  295. }
  296. spin_unlock_irqrestore(&cs->lock, flags);
  297. }
  298. printk(KERN_DEBUG"isar firmware block %5d words loaded\n",
  299. blk_head.len);
  300. }
  301. /* 10ms delay */
  302. cnt = 10;
  303. while (cnt--)
  304. udelay(1000);
  305. msg[0] = 0xff;
  306. msg[1] = 0xfe;
  307. ireg->bstat = 0;
  308. spin_lock_irqsave(&cs->lock, flags);
  309. if (!sendmsg(cs, ISAR_HIS_STDSP, 0, 2, msg)) {
  310. printk(KERN_ERR"isar sendmsg start dsp failed\n");
  311. ret = 1;goto reterr_unlock;
  312. }
  313. if (!waitrecmsg(cs, &len, tmp, 100000)) {
  314. printk(KERN_ERR"isar waitrecmsg start dsp failed\n");
  315. ret = 1;goto reterr_unlock;
  316. }
  317. if ((ireg->iis != ISAR_IIS_STDSP) || ireg->cmsb || len) {
  318. printk(KERN_ERR"isar wrong start dsp response (%x,%x,%x)\n",
  319. ireg->iis, ireg->cmsb, len);
  320. ret = 1;goto reterr_unlock;
  321. } else
  322. printk(KERN_DEBUG"isar start dsp success\n");
  323. /* NORMAL mode entered */
  324. /* Enable IRQs of ISAR */
  325. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, ISAR_IRQSTA);
  326. spin_unlock_irqrestore(&cs->lock, flags);
  327. cnt = 1000; /* max 1s */
  328. while ((!ireg->bstat) && cnt) {
  329. udelay(1000);
  330. cnt--;
  331. }
  332. if (!cnt) {
  333. printk(KERN_ERR"isar no general status event received\n");
  334. ret = 1;goto reterror;
  335. } else {
  336. printk(KERN_DEBUG"isar general status event %x\n",
  337. ireg->bstat);
  338. }
  339. /* 10ms delay */
  340. cnt = 10;
  341. while (cnt--)
  342. udelay(1000);
  343. spin_lock_irqsave(&cs->lock, flags);
  344. ireg->iis = 0;
  345. if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_STST, 0, NULL)) {
  346. printk(KERN_ERR"isar sendmsg self tst failed\n");
  347. ret = 1;goto reterr_unlock;
  348. }
  349. cnt = 10000; /* max 100 ms */
  350. spin_unlock_irqrestore(&cs->lock, flags);
  351. while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
  352. udelay(10);
  353. cnt--;
  354. }
  355. udelay(1000);
  356. if (!cnt) {
  357. printk(KERN_ERR"isar no self tst response\n");
  358. ret = 1;goto reterror;
  359. }
  360. if ((ireg->cmsb == ISAR_CTRL_STST) && (ireg->clsb == 1)
  361. && (ireg->par[0] == 0)) {
  362. printk(KERN_DEBUG"isar selftest OK\n");
  363. } else {
  364. printk(KERN_DEBUG"isar selftest not OK %x/%x/%x\n",
  365. ireg->cmsb, ireg->clsb, ireg->par[0]);
  366. ret = 1;goto reterror;
  367. }
  368. spin_lock_irqsave(&cs->lock, flags);
  369. ireg->iis = 0;
  370. if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_SWVER, 0, NULL)) {
  371. printk(KERN_ERR"isar RQST SVN failed\n");
  372. ret = 1;goto reterr_unlock;
  373. }
  374. spin_unlock_irqrestore(&cs->lock, flags);
  375. cnt = 30000; /* max 300 ms */
  376. while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
  377. udelay(10);
  378. cnt--;
  379. }
  380. udelay(1000);
  381. if (!cnt) {
  382. printk(KERN_ERR"isar no SVN response\n");
  383. ret = 1;goto reterror;
  384. } else {
  385. if ((ireg->cmsb == ISAR_CTRL_SWVER) && (ireg->clsb == 1))
  386. printk(KERN_DEBUG"isar software version %#x\n",
  387. ireg->par[0]);
  388. else {
  389. printk(KERN_ERR"isar wrong swver response (%x,%x) cnt(%d)\n",
  390. ireg->cmsb, ireg->clsb, cnt);
  391. ret = 1;goto reterror;
  392. }
  393. }
  394. spin_lock_irqsave(&cs->lock, flags);
  395. cs->debug = debug;
  396. isar_setup(cs);
  397. ret = 0;
  398. reterr_unlock:
  399. spin_unlock_irqrestore(&cs->lock, flags);
  400. reterror:
  401. cs->debug = debug;
  402. if (ret)
  403. /* disable ISAR IRQ */
  404. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
  405. kfree(msg);
  406. kfree(tmpmsg);
  407. return(ret);
  408. }
  409. #define B_LL_NOCARRIER 8
  410. #define B_LL_CONNECT 9
  411. #define B_LL_OK 10
  412. static void
  413. isar_bh(struct work_struct *work)
  414. {
  415. struct BCState *bcs = container_of(work, struct BCState, tqueue);
  416. BChannel_bh(work);
  417. if (test_and_clear_bit(B_LL_NOCARRIER, &bcs->event))
  418. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_NOCARR);
  419. if (test_and_clear_bit(B_LL_CONNECT, &bcs->event))
  420. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  421. if (test_and_clear_bit(B_LL_OK, &bcs->event))
  422. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_OK);
  423. }
  424. static void
  425. send_DLE_ETX(struct BCState *bcs)
  426. {
  427. u_char dleetx[2] = {DLE,ETX};
  428. struct sk_buff *skb;
  429. if ((skb = dev_alloc_skb(2))) {
  430. memcpy(skb_put(skb, 2), dleetx, 2);
  431. skb_queue_tail(&bcs->rqueue, skb);
  432. schedule_event(bcs, B_RCVBUFREADY);
  433. } else {
  434. printk(KERN_WARNING "HiSax: skb out of memory\n");
  435. }
  436. }
  437. static inline int
  438. dle_count(unsigned char *buf, int len)
  439. {
  440. int count = 0;
  441. while (len--)
  442. if (*buf++ == DLE)
  443. count++;
  444. return count;
  445. }
  446. static inline void
  447. insert_dle(unsigned char *dest, unsigned char *src, int count) {
  448. /* <DLE> in input stream have to be flagged as <DLE><DLE> */
  449. while (count--) {
  450. *dest++ = *src;
  451. if (*src++ == DLE)
  452. *dest++ = DLE;
  453. }
  454. }
  455. static void
  456. isar_rcv_frame(struct IsdnCardState *cs, struct BCState *bcs)
  457. {
  458. u_char *ptr;
  459. struct sk_buff *skb;
  460. struct isar_reg *ireg = bcs->hw.isar.reg;
  461. if (!ireg->clsb) {
  462. debugl1(cs, "isar zero len frame");
  463. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  464. return;
  465. }
  466. switch (bcs->mode) {
  467. case L1_MODE_NULL:
  468. debugl1(cs, "isar mode 0 spurious IIS_RDATA %x/%x/%x",
  469. ireg->iis, ireg->cmsb, ireg->clsb);
  470. printk(KERN_WARNING"isar mode 0 spurious IIS_RDATA %x/%x/%x\n",
  471. ireg->iis, ireg->cmsb, ireg->clsb);
  472. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  473. break;
  474. case L1_MODE_TRANS:
  475. case L1_MODE_V32:
  476. if ((skb = dev_alloc_skb(ireg->clsb))) {
  477. rcv_mbox(cs, ireg, (u_char *)skb_put(skb, ireg->clsb));
  478. skb_queue_tail(&bcs->rqueue, skb);
  479. schedule_event(bcs, B_RCVBUFREADY);
  480. } else {
  481. printk(KERN_WARNING "HiSax: skb out of memory\n");
  482. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  483. }
  484. break;
  485. case L1_MODE_HDLC:
  486. if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
  487. if (cs->debug & L1_DEB_WARN)
  488. debugl1(cs, "isar_rcv_frame: incoming packet too large");
  489. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  490. bcs->hw.isar.rcvidx = 0;
  491. } else if (ireg->cmsb & HDLC_ERROR) {
  492. if (cs->debug & L1_DEB_WARN)
  493. debugl1(cs, "isar frame error %x len %d",
  494. ireg->cmsb, ireg->clsb);
  495. #ifdef ERROR_STATISTIC
  496. if (ireg->cmsb & HDLC_ERR_RER)
  497. bcs->err_inv++;
  498. if (ireg->cmsb & HDLC_ERR_CER)
  499. bcs->err_crc++;
  500. #endif
  501. bcs->hw.isar.rcvidx = 0;
  502. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  503. } else {
  504. if (ireg->cmsb & HDLC_FSD)
  505. bcs->hw.isar.rcvidx = 0;
  506. ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
  507. bcs->hw.isar.rcvidx += ireg->clsb;
  508. rcv_mbox(cs, ireg, ptr);
  509. if (ireg->cmsb & HDLC_FED) {
  510. if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
  511. if (cs->debug & L1_DEB_WARN)
  512. debugl1(cs, "isar frame to short %d",
  513. bcs->hw.isar.rcvidx);
  514. } else if (!(skb = dev_alloc_skb(bcs->hw.isar.rcvidx-2))) {
  515. printk(KERN_WARNING "ISAR: receive out of memory\n");
  516. } else {
  517. memcpy(skb_put(skb, bcs->hw.isar.rcvidx-2),
  518. bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx-2);
  519. skb_queue_tail(&bcs->rqueue, skb);
  520. schedule_event(bcs, B_RCVBUFREADY);
  521. }
  522. bcs->hw.isar.rcvidx = 0;
  523. }
  524. }
  525. break;
  526. case L1_MODE_FAX:
  527. if (bcs->hw.isar.state != STFAX_ACTIV) {
  528. if (cs->debug & L1_DEB_WARN)
  529. debugl1(cs, "isar_rcv_frame: not ACTIV");
  530. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  531. bcs->hw.isar.rcvidx = 0;
  532. break;
  533. }
  534. if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) {
  535. rcv_mbox(cs, ireg, bcs->hw.isar.rcvbuf);
  536. bcs->hw.isar.rcvidx = ireg->clsb +
  537. dle_count(bcs->hw.isar.rcvbuf, ireg->clsb);
  538. if (cs->debug & L1_DEB_HSCX)
  539. debugl1(cs, "isar_rcv_frame: raw(%d) dle(%d)",
  540. ireg->clsb, bcs->hw.isar.rcvidx);
  541. if ((skb = dev_alloc_skb(bcs->hw.isar.rcvidx))) {
  542. insert_dle((u_char *)skb_put(skb, bcs->hw.isar.rcvidx),
  543. bcs->hw.isar.rcvbuf, ireg->clsb);
  544. skb_queue_tail(&bcs->rqueue, skb);
  545. schedule_event(bcs, B_RCVBUFREADY);
  546. if (ireg->cmsb & SART_NMD) { /* ABORT */
  547. if (cs->debug & L1_DEB_WARN)
  548. debugl1(cs, "isar_rcv_frame: no more data");
  549. bcs->hw.isar.rcvidx = 0;
  550. send_DLE_ETX(bcs);
  551. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) |
  552. ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC,
  553. 0, NULL);
  554. bcs->hw.isar.state = STFAX_ESCAPE;
  555. schedule_event(bcs, B_LL_NOCARRIER);
  556. }
  557. } else {
  558. printk(KERN_WARNING "HiSax: skb out of memory\n");
  559. }
  560. break;
  561. }
  562. if (bcs->hw.isar.cmd != PCTRL_CMD_FRH) {
  563. if (cs->debug & L1_DEB_WARN)
  564. debugl1(cs, "isar_rcv_frame: unknown fax mode %x",
  565. bcs->hw.isar.cmd);
  566. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  567. bcs->hw.isar.rcvidx = 0;
  568. break;
  569. }
  570. /* PCTRL_CMD_FRH */
  571. if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
  572. if (cs->debug & L1_DEB_WARN)
  573. debugl1(cs, "isar_rcv_frame: incoming packet too large");
  574. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  575. bcs->hw.isar.rcvidx = 0;
  576. } else if (ireg->cmsb & HDLC_ERROR) {
  577. if (cs->debug & L1_DEB_WARN)
  578. debugl1(cs, "isar frame error %x len %d",
  579. ireg->cmsb, ireg->clsb);
  580. bcs->hw.isar.rcvidx = 0;
  581. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  582. } else {
  583. if (ireg->cmsb & HDLC_FSD) {
  584. bcs->hw.isar.rcvidx = 0;
  585. }
  586. ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
  587. bcs->hw.isar.rcvidx += ireg->clsb;
  588. rcv_mbox(cs, ireg, ptr);
  589. if (ireg->cmsb & HDLC_FED) {
  590. int len = bcs->hw.isar.rcvidx +
  591. dle_count(bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx);
  592. if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
  593. if (cs->debug & L1_DEB_WARN)
  594. debugl1(cs, "isar frame to short %d",
  595. bcs->hw.isar.rcvidx);
  596. printk(KERN_WARNING "ISAR: frame to short %d\n",
  597. bcs->hw.isar.rcvidx);
  598. } else if (!(skb = dev_alloc_skb(len))) {
  599. printk(KERN_WARNING "ISAR: receive out of memory\n");
  600. } else {
  601. insert_dle((u_char *)skb_put(skb, len),
  602. bcs->hw.isar.rcvbuf,
  603. bcs->hw.isar.rcvidx);
  604. skb_queue_tail(&bcs->rqueue, skb);
  605. schedule_event(bcs, B_RCVBUFREADY);
  606. send_DLE_ETX(bcs);
  607. schedule_event(bcs, B_LL_OK);
  608. test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  609. }
  610. bcs->hw.isar.rcvidx = 0;
  611. }
  612. }
  613. if (ireg->cmsb & SART_NMD) { /* ABORT */
  614. if (cs->debug & L1_DEB_WARN)
  615. debugl1(cs, "isar_rcv_frame: no more data");
  616. bcs->hw.isar.rcvidx = 0;
  617. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) |
  618. ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
  619. bcs->hw.isar.state = STFAX_ESCAPE;
  620. if (test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag)) {
  621. send_DLE_ETX(bcs);
  622. schedule_event(bcs, B_LL_NOCARRIER);
  623. }
  624. }
  625. break;
  626. default:
  627. printk(KERN_ERR"isar_rcv_frame mode (%x)error\n", bcs->mode);
  628. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  629. break;
  630. }
  631. }
  632. void
  633. isar_fill_fifo(struct BCState *bcs)
  634. {
  635. struct IsdnCardState *cs = bcs->cs;
  636. int count;
  637. u_char msb;
  638. u_char *ptr;
  639. if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
  640. debugl1(cs, "isar_fill_fifo");
  641. if (!bcs->tx_skb)
  642. return;
  643. if (bcs->tx_skb->len <= 0)
  644. return;
  645. if (!(bcs->hw.isar.reg->bstat &
  646. (bcs->hw.isar.dpath == 1 ? BSTAT_RDM1 : BSTAT_RDM2)))
  647. return;
  648. if (bcs->tx_skb->len > bcs->hw.isar.mml) {
  649. msb = 0;
  650. count = bcs->hw.isar.mml;
  651. } else {
  652. count = bcs->tx_skb->len;
  653. msb = HDLC_FED;
  654. }
  655. ptr = bcs->tx_skb->data;
  656. if (!bcs->hw.isar.txcnt) {
  657. msb |= HDLC_FST;
  658. if ((bcs->mode == L1_MODE_FAX) &&
  659. (bcs->hw.isar.cmd == PCTRL_CMD_FTH)) {
  660. if (bcs->tx_skb->len > 1) {
  661. if ((ptr[0]== 0xff) && (ptr[1] == 0x13))
  662. /* last frame */
  663. test_and_set_bit(BC_FLG_LASTDATA,
  664. &bcs->Flag);
  665. }
  666. }
  667. }
  668. skb_pull(bcs->tx_skb, count);
  669. bcs->tx_cnt -= count;
  670. bcs->hw.isar.txcnt += count;
  671. switch (bcs->mode) {
  672. case L1_MODE_NULL:
  673. printk(KERN_ERR"isar_fill_fifo wrong mode 0\n");
  674. break;
  675. case L1_MODE_TRANS:
  676. case L1_MODE_V32:
  677. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
  678. 0, count, ptr);
  679. break;
  680. case L1_MODE_HDLC:
  681. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
  682. msb, count, ptr);
  683. break;
  684. case L1_MODE_FAX:
  685. if (bcs->hw.isar.state != STFAX_ACTIV) {
  686. if (cs->debug & L1_DEB_WARN)
  687. debugl1(cs, "isar_fill_fifo: not ACTIV");
  688. } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
  689. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
  690. msb, count, ptr);
  691. } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) {
  692. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
  693. 0, count, ptr);
  694. } else {
  695. if (cs->debug & L1_DEB_WARN)
  696. debugl1(cs, "isar_fill_fifo: not FTH/FTM");
  697. }
  698. break;
  699. default:
  700. if (cs->debug)
  701. debugl1(cs, "isar_fill_fifo mode(%x) error", bcs->mode);
  702. printk(KERN_ERR"isar_fill_fifo mode(%x) error\n", bcs->mode);
  703. break;
  704. }
  705. }
  706. static inline
  707. struct BCState *sel_bcs_isar(struct IsdnCardState *cs, u_char dpath)
  708. {
  709. if ((!dpath) || (dpath == 3))
  710. return(NULL);
  711. if (cs->bcs[0].hw.isar.dpath == dpath)
  712. return(&cs->bcs[0]);
  713. if (cs->bcs[1].hw.isar.dpath == dpath)
  714. return(&cs->bcs[1]);
  715. return(NULL);
  716. }
  717. static void
  718. send_frames(struct BCState *bcs)
  719. {
  720. if (bcs->tx_skb) {
  721. if (bcs->tx_skb->len) {
  722. isar_fill_fifo(bcs);
  723. return;
  724. } else {
  725. if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
  726. (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
  727. u_long flags;
  728. spin_lock_irqsave(&bcs->aclock, flags);
  729. bcs->ackcnt += bcs->hw.isar.txcnt;
  730. spin_unlock_irqrestore(&bcs->aclock, flags);
  731. schedule_event(bcs, B_ACKPENDING);
  732. }
  733. if (bcs->mode == L1_MODE_FAX) {
  734. if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
  735. if (test_bit(BC_FLG_LASTDATA, &bcs->Flag)) {
  736. test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag);
  737. }
  738. } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) {
  739. if (test_bit(BC_FLG_DLEETX, &bcs->Flag)) {
  740. test_and_set_bit(BC_FLG_LASTDATA, &bcs->Flag);
  741. test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag);
  742. }
  743. }
  744. }
  745. dev_kfree_skb_any(bcs->tx_skb);
  746. bcs->hw.isar.txcnt = 0;
  747. bcs->tx_skb = NULL;
  748. }
  749. }
  750. if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
  751. bcs->hw.isar.txcnt = 0;
  752. test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
  753. isar_fill_fifo(bcs);
  754. } else {
  755. if (test_and_clear_bit(BC_FLG_DLEETX, &bcs->Flag)) {
  756. if (test_and_clear_bit(BC_FLG_LASTDATA, &bcs->Flag)) {
  757. if (test_and_clear_bit(BC_FLG_NMD_DATA, &bcs->Flag)) {
  758. u_char dummy = 0;
  759. sendmsg(bcs->cs, SET_DPS(bcs->hw.isar.dpath) |
  760. ISAR_HIS_SDATA, 0x01, 1, &dummy);
  761. }
  762. test_and_set_bit(BC_FLG_LL_OK, &bcs->Flag);
  763. } else {
  764. schedule_event(bcs, B_LL_CONNECT);
  765. }
  766. }
  767. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  768. schedule_event(bcs, B_XMTBUFREADY);
  769. }
  770. }
  771. static inline void
  772. check_send(struct IsdnCardState *cs, u_char rdm)
  773. {
  774. struct BCState *bcs;
  775. if (rdm & BSTAT_RDM1) {
  776. if ((bcs = sel_bcs_isar(cs, 1))) {
  777. if (bcs->mode) {
  778. send_frames(bcs);
  779. }
  780. }
  781. }
  782. if (rdm & BSTAT_RDM2) {
  783. if ((bcs = sel_bcs_isar(cs, 2))) {
  784. if (bcs->mode) {
  785. send_frames(bcs);
  786. }
  787. }
  788. }
  789. }
  790. static const char *dmril[] = {"NO SPEED", "1200/75", "NODEF2", "75/1200",
  791. "NODEF4", "300", "600", "1200", "2400",
  792. "4800", "7200", "9600nt", "9600t", "12000",
  793. "14400", "WRONG"};
  794. static const char *dmrim[] = {"NO MOD", "NO DEF", "V32/V32b", "V22", "V21",
  795. "Bell103", "V23", "Bell202", "V17", "V29",
  796. "V27ter"};
  797. static void
  798. isar_pump_status_rsp(struct BCState *bcs, struct isar_reg *ireg) {
  799. struct IsdnCardState *cs = bcs->cs;
  800. u_char ril = ireg->par[0];
  801. u_char rim;
  802. if (!test_and_clear_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags))
  803. return;
  804. if (ril > 14) {
  805. if (cs->debug & L1_DEB_WARN)
  806. debugl1(cs, "wrong pstrsp ril=%d",ril);
  807. ril = 15;
  808. }
  809. switch(ireg->par[1]) {
  810. case 0:
  811. rim = 0;
  812. break;
  813. case 0x20:
  814. rim = 2;
  815. break;
  816. case 0x40:
  817. rim = 3;
  818. break;
  819. case 0x41:
  820. rim = 4;
  821. break;
  822. case 0x51:
  823. rim = 5;
  824. break;
  825. case 0x61:
  826. rim = 6;
  827. break;
  828. case 0x71:
  829. rim = 7;
  830. break;
  831. case 0x82:
  832. rim = 8;
  833. break;
  834. case 0x92:
  835. rim = 9;
  836. break;
  837. case 0xa2:
  838. rim = 10;
  839. break;
  840. default:
  841. rim = 1;
  842. break;
  843. }
  844. sprintf(bcs->hw.isar.conmsg,"%s %s", dmril[ril], dmrim[rim]);
  845. bcs->conmsg = bcs->hw.isar.conmsg;
  846. if (cs->debug & L1_DEB_HSCX)
  847. debugl1(cs, "pump strsp %s", bcs->conmsg);
  848. }
  849. static void
  850. isar_pump_statev_modem(struct BCState *bcs, u_char devt) {
  851. struct IsdnCardState *cs = bcs->cs;
  852. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  853. switch(devt) {
  854. case PSEV_10MS_TIMER:
  855. if (cs->debug & L1_DEB_HSCX)
  856. debugl1(cs, "pump stev TIMER");
  857. break;
  858. case PSEV_CON_ON:
  859. if (cs->debug & L1_DEB_HSCX)
  860. debugl1(cs, "pump stev CONNECT");
  861. l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
  862. break;
  863. case PSEV_CON_OFF:
  864. if (cs->debug & L1_DEB_HSCX)
  865. debugl1(cs, "pump stev NO CONNECT");
  866. sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  867. l1_msg_b(bcs->st, PH_DEACTIVATE | REQUEST, NULL);
  868. break;
  869. case PSEV_V24_OFF:
  870. if (cs->debug & L1_DEB_HSCX)
  871. debugl1(cs, "pump stev V24 OFF");
  872. break;
  873. case PSEV_CTS_ON:
  874. if (cs->debug & L1_DEB_HSCX)
  875. debugl1(cs, "pump stev CTS ON");
  876. break;
  877. case PSEV_CTS_OFF:
  878. if (cs->debug & L1_DEB_HSCX)
  879. debugl1(cs, "pump stev CTS OFF");
  880. break;
  881. case PSEV_DCD_ON:
  882. if (cs->debug & L1_DEB_HSCX)
  883. debugl1(cs, "pump stev CARRIER ON");
  884. test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
  885. sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  886. break;
  887. case PSEV_DCD_OFF:
  888. if (cs->debug & L1_DEB_HSCX)
  889. debugl1(cs, "pump stev CARRIER OFF");
  890. break;
  891. case PSEV_DSR_ON:
  892. if (cs->debug & L1_DEB_HSCX)
  893. debugl1(cs, "pump stev DSR ON");
  894. break;
  895. case PSEV_DSR_OFF:
  896. if (cs->debug & L1_DEB_HSCX)
  897. debugl1(cs, "pump stev DSR_OFF");
  898. break;
  899. case PSEV_REM_RET:
  900. if (cs->debug & L1_DEB_HSCX)
  901. debugl1(cs, "pump stev REMOTE RETRAIN");
  902. break;
  903. case PSEV_REM_REN:
  904. if (cs->debug & L1_DEB_HSCX)
  905. debugl1(cs, "pump stev REMOTE RENEGOTIATE");
  906. break;
  907. case PSEV_GSTN_CLR:
  908. if (cs->debug & L1_DEB_HSCX)
  909. debugl1(cs, "pump stev GSTN CLEAR", devt);
  910. break;
  911. default:
  912. if (cs->debug & L1_DEB_HSCX)
  913. debugl1(cs, "unknown pump stev %x", devt);
  914. break;
  915. }
  916. }
  917. static void
  918. ll_deliver_faxstat(struct BCState *bcs, u_char status)
  919. {
  920. isdn_ctrl ic;
  921. struct Channel *chanp = (struct Channel *) bcs->st->lli.userdata;
  922. if (bcs->cs->debug & L1_DEB_HSCX)
  923. debugl1(bcs->cs, "HL->LL FAXIND %x", status);
  924. ic.driver = bcs->cs->myid;
  925. ic.command = ISDN_STAT_FAXIND;
  926. ic.arg = chanp->chan;
  927. ic.parm.aux.cmd = status;
  928. bcs->cs->iif.statcallb(&ic);
  929. }
  930. static void
  931. isar_pump_statev_fax(struct BCState *bcs, u_char devt) {
  932. struct IsdnCardState *cs = bcs->cs;
  933. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  934. u_char p1;
  935. switch(devt) {
  936. case PSEV_10MS_TIMER:
  937. if (cs->debug & L1_DEB_HSCX)
  938. debugl1(cs, "pump stev TIMER");
  939. break;
  940. case PSEV_RSP_READY:
  941. if (cs->debug & L1_DEB_HSCX)
  942. debugl1(cs, "pump stev RSP_READY");
  943. bcs->hw.isar.state = STFAX_READY;
  944. l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
  945. if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
  946. isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FRH, 3);
  947. } else {
  948. isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FTH, 3);
  949. }
  950. break;
  951. case PSEV_LINE_TX_H:
  952. if (bcs->hw.isar.state == STFAX_LINE) {
  953. if (cs->debug & L1_DEB_HSCX)
  954. debugl1(cs, "pump stev LINE_TX_H");
  955. bcs->hw.isar.state = STFAX_CONT;
  956. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
  957. } else {
  958. if (cs->debug & L1_DEB_WARN)
  959. debugl1(cs, "pump stev LINE_TX_H wrong st %x",
  960. bcs->hw.isar.state);
  961. }
  962. break;
  963. case PSEV_LINE_RX_H:
  964. if (bcs->hw.isar.state == STFAX_LINE) {
  965. if (cs->debug & L1_DEB_HSCX)
  966. debugl1(cs, "pump stev LINE_RX_H");
  967. bcs->hw.isar.state = STFAX_CONT;
  968. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
  969. } else {
  970. if (cs->debug & L1_DEB_WARN)
  971. debugl1(cs, "pump stev LINE_RX_H wrong st %x",
  972. bcs->hw.isar.state);
  973. }
  974. break;
  975. case PSEV_LINE_TX_B:
  976. if (bcs->hw.isar.state == STFAX_LINE) {
  977. if (cs->debug & L1_DEB_HSCX)
  978. debugl1(cs, "pump stev LINE_TX_B");
  979. bcs->hw.isar.state = STFAX_CONT;
  980. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
  981. } else {
  982. if (cs->debug & L1_DEB_WARN)
  983. debugl1(cs, "pump stev LINE_TX_B wrong st %x",
  984. bcs->hw.isar.state);
  985. }
  986. break;
  987. case PSEV_LINE_RX_B:
  988. if (bcs->hw.isar.state == STFAX_LINE) {
  989. if (cs->debug & L1_DEB_HSCX)
  990. debugl1(cs, "pump stev LINE_RX_B");
  991. bcs->hw.isar.state = STFAX_CONT;
  992. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
  993. } else {
  994. if (cs->debug & L1_DEB_WARN)
  995. debugl1(cs, "pump stev LINE_RX_B wrong st %x",
  996. bcs->hw.isar.state);
  997. }
  998. break;
  999. case PSEV_RSP_CONN:
  1000. if (bcs->hw.isar.state == STFAX_CONT) {
  1001. if (cs->debug & L1_DEB_HSCX)
  1002. debugl1(cs, "pump stev RSP_CONN");
  1003. bcs->hw.isar.state = STFAX_ACTIV;
  1004. test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
  1005. sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  1006. if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
  1007. /* 1s Flags before data */
  1008. if (test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag))
  1009. del_timer(&bcs->hw.isar.ftimer);
  1010. /* 1000 ms */
  1011. bcs->hw.isar.ftimer.expires =
  1012. jiffies + ((1000 * HZ)/1000);
  1013. test_and_set_bit(BC_FLG_LL_CONN,
  1014. &bcs->Flag);
  1015. add_timer(&bcs->hw.isar.ftimer);
  1016. } else {
  1017. schedule_event(bcs, B_LL_CONNECT);
  1018. }
  1019. } else {
  1020. if (cs->debug & L1_DEB_WARN)
  1021. debugl1(cs, "pump stev RSP_CONN wrong st %x",
  1022. bcs->hw.isar.state);
  1023. }
  1024. break;
  1025. case PSEV_FLAGS_DET:
  1026. if (cs->debug & L1_DEB_HSCX)
  1027. debugl1(cs, "pump stev FLAGS_DET");
  1028. break;
  1029. case PSEV_RSP_DISC:
  1030. if (cs->debug & L1_DEB_HSCX)
  1031. debugl1(cs, "pump stev RSP_DISC");
  1032. if (bcs->hw.isar.state == STFAX_ESCAPE) {
  1033. p1 = 5;
  1034. switch(bcs->hw.isar.newcmd) {
  1035. case 0:
  1036. bcs->hw.isar.state = STFAX_READY;
  1037. break;
  1038. case PCTRL_CMD_FTM:
  1039. p1 = 2;
  1040. case PCTRL_CMD_FTH:
  1041. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
  1042. PCTRL_CMD_SILON, 1, &p1);
  1043. bcs->hw.isar.state = STFAX_SILDET;
  1044. break;
  1045. case PCTRL_CMD_FRM:
  1046. if (frm_extra_delay)
  1047. mdelay(frm_extra_delay);
  1048. case PCTRL_CMD_FRH:
  1049. p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod;
  1050. bcs->hw.isar.newmod = 0;
  1051. bcs->hw.isar.cmd = bcs->hw.isar.newcmd;
  1052. bcs->hw.isar.newcmd = 0;
  1053. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
  1054. bcs->hw.isar.cmd, 1, &p1);
  1055. bcs->hw.isar.state = STFAX_LINE;
  1056. bcs->hw.isar.try_mod = 3;
  1057. break;
  1058. default:
  1059. if (cs->debug & L1_DEB_HSCX)
  1060. debugl1(cs, "RSP_DISC unknown newcmd %x", bcs->hw.isar.newcmd);
  1061. break;
  1062. }
  1063. } else if (bcs->hw.isar.state == STFAX_ACTIV) {
  1064. if (test_and_clear_bit(BC_FLG_LL_OK, &bcs->Flag)) {
  1065. schedule_event(bcs, B_LL_OK);
  1066. } else if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) {
  1067. send_DLE_ETX(bcs);
  1068. schedule_event(bcs, B_LL_NOCARRIER);
  1069. } else {
  1070. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
  1071. }
  1072. bcs->hw.isar.state = STFAX_READY;
  1073. } else {
  1074. bcs->hw.isar.state = STFAX_READY;
  1075. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
  1076. }
  1077. break;
  1078. case PSEV_RSP_SILDET:
  1079. if (cs->debug & L1_DEB_HSCX)
  1080. debugl1(cs, "pump stev RSP_SILDET");
  1081. if (bcs->hw.isar.state == STFAX_SILDET) {
  1082. p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod;
  1083. bcs->hw.isar.newmod = 0;
  1084. bcs->hw.isar.cmd = bcs->hw.isar.newcmd;
  1085. bcs->hw.isar.newcmd = 0;
  1086. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
  1087. bcs->hw.isar.cmd, 1, &p1);
  1088. bcs->hw.isar.state = STFAX_LINE;
  1089. bcs->hw.isar.try_mod = 3;
  1090. }
  1091. break;
  1092. case PSEV_RSP_SILOFF:
  1093. if (cs->debug & L1_DEB_HSCX)
  1094. debugl1(cs, "pump stev RSP_SILOFF");
  1095. break;
  1096. case PSEV_RSP_FCERR:
  1097. if (bcs->hw.isar.state == STFAX_LINE) {
  1098. if (cs->debug & L1_DEB_HSCX)
  1099. debugl1(cs, "pump stev RSP_FCERR try %d",
  1100. bcs->hw.isar.try_mod);
  1101. if (bcs->hw.isar.try_mod--) {
  1102. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
  1103. bcs->hw.isar.cmd, 1,
  1104. &bcs->hw.isar.mod);
  1105. break;
  1106. }
  1107. }
  1108. if (cs->debug & L1_DEB_HSCX)
  1109. debugl1(cs, "pump stev RSP_FCERR");
  1110. bcs->hw.isar.state = STFAX_ESCAPE;
  1111. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
  1112. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
  1113. break;
  1114. default:
  1115. break;
  1116. }
  1117. }
  1118. static char debbuf[128];
  1119. void
  1120. isar_int_main(struct IsdnCardState *cs)
  1121. {
  1122. struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
  1123. struct BCState *bcs;
  1124. get_irq_infos(cs, ireg);
  1125. switch (ireg->iis & ISAR_IIS_MSCMSD) {
  1126. case ISAR_IIS_RDATA:
  1127. if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
  1128. isar_rcv_frame(cs, bcs);
  1129. } else {
  1130. debugl1(cs, "isar spurious IIS_RDATA %x/%x/%x",
  1131. ireg->iis, ireg->cmsb, ireg->clsb);
  1132. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1133. }
  1134. break;
  1135. case ISAR_IIS_GSTEV:
  1136. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1137. ireg->bstat |= ireg->cmsb;
  1138. check_send(cs, ireg->cmsb);
  1139. break;
  1140. case ISAR_IIS_BSTEV:
  1141. #ifdef ERROR_STATISTIC
  1142. if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
  1143. if (ireg->cmsb == BSTEV_TBO)
  1144. bcs->err_tx++;
  1145. if (ireg->cmsb == BSTEV_RBO)
  1146. bcs->err_rdo++;
  1147. }
  1148. #endif
  1149. if (cs->debug & L1_DEB_WARN)
  1150. debugl1(cs, "Buffer STEV dpath%d msb(%x)",
  1151. ireg->iis>>6, ireg->cmsb);
  1152. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1153. break;
  1154. case ISAR_IIS_PSTEV:
  1155. if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
  1156. rcv_mbox(cs, ireg, (u_char *)ireg->par);
  1157. if (bcs->mode == L1_MODE_V32) {
  1158. isar_pump_statev_modem(bcs, ireg->cmsb);
  1159. } else if (bcs->mode == L1_MODE_FAX) {
  1160. isar_pump_statev_fax(bcs, ireg->cmsb);
  1161. } else if (ireg->cmsb == PSEV_10MS_TIMER) {
  1162. if (cs->debug & L1_DEB_HSCX)
  1163. debugl1(cs, "pump stev TIMER");
  1164. } else {
  1165. if (cs->debug & L1_DEB_WARN)
  1166. debugl1(cs, "isar IIS_PSTEV pmode %d stat %x",
  1167. bcs->mode, ireg->cmsb);
  1168. }
  1169. } else {
  1170. debugl1(cs, "isar spurious IIS_PSTEV %x/%x/%x",
  1171. ireg->iis, ireg->cmsb, ireg->clsb);
  1172. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1173. }
  1174. break;
  1175. case ISAR_IIS_PSTRSP:
  1176. if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
  1177. rcv_mbox(cs, ireg, (u_char *)ireg->par);
  1178. isar_pump_status_rsp(bcs, ireg);
  1179. } else {
  1180. debugl1(cs, "isar spurious IIS_PSTRSP %x/%x/%x",
  1181. ireg->iis, ireg->cmsb, ireg->clsb);
  1182. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1183. }
  1184. break;
  1185. case ISAR_IIS_DIAG:
  1186. case ISAR_IIS_BSTRSP:
  1187. case ISAR_IIS_IOM2RSP:
  1188. rcv_mbox(cs, ireg, (u_char *)ireg->par);
  1189. if ((cs->debug & (L1_DEB_HSCX | L1_DEB_HSCX_FIFO))
  1190. == L1_DEB_HSCX) {
  1191. u_char *tp=debbuf;
  1192. tp += sprintf(debbuf, "msg iis(%x) msb(%x)",
  1193. ireg->iis, ireg->cmsb);
  1194. QuickHex(tp, (u_char *)ireg->par, ireg->clsb);
  1195. debugl1(cs, debbuf);
  1196. }
  1197. break;
  1198. case ISAR_IIS_INVMSG:
  1199. rcv_mbox(cs, ireg, debbuf);
  1200. if (cs->debug & L1_DEB_WARN)
  1201. debugl1(cs, "invalid msg his:%x",
  1202. ireg->cmsb);
  1203. break;
  1204. default:
  1205. rcv_mbox(cs, ireg, debbuf);
  1206. if (cs->debug & L1_DEB_WARN)
  1207. debugl1(cs, "unhandled msg iis(%x) ctrl(%x/%x)",
  1208. ireg->iis, ireg->cmsb, ireg->clsb);
  1209. break;
  1210. }
  1211. }
  1212. static void
  1213. ftimer_handler(struct BCState *bcs) {
  1214. if (bcs->cs->debug)
  1215. debugl1(bcs->cs, "ftimer flags %04x",
  1216. bcs->Flag);
  1217. test_and_clear_bit(BC_FLG_FTI_RUN, &bcs->Flag);
  1218. if (test_and_clear_bit(BC_FLG_LL_CONN, &bcs->Flag)) {
  1219. schedule_event(bcs, B_LL_CONNECT);
  1220. }
  1221. if (test_and_clear_bit(BC_FLG_FTI_FTS, &bcs->Flag)) {
  1222. schedule_event(bcs, B_LL_OK);
  1223. }
  1224. }
  1225. static void
  1226. setup_pump(struct BCState *bcs) {
  1227. struct IsdnCardState *cs = bcs->cs;
  1228. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  1229. u_char ctrl, param[6];
  1230. switch (bcs->mode) {
  1231. case L1_MODE_NULL:
  1232. case L1_MODE_TRANS:
  1233. case L1_MODE_HDLC:
  1234. sendmsg(cs, dps | ISAR_HIS_PUMPCFG, PMOD_BYPASS, 0, NULL);
  1235. break;
  1236. case L1_MODE_V32:
  1237. ctrl = PMOD_DATAMODEM;
  1238. if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
  1239. ctrl |= PCTRL_ORIG;
  1240. param[5] = PV32P6_CTN;
  1241. } else {
  1242. param[5] = PV32P6_ATN;
  1243. }
  1244. param[0] = para_TOA; /* 6 db */
  1245. param[1] = PV32P2_V23R | PV32P2_V22A | PV32P2_V22B |
  1246. PV32P2_V22C | PV32P2_V21 | PV32P2_BEL;
  1247. param[2] = PV32P3_AMOD | PV32P3_V32B | PV32P3_V23B;
  1248. param[3] = PV32P4_UT144;
  1249. param[4] = PV32P5_UT144;
  1250. sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 6, param);
  1251. break;
  1252. case L1_MODE_FAX:
  1253. ctrl = PMOD_FAX;
  1254. if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
  1255. ctrl |= PCTRL_ORIG;
  1256. param[1] = PFAXP2_CTN;
  1257. } else {
  1258. param[1] = PFAXP2_ATN;
  1259. }
  1260. param[0] = para_TOA; /* 6 db */
  1261. sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 2, param);
  1262. bcs->hw.isar.state = STFAX_NULL;
  1263. bcs->hw.isar.newcmd = 0;
  1264. bcs->hw.isar.newmod = 0;
  1265. test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag);
  1266. break;
  1267. }
  1268. udelay(1000);
  1269. sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  1270. udelay(1000);
  1271. }
  1272. static void
  1273. setup_sart(struct BCState *bcs) {
  1274. struct IsdnCardState *cs = bcs->cs;
  1275. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  1276. u_char ctrl, param[2];
  1277. switch (bcs->mode) {
  1278. case L1_MODE_NULL:
  1279. sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_DISABLE, 0,
  1280. NULL);
  1281. break;
  1282. case L1_MODE_TRANS:
  1283. sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_BINARY, 2,
  1284. "\0\0");
  1285. break;
  1286. case L1_MODE_HDLC:
  1287. param[0] = 0;
  1288. sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_HDLC, 1,
  1289. param);
  1290. break;
  1291. case L1_MODE_V32:
  1292. ctrl = SMODE_V14 | SCTRL_HDMC_BOTH;
  1293. param[0] = S_P1_CHS_8;
  1294. param[1] = S_P2_BFT_DEF;
  1295. sendmsg(cs, dps | ISAR_HIS_SARTCFG, ctrl, 2,
  1296. param);
  1297. break;
  1298. case L1_MODE_FAX:
  1299. /* SART must not configured with FAX */
  1300. break;
  1301. }
  1302. udelay(1000);
  1303. sendmsg(cs, dps | ISAR_HIS_BSTREQ, 0, 0, NULL);
  1304. udelay(1000);
  1305. }
  1306. static void
  1307. setup_iom2(struct BCState *bcs) {
  1308. struct IsdnCardState *cs = bcs->cs;
  1309. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  1310. u_char cmsb = IOM_CTRL_ENA, msg[5] = {IOM_P1_TXD,0,0,0,0};
  1311. if (bcs->channel)
  1312. msg[1] = msg[3] = 1;
  1313. switch (bcs->mode) {
  1314. case L1_MODE_NULL:
  1315. cmsb = 0;
  1316. /* dummy slot */
  1317. msg[1] = msg[3] = bcs->hw.isar.dpath + 2;
  1318. break;
  1319. case L1_MODE_TRANS:
  1320. case L1_MODE_HDLC:
  1321. break;
  1322. case L1_MODE_V32:
  1323. case L1_MODE_FAX:
  1324. cmsb |= IOM_CTRL_ALAW | IOM_CTRL_RCV;
  1325. break;
  1326. }
  1327. sendmsg(cs, dps | ISAR_HIS_IOM2CFG, cmsb, 5, msg);
  1328. udelay(1000);
  1329. sendmsg(cs, dps | ISAR_HIS_IOM2REQ, 0, 0, NULL);
  1330. udelay(1000);
  1331. }
  1332. static int
  1333. modeisar(struct BCState *bcs, int mode, int bc)
  1334. {
  1335. struct IsdnCardState *cs = bcs->cs;
  1336. /* Here we are selecting the best datapath for requested mode */
  1337. if(bcs->mode == L1_MODE_NULL) { /* New Setup */
  1338. bcs->channel = bc;
  1339. switch (mode) {
  1340. case L1_MODE_NULL: /* init */
  1341. if (!bcs->hw.isar.dpath)
  1342. /* no init for dpath 0 */
  1343. return(0);
  1344. break;
  1345. case L1_MODE_TRANS:
  1346. case L1_MODE_HDLC:
  1347. /* best is datapath 2 */
  1348. if (!test_and_set_bit(ISAR_DP2_USE,
  1349. &bcs->hw.isar.reg->Flags))
  1350. bcs->hw.isar.dpath = 2;
  1351. else if (!test_and_set_bit(ISAR_DP1_USE,
  1352. &bcs->hw.isar.reg->Flags))
  1353. bcs->hw.isar.dpath = 1;
  1354. else {
  1355. printk(KERN_WARNING"isar modeisar both pathes in use\n");
  1356. return(1);
  1357. }
  1358. break;
  1359. case L1_MODE_V32:
  1360. case L1_MODE_FAX:
  1361. /* only datapath 1 */
  1362. if (!test_and_set_bit(ISAR_DP1_USE,
  1363. &bcs->hw.isar.reg->Flags))
  1364. bcs->hw.isar.dpath = 1;
  1365. else {
  1366. printk(KERN_WARNING"isar modeisar analog funktions only with DP1\n");
  1367. debugl1(cs, "isar modeisar analog funktions only with DP1");
  1368. return(1);
  1369. }
  1370. break;
  1371. }
  1372. }
  1373. if (cs->debug & L1_DEB_HSCX)
  1374. debugl1(cs, "isar dp%d mode %d->%d ichan %d",
  1375. bcs->hw.isar.dpath, bcs->mode, mode, bc);
  1376. bcs->mode = mode;
  1377. setup_pump(bcs);
  1378. setup_iom2(bcs);
  1379. setup_sart(bcs);
  1380. if (bcs->mode == L1_MODE_NULL) {
  1381. /* Clear resources */
  1382. if (bcs->hw.isar.dpath == 1)
  1383. test_and_clear_bit(ISAR_DP1_USE, &bcs->hw.isar.reg->Flags);
  1384. else if (bcs->hw.isar.dpath == 2)
  1385. test_and_clear_bit(ISAR_DP2_USE, &bcs->hw.isar.reg->Flags);
  1386. bcs->hw.isar.dpath = 0;
  1387. }
  1388. return(0);
  1389. }
  1390. static void
  1391. isar_pump_cmd(struct BCState *bcs, u_char cmd, u_char para)
  1392. {
  1393. struct IsdnCardState *cs = bcs->cs;
  1394. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  1395. u_char ctrl = 0, nom = 0, p1 = 0;
  1396. switch(cmd) {
  1397. case ISDN_FAX_CLASS1_FTM:
  1398. test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  1399. if (bcs->hw.isar.state == STFAX_READY) {
  1400. p1 = para;
  1401. ctrl = PCTRL_CMD_FTM;
  1402. nom = 1;
  1403. bcs->hw.isar.state = STFAX_LINE;
  1404. bcs->hw.isar.cmd = ctrl;
  1405. bcs->hw.isar.mod = para;
  1406. bcs->hw.isar.newmod = 0;
  1407. bcs->hw.isar.newcmd = 0;
  1408. bcs->hw.isar.try_mod = 3;
  1409. } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
  1410. (bcs->hw.isar.cmd == PCTRL_CMD_FTM) &&
  1411. (bcs->hw.isar.mod == para)) {
  1412. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  1413. } else {
  1414. bcs->hw.isar.newmod = para;
  1415. bcs->hw.isar.newcmd = PCTRL_CMD_FTM;
  1416. nom = 0;
  1417. ctrl = PCTRL_CMD_ESC;
  1418. bcs->hw.isar.state = STFAX_ESCAPE;
  1419. }
  1420. break;
  1421. case ISDN_FAX_CLASS1_FTH:
  1422. test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  1423. if (bcs->hw.isar.state == STFAX_READY) {
  1424. p1 = para;
  1425. ctrl = PCTRL_CMD_FTH;
  1426. nom = 1;
  1427. bcs->hw.isar.state = STFAX_LINE;
  1428. bcs->hw.isar.cmd = ctrl;
  1429. bcs->hw.isar.mod = para;
  1430. bcs->hw.isar.newmod = 0;
  1431. bcs->hw.isar.newcmd = 0;
  1432. bcs->hw.isar.try_mod = 3;
  1433. } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
  1434. (bcs->hw.isar.cmd == PCTRL_CMD_FTH) &&
  1435. (bcs->hw.isar.mod == para)) {
  1436. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  1437. } else {
  1438. bcs->hw.isar.newmod = para;
  1439. bcs->hw.isar.newcmd = PCTRL_CMD_FTH;
  1440. nom = 0;
  1441. ctrl = PCTRL_CMD_ESC;
  1442. bcs->hw.isar.state = STFAX_ESCAPE;
  1443. }
  1444. break;
  1445. case ISDN_FAX_CLASS1_FRM:
  1446. test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  1447. if (bcs->hw.isar.state == STFAX_READY) {
  1448. p1 = para;
  1449. ctrl = PCTRL_CMD_FRM;
  1450. nom = 1;
  1451. bcs->hw.isar.state = STFAX_LINE;
  1452. bcs->hw.isar.cmd = ctrl;
  1453. bcs->hw.isar.mod = para;
  1454. bcs->hw.isar.newmod = 0;
  1455. bcs->hw.isar.newcmd = 0;
  1456. bcs->hw.isar.try_mod = 3;
  1457. } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
  1458. (bcs->hw.isar.cmd == PCTRL_CMD_FRM) &&
  1459. (bcs->hw.isar.mod == para)) {
  1460. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  1461. } else {
  1462. bcs->hw.isar.newmod = para;
  1463. bcs->hw.isar.newcmd = PCTRL_CMD_FRM;
  1464. nom = 0;
  1465. ctrl = PCTRL_CMD_ESC;
  1466. bcs->hw.isar.state = STFAX_ESCAPE;
  1467. }
  1468. break;
  1469. case ISDN_FAX_CLASS1_FRH:
  1470. test_and_set_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  1471. if (bcs->hw.isar.state == STFAX_READY) {
  1472. p1 = para;
  1473. ctrl = PCTRL_CMD_FRH;
  1474. nom = 1;
  1475. bcs->hw.isar.state = STFAX_LINE;
  1476. bcs->hw.isar.cmd = ctrl;
  1477. bcs->hw.isar.mod = para;
  1478. bcs->hw.isar.newmod = 0;
  1479. bcs->hw.isar.newcmd = 0;
  1480. bcs->hw.isar.try_mod = 3;
  1481. } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
  1482. (bcs->hw.isar.cmd == PCTRL_CMD_FRH) &&
  1483. (bcs->hw.isar.mod == para)) {
  1484. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  1485. } else {
  1486. bcs->hw.isar.newmod = para;
  1487. bcs->hw.isar.newcmd = PCTRL_CMD_FRH;
  1488. nom = 0;
  1489. ctrl = PCTRL_CMD_ESC;
  1490. bcs->hw.isar.state = STFAX_ESCAPE;
  1491. }
  1492. break;
  1493. case ISDN_FAXPUMP_HALT:
  1494. bcs->hw.isar.state = STFAX_NULL;
  1495. nom = 0;
  1496. ctrl = PCTRL_CMD_HALT;
  1497. break;
  1498. }
  1499. if (ctrl)
  1500. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, ctrl, nom, &p1);
  1501. }
  1502. static void
  1503. isar_setup(struct IsdnCardState *cs)
  1504. {
  1505. u_char msg;
  1506. int i;
  1507. /* Dpath 1, 2 */
  1508. msg = 61;
  1509. for (i=0; i<2; i++) {
  1510. /* Buffer Config */
  1511. sendmsg(cs, (i ? ISAR_HIS_DPS2 : ISAR_HIS_DPS1) |
  1512. ISAR_HIS_P12CFG, 4, 1, &msg);
  1513. cs->bcs[i].hw.isar.mml = msg;
  1514. cs->bcs[i].mode = 0;
  1515. cs->bcs[i].hw.isar.dpath = i + 1;
  1516. modeisar(&cs->bcs[i], 0, 0);
  1517. INIT_WORK(&cs->bcs[i].tqueue, isar_bh);
  1518. }
  1519. }
  1520. static void
  1521. isar_l2l1(struct PStack *st, int pr, void *arg)
  1522. {
  1523. struct BCState *bcs = st->l1.bcs;
  1524. struct sk_buff *skb = arg;
  1525. int ret;
  1526. u_long flags;
  1527. switch (pr) {
  1528. case (PH_DATA | REQUEST):
  1529. spin_lock_irqsave(&bcs->cs->lock, flags);
  1530. if (bcs->tx_skb) {
  1531. skb_queue_tail(&bcs->squeue, skb);
  1532. } else {
  1533. bcs->tx_skb = skb;
  1534. test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
  1535. if (bcs->cs->debug & L1_DEB_HSCX)
  1536. debugl1(bcs->cs, "DRQ set BC_FLG_BUSY");
  1537. bcs->hw.isar.txcnt = 0;
  1538. bcs->cs->BC_Send_Data(bcs);
  1539. }
  1540. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1541. break;
  1542. case (PH_PULL | INDICATION):
  1543. spin_lock_irqsave(&bcs->cs->lock, flags);
  1544. if (bcs->tx_skb) {
  1545. printk(KERN_WARNING "isar_l2l1: this shouldn't happen\n");
  1546. } else {
  1547. test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
  1548. if (bcs->cs->debug & L1_DEB_HSCX)
  1549. debugl1(bcs->cs, "PUI set BC_FLG_BUSY");
  1550. bcs->tx_skb = skb;
  1551. bcs->hw.isar.txcnt = 0;
  1552. bcs->cs->BC_Send_Data(bcs);
  1553. }
  1554. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1555. break;
  1556. case (PH_PULL | REQUEST):
  1557. if (!bcs->tx_skb) {
  1558. test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
  1559. st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
  1560. } else
  1561. test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
  1562. break;
  1563. case (PH_ACTIVATE | REQUEST):
  1564. spin_lock_irqsave(&bcs->cs->lock, flags);
  1565. test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
  1566. bcs->hw.isar.conmsg[0] = 0;
  1567. if (test_bit(FLG_ORIG, &st->l2.flag))
  1568. test_and_set_bit(BC_FLG_ORIG, &bcs->Flag);
  1569. else
  1570. test_and_clear_bit(BC_FLG_ORIG, &bcs->Flag);
  1571. switch(st->l1.mode) {
  1572. case L1_MODE_TRANS:
  1573. case L1_MODE_HDLC:
  1574. ret = modeisar(bcs, st->l1.mode, st->l1.bc);
  1575. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1576. if (ret)
  1577. l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
  1578. else
  1579. l1_msg_b(st, PH_ACTIVATE | REQUEST, arg);
  1580. break;
  1581. case L1_MODE_V32:
  1582. case L1_MODE_FAX:
  1583. ret = modeisar(bcs, st->l1.mode, st->l1.bc);
  1584. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1585. if (ret)
  1586. l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
  1587. break;
  1588. default:
  1589. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1590. break;
  1591. }
  1592. break;
  1593. case (PH_DEACTIVATE | REQUEST):
  1594. l1_msg_b(st, pr, arg);
  1595. break;
  1596. case (PH_DEACTIVATE | CONFIRM):
  1597. spin_lock_irqsave(&bcs->cs->lock, flags);
  1598. switch(st->l1.mode) {
  1599. case L1_MODE_TRANS:
  1600. case L1_MODE_HDLC:
  1601. case L1_MODE_V32:
  1602. break;
  1603. case L1_MODE_FAX:
  1604. isar_pump_cmd(bcs, ISDN_FAXPUMP_HALT, 0);
  1605. break;
  1606. }
  1607. test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
  1608. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  1609. if (bcs->cs->debug & L1_DEB_HSCX)
  1610. debugl1(bcs->cs, "PDAC clear BC_FLG_BUSY");
  1611. modeisar(bcs, 0, st->l1.bc);
  1612. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1613. st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
  1614. break;
  1615. }
  1616. }
  1617. static void
  1618. close_isarstate(struct BCState *bcs)
  1619. {
  1620. modeisar(bcs, 0, bcs->channel);
  1621. if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
  1622. kfree(bcs->hw.isar.rcvbuf);
  1623. bcs->hw.isar.rcvbuf = NULL;
  1624. skb_queue_purge(&bcs->rqueue);
  1625. skb_queue_purge(&bcs->squeue);
  1626. if (bcs->tx_skb) {
  1627. dev_kfree_skb_any(bcs->tx_skb);
  1628. bcs->tx_skb = NULL;
  1629. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  1630. if (bcs->cs->debug & L1_DEB_HSCX)
  1631. debugl1(bcs->cs, "closeisar clear BC_FLG_BUSY");
  1632. }
  1633. }
  1634. del_timer(&bcs->hw.isar.ftimer);
  1635. }
  1636. static int
  1637. open_isarstate(struct IsdnCardState *cs, struct BCState *bcs)
  1638. {
  1639. if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
  1640. if (!(bcs->hw.isar.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
  1641. printk(KERN_WARNING
  1642. "HiSax: No memory for isar.rcvbuf\n");
  1643. return (1);
  1644. }
  1645. skb_queue_head_init(&bcs->rqueue);
  1646. skb_queue_head_init(&bcs->squeue);
  1647. }
  1648. bcs->tx_skb = NULL;
  1649. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  1650. if (cs->debug & L1_DEB_HSCX)
  1651. debugl1(cs, "openisar clear BC_FLG_BUSY");
  1652. bcs->event = 0;
  1653. bcs->hw.isar.rcvidx = 0;
  1654. bcs->tx_cnt = 0;
  1655. return (0);
  1656. }
  1657. static int
  1658. setstack_isar(struct PStack *st, struct BCState *bcs)
  1659. {
  1660. bcs->channel = st->l1.bc;
  1661. if (open_isarstate(st->l1.hardware, bcs))
  1662. return (-1);
  1663. st->l1.bcs = bcs;
  1664. st->l2.l2l1 = isar_l2l1;
  1665. setstack_manager(st);
  1666. bcs->st = st;
  1667. setstack_l1_B(st);
  1668. return (0);
  1669. }
  1670. int
  1671. isar_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) {
  1672. u_long adr;
  1673. int features, i;
  1674. struct BCState *bcs;
  1675. if (cs->debug & L1_DEB_HSCX)
  1676. debugl1(cs, "isar_auxcmd cmd/ch %x/%d", ic->command, ic->arg);
  1677. switch (ic->command) {
  1678. case (ISDN_CMD_FAXCMD):
  1679. bcs = cs->channel[ic->arg].bcs;
  1680. if (cs->debug & L1_DEB_HSCX)
  1681. debugl1(cs, "isar_auxcmd cmd/subcmd %d/%d",
  1682. ic->parm.aux.cmd, ic->parm.aux.subcmd);
  1683. switch(ic->parm.aux.cmd) {
  1684. case ISDN_FAX_CLASS1_CTRL:
  1685. if (ic->parm.aux.subcmd == ETX)
  1686. test_and_set_bit(BC_FLG_DLEETX,
  1687. &bcs->Flag);
  1688. break;
  1689. case ISDN_FAX_CLASS1_FTS:
  1690. if (ic->parm.aux.subcmd == AT_QUERY) {
  1691. ic->command = ISDN_STAT_FAXIND;
  1692. ic->parm.aux.cmd = ISDN_FAX_CLASS1_OK;
  1693. cs->iif.statcallb(ic);
  1694. return(0);
  1695. } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) {
  1696. strcpy(ic->parm.aux.para, "0-255");
  1697. ic->command = ISDN_STAT_FAXIND;
  1698. ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
  1699. cs->iif.statcallb(ic);
  1700. return(0);
  1701. } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) {
  1702. if (cs->debug & L1_DEB_HSCX)
  1703. debugl1(cs, "isar_auxcmd %s=%d",
  1704. FC1_CMD[ic->parm.aux.cmd], ic->parm.aux.para[0]);
  1705. if (bcs->hw.isar.state == STFAX_READY) {
  1706. if (! ic->parm.aux.para[0]) {
  1707. ic->command = ISDN_STAT_FAXIND;
  1708. ic->parm.aux.cmd = ISDN_FAX_CLASS1_OK;
  1709. cs->iif.statcallb(ic);
  1710. return(0);
  1711. }
  1712. if (! test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag)) {
  1713. /* n*10 ms */
  1714. bcs->hw.isar.ftimer.expires =
  1715. jiffies + ((ic->parm.aux.para[0] * 10 * HZ)/1000);
  1716. test_and_set_bit(BC_FLG_FTI_FTS, &bcs->Flag);
  1717. add_timer(&bcs->hw.isar.ftimer);
  1718. return(0);
  1719. } else {
  1720. if (cs->debug)
  1721. debugl1(cs, "isar FTS=%d and FTI busy",
  1722. ic->parm.aux.para[0]);
  1723. }
  1724. } else {
  1725. if (cs->debug)
  1726. debugl1(cs, "isar FTS=%d and isar.state not ready(%x)",
  1727. ic->parm.aux.para[0],bcs->hw.isar.state);
  1728. }
  1729. ic->command = ISDN_STAT_FAXIND;
  1730. ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR;
  1731. cs->iif.statcallb(ic);
  1732. }
  1733. break;
  1734. case ISDN_FAX_CLASS1_FRM:
  1735. case ISDN_FAX_CLASS1_FRH:
  1736. case ISDN_FAX_CLASS1_FTM:
  1737. case ISDN_FAX_CLASS1_FTH:
  1738. if (ic->parm.aux.subcmd == AT_QUERY) {
  1739. sprintf(ic->parm.aux.para,
  1740. "%d", bcs->hw.isar.mod);
  1741. ic->command = ISDN_STAT_FAXIND;
  1742. ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
  1743. cs->iif.statcallb(ic);
  1744. return(0);
  1745. } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) {
  1746. char *p = ic->parm.aux.para;
  1747. for(i=0;i<FAXMODCNT;i++)
  1748. if ((1<<i) & modmask)
  1749. p += sprintf(p, "%d,", faxmodulation[i]);
  1750. p--;
  1751. *p=0;
  1752. ic->command = ISDN_STAT_FAXIND;
  1753. ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
  1754. cs->iif.statcallb(ic);
  1755. return(0);
  1756. } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) {
  1757. if (cs->debug & L1_DEB_HSCX)
  1758. debugl1(cs, "isar_auxcmd %s=%d",
  1759. FC1_CMD[ic->parm.aux.cmd], ic->parm.aux.para[0]);
  1760. for(i=0;i<FAXMODCNT;i++)
  1761. if (faxmodulation[i]==ic->parm.aux.para[0])
  1762. break;
  1763. if ((i < FAXMODCNT) && ((1<<i) & modmask) &&
  1764. test_bit(BC_FLG_INIT, &bcs->Flag)) {
  1765. isar_pump_cmd(bcs,
  1766. ic->parm.aux.cmd,
  1767. ic->parm.aux.para[0]);
  1768. return(0);
  1769. }
  1770. }
  1771. /* wrong modulation or not activ */
  1772. /* fall through */
  1773. default:
  1774. ic->command = ISDN_STAT_FAXIND;
  1775. ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR;
  1776. cs->iif.statcallb(ic);
  1777. }
  1778. break;
  1779. case (ISDN_CMD_IOCTL):
  1780. switch (ic->arg) {
  1781. case 9: /* load firmware */
  1782. features = ISDN_FEATURE_L2_MODEM |
  1783. ISDN_FEATURE_L2_FAX |
  1784. ISDN_FEATURE_L3_FCLASS1;
  1785. memcpy(&adr, ic->parm.num, sizeof(ulong));
  1786. if (isar_load_firmware(cs, (u_char __user *)adr))
  1787. return(1);
  1788. else
  1789. ll_run(cs, features);
  1790. break;
  1791. case 20:
  1792. features = *(unsigned int *) ic->parm.num;
  1793. printk(KERN_DEBUG "HiSax: max modulation old(%04x) new(%04x)\n",
  1794. modmask, features);
  1795. modmask = features;
  1796. break;
  1797. case 21:
  1798. features = *(unsigned int *) ic->parm.num;
  1799. printk(KERN_DEBUG "HiSax: FRM extra delay old(%d) new(%d) ms\n",
  1800. frm_extra_delay, features);
  1801. if (features >= 0)
  1802. frm_extra_delay = features;
  1803. break;
  1804. case 22:
  1805. features = *(unsigned int *) ic->parm.num;
  1806. printk(KERN_DEBUG "HiSax: TOA old(%d) new(%d) db\n",
  1807. para_TOA, features);
  1808. if (features >= 0 && features < 32)
  1809. para_TOA = features;
  1810. break;
  1811. default:
  1812. printk(KERN_DEBUG "HiSax: invalid ioctl %d\n",
  1813. (int) ic->arg);
  1814. return(-EINVAL);
  1815. }
  1816. break;
  1817. default:
  1818. return(-EINVAL);
  1819. }
  1820. return(0);
  1821. }
  1822. void initisar(struct IsdnCardState *cs)
  1823. {
  1824. cs->bcs[0].BC_SetStack = setstack_isar;
  1825. cs->bcs[1].BC_SetStack = setstack_isar;
  1826. cs->bcs[0].BC_Close = close_isarstate;
  1827. cs->bcs[1].BC_Close = close_isarstate;
  1828. cs->bcs[0].hw.isar.ftimer.function = (void *) ftimer_handler;
  1829. cs->bcs[0].hw.isar.ftimer.data = (long) &cs->bcs[0];
  1830. init_timer(&cs->bcs[0].hw.isar.ftimer);
  1831. cs->bcs[1].hw.isar.ftimer.function = (void *) ftimer_handler;
  1832. cs->bcs[1].hw.isar.ftimer.data = (long) &cs->bcs[1];
  1833. init_timer(&cs->bcs[1].hw.isar.ftimer);
  1834. }