radeon_object.c 12 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30. * Dave Airlie
  31. */
  32. #include <linux/list.h>
  33. #include <linux/slab.h>
  34. #include <drm/drmP.h>
  35. #include "radeon_drm.h"
  36. #include "radeon.h"
  37. int radeon_ttm_init(struct radeon_device *rdev);
  38. void radeon_ttm_fini(struct radeon_device *rdev);
  39. static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  40. /*
  41. * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  42. * function are calling it.
  43. */
  44. static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  45. {
  46. struct radeon_bo *bo;
  47. bo = container_of(tbo, struct radeon_bo, tbo);
  48. mutex_lock(&bo->rdev->gem.mutex);
  49. list_del_init(&bo->list);
  50. mutex_unlock(&bo->rdev->gem.mutex);
  51. radeon_bo_clear_surface_reg(bo);
  52. kfree(bo);
  53. }
  54. bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  55. {
  56. if (bo->destroy == &radeon_ttm_bo_destroy)
  57. return true;
  58. return false;
  59. }
  60. void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  61. {
  62. u32 c = 0;
  63. rbo->placement.fpfn = 0;
  64. rbo->placement.lpfn = 0;
  65. rbo->placement.placement = rbo->placements;
  66. rbo->placement.busy_placement = rbo->placements;
  67. if (domain & RADEON_GEM_DOMAIN_VRAM)
  68. rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  69. TTM_PL_FLAG_VRAM;
  70. if (domain & RADEON_GEM_DOMAIN_GTT)
  71. rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  72. if (domain & RADEON_GEM_DOMAIN_CPU)
  73. rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  74. if (!c)
  75. rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  76. rbo->placement.num_placement = c;
  77. rbo->placement.num_busy_placement = c;
  78. }
  79. int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
  80. unsigned long size, bool kernel, u32 domain,
  81. struct radeon_bo **bo_ptr)
  82. {
  83. struct radeon_bo *bo;
  84. enum ttm_bo_type type;
  85. int r;
  86. if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
  87. rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
  88. }
  89. if (kernel) {
  90. type = ttm_bo_type_kernel;
  91. } else {
  92. type = ttm_bo_type_device;
  93. }
  94. *bo_ptr = NULL;
  95. bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
  96. if (bo == NULL)
  97. return -ENOMEM;
  98. bo->rdev = rdev;
  99. bo->gobj = gobj;
  100. bo->surface_reg = -1;
  101. INIT_LIST_HEAD(&bo->list);
  102. radeon_ttm_placement_from_domain(bo, domain);
  103. /* Kernel allocation are uninterruptible */
  104. r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
  105. &bo->placement, 0, 0, !kernel, NULL, size,
  106. &radeon_ttm_bo_destroy);
  107. if (unlikely(r != 0)) {
  108. if (r != -ERESTARTSYS)
  109. dev_err(rdev->dev,
  110. "object_init failed for (%lu, 0x%08X)\n",
  111. size, domain);
  112. return r;
  113. }
  114. *bo_ptr = bo;
  115. if (gobj) {
  116. mutex_lock(&bo->rdev->gem.mutex);
  117. list_add_tail(&bo->list, &rdev->gem.objects);
  118. mutex_unlock(&bo->rdev->gem.mutex);
  119. }
  120. return 0;
  121. }
  122. int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
  123. {
  124. bool is_iomem;
  125. int r;
  126. if (bo->kptr) {
  127. if (ptr) {
  128. *ptr = bo->kptr;
  129. }
  130. return 0;
  131. }
  132. r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
  133. if (r) {
  134. return r;
  135. }
  136. bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
  137. if (ptr) {
  138. *ptr = bo->kptr;
  139. }
  140. radeon_bo_check_tiling(bo, 0, 0);
  141. return 0;
  142. }
  143. void radeon_bo_kunmap(struct radeon_bo *bo)
  144. {
  145. if (bo->kptr == NULL)
  146. return;
  147. bo->kptr = NULL;
  148. radeon_bo_check_tiling(bo, 0, 0);
  149. ttm_bo_kunmap(&bo->kmap);
  150. }
  151. void radeon_bo_unref(struct radeon_bo **bo)
  152. {
  153. struct ttm_buffer_object *tbo;
  154. if ((*bo) == NULL)
  155. return;
  156. tbo = &((*bo)->tbo);
  157. ttm_bo_unref(&tbo);
  158. if (tbo == NULL)
  159. *bo = NULL;
  160. }
  161. int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
  162. {
  163. int r, i;
  164. if (bo->pin_count) {
  165. bo->pin_count++;
  166. if (gpu_addr)
  167. *gpu_addr = radeon_bo_gpu_offset(bo);
  168. return 0;
  169. }
  170. radeon_ttm_placement_from_domain(bo, domain);
  171. if (domain == RADEON_GEM_DOMAIN_VRAM) {
  172. /* force to pin into visible video ram */
  173. bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
  174. }
  175. for (i = 0; i < bo->placement.num_placement; i++)
  176. bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
  177. r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
  178. if (likely(r == 0)) {
  179. bo->pin_count = 1;
  180. if (gpu_addr != NULL)
  181. *gpu_addr = radeon_bo_gpu_offset(bo);
  182. }
  183. if (unlikely(r != 0))
  184. dev_err(bo->rdev->dev, "%p pin failed\n", bo);
  185. return r;
  186. }
  187. int radeon_bo_unpin(struct radeon_bo *bo)
  188. {
  189. int r, i;
  190. if (!bo->pin_count) {
  191. dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
  192. return 0;
  193. }
  194. bo->pin_count--;
  195. if (bo->pin_count)
  196. return 0;
  197. for (i = 0; i < bo->placement.num_placement; i++)
  198. bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
  199. r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
  200. if (unlikely(r != 0))
  201. dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
  202. return r;
  203. }
  204. int radeon_bo_evict_vram(struct radeon_device *rdev)
  205. {
  206. /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
  207. if (0 && (rdev->flags & RADEON_IS_IGP)) {
  208. if (rdev->mc.igp_sideport_enabled == false)
  209. /* Useless to evict on IGP chips */
  210. return 0;
  211. }
  212. return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
  213. }
  214. void radeon_bo_force_delete(struct radeon_device *rdev)
  215. {
  216. struct radeon_bo *bo, *n;
  217. struct drm_gem_object *gobj;
  218. if (list_empty(&rdev->gem.objects)) {
  219. return;
  220. }
  221. dev_err(rdev->dev, "Userspace still has active objects !\n");
  222. list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
  223. mutex_lock(&rdev->ddev->struct_mutex);
  224. gobj = bo->gobj;
  225. dev_err(rdev->dev, "%p %p %lu %lu force free\n",
  226. gobj, bo, (unsigned long)gobj->size,
  227. *((unsigned long *)&gobj->refcount));
  228. mutex_lock(&bo->rdev->gem.mutex);
  229. list_del_init(&bo->list);
  230. mutex_unlock(&bo->rdev->gem.mutex);
  231. radeon_bo_unref(&bo);
  232. gobj->driver_private = NULL;
  233. drm_gem_object_unreference(gobj);
  234. mutex_unlock(&rdev->ddev->struct_mutex);
  235. }
  236. }
  237. int radeon_bo_init(struct radeon_device *rdev)
  238. {
  239. /* Add an MTRR for the VRAM */
  240. rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
  241. MTRR_TYPE_WRCOMB, 1);
  242. DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
  243. rdev->mc.mc_vram_size >> 20,
  244. (unsigned long long)rdev->mc.aper_size >> 20);
  245. DRM_INFO("RAM width %dbits %cDR\n",
  246. rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
  247. return radeon_ttm_init(rdev);
  248. }
  249. void radeon_bo_fini(struct radeon_device *rdev)
  250. {
  251. radeon_ttm_fini(rdev);
  252. }
  253. void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
  254. struct list_head *head)
  255. {
  256. if (lobj->wdomain) {
  257. list_add(&lobj->list, head);
  258. } else {
  259. list_add_tail(&lobj->list, head);
  260. }
  261. }
  262. int radeon_bo_list_reserve(struct list_head *head)
  263. {
  264. struct radeon_bo_list *lobj;
  265. int r;
  266. list_for_each_entry(lobj, head, list){
  267. r = radeon_bo_reserve(lobj->bo, false);
  268. if (unlikely(r != 0))
  269. return r;
  270. }
  271. return 0;
  272. }
  273. void radeon_bo_list_unreserve(struct list_head *head)
  274. {
  275. struct radeon_bo_list *lobj;
  276. list_for_each_entry(lobj, head, list) {
  277. /* only unreserve object we successfully reserved */
  278. if (radeon_bo_is_reserved(lobj->bo))
  279. radeon_bo_unreserve(lobj->bo);
  280. }
  281. }
  282. int radeon_bo_list_validate(struct list_head *head)
  283. {
  284. struct radeon_bo_list *lobj;
  285. struct radeon_bo *bo;
  286. int r;
  287. r = radeon_bo_list_reserve(head);
  288. if (unlikely(r != 0)) {
  289. return r;
  290. }
  291. list_for_each_entry(lobj, head, list) {
  292. bo = lobj->bo;
  293. if (!bo->pin_count) {
  294. if (lobj->wdomain) {
  295. radeon_ttm_placement_from_domain(bo,
  296. lobj->wdomain);
  297. } else {
  298. radeon_ttm_placement_from_domain(bo,
  299. lobj->rdomain);
  300. }
  301. r = ttm_bo_validate(&bo->tbo, &bo->placement,
  302. true, false);
  303. if (unlikely(r))
  304. return r;
  305. }
  306. lobj->gpu_offset = radeon_bo_gpu_offset(bo);
  307. lobj->tiling_flags = bo->tiling_flags;
  308. }
  309. return 0;
  310. }
  311. void radeon_bo_list_fence(struct list_head *head, void *fence)
  312. {
  313. struct radeon_bo_list *lobj;
  314. struct radeon_bo *bo;
  315. struct radeon_fence *old_fence = NULL;
  316. list_for_each_entry(lobj, head, list) {
  317. bo = lobj->bo;
  318. spin_lock(&bo->tbo.lock);
  319. old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
  320. bo->tbo.sync_obj = radeon_fence_ref(fence);
  321. bo->tbo.sync_obj_arg = NULL;
  322. spin_unlock(&bo->tbo.lock);
  323. if (old_fence) {
  324. radeon_fence_unref(&old_fence);
  325. }
  326. }
  327. }
  328. int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
  329. struct vm_area_struct *vma)
  330. {
  331. return ttm_fbdev_mmap(vma, &bo->tbo);
  332. }
  333. int radeon_bo_get_surface_reg(struct radeon_bo *bo)
  334. {
  335. struct radeon_device *rdev = bo->rdev;
  336. struct radeon_surface_reg *reg;
  337. struct radeon_bo *old_object;
  338. int steal;
  339. int i;
  340. BUG_ON(!atomic_read(&bo->tbo.reserved));
  341. if (!bo->tiling_flags)
  342. return 0;
  343. if (bo->surface_reg >= 0) {
  344. reg = &rdev->surface_regs[bo->surface_reg];
  345. i = bo->surface_reg;
  346. goto out;
  347. }
  348. steal = -1;
  349. for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  350. reg = &rdev->surface_regs[i];
  351. if (!reg->bo)
  352. break;
  353. old_object = reg->bo;
  354. if (old_object->pin_count == 0)
  355. steal = i;
  356. }
  357. /* if we are all out */
  358. if (i == RADEON_GEM_MAX_SURFACES) {
  359. if (steal == -1)
  360. return -ENOMEM;
  361. /* find someone with a surface reg and nuke their BO */
  362. reg = &rdev->surface_regs[steal];
  363. old_object = reg->bo;
  364. /* blow away the mapping */
  365. DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
  366. ttm_bo_unmap_virtual(&old_object->tbo);
  367. old_object->surface_reg = -1;
  368. i = steal;
  369. }
  370. bo->surface_reg = i;
  371. reg->bo = bo;
  372. out:
  373. radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
  374. bo->tbo.mem.mm_node->start << PAGE_SHIFT,
  375. bo->tbo.num_pages << PAGE_SHIFT);
  376. return 0;
  377. }
  378. static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
  379. {
  380. struct radeon_device *rdev = bo->rdev;
  381. struct radeon_surface_reg *reg;
  382. if (bo->surface_reg == -1)
  383. return;
  384. reg = &rdev->surface_regs[bo->surface_reg];
  385. radeon_clear_surface_reg(rdev, bo->surface_reg);
  386. reg->bo = NULL;
  387. bo->surface_reg = -1;
  388. }
  389. int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
  390. uint32_t tiling_flags, uint32_t pitch)
  391. {
  392. int r;
  393. r = radeon_bo_reserve(bo, false);
  394. if (unlikely(r != 0))
  395. return r;
  396. bo->tiling_flags = tiling_flags;
  397. bo->pitch = pitch;
  398. radeon_bo_unreserve(bo);
  399. return 0;
  400. }
  401. void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
  402. uint32_t *tiling_flags,
  403. uint32_t *pitch)
  404. {
  405. BUG_ON(!atomic_read(&bo->tbo.reserved));
  406. if (tiling_flags)
  407. *tiling_flags = bo->tiling_flags;
  408. if (pitch)
  409. *pitch = bo->pitch;
  410. }
  411. int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
  412. bool force_drop)
  413. {
  414. BUG_ON(!atomic_read(&bo->tbo.reserved));
  415. if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
  416. return 0;
  417. if (force_drop) {
  418. radeon_bo_clear_surface_reg(bo);
  419. return 0;
  420. }
  421. if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
  422. if (!has_moved)
  423. return 0;
  424. if (bo->surface_reg >= 0)
  425. radeon_bo_clear_surface_reg(bo);
  426. return 0;
  427. }
  428. if ((bo->surface_reg >= 0) && !has_moved)
  429. return 0;
  430. return radeon_bo_get_surface_reg(bo);
  431. }
  432. void radeon_bo_move_notify(struct ttm_buffer_object *bo,
  433. struct ttm_mem_reg *mem)
  434. {
  435. struct radeon_bo *rbo;
  436. if (!radeon_ttm_bo_is_radeon_bo(bo))
  437. return;
  438. rbo = container_of(bo, struct radeon_bo, tbo);
  439. radeon_bo_check_tiling(rbo, 0, 1);
  440. }
  441. void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
  442. {
  443. struct radeon_bo *rbo;
  444. if (!radeon_ttm_bo_is_radeon_bo(bo))
  445. return;
  446. rbo = container_of(bo, struct radeon_bo, tbo);
  447. radeon_bo_check_tiling(rbo, 0, 0);
  448. }