i915_debugfs.c 22 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "i915_drm.h"
  34. #include "i915_drv.h"
  35. #define DRM_I915_RING_DEBUG 1
  36. #if defined(CONFIG_DEBUG_FS)
  37. #define ACTIVE_LIST 1
  38. #define FLUSHING_LIST 2
  39. #define INACTIVE_LIST 3
  40. static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv)
  41. {
  42. if (obj_priv->user_pin_count > 0)
  43. return "P";
  44. else if (obj_priv->pin_count > 0)
  45. return "p";
  46. else
  47. return " ";
  48. }
  49. static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv)
  50. {
  51. switch (obj_priv->tiling_mode) {
  52. default:
  53. case I915_TILING_NONE: return " ";
  54. case I915_TILING_X: return "X";
  55. case I915_TILING_Y: return "Y";
  56. }
  57. }
  58. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  59. {
  60. struct drm_info_node *node = (struct drm_info_node *) m->private;
  61. uintptr_t list = (uintptr_t) node->info_ent->data;
  62. struct list_head *head;
  63. struct drm_device *dev = node->minor->dev;
  64. drm_i915_private_t *dev_priv = dev->dev_private;
  65. struct drm_i915_gem_object *obj_priv;
  66. spinlock_t *lock = NULL;
  67. switch (list) {
  68. case ACTIVE_LIST:
  69. seq_printf(m, "Active:\n");
  70. lock = &dev_priv->mm.active_list_lock;
  71. head = &dev_priv->mm.active_list;
  72. break;
  73. case INACTIVE_LIST:
  74. seq_printf(m, "Inactive:\n");
  75. head = &dev_priv->mm.inactive_list;
  76. break;
  77. case FLUSHING_LIST:
  78. seq_printf(m, "Flushing:\n");
  79. head = &dev_priv->mm.flushing_list;
  80. break;
  81. default:
  82. DRM_INFO("Ooops, unexpected list\n");
  83. return 0;
  84. }
  85. if (lock)
  86. spin_lock(lock);
  87. list_for_each_entry(obj_priv, head, list)
  88. {
  89. struct drm_gem_object *obj = obj_priv->obj;
  90. seq_printf(m, " %p: %s %8zd %08x %08x %d%s%s",
  91. obj,
  92. get_pin_flag(obj_priv),
  93. obj->size,
  94. obj->read_domains, obj->write_domain,
  95. obj_priv->last_rendering_seqno,
  96. obj_priv->dirty ? " dirty" : "",
  97. obj_priv->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  98. if (obj->name)
  99. seq_printf(m, " (name: %d)", obj->name);
  100. if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
  101. seq_printf(m, " (fence: %d)", obj_priv->fence_reg);
  102. if (obj_priv->gtt_space != NULL)
  103. seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset);
  104. seq_printf(m, "\n");
  105. }
  106. if (lock)
  107. spin_unlock(lock);
  108. return 0;
  109. }
  110. static int i915_gem_request_info(struct seq_file *m, void *data)
  111. {
  112. struct drm_info_node *node = (struct drm_info_node *) m->private;
  113. struct drm_device *dev = node->minor->dev;
  114. drm_i915_private_t *dev_priv = dev->dev_private;
  115. struct drm_i915_gem_request *gem_request;
  116. seq_printf(m, "Request:\n");
  117. list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) {
  118. seq_printf(m, " %d @ %d\n",
  119. gem_request->seqno,
  120. (int) (jiffies - gem_request->emitted_jiffies));
  121. }
  122. return 0;
  123. }
  124. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  125. {
  126. struct drm_info_node *node = (struct drm_info_node *) m->private;
  127. struct drm_device *dev = node->minor->dev;
  128. drm_i915_private_t *dev_priv = dev->dev_private;
  129. if (dev_priv->hw_status_page != NULL) {
  130. seq_printf(m, "Current sequence: %d\n",
  131. i915_get_gem_seqno(dev));
  132. } else {
  133. seq_printf(m, "Current sequence: hws uninitialized\n");
  134. }
  135. seq_printf(m, "Waiter sequence: %d\n",
  136. dev_priv->mm.waiting_gem_seqno);
  137. seq_printf(m, "IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno);
  138. return 0;
  139. }
  140. static int i915_interrupt_info(struct seq_file *m, void *data)
  141. {
  142. struct drm_info_node *node = (struct drm_info_node *) m->private;
  143. struct drm_device *dev = node->minor->dev;
  144. drm_i915_private_t *dev_priv = dev->dev_private;
  145. if (!HAS_PCH_SPLIT(dev)) {
  146. seq_printf(m, "Interrupt enable: %08x\n",
  147. I915_READ(IER));
  148. seq_printf(m, "Interrupt identity: %08x\n",
  149. I915_READ(IIR));
  150. seq_printf(m, "Interrupt mask: %08x\n",
  151. I915_READ(IMR));
  152. seq_printf(m, "Pipe A stat: %08x\n",
  153. I915_READ(PIPEASTAT));
  154. seq_printf(m, "Pipe B stat: %08x\n",
  155. I915_READ(PIPEBSTAT));
  156. } else {
  157. seq_printf(m, "North Display Interrupt enable: %08x\n",
  158. I915_READ(DEIER));
  159. seq_printf(m, "North Display Interrupt identity: %08x\n",
  160. I915_READ(DEIIR));
  161. seq_printf(m, "North Display Interrupt mask: %08x\n",
  162. I915_READ(DEIMR));
  163. seq_printf(m, "South Display Interrupt enable: %08x\n",
  164. I915_READ(SDEIER));
  165. seq_printf(m, "South Display Interrupt identity: %08x\n",
  166. I915_READ(SDEIIR));
  167. seq_printf(m, "South Display Interrupt mask: %08x\n",
  168. I915_READ(SDEIMR));
  169. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  170. I915_READ(GTIER));
  171. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  172. I915_READ(GTIIR));
  173. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  174. I915_READ(GTIMR));
  175. }
  176. seq_printf(m, "Interrupts received: %d\n",
  177. atomic_read(&dev_priv->irq_received));
  178. if (dev_priv->hw_status_page != NULL) {
  179. seq_printf(m, "Current sequence: %d\n",
  180. i915_get_gem_seqno(dev));
  181. } else {
  182. seq_printf(m, "Current sequence: hws uninitialized\n");
  183. }
  184. seq_printf(m, "Waiter sequence: %d\n",
  185. dev_priv->mm.waiting_gem_seqno);
  186. seq_printf(m, "IRQ sequence: %d\n",
  187. dev_priv->mm.irq_gem_seqno);
  188. return 0;
  189. }
  190. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  191. {
  192. struct drm_info_node *node = (struct drm_info_node *) m->private;
  193. struct drm_device *dev = node->minor->dev;
  194. drm_i915_private_t *dev_priv = dev->dev_private;
  195. int i;
  196. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  197. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  198. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  199. struct drm_gem_object *obj = dev_priv->fence_regs[i].obj;
  200. if (obj == NULL) {
  201. seq_printf(m, "Fenced object[%2d] = unused\n", i);
  202. } else {
  203. struct drm_i915_gem_object *obj_priv;
  204. obj_priv = to_intel_bo(obj);
  205. seq_printf(m, "Fenced object[%2d] = %p: %s "
  206. "%08x %08zx %08x %s %08x %08x %d",
  207. i, obj, get_pin_flag(obj_priv),
  208. obj_priv->gtt_offset,
  209. obj->size, obj_priv->stride,
  210. get_tiling_flag(obj_priv),
  211. obj->read_domains, obj->write_domain,
  212. obj_priv->last_rendering_seqno);
  213. if (obj->name)
  214. seq_printf(m, " (name: %d)", obj->name);
  215. seq_printf(m, "\n");
  216. }
  217. }
  218. return 0;
  219. }
  220. static int i915_hws_info(struct seq_file *m, void *data)
  221. {
  222. struct drm_info_node *node = (struct drm_info_node *) m->private;
  223. struct drm_device *dev = node->minor->dev;
  224. drm_i915_private_t *dev_priv = dev->dev_private;
  225. int i;
  226. volatile u32 *hws;
  227. hws = (volatile u32 *)dev_priv->hw_status_page;
  228. if (hws == NULL)
  229. return 0;
  230. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  231. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  232. i * 4,
  233. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  234. }
  235. return 0;
  236. }
  237. static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count)
  238. {
  239. int page, i;
  240. uint32_t *mem;
  241. for (page = 0; page < page_count; page++) {
  242. mem = kmap_atomic(pages[page], KM_USER0);
  243. for (i = 0; i < PAGE_SIZE; i += 4)
  244. seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
  245. kunmap_atomic(mem, KM_USER0);
  246. }
  247. }
  248. static int i915_batchbuffer_info(struct seq_file *m, void *data)
  249. {
  250. struct drm_info_node *node = (struct drm_info_node *) m->private;
  251. struct drm_device *dev = node->minor->dev;
  252. drm_i915_private_t *dev_priv = dev->dev_private;
  253. struct drm_gem_object *obj;
  254. struct drm_i915_gem_object *obj_priv;
  255. int ret;
  256. spin_lock(&dev_priv->mm.active_list_lock);
  257. list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
  258. obj = obj_priv->obj;
  259. if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
  260. ret = i915_gem_object_get_pages(obj, 0);
  261. if (ret) {
  262. DRM_ERROR("Failed to get pages: %d\n", ret);
  263. spin_unlock(&dev_priv->mm.active_list_lock);
  264. return ret;
  265. }
  266. seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset);
  267. i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE);
  268. i915_gem_object_put_pages(obj);
  269. }
  270. }
  271. spin_unlock(&dev_priv->mm.active_list_lock);
  272. return 0;
  273. }
  274. static int i915_ringbuffer_data(struct seq_file *m, void *data)
  275. {
  276. struct drm_info_node *node = (struct drm_info_node *) m->private;
  277. struct drm_device *dev = node->minor->dev;
  278. drm_i915_private_t *dev_priv = dev->dev_private;
  279. u8 *virt;
  280. uint32_t *ptr, off;
  281. if (!dev_priv->ring.ring_obj) {
  282. seq_printf(m, "No ringbuffer setup\n");
  283. return 0;
  284. }
  285. virt = dev_priv->ring.virtual_start;
  286. for (off = 0; off < dev_priv->ring.Size; off += 4) {
  287. ptr = (uint32_t *)(virt + off);
  288. seq_printf(m, "%08x : %08x\n", off, *ptr);
  289. }
  290. return 0;
  291. }
  292. static int i915_ringbuffer_info(struct seq_file *m, void *data)
  293. {
  294. struct drm_info_node *node = (struct drm_info_node *) m->private;
  295. struct drm_device *dev = node->minor->dev;
  296. drm_i915_private_t *dev_priv = dev->dev_private;
  297. unsigned int head, tail;
  298. head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  299. tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  300. seq_printf(m, "RingHead : %08x\n", head);
  301. seq_printf(m, "RingTail : %08x\n", tail);
  302. seq_printf(m, "RingSize : %08lx\n", dev_priv->ring.Size);
  303. seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));
  304. return 0;
  305. }
  306. static const char *pin_flag(int pinned)
  307. {
  308. if (pinned > 0)
  309. return " P";
  310. else if (pinned < 0)
  311. return " p";
  312. else
  313. return "";
  314. }
  315. static const char *tiling_flag(int tiling)
  316. {
  317. switch (tiling) {
  318. default:
  319. case I915_TILING_NONE: return "";
  320. case I915_TILING_X: return " X";
  321. case I915_TILING_Y: return " Y";
  322. }
  323. }
  324. static const char *dirty_flag(int dirty)
  325. {
  326. return dirty ? " dirty" : "";
  327. }
  328. static const char *purgeable_flag(int purgeable)
  329. {
  330. return purgeable ? " purgeable" : "";
  331. }
  332. static int i915_error_state(struct seq_file *m, void *unused)
  333. {
  334. struct drm_info_node *node = (struct drm_info_node *) m->private;
  335. struct drm_device *dev = node->minor->dev;
  336. drm_i915_private_t *dev_priv = dev->dev_private;
  337. struct drm_i915_error_state *error;
  338. unsigned long flags;
  339. int i, page, offset, elt;
  340. spin_lock_irqsave(&dev_priv->error_lock, flags);
  341. if (!dev_priv->first_error) {
  342. seq_printf(m, "no error state collected\n");
  343. goto out;
  344. }
  345. error = dev_priv->first_error;
  346. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  347. error->time.tv_usec);
  348. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  349. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  350. seq_printf(m, " PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  351. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
  352. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
  353. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
  354. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
  355. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
  356. if (IS_I965G(dev)) {
  357. seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
  358. seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
  359. }
  360. seq_printf(m, "seqno: 0x%08x\n", error->seqno);
  361. if (error->active_bo_count) {
  362. seq_printf(m, "Buffers [%d]:\n", error->active_bo_count);
  363. for (i = 0; i < error->active_bo_count; i++) {
  364. seq_printf(m, " %08x %8zd %08x %08x %08x%s%s%s%s",
  365. error->active_bo[i].gtt_offset,
  366. error->active_bo[i].size,
  367. error->active_bo[i].read_domains,
  368. error->active_bo[i].write_domain,
  369. error->active_bo[i].seqno,
  370. pin_flag(error->active_bo[i].pinned),
  371. tiling_flag(error->active_bo[i].tiling),
  372. dirty_flag(error->active_bo[i].dirty),
  373. purgeable_flag(error->active_bo[i].purgeable));
  374. if (error->active_bo[i].name)
  375. seq_printf(m, " (name: %d)", error->active_bo[i].name);
  376. if (error->active_bo[i].fence_reg != I915_FENCE_REG_NONE)
  377. seq_printf(m, " (fence: %d)", error->active_bo[i].fence_reg);
  378. seq_printf(m, "\n");
  379. }
  380. }
  381. for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
  382. if (error->batchbuffer[i]) {
  383. struct drm_i915_error_object *obj = error->batchbuffer[i];
  384. seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
  385. offset = 0;
  386. for (page = 0; page < obj->page_count; page++) {
  387. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  388. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  389. offset += 4;
  390. }
  391. }
  392. }
  393. }
  394. if (error->ringbuffer) {
  395. struct drm_i915_error_object *obj = error->ringbuffer;
  396. seq_printf(m, "--- ringbuffer = 0x%08x\n", obj->gtt_offset);
  397. offset = 0;
  398. for (page = 0; page < obj->page_count; page++) {
  399. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  400. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  401. offset += 4;
  402. }
  403. }
  404. }
  405. out:
  406. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  407. return 0;
  408. }
  409. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  410. {
  411. struct drm_info_node *node = (struct drm_info_node *) m->private;
  412. struct drm_device *dev = node->minor->dev;
  413. drm_i915_private_t *dev_priv = dev->dev_private;
  414. u16 crstanddelay = I915_READ16(CRSTANDVID);
  415. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  416. return 0;
  417. }
  418. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  419. {
  420. struct drm_info_node *node = (struct drm_info_node *) m->private;
  421. struct drm_device *dev = node->minor->dev;
  422. drm_i915_private_t *dev_priv = dev->dev_private;
  423. u16 rgvswctl = I915_READ16(MEMSWCTL);
  424. seq_printf(m, "Last command: 0x%01x\n", (rgvswctl >> 13) & 0x3);
  425. seq_printf(m, "Command status: %d\n", (rgvswctl >> 12) & 1);
  426. seq_printf(m, "P%d DELAY 0x%02x\n", (rgvswctl >> 8) & 0xf,
  427. rgvswctl & 0x3f);
  428. return 0;
  429. }
  430. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  431. {
  432. struct drm_info_node *node = (struct drm_info_node *) m->private;
  433. struct drm_device *dev = node->minor->dev;
  434. drm_i915_private_t *dev_priv = dev->dev_private;
  435. u32 delayfreq;
  436. int i;
  437. for (i = 0; i < 16; i++) {
  438. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  439. seq_printf(m, "P%02dVIDFREQ: 0x%08x\n", i, delayfreq);
  440. }
  441. return 0;
  442. }
  443. static inline int MAP_TO_MV(int map)
  444. {
  445. return 1250 - (map * 25);
  446. }
  447. static int i915_inttoext_table(struct seq_file *m, void *unused)
  448. {
  449. struct drm_info_node *node = (struct drm_info_node *) m->private;
  450. struct drm_device *dev = node->minor->dev;
  451. drm_i915_private_t *dev_priv = dev->dev_private;
  452. u32 inttoext;
  453. int i;
  454. for (i = 1; i <= 32; i++) {
  455. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  456. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  457. }
  458. return 0;
  459. }
  460. static int i915_drpc_info(struct seq_file *m, void *unused)
  461. {
  462. struct drm_info_node *node = (struct drm_info_node *) m->private;
  463. struct drm_device *dev = node->minor->dev;
  464. drm_i915_private_t *dev_priv = dev->dev_private;
  465. u32 rgvmodectl = I915_READ(MEMMODECTL);
  466. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  467. "yes" : "no");
  468. seq_printf(m, "Boost freq: %d\n",
  469. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  470. MEMMODE_BOOST_FREQ_SHIFT);
  471. seq_printf(m, "HW control enabled: %s\n",
  472. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  473. seq_printf(m, "SW control enabled: %s\n",
  474. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  475. seq_printf(m, "Gated voltage change: %s\n",
  476. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  477. seq_printf(m, "Starting frequency: P%d\n",
  478. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  479. seq_printf(m, "Max frequency: P%d\n",
  480. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  481. seq_printf(m, "Min frequency: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  482. return 0;
  483. }
  484. static int i915_fbc_status(struct seq_file *m, void *unused)
  485. {
  486. struct drm_info_node *node = (struct drm_info_node *) m->private;
  487. struct drm_device *dev = node->minor->dev;
  488. struct drm_crtc *crtc;
  489. drm_i915_private_t *dev_priv = dev->dev_private;
  490. bool fbc_enabled = false;
  491. if (!dev_priv->display.fbc_enabled) {
  492. seq_printf(m, "FBC unsupported on this chipset\n");
  493. return 0;
  494. }
  495. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  496. if (!crtc->enabled)
  497. continue;
  498. if (dev_priv->display.fbc_enabled(crtc))
  499. fbc_enabled = true;
  500. }
  501. if (fbc_enabled) {
  502. seq_printf(m, "FBC enabled\n");
  503. } else {
  504. seq_printf(m, "FBC disabled: ");
  505. switch (dev_priv->no_fbc_reason) {
  506. case FBC_STOLEN_TOO_SMALL:
  507. seq_printf(m, "not enough stolen memory");
  508. break;
  509. case FBC_UNSUPPORTED_MODE:
  510. seq_printf(m, "mode not supported");
  511. break;
  512. case FBC_MODE_TOO_LARGE:
  513. seq_printf(m, "mode too large");
  514. break;
  515. case FBC_BAD_PLANE:
  516. seq_printf(m, "FBC unsupported on plane");
  517. break;
  518. case FBC_NOT_TILED:
  519. seq_printf(m, "scanout buffer not tiled");
  520. break;
  521. default:
  522. seq_printf(m, "unknown reason");
  523. }
  524. seq_printf(m, "\n");
  525. }
  526. return 0;
  527. }
  528. static int i915_sr_status(struct seq_file *m, void *unused)
  529. {
  530. struct drm_info_node *node = (struct drm_info_node *) m->private;
  531. struct drm_device *dev = node->minor->dev;
  532. drm_i915_private_t *dev_priv = dev->dev_private;
  533. bool sr_enabled = false;
  534. if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev))
  535. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  536. else if (IS_I915GM(dev))
  537. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  538. else if (IS_PINEVIEW(dev))
  539. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  540. seq_printf(m, "self-refresh: %s\n", sr_enabled ? "enabled" :
  541. "disabled");
  542. return 0;
  543. }
  544. static int
  545. i915_wedged_open(struct inode *inode,
  546. struct file *filp)
  547. {
  548. filp->private_data = inode->i_private;
  549. return 0;
  550. }
  551. static ssize_t
  552. i915_wedged_read(struct file *filp,
  553. char __user *ubuf,
  554. size_t max,
  555. loff_t *ppos)
  556. {
  557. struct drm_device *dev = filp->private_data;
  558. drm_i915_private_t *dev_priv = dev->dev_private;
  559. char buf[80];
  560. int len;
  561. len = snprintf(buf, sizeof (buf),
  562. "wedged : %d\n",
  563. atomic_read(&dev_priv->mm.wedged));
  564. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  565. }
  566. static ssize_t
  567. i915_wedged_write(struct file *filp,
  568. const char __user *ubuf,
  569. size_t cnt,
  570. loff_t *ppos)
  571. {
  572. struct drm_device *dev = filp->private_data;
  573. drm_i915_private_t *dev_priv = dev->dev_private;
  574. char buf[20];
  575. int val = 1;
  576. if (cnt > 0) {
  577. if (cnt > sizeof (buf) - 1)
  578. return -EINVAL;
  579. if (copy_from_user(buf, ubuf, cnt))
  580. return -EFAULT;
  581. buf[cnt] = 0;
  582. val = simple_strtoul(buf, NULL, 0);
  583. }
  584. DRM_INFO("Manually setting wedged to %d\n", val);
  585. atomic_set(&dev_priv->mm.wedged, val);
  586. if (val) {
  587. DRM_WAKEUP(&dev_priv->irq_queue);
  588. queue_work(dev_priv->wq, &dev_priv->error_work);
  589. }
  590. return cnt;
  591. }
  592. static const struct file_operations i915_wedged_fops = {
  593. .owner = THIS_MODULE,
  594. .open = i915_wedged_open,
  595. .read = i915_wedged_read,
  596. .write = i915_wedged_write,
  597. };
  598. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  599. * allocated we need to hook into the minor for release. */
  600. static int
  601. drm_add_fake_info_node(struct drm_minor *minor,
  602. struct dentry *ent,
  603. const void *key)
  604. {
  605. struct drm_info_node *node;
  606. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  607. if (node == NULL) {
  608. debugfs_remove(ent);
  609. return -ENOMEM;
  610. }
  611. node->minor = minor;
  612. node->dent = ent;
  613. node->info_ent = (void *) key;
  614. list_add(&node->list, &minor->debugfs_nodes.list);
  615. return 0;
  616. }
  617. static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
  618. {
  619. struct drm_device *dev = minor->dev;
  620. struct dentry *ent;
  621. ent = debugfs_create_file("i915_wedged",
  622. S_IRUGO | S_IWUSR,
  623. root, dev,
  624. &i915_wedged_fops);
  625. if (IS_ERR(ent))
  626. return PTR_ERR(ent);
  627. return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
  628. }
  629. static struct drm_info_list i915_debugfs_list[] = {
  630. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  631. {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
  632. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  633. {"i915_gem_request", i915_gem_request_info, 0},
  634. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  635. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  636. {"i915_gem_interrupt", i915_interrupt_info, 0},
  637. {"i915_gem_hws", i915_hws_info, 0},
  638. {"i915_ringbuffer_data", i915_ringbuffer_data, 0},
  639. {"i915_ringbuffer_info", i915_ringbuffer_info, 0},
  640. {"i915_batchbuffers", i915_batchbuffer_info, 0},
  641. {"i915_error_state", i915_error_state, 0},
  642. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  643. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  644. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  645. {"i915_inttoext_table", i915_inttoext_table, 0},
  646. {"i915_drpc_info", i915_drpc_info, 0},
  647. {"i915_fbc_status", i915_fbc_status, 0},
  648. {"i915_sr_status", i915_sr_status, 0},
  649. };
  650. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  651. int i915_debugfs_init(struct drm_minor *minor)
  652. {
  653. int ret;
  654. ret = i915_wedged_create(minor->debugfs_root, minor);
  655. if (ret)
  656. return ret;
  657. return drm_debugfs_create_files(i915_debugfs_list,
  658. I915_DEBUGFS_ENTRIES,
  659. minor->debugfs_root, minor);
  660. }
  661. void i915_debugfs_cleanup(struct drm_minor *minor)
  662. {
  663. drm_debugfs_remove_files(i915_debugfs_list,
  664. I915_DEBUGFS_ENTRIES, minor);
  665. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  666. 1, minor);
  667. }
  668. #endif /* CONFIG_DEBUG_FS */