Kconfig 5.0 KB

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  1. #
  2. # DMA engine configuration
  3. #
  4. menuconfig DMADEVICES
  5. bool "DMA Engine support"
  6. depends on HAS_DMA
  7. help
  8. DMA engines can do asynchronous data transfers without
  9. involving the host CPU. Currently, this framework can be
  10. used to offload memory copies in the network stack and
  11. RAID operations in the MD driver. This menu only presents
  12. DMA Device drivers supported by the configured arch, it may
  13. be empty in some cases.
  14. config DMADEVICES_DEBUG
  15. bool "DMA Engine debugging"
  16. depends on DMADEVICES != n
  17. help
  18. This is an option for use by developers; most people should
  19. say N here. This enables DMA engine core and driver debugging.
  20. config DMADEVICES_VDEBUG
  21. bool "DMA Engine verbose debugging"
  22. depends on DMADEVICES_DEBUG != n
  23. help
  24. This is an option for use by developers; most people should
  25. say N here. This enables deeper (more verbose) debugging of
  26. the DMA engine core and drivers.
  27. if DMADEVICES
  28. comment "DMA Devices"
  29. config ASYNC_TX_DISABLE_CHANNEL_SWITCH
  30. bool
  31. config INTEL_IOATDMA
  32. tristate "Intel I/OAT DMA support"
  33. depends on PCI && X86
  34. select DMA_ENGINE
  35. select DCA
  36. select ASYNC_TX_DISABLE_CHANNEL_SWITCH
  37. select ASYNC_TX_DISABLE_PQ_VAL_DMA
  38. select ASYNC_TX_DISABLE_XOR_VAL_DMA
  39. help
  40. Enable support for the Intel(R) I/OAT DMA engine present
  41. in recent Intel Xeon chipsets.
  42. Say Y here if you have such a chipset.
  43. If unsure, say N.
  44. config INTEL_IOP_ADMA
  45. tristate "Intel IOP ADMA support"
  46. depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
  47. select DMA_ENGINE
  48. help
  49. Enable support for the Intel(R) IOP Series RAID engines.
  50. config DW_DMAC
  51. tristate "Synopsys DesignWare AHB DMA support"
  52. depends on AVR32
  53. select DMA_ENGINE
  54. default y if CPU_AT32AP7000
  55. help
  56. Support the Synopsys DesignWare AHB DMA controller. This
  57. can be integrated in chips such as the Atmel AT32ap7000.
  58. config AT_HDMAC
  59. tristate "Atmel AHB DMA support"
  60. depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
  61. select DMA_ENGINE
  62. help
  63. Support the Atmel AHB DMA controller. This can be integrated in
  64. chips such as the Atmel AT91SAM9RL.
  65. config FSL_DMA
  66. tristate "Freescale Elo and Elo Plus DMA support"
  67. depends on FSL_SOC
  68. select DMA_ENGINE
  69. ---help---
  70. Enable support for the Freescale Elo and Elo Plus DMA controllers.
  71. The Elo is the DMA controller on some 82xx and 83xx parts, and the
  72. Elo Plus is the DMA controller on 85xx and 86xx parts.
  73. config MPC512X_DMA
  74. tristate "Freescale MPC512x built-in DMA engine support"
  75. depends on PPC_MPC512x
  76. select DMA_ENGINE
  77. ---help---
  78. Enable support for the Freescale MPC512x built-in DMA engine.
  79. config MV_XOR
  80. bool "Marvell XOR engine support"
  81. depends on PLAT_ORION
  82. select DMA_ENGINE
  83. ---help---
  84. Enable support for the Marvell XOR engine.
  85. config MX3_IPU
  86. bool "MX3x Image Processing Unit support"
  87. depends on ARCH_MX3
  88. select DMA_ENGINE
  89. default y
  90. help
  91. If you plan to use the Image Processing unit in the i.MX3x, say
  92. Y here. If unsure, select Y.
  93. config MX3_IPU_IRQS
  94. int "Number of dynamically mapped interrupts for IPU"
  95. depends on MX3_IPU
  96. range 2 137
  97. default 4
  98. help
  99. Out of 137 interrupt sources on i.MX31 IPU only very few are used.
  100. To avoid bloating the irq_desc[] array we allocate a sufficient
  101. number of IRQ slots and map them dynamically to specific sources.
  102. config TXX9_DMAC
  103. tristate "Toshiba TXx9 SoC DMA support"
  104. depends on MACH_TX49XX || MACH_TX39XX
  105. select DMA_ENGINE
  106. help
  107. Support the TXx9 SoC internal DMA controller. This can be
  108. integrated in chips such as the Toshiba TX4927/38/39.
  109. config SH_DMAE
  110. tristate "Renesas SuperH DMAC support"
  111. depends on SUPERH && SH_DMA
  112. depends on !SH_DMA_API
  113. select DMA_ENGINE
  114. help
  115. Enable support for the Renesas SuperH DMA controllers.
  116. config COH901318
  117. bool "ST-Ericsson COH901318 DMA support"
  118. select DMA_ENGINE
  119. depends on ARCH_U300
  120. help
  121. Enable support for ST-Ericsson COH 901 318 DMA.
  122. config AMCC_PPC440SPE_ADMA
  123. tristate "AMCC PPC440SPe ADMA support"
  124. depends on 440SPe || 440SP
  125. select DMA_ENGINE
  126. select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
  127. help
  128. Enable support for the AMCC PPC440SPe RAID engines.
  129. config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
  130. bool
  131. config DMA_ENGINE
  132. bool
  133. comment "DMA Clients"
  134. depends on DMA_ENGINE
  135. config NET_DMA
  136. bool "Network: TCP receive copy offload"
  137. depends on DMA_ENGINE && NET
  138. default (INTEL_IOATDMA || FSL_DMA)
  139. help
  140. This enables the use of DMA engines in the network stack to
  141. offload receive copy-to-user operations, freeing CPU cycles.
  142. Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
  143. say N.
  144. config ASYNC_TX_DMA
  145. bool "Async_tx: Offload support for the async_tx api"
  146. depends on DMA_ENGINE
  147. help
  148. This allows the async_tx api to take advantage of offload engines for
  149. memcpy, memset, xor, and raid6 p+q operations. If your platform has
  150. a dma engine that can perform raid operations and you have enabled
  151. MD_RAID456 say Y.
  152. If unsure, say N.
  153. config DMATEST
  154. tristate "DMA Test client"
  155. depends on DMA_ENGINE
  156. help
  157. Simple DMA test client. Say N unless you're debugging a
  158. DMA Device driver.
  159. endif