solos-pci.c 34 KB

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  1. /*
  2. * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
  3. * Traverse Technologies -- http://www.traverse.com.au/
  4. * Xrio Limited -- http://www.xrio.com/
  5. *
  6. *
  7. * Copyright © 2008 Traverse Technologies
  8. * Copyright © 2008 Intel Corporation
  9. *
  10. * Authors: Nathan Williams <nathan@traverse.com.au>
  11. * David Woodhouse <dwmw2@infradead.org>
  12. * Treker Chen <treker@xrio.com>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License
  16. * version 2, as published by the Free Software Foundation.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/kernel.h>
  28. #include <linux/errno.h>
  29. #include <linux/ioport.h>
  30. #include <linux/types.h>
  31. #include <linux/pci.h>
  32. #include <linux/atm.h>
  33. #include <linux/atmdev.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/sysfs.h>
  36. #include <linux/device.h>
  37. #include <linux/kobject.h>
  38. #include <linux/firmware.h>
  39. #include <linux/ctype.h>
  40. #include <linux/swab.h>
  41. #include <linux/slab.h>
  42. #define VERSION "0.07"
  43. #define PTAG "solos-pci"
  44. #define CONFIG_RAM_SIZE 128
  45. #define FLAGS_ADDR 0x7C
  46. #define IRQ_EN_ADDR 0x78
  47. #define FPGA_VER 0x74
  48. #define IRQ_CLEAR 0x70
  49. #define WRITE_FLASH 0x6C
  50. #define PORTS 0x68
  51. #define FLASH_BLOCK 0x64
  52. #define FLASH_BUSY 0x60
  53. #define FPGA_MODE 0x5C
  54. #define FLASH_MODE 0x58
  55. #define TX_DMA_ADDR(port) (0x40 + (4 * (port)))
  56. #define RX_DMA_ADDR(port) (0x30 + (4 * (port)))
  57. #define DATA_RAM_SIZE 32768
  58. #define BUF_SIZE 2048
  59. #define OLD_BUF_SIZE 4096 /* For FPGA versions <= 2*/
  60. #define FPGA_PAGE 528 /* FPGA flash page size*/
  61. #define SOLOS_PAGE 512 /* Solos flash page size*/
  62. #define FPGA_BLOCK (FPGA_PAGE * 8) /* FPGA flash block size*/
  63. #define SOLOS_BLOCK (SOLOS_PAGE * 8) /* Solos flash block size*/
  64. #define RX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2)
  65. #define TX_BUF(card, nr) ((card->buffers) + (nr)*(card->buffer_size)*2 + (card->buffer_size))
  66. #define FLASH_BUF ((card->buffers) + 4*(card->buffer_size)*2)
  67. #define RX_DMA_SIZE 2048
  68. #define FPGA_VERSION(a,b) (((a) << 8) + (b))
  69. #define LEGACY_BUFFERS 2
  70. #define DMA_SUPPORTED 4
  71. static int reset = 0;
  72. static int atmdebug = 0;
  73. static int firmware_upgrade = 0;
  74. static int fpga_upgrade = 0;
  75. static int db_firmware_upgrade = 0;
  76. static int db_fpga_upgrade = 0;
  77. struct pkt_hdr {
  78. __le16 size;
  79. __le16 vpi;
  80. __le16 vci;
  81. __le16 type;
  82. };
  83. struct solos_skb_cb {
  84. struct atm_vcc *vcc;
  85. uint32_t dma_addr;
  86. };
  87. #define SKB_CB(skb) ((struct solos_skb_cb *)skb->cb)
  88. #define PKT_DATA 0
  89. #define PKT_COMMAND 1
  90. #define PKT_POPEN 3
  91. #define PKT_PCLOSE 4
  92. #define PKT_STATUS 5
  93. struct solos_card {
  94. void __iomem *config_regs;
  95. void __iomem *buffers;
  96. int nr_ports;
  97. int tx_mask;
  98. struct pci_dev *dev;
  99. struct atm_dev *atmdev[4];
  100. struct tasklet_struct tlet;
  101. spinlock_t tx_lock;
  102. spinlock_t tx_queue_lock;
  103. spinlock_t cli_queue_lock;
  104. spinlock_t param_queue_lock;
  105. struct list_head param_queue;
  106. struct sk_buff_head tx_queue[4];
  107. struct sk_buff_head cli_queue[4];
  108. struct sk_buff *tx_skb[4];
  109. struct sk_buff *rx_skb[4];
  110. wait_queue_head_t param_wq;
  111. wait_queue_head_t fw_wq;
  112. int using_dma;
  113. int fpga_version;
  114. int buffer_size;
  115. };
  116. struct solos_param {
  117. struct list_head list;
  118. pid_t pid;
  119. int port;
  120. struct sk_buff *response;
  121. };
  122. #define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
  123. MODULE_AUTHOR("Traverse Technologies <support@traverse.com.au>");
  124. MODULE_DESCRIPTION("Solos PCI driver");
  125. MODULE_VERSION(VERSION);
  126. MODULE_LICENSE("GPL");
  127. MODULE_FIRMWARE("solos-FPGA.bin");
  128. MODULE_FIRMWARE("solos-Firmware.bin");
  129. MODULE_FIRMWARE("solos-db-FPGA.bin");
  130. MODULE_PARM_DESC(reset, "Reset Solos chips on startup");
  131. MODULE_PARM_DESC(atmdebug, "Print ATM data");
  132. MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
  133. MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
  134. MODULE_PARM_DESC(db_firmware_upgrade, "Initiate daughter board Solos firmware upgrade");
  135. MODULE_PARM_DESC(db_fpga_upgrade, "Initiate daughter board FPGA upgrade");
  136. module_param(reset, int, 0444);
  137. module_param(atmdebug, int, 0644);
  138. module_param(firmware_upgrade, int, 0444);
  139. module_param(fpga_upgrade, int, 0444);
  140. module_param(db_firmware_upgrade, int, 0444);
  141. module_param(db_fpga_upgrade, int, 0444);
  142. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  143. struct atm_vcc *vcc);
  144. static uint32_t fpga_tx(struct solos_card *);
  145. static irqreturn_t solos_irq(int irq, void *dev_id);
  146. static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);
  147. static int list_vccs(int vci);
  148. static void release_vccs(struct atm_dev *dev);
  149. static int atm_init(struct solos_card *);
  150. static void atm_remove(struct solos_card *);
  151. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);
  152. static void solos_bh(unsigned long);
  153. static int print_buffer(struct sk_buff *buf);
  154. static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)
  155. {
  156. if (vcc->pop)
  157. vcc->pop(vcc, skb);
  158. else
  159. dev_kfree_skb_any(skb);
  160. }
  161. static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,
  162. char *buf)
  163. {
  164. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  165. struct solos_card *card = atmdev->dev_data;
  166. struct solos_param prm;
  167. struct sk_buff *skb;
  168. struct pkt_hdr *header;
  169. int buflen;
  170. buflen = strlen(attr->attr.name) + 10;
  171. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  172. if (!skb) {
  173. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_show()\n");
  174. return -ENOMEM;
  175. }
  176. header = (void *)skb_put(skb, sizeof(*header));
  177. buflen = snprintf((void *)&header[1], buflen - 1,
  178. "L%05d\n%s\n", current->pid, attr->attr.name);
  179. skb_put(skb, buflen);
  180. header->size = cpu_to_le16(buflen);
  181. header->vpi = cpu_to_le16(0);
  182. header->vci = cpu_to_le16(0);
  183. header->type = cpu_to_le16(PKT_COMMAND);
  184. prm.pid = current->pid;
  185. prm.response = NULL;
  186. prm.port = SOLOS_CHAN(atmdev);
  187. spin_lock_irq(&card->param_queue_lock);
  188. list_add(&prm.list, &card->param_queue);
  189. spin_unlock_irq(&card->param_queue_lock);
  190. fpga_queue(card, prm.port, skb, NULL);
  191. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  192. spin_lock_irq(&card->param_queue_lock);
  193. list_del(&prm.list);
  194. spin_unlock_irq(&card->param_queue_lock);
  195. if (!prm.response)
  196. return -EIO;
  197. buflen = prm.response->len;
  198. memcpy(buf, prm.response->data, buflen);
  199. kfree_skb(prm.response);
  200. return buflen;
  201. }
  202. static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,
  203. const char *buf, size_t count)
  204. {
  205. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  206. struct solos_card *card = atmdev->dev_data;
  207. struct solos_param prm;
  208. struct sk_buff *skb;
  209. struct pkt_hdr *header;
  210. int buflen;
  211. ssize_t ret;
  212. buflen = strlen(attr->attr.name) + 11 + count;
  213. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  214. if (!skb) {
  215. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_store()\n");
  216. return -ENOMEM;
  217. }
  218. header = (void *)skb_put(skb, sizeof(*header));
  219. buflen = snprintf((void *)&header[1], buflen - 1,
  220. "L%05d\n%s\n%s\n", current->pid, attr->attr.name, buf);
  221. skb_put(skb, buflen);
  222. header->size = cpu_to_le16(buflen);
  223. header->vpi = cpu_to_le16(0);
  224. header->vci = cpu_to_le16(0);
  225. header->type = cpu_to_le16(PKT_COMMAND);
  226. prm.pid = current->pid;
  227. prm.response = NULL;
  228. prm.port = SOLOS_CHAN(atmdev);
  229. spin_lock_irq(&card->param_queue_lock);
  230. list_add(&prm.list, &card->param_queue);
  231. spin_unlock_irq(&card->param_queue_lock);
  232. fpga_queue(card, prm.port, skb, NULL);
  233. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  234. spin_lock_irq(&card->param_queue_lock);
  235. list_del(&prm.list);
  236. spin_unlock_irq(&card->param_queue_lock);
  237. skb = prm.response;
  238. if (!skb)
  239. return -EIO;
  240. buflen = skb->len;
  241. /* Sometimes it has a newline, sometimes it doesn't. */
  242. if (skb->data[buflen - 1] == '\n')
  243. buflen--;
  244. if (buflen == 2 && !strncmp(skb->data, "OK", 2))
  245. ret = count;
  246. else if (buflen == 5 && !strncmp(skb->data, "ERROR", 5))
  247. ret = -EIO;
  248. else {
  249. /* We know we have enough space allocated for this; we allocated
  250. it ourselves */
  251. skb->data[buflen] = 0;
  252. dev_warn(&card->dev->dev, "Unexpected parameter response: '%s'\n",
  253. skb->data);
  254. ret = -EIO;
  255. }
  256. kfree_skb(skb);
  257. return ret;
  258. }
  259. static char *next_string(struct sk_buff *skb)
  260. {
  261. int i = 0;
  262. char *this = skb->data;
  263. for (i = 0; i < skb->len; i++) {
  264. if (this[i] == '\n') {
  265. this[i] = 0;
  266. skb_pull(skb, i + 1);
  267. return this;
  268. }
  269. if (!isprint(this[i]))
  270. return NULL;
  271. }
  272. return NULL;
  273. }
  274. /*
  275. * Status packet has fields separated by \n, starting with a version number
  276. * for the information therein. Fields are....
  277. *
  278. * packet version
  279. * RxBitRate (version >= 1)
  280. * TxBitRate (version >= 1)
  281. * State (version >= 1)
  282. * LocalSNRMargin (version >= 1)
  283. * LocalLineAttn (version >= 1)
  284. */
  285. static int process_status(struct solos_card *card, int port, struct sk_buff *skb)
  286. {
  287. char *str, *end, *state_str, *snr, *attn;
  288. int ver, rate_up, rate_down;
  289. if (!card->atmdev[port])
  290. return -ENODEV;
  291. str = next_string(skb);
  292. if (!str)
  293. return -EIO;
  294. ver = simple_strtol(str, NULL, 10);
  295. if (ver < 1) {
  296. dev_warn(&card->dev->dev, "Unexpected status interrupt version %d\n",
  297. ver);
  298. return -EIO;
  299. }
  300. str = next_string(skb);
  301. if (!str)
  302. return -EIO;
  303. if (!strcmp(str, "ERROR")) {
  304. dev_dbg(&card->dev->dev, "Status packet indicated Solos error on port %d (starting up?)\n",
  305. port);
  306. return 0;
  307. }
  308. rate_down = simple_strtol(str, &end, 10);
  309. if (*end)
  310. return -EIO;
  311. str = next_string(skb);
  312. if (!str)
  313. return -EIO;
  314. rate_up = simple_strtol(str, &end, 10);
  315. if (*end)
  316. return -EIO;
  317. state_str = next_string(skb);
  318. if (!state_str)
  319. return -EIO;
  320. /* Anything but 'Showtime' is down */
  321. if (strcmp(state_str, "Showtime")) {
  322. card->atmdev[port]->signal = ATM_PHY_SIG_LOST;
  323. release_vccs(card->atmdev[port]);
  324. dev_info(&card->dev->dev, "Port %d: %s\n", port, state_str);
  325. return 0;
  326. }
  327. snr = next_string(skb);
  328. if (!snr)
  329. return -EIO;
  330. attn = next_string(skb);
  331. if (!attn)
  332. return -EIO;
  333. dev_info(&card->dev->dev, "Port %d: %s @%d/%d kb/s%s%s%s%s\n",
  334. port, state_str, rate_down/1000, rate_up/1000,
  335. snr[0]?", SNR ":"", snr, attn[0]?", Attn ":"", attn);
  336. card->atmdev[port]->link_rate = rate_down / 424;
  337. card->atmdev[port]->signal = ATM_PHY_SIG_FOUND;
  338. return 0;
  339. }
  340. static int process_command(struct solos_card *card, int port, struct sk_buff *skb)
  341. {
  342. struct solos_param *prm;
  343. unsigned long flags;
  344. int cmdpid;
  345. int found = 0;
  346. if (skb->len < 7)
  347. return 0;
  348. if (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||
  349. !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||
  350. !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||
  351. skb->data[6] != '\n')
  352. return 0;
  353. cmdpid = simple_strtol(&skb->data[1], NULL, 10);
  354. spin_lock_irqsave(&card->param_queue_lock, flags);
  355. list_for_each_entry(prm, &card->param_queue, list) {
  356. if (prm->port == port && prm->pid == cmdpid) {
  357. prm->response = skb;
  358. skb_pull(skb, 7);
  359. wake_up(&card->param_wq);
  360. found = 1;
  361. break;
  362. }
  363. }
  364. spin_unlock_irqrestore(&card->param_queue_lock, flags);
  365. return found;
  366. }
  367. static ssize_t console_show(struct device *dev, struct device_attribute *attr,
  368. char *buf)
  369. {
  370. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  371. struct solos_card *card = atmdev->dev_data;
  372. struct sk_buff *skb;
  373. spin_lock(&card->cli_queue_lock);
  374. skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
  375. spin_unlock(&card->cli_queue_lock);
  376. if(skb == NULL)
  377. return sprintf(buf, "No data.\n");
  378. memcpy(buf, skb->data, skb->len);
  379. dev_dbg(&card->dev->dev, "len: %d\n", skb->len);
  380. kfree_skb(skb);
  381. return skb->len;
  382. }
  383. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)
  384. {
  385. struct sk_buff *skb;
  386. struct pkt_hdr *header;
  387. if (size > (BUF_SIZE - sizeof(*header))) {
  388. dev_dbg(&card->dev->dev, "Command is too big. Dropping request\n");
  389. return 0;
  390. }
  391. skb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);
  392. if (!skb) {
  393. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in send_command()\n");
  394. return 0;
  395. }
  396. header = (void *)skb_put(skb, sizeof(*header));
  397. header->size = cpu_to_le16(size);
  398. header->vpi = cpu_to_le16(0);
  399. header->vci = cpu_to_le16(0);
  400. header->type = cpu_to_le16(PKT_COMMAND);
  401. memcpy(skb_put(skb, size), buf, size);
  402. fpga_queue(card, dev, skb, NULL);
  403. return 0;
  404. }
  405. static ssize_t console_store(struct device *dev, struct device_attribute *attr,
  406. const char *buf, size_t count)
  407. {
  408. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  409. struct solos_card *card = atmdev->dev_data;
  410. int err;
  411. err = send_command(card, SOLOS_CHAN(atmdev), buf, count);
  412. return err?:count;
  413. }
  414. static DEVICE_ATTR(console, 0644, console_show, console_store);
  415. #define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);
  416. #define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);
  417. #include "solos-attrlist.c"
  418. #undef SOLOS_ATTR_RO
  419. #undef SOLOS_ATTR_RW
  420. #define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,
  421. #define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,
  422. static struct attribute *solos_attrs[] = {
  423. #include "solos-attrlist.c"
  424. NULL
  425. };
  426. static struct attribute_group solos_attr_group = {
  427. .attrs = solos_attrs,
  428. .name = "parameters",
  429. };
  430. static int flash_upgrade(struct solos_card *card, int chip)
  431. {
  432. const struct firmware *fw;
  433. const char *fw_name;
  434. uint32_t data32 = 0;
  435. int blocksize = 0;
  436. int numblocks = 0;
  437. int offset;
  438. switch (chip) {
  439. case 0:
  440. fw_name = "solos-FPGA.bin";
  441. blocksize = FPGA_BLOCK;
  442. break;
  443. case 1:
  444. fw_name = "solos-Firmware.bin";
  445. blocksize = SOLOS_BLOCK;
  446. break;
  447. case 2:
  448. if (card->fpga_version > LEGACY_BUFFERS){
  449. fw_name = "solos-db-FPGA.bin";
  450. blocksize = FPGA_BLOCK;
  451. } else {
  452. dev_info(&card->dev->dev, "FPGA version doesn't support"
  453. " daughter board upgrades\n");
  454. return -EPERM;
  455. }
  456. break;
  457. case 3:
  458. if (card->fpga_version > LEGACY_BUFFERS){
  459. fw_name = "solos-Firmware.bin";
  460. blocksize = SOLOS_BLOCK;
  461. } else {
  462. dev_info(&card->dev->dev, "FPGA version doesn't support"
  463. " daughter board upgrades\n");
  464. return -EPERM;
  465. }
  466. break;
  467. default:
  468. return -ENODEV;
  469. }
  470. if (request_firmware(&fw, fw_name, &card->dev->dev))
  471. return -ENOENT;
  472. dev_info(&card->dev->dev, "Flash upgrade starting\n");
  473. numblocks = fw->size / blocksize;
  474. dev_info(&card->dev->dev, "Firmware size: %zd\n", fw->size);
  475. dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
  476. dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
  477. iowrite32(1, card->config_regs + FPGA_MODE);
  478. data32 = ioread32(card->config_regs + FPGA_MODE);
  479. /* Set mode to Chip Erase */
  480. if(chip == 0 || chip == 2)
  481. dev_info(&card->dev->dev, "Set FPGA Flash mode to FPGA Chip Erase\n");
  482. if(chip == 1 || chip == 3)
  483. dev_info(&card->dev->dev, "Set FPGA Flash mode to Solos Chip Erase\n");
  484. iowrite32((chip * 2), card->config_regs + FLASH_MODE);
  485. iowrite32(1, card->config_regs + WRITE_FLASH);
  486. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  487. for (offset = 0; offset < fw->size; offset += blocksize) {
  488. int i;
  489. /* Clear write flag */
  490. iowrite32(0, card->config_regs + WRITE_FLASH);
  491. /* Set mode to Block Write */
  492. /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */
  493. iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);
  494. /* Copy block to buffer, swapping each 16 bits */
  495. for(i = 0; i < blocksize; i += 4) {
  496. uint32_t word = swahb32p((uint32_t *)(fw->data + offset + i));
  497. if(card->fpga_version > LEGACY_BUFFERS)
  498. iowrite32(word, FLASH_BUF + i);
  499. else
  500. iowrite32(word, RX_BUF(card, 3) + i);
  501. }
  502. /* Specify block number and then trigger flash write */
  503. iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);
  504. iowrite32(1, card->config_regs + WRITE_FLASH);
  505. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  506. }
  507. release_firmware(fw);
  508. iowrite32(0, card->config_regs + WRITE_FLASH);
  509. iowrite32(0, card->config_regs + FPGA_MODE);
  510. iowrite32(0, card->config_regs + FLASH_MODE);
  511. dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
  512. return 0;
  513. }
  514. static irqreturn_t solos_irq(int irq, void *dev_id)
  515. {
  516. struct solos_card *card = dev_id;
  517. int handled = 1;
  518. iowrite32(0, card->config_regs + IRQ_CLEAR);
  519. /* If we're up and running, just kick the tasklet to process TX/RX */
  520. if (card->atmdev[0])
  521. tasklet_schedule(&card->tlet);
  522. else
  523. wake_up(&card->fw_wq);
  524. return IRQ_RETVAL(handled);
  525. }
  526. void solos_bh(unsigned long card_arg)
  527. {
  528. struct solos_card *card = (void *)card_arg;
  529. uint32_t card_flags;
  530. uint32_t rx_done = 0;
  531. int port;
  532. /*
  533. * Since fpga_tx() is going to need to read the flags under its lock,
  534. * it can return them to us so that we don't have to hit PCI MMIO
  535. * again for the same information
  536. */
  537. card_flags = fpga_tx(card);
  538. for (port = 0; port < card->nr_ports; port++) {
  539. if (card_flags & (0x10 << port)) {
  540. struct pkt_hdr _hdr, *header;
  541. struct sk_buff *skb;
  542. struct atm_vcc *vcc;
  543. int size;
  544. if (card->using_dma) {
  545. skb = card->rx_skb[port];
  546. card->rx_skb[port] = NULL;
  547. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  548. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  549. header = (void *)skb->data;
  550. size = le16_to_cpu(header->size);
  551. skb_put(skb, size + sizeof(*header));
  552. skb_pull(skb, sizeof(*header));
  553. } else {
  554. header = &_hdr;
  555. rx_done |= 0x10 << port;
  556. memcpy_fromio(header, RX_BUF(card, port), sizeof(*header));
  557. size = le16_to_cpu(header->size);
  558. if (size > (card->buffer_size - sizeof(*header))){
  559. dev_warn(&card->dev->dev, "Invalid buffer size\n");
  560. continue;
  561. }
  562. skb = alloc_skb(size + 1, GFP_ATOMIC);
  563. if (!skb) {
  564. if (net_ratelimit())
  565. dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n");
  566. continue;
  567. }
  568. memcpy_fromio(skb_put(skb, size),
  569. RX_BUF(card, port) + sizeof(*header),
  570. size);
  571. }
  572. if (atmdebug) {
  573. dev_info(&card->dev->dev, "Received: device %d\n", port);
  574. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  575. size, le16_to_cpu(header->vpi),
  576. le16_to_cpu(header->vci));
  577. print_buffer(skb);
  578. }
  579. switch (le16_to_cpu(header->type)) {
  580. case PKT_DATA:
  581. vcc = find_vcc(card->atmdev[port], le16_to_cpu(header->vpi),
  582. le16_to_cpu(header->vci));
  583. if (!vcc) {
  584. if (net_ratelimit())
  585. dev_warn(&card->dev->dev, "Received packet for unknown VCI.VPI %d.%d on port %d\n",
  586. le16_to_cpu(header->vci), le16_to_cpu(header->vpi),
  587. port);
  588. continue;
  589. }
  590. atm_charge(vcc, skb->truesize);
  591. vcc->push(vcc, skb);
  592. atomic_inc(&vcc->stats->rx);
  593. break;
  594. case PKT_STATUS:
  595. if (process_status(card, port, skb) &&
  596. net_ratelimit()) {
  597. dev_warn(&card->dev->dev, "Bad status packet of %d bytes on port %d:\n", skb->len, port);
  598. print_buffer(skb);
  599. }
  600. dev_kfree_skb_any(skb);
  601. break;
  602. case PKT_COMMAND:
  603. default: /* FIXME: Not really, surely? */
  604. if (process_command(card, port, skb))
  605. break;
  606. spin_lock(&card->cli_queue_lock);
  607. if (skb_queue_len(&card->cli_queue[port]) > 10) {
  608. if (net_ratelimit())
  609. dev_warn(&card->dev->dev, "Dropping console response on port %d\n",
  610. port);
  611. dev_kfree_skb_any(skb);
  612. } else
  613. skb_queue_tail(&card->cli_queue[port], skb);
  614. spin_unlock(&card->cli_queue_lock);
  615. break;
  616. }
  617. }
  618. /* Allocate RX skbs for any ports which need them */
  619. if (card->using_dma && card->atmdev[port] &&
  620. !card->rx_skb[port]) {
  621. struct sk_buff *skb = alloc_skb(RX_DMA_SIZE, GFP_ATOMIC);
  622. if (skb) {
  623. SKB_CB(skb)->dma_addr =
  624. pci_map_single(card->dev, skb->data,
  625. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  626. iowrite32(SKB_CB(skb)->dma_addr,
  627. card->config_regs + RX_DMA_ADDR(port));
  628. card->rx_skb[port] = skb;
  629. } else {
  630. if (net_ratelimit())
  631. dev_warn(&card->dev->dev, "Failed to allocate RX skb");
  632. /* We'll have to try again later */
  633. tasklet_schedule(&card->tlet);
  634. }
  635. }
  636. }
  637. if (rx_done)
  638. iowrite32(rx_done, card->config_regs + FLAGS_ADDR);
  639. return;
  640. }
  641. static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
  642. {
  643. struct hlist_head *head;
  644. struct atm_vcc *vcc = NULL;
  645. struct hlist_node *node;
  646. struct sock *s;
  647. read_lock(&vcc_sklist_lock);
  648. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  649. sk_for_each(s, node, head) {
  650. vcc = atm_sk(s);
  651. if (vcc->dev == dev && vcc->vci == vci &&
  652. vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE)
  653. goto out;
  654. }
  655. vcc = NULL;
  656. out:
  657. read_unlock(&vcc_sklist_lock);
  658. return vcc;
  659. }
  660. static int list_vccs(int vci)
  661. {
  662. struct hlist_head *head;
  663. struct atm_vcc *vcc;
  664. struct hlist_node *node;
  665. struct sock *s;
  666. int num_found = 0;
  667. int i;
  668. read_lock(&vcc_sklist_lock);
  669. if (vci != 0){
  670. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  671. sk_for_each(s, node, head) {
  672. num_found ++;
  673. vcc = atm_sk(s);
  674. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  675. vcc->dev->number,
  676. vcc->vpi,
  677. vcc->vci);
  678. }
  679. } else {
  680. for(i = 0; i < VCC_HTABLE_SIZE; i++){
  681. head = &vcc_hash[i];
  682. sk_for_each(s, node, head) {
  683. num_found ++;
  684. vcc = atm_sk(s);
  685. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  686. vcc->dev->number,
  687. vcc->vpi,
  688. vcc->vci);
  689. }
  690. }
  691. }
  692. read_unlock(&vcc_sklist_lock);
  693. return num_found;
  694. }
  695. static void release_vccs(struct atm_dev *dev)
  696. {
  697. int i;
  698. write_lock_irq(&vcc_sklist_lock);
  699. for (i = 0; i < VCC_HTABLE_SIZE; i++) {
  700. struct hlist_head *head = &vcc_hash[i];
  701. struct hlist_node *node, *tmp;
  702. struct sock *s;
  703. struct atm_vcc *vcc;
  704. sk_for_each_safe(s, node, tmp, head) {
  705. vcc = atm_sk(s);
  706. if (vcc->dev == dev) {
  707. vcc_release_async(vcc, -EPIPE);
  708. sk_del_node_init(s);
  709. }
  710. }
  711. }
  712. write_unlock_irq(&vcc_sklist_lock);
  713. }
  714. static int popen(struct atm_vcc *vcc)
  715. {
  716. struct solos_card *card = vcc->dev->dev_data;
  717. struct sk_buff *skb;
  718. struct pkt_hdr *header;
  719. if (vcc->qos.aal != ATM_AAL5) {
  720. dev_warn(&card->dev->dev, "Unsupported ATM type %d\n",
  721. vcc->qos.aal);
  722. return -EINVAL;
  723. }
  724. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  725. if (!skb && net_ratelimit()) {
  726. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in popen()\n");
  727. return -ENOMEM;
  728. }
  729. header = (void *)skb_put(skb, sizeof(*header));
  730. header->size = cpu_to_le16(0);
  731. header->vpi = cpu_to_le16(vcc->vpi);
  732. header->vci = cpu_to_le16(vcc->vci);
  733. header->type = cpu_to_le16(PKT_POPEN);
  734. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  735. set_bit(ATM_VF_ADDR, &vcc->flags);
  736. set_bit(ATM_VF_READY, &vcc->flags);
  737. list_vccs(0);
  738. return 0;
  739. }
  740. static void pclose(struct atm_vcc *vcc)
  741. {
  742. struct solos_card *card = vcc->dev->dev_data;
  743. struct sk_buff *skb;
  744. struct pkt_hdr *header;
  745. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  746. if (!skb) {
  747. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in pclose()\n");
  748. return;
  749. }
  750. header = (void *)skb_put(skb, sizeof(*header));
  751. header->size = cpu_to_le16(0);
  752. header->vpi = cpu_to_le16(vcc->vpi);
  753. header->vci = cpu_to_le16(vcc->vci);
  754. header->type = cpu_to_le16(PKT_PCLOSE);
  755. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  756. clear_bit(ATM_VF_ADDR, &vcc->flags);
  757. clear_bit(ATM_VF_READY, &vcc->flags);
  758. return;
  759. }
  760. static int print_buffer(struct sk_buff *buf)
  761. {
  762. int len,i;
  763. char msg[500];
  764. char item[10];
  765. len = buf->len;
  766. for (i = 0; i < len; i++){
  767. if(i % 8 == 0)
  768. sprintf(msg, "%02X: ", i);
  769. sprintf(item,"%02X ",*(buf->data + i));
  770. strcat(msg, item);
  771. if(i % 8 == 7) {
  772. sprintf(item, "\n");
  773. strcat(msg, item);
  774. printk(KERN_DEBUG "%s", msg);
  775. }
  776. }
  777. if (i % 8 != 0) {
  778. sprintf(item, "\n");
  779. strcat(msg, item);
  780. printk(KERN_DEBUG "%s", msg);
  781. }
  782. printk(KERN_DEBUG "\n");
  783. return 0;
  784. }
  785. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  786. struct atm_vcc *vcc)
  787. {
  788. int old_len;
  789. unsigned long flags;
  790. SKB_CB(skb)->vcc = vcc;
  791. spin_lock_irqsave(&card->tx_queue_lock, flags);
  792. old_len = skb_queue_len(&card->tx_queue[port]);
  793. skb_queue_tail(&card->tx_queue[port], skb);
  794. if (!old_len)
  795. card->tx_mask |= (1 << port);
  796. spin_unlock_irqrestore(&card->tx_queue_lock, flags);
  797. /* Theoretically we could just schedule the tasklet here, but
  798. that introduces latency we don't want -- it's noticeable */
  799. if (!old_len)
  800. fpga_tx(card);
  801. }
  802. static uint32_t fpga_tx(struct solos_card *card)
  803. {
  804. uint32_t tx_pending, card_flags;
  805. uint32_t tx_started = 0;
  806. struct sk_buff *skb;
  807. struct atm_vcc *vcc;
  808. unsigned char port;
  809. unsigned long flags;
  810. spin_lock_irqsave(&card->tx_lock, flags);
  811. card_flags = ioread32(card->config_regs + FLAGS_ADDR);
  812. /*
  813. * The queue lock is required for _writing_ to tx_mask, but we're
  814. * OK to read it here without locking. The only potential update
  815. * that we could race with is in fpga_queue() where it sets a bit
  816. * for a new port... but it's going to call this function again if
  817. * it's doing that, anyway.
  818. */
  819. tx_pending = card->tx_mask & ~card_flags;
  820. for (port = 0; tx_pending; tx_pending >>= 1, port++) {
  821. if (tx_pending & 1) {
  822. struct sk_buff *oldskb = card->tx_skb[port];
  823. if (oldskb)
  824. pci_unmap_single(card->dev, SKB_CB(oldskb)->dma_addr,
  825. oldskb->len, PCI_DMA_TODEVICE);
  826. spin_lock(&card->tx_queue_lock);
  827. skb = skb_dequeue(&card->tx_queue[port]);
  828. if (!skb)
  829. card->tx_mask &= ~(1 << port);
  830. spin_unlock(&card->tx_queue_lock);
  831. if (skb && !card->using_dma) {
  832. memcpy_toio(TX_BUF(card, port), skb->data, skb->len);
  833. tx_started |= 1 << port;
  834. oldskb = skb; /* We're done with this skb already */
  835. } else if (skb && card->using_dma) {
  836. SKB_CB(skb)->dma_addr = pci_map_single(card->dev, skb->data,
  837. skb->len, PCI_DMA_TODEVICE);
  838. iowrite32(SKB_CB(skb)->dma_addr,
  839. card->config_regs + TX_DMA_ADDR(port));
  840. }
  841. if (!oldskb)
  842. continue;
  843. /* Clean up and free oldskb now it's gone */
  844. if (atmdebug) {
  845. dev_info(&card->dev->dev, "Transmitted: port %d\n",
  846. port);
  847. print_buffer(oldskb);
  848. }
  849. vcc = SKB_CB(oldskb)->vcc;
  850. if (vcc) {
  851. atomic_inc(&vcc->stats->tx);
  852. solos_pop(vcc, oldskb);
  853. } else
  854. dev_kfree_skb_irq(oldskb);
  855. }
  856. }
  857. /* For non-DMA TX, write the 'TX start' bit for all four ports simultaneously */
  858. if (tx_started)
  859. iowrite32(tx_started, card->config_regs + FLAGS_ADDR);
  860. spin_unlock_irqrestore(&card->tx_lock, flags);
  861. return card_flags;
  862. }
  863. static int psend(struct atm_vcc *vcc, struct sk_buff *skb)
  864. {
  865. struct solos_card *card = vcc->dev->dev_data;
  866. struct pkt_hdr *header;
  867. int pktlen;
  868. pktlen = skb->len;
  869. if (pktlen > (BUF_SIZE - sizeof(*header))) {
  870. dev_warn(&card->dev->dev, "Length of PDU is too large. Dropping PDU.\n");
  871. solos_pop(vcc, skb);
  872. return 0;
  873. }
  874. if (!skb_clone_writable(skb, sizeof(*header))) {
  875. int expand_by = 0;
  876. int ret;
  877. if (skb_headroom(skb) < sizeof(*header))
  878. expand_by = sizeof(*header) - skb_headroom(skb);
  879. ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
  880. if (ret) {
  881. dev_warn(&card->dev->dev, "pskb_expand_head failed.\n");
  882. solos_pop(vcc, skb);
  883. return ret;
  884. }
  885. }
  886. header = (void *)skb_push(skb, sizeof(*header));
  887. /* This does _not_ include the size of the header */
  888. header->size = cpu_to_le16(pktlen);
  889. header->vpi = cpu_to_le16(vcc->vpi);
  890. header->vci = cpu_to_le16(vcc->vci);
  891. header->type = cpu_to_le16(PKT_DATA);
  892. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);
  893. return 0;
  894. }
  895. static struct atmdev_ops fpga_ops = {
  896. .open = popen,
  897. .close = pclose,
  898. .ioctl = NULL,
  899. .getsockopt = NULL,
  900. .setsockopt = NULL,
  901. .send = psend,
  902. .send_oam = NULL,
  903. .phy_put = NULL,
  904. .phy_get = NULL,
  905. .change_qos = NULL,
  906. .proc_read = NULL,
  907. .owner = THIS_MODULE
  908. };
  909. static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
  910. {
  911. int err;
  912. uint16_t fpga_ver;
  913. uint8_t major_ver, minor_ver;
  914. uint32_t data32;
  915. struct solos_card *card;
  916. card = kzalloc(sizeof(*card), GFP_KERNEL);
  917. if (!card)
  918. return -ENOMEM;
  919. card->dev = dev;
  920. init_waitqueue_head(&card->fw_wq);
  921. init_waitqueue_head(&card->param_wq);
  922. err = pci_enable_device(dev);
  923. if (err) {
  924. dev_warn(&dev->dev, "Failed to enable PCI device\n");
  925. goto out;
  926. }
  927. err = pci_set_dma_mask(dev, DMA_BIT_MASK(32));
  928. if (err) {
  929. dev_warn(&dev->dev, "Failed to set 32-bit DMA mask\n");
  930. goto out;
  931. }
  932. err = pci_request_regions(dev, "solos");
  933. if (err) {
  934. dev_warn(&dev->dev, "Failed to request regions\n");
  935. goto out;
  936. }
  937. card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
  938. if (!card->config_regs) {
  939. dev_warn(&dev->dev, "Failed to ioremap config registers\n");
  940. goto out_release_regions;
  941. }
  942. card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
  943. if (!card->buffers) {
  944. dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
  945. goto out_unmap_config;
  946. }
  947. if (reset) {
  948. iowrite32(1, card->config_regs + FPGA_MODE);
  949. data32 = ioread32(card->config_regs + FPGA_MODE);
  950. iowrite32(0, card->config_regs + FPGA_MODE);
  951. data32 = ioread32(card->config_regs + FPGA_MODE);
  952. }
  953. data32 = ioread32(card->config_regs + FPGA_VER);
  954. fpga_ver = (data32 & 0x0000FFFF);
  955. major_ver = ((data32 & 0xFF000000) >> 24);
  956. minor_ver = ((data32 & 0x00FF0000) >> 16);
  957. card->fpga_version = FPGA_VERSION(major_ver,minor_ver);
  958. if (card->fpga_version > LEGACY_BUFFERS)
  959. card->buffer_size = BUF_SIZE;
  960. else
  961. card->buffer_size = OLD_BUF_SIZE;
  962. dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
  963. major_ver, minor_ver, fpga_ver);
  964. if (card->fpga_version >= DMA_SUPPORTED){
  965. card->using_dma = 1;
  966. } else {
  967. card->using_dma = 0;
  968. /* Set RX empty flag for all ports */
  969. iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
  970. }
  971. data32 = ioread32(card->config_regs + PORTS);
  972. card->nr_ports = (data32 & 0x000000FF);
  973. pci_set_drvdata(dev, card);
  974. tasklet_init(&card->tlet, solos_bh, (unsigned long)card);
  975. spin_lock_init(&card->tx_lock);
  976. spin_lock_init(&card->tx_queue_lock);
  977. spin_lock_init(&card->cli_queue_lock);
  978. spin_lock_init(&card->param_queue_lock);
  979. INIT_LIST_HEAD(&card->param_queue);
  980. err = request_irq(dev->irq, solos_irq, IRQF_SHARED,
  981. "solos-pci", card);
  982. if (err) {
  983. dev_dbg(&card->dev->dev, "Failed to request interrupt IRQ: %d\n", dev->irq);
  984. goto out_unmap_both;
  985. }
  986. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  987. if (fpga_upgrade)
  988. flash_upgrade(card, 0);
  989. if (firmware_upgrade)
  990. flash_upgrade(card, 1);
  991. if (db_fpga_upgrade)
  992. flash_upgrade(card, 2);
  993. if (db_firmware_upgrade)
  994. flash_upgrade(card, 3);
  995. err = atm_init(card);
  996. if (err)
  997. goto out_free_irq;
  998. return 0;
  999. out_free_irq:
  1000. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1001. free_irq(dev->irq, card);
  1002. tasklet_kill(&card->tlet);
  1003. out_unmap_both:
  1004. pci_set_drvdata(dev, NULL);
  1005. pci_iounmap(dev, card->config_regs);
  1006. out_unmap_config:
  1007. pci_iounmap(dev, card->buffers);
  1008. out_release_regions:
  1009. pci_release_regions(dev);
  1010. out:
  1011. kfree(card);
  1012. return err;
  1013. }
  1014. static int atm_init(struct solos_card *card)
  1015. {
  1016. int i;
  1017. for (i = 0; i < card->nr_ports; i++) {
  1018. struct sk_buff *skb;
  1019. struct pkt_hdr *header;
  1020. skb_queue_head_init(&card->tx_queue[i]);
  1021. skb_queue_head_init(&card->cli_queue[i]);
  1022. card->atmdev[i] = atm_dev_register("solos-pci", &fpga_ops, -1, NULL);
  1023. if (!card->atmdev[i]) {
  1024. dev_err(&card->dev->dev, "Could not register ATM device %d\n", i);
  1025. atm_remove(card);
  1026. return -ENODEV;
  1027. }
  1028. if (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))
  1029. dev_err(&card->dev->dev, "Could not register console for ATM device %d\n", i);
  1030. if (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))
  1031. dev_err(&card->dev->dev, "Could not register parameter group for ATM device %d\n", i);
  1032. dev_info(&card->dev->dev, "Registered ATM device %d\n", card->atmdev[i]->number);
  1033. card->atmdev[i]->ci_range.vpi_bits = 8;
  1034. card->atmdev[i]->ci_range.vci_bits = 16;
  1035. card->atmdev[i]->dev_data = card;
  1036. card->atmdev[i]->phy_data = (void *)(unsigned long)i;
  1037. card->atmdev[i]->signal = ATM_PHY_SIG_UNKNOWN;
  1038. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  1039. if (!skb) {
  1040. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in atm_init()\n");
  1041. continue;
  1042. }
  1043. header = (void *)skb_put(skb, sizeof(*header));
  1044. header->size = cpu_to_le16(0);
  1045. header->vpi = cpu_to_le16(0);
  1046. header->vci = cpu_to_le16(0);
  1047. header->type = cpu_to_le16(PKT_STATUS);
  1048. fpga_queue(card, i, skb, NULL);
  1049. }
  1050. return 0;
  1051. }
  1052. static void atm_remove(struct solos_card *card)
  1053. {
  1054. int i;
  1055. for (i = 0; i < card->nr_ports; i++) {
  1056. if (card->atmdev[i]) {
  1057. struct sk_buff *skb;
  1058. dev_info(&card->dev->dev, "Unregistering ATM device %d\n", card->atmdev[i]->number);
  1059. sysfs_remove_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group);
  1060. atm_dev_deregister(card->atmdev[i]);
  1061. skb = card->rx_skb[i];
  1062. if (skb) {
  1063. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  1064. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  1065. dev_kfree_skb(skb);
  1066. }
  1067. skb = card->tx_skb[i];
  1068. if (skb) {
  1069. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  1070. skb->len, PCI_DMA_TODEVICE);
  1071. dev_kfree_skb(skb);
  1072. }
  1073. while ((skb = skb_dequeue(&card->tx_queue[i])))
  1074. dev_kfree_skb(skb);
  1075. }
  1076. }
  1077. }
  1078. static void fpga_remove(struct pci_dev *dev)
  1079. {
  1080. struct solos_card *card = pci_get_drvdata(dev);
  1081. /* Disable IRQs */
  1082. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1083. /* Reset FPGA */
  1084. iowrite32(1, card->config_regs + FPGA_MODE);
  1085. (void)ioread32(card->config_regs + FPGA_MODE);
  1086. atm_remove(card);
  1087. free_irq(dev->irq, card);
  1088. tasklet_kill(&card->tlet);
  1089. /* Release device from reset */
  1090. iowrite32(0, card->config_regs + FPGA_MODE);
  1091. (void)ioread32(card->config_regs + FPGA_MODE);
  1092. pci_iounmap(dev, card->buffers);
  1093. pci_iounmap(dev, card->config_regs);
  1094. pci_release_regions(dev);
  1095. pci_disable_device(dev);
  1096. pci_set_drvdata(dev, NULL);
  1097. kfree(card);
  1098. }
  1099. static struct pci_device_id fpga_pci_tbl[] __devinitdata = {
  1100. { 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1101. { 0, }
  1102. };
  1103. MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);
  1104. static struct pci_driver fpga_driver = {
  1105. .name = "solos",
  1106. .id_table = fpga_pci_tbl,
  1107. .probe = fpga_probe,
  1108. .remove = fpga_remove,
  1109. };
  1110. static int __init solos_pci_init(void)
  1111. {
  1112. printk(KERN_INFO "Solos PCI Driver Version %s\n", VERSION);
  1113. return pci_register_driver(&fpga_driver);
  1114. }
  1115. static void __exit solos_pci_exit(void)
  1116. {
  1117. pci_unregister_driver(&fpga_driver);
  1118. printk(KERN_INFO "Solos PCI Driver %s Unloaded\n", VERSION);
  1119. }
  1120. module_init(solos_pci_init);
  1121. module_exit(solos_pci_exit);