dmaengine.h 2.1 KB

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  1. /*
  2. * Header for the new SH dmaengine driver
  3. *
  4. * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #ifndef ASM_DMAENGINE_H
  11. #define ASM_DMAENGINE_H
  12. #include <linux/dmaengine.h>
  13. #include <linux/list.h>
  14. #include <asm/dma-register.h>
  15. #define SH_DMAC_MAX_CHANNELS 6
  16. enum sh_dmae_slave_chan_id {
  17. SHDMA_SLAVE_SCIF0_TX,
  18. SHDMA_SLAVE_SCIF0_RX,
  19. SHDMA_SLAVE_SCIF1_TX,
  20. SHDMA_SLAVE_SCIF1_RX,
  21. SHDMA_SLAVE_SCIF2_TX,
  22. SHDMA_SLAVE_SCIF2_RX,
  23. SHDMA_SLAVE_SCIF3_TX,
  24. SHDMA_SLAVE_SCIF3_RX,
  25. SHDMA_SLAVE_SCIF4_TX,
  26. SHDMA_SLAVE_SCIF4_RX,
  27. SHDMA_SLAVE_SCIF5_TX,
  28. SHDMA_SLAVE_SCIF5_RX,
  29. SHDMA_SLAVE_SIUA_TX,
  30. SHDMA_SLAVE_SIUA_RX,
  31. SHDMA_SLAVE_SIUB_TX,
  32. SHDMA_SLAVE_SIUB_RX,
  33. SHDMA_SLAVE_NUMBER, /* Must stay last */
  34. };
  35. struct sh_dmae_slave_config {
  36. enum sh_dmae_slave_chan_id slave_id;
  37. dma_addr_t addr;
  38. u32 chcr;
  39. char mid_rid;
  40. };
  41. struct sh_dmae_channel {
  42. unsigned int offset;
  43. unsigned int dmars;
  44. unsigned int dmars_bit;
  45. };
  46. struct sh_dmae_pdata {
  47. struct sh_dmae_slave_config *slave;
  48. int slave_num;
  49. struct sh_dmae_channel *channel;
  50. int channel_num;
  51. unsigned int ts_low_shift;
  52. unsigned int ts_low_mask;
  53. unsigned int ts_high_shift;
  54. unsigned int ts_high_mask;
  55. unsigned int *ts_shift;
  56. int ts_shift_num;
  57. u16 dmaor_init;
  58. };
  59. struct device;
  60. /* Used by slave DMA clients to request DMA to/from a specific peripheral */
  61. struct sh_dmae_slave {
  62. enum sh_dmae_slave_chan_id slave_id; /* Set by the platform */
  63. struct device *dma_dev; /* Set by the platform */
  64. struct sh_dmae_slave_config *config; /* Set by the driver */
  65. };
  66. struct sh_dmae_regs {
  67. u32 sar; /* SAR / source address */
  68. u32 dar; /* DAR / destination address */
  69. u32 tcr; /* TCR / transfer count */
  70. };
  71. struct sh_desc {
  72. struct sh_dmae_regs hw;
  73. struct list_head node;
  74. struct dma_async_tx_descriptor async_tx;
  75. enum dma_data_direction direction;
  76. dma_cookie_t cookie;
  77. size_t partial;
  78. int chunks;
  79. int mark;
  80. };
  81. #endif