fsl_msi.c 8.1 KB

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  1. /*
  2. * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
  3. *
  4. * Author: Tony Li <tony.li@freescale.com>
  5. * Jason Jin <Jason.jin@freescale.com>
  6. *
  7. * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; version 2 of the
  12. * License.
  13. *
  14. */
  15. #include <linux/irq.h>
  16. #include <linux/bootmem.h>
  17. #include <linux/msi.h>
  18. #include <linux/pci.h>
  19. #include <linux/slab.h>
  20. #include <linux/of_platform.h>
  21. #include <sysdev/fsl_soc.h>
  22. #include <asm/prom.h>
  23. #include <asm/hw_irq.h>
  24. #include <asm/ppc-pci.h>
  25. #include "fsl_msi.h"
  26. struct fsl_msi_feature {
  27. u32 fsl_pic_ip;
  28. u32 msiir_offset;
  29. };
  30. static struct fsl_msi *fsl_msi;
  31. static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
  32. {
  33. return in_be32(base + (reg >> 2));
  34. }
  35. /*
  36. * We do not need this actually. The MSIR register has been read once
  37. * in the cascade interrupt. So, this MSI interrupt has been acked
  38. */
  39. static void fsl_msi_end_irq(unsigned int virq)
  40. {
  41. }
  42. static struct irq_chip fsl_msi_chip = {
  43. .mask = mask_msi_irq,
  44. .unmask = unmask_msi_irq,
  45. .ack = fsl_msi_end_irq,
  46. .name = "FSL-MSI",
  47. };
  48. static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
  49. irq_hw_number_t hw)
  50. {
  51. struct irq_chip *chip = &fsl_msi_chip;
  52. irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
  53. set_irq_chip_and_handler(virq, chip, handle_edge_irq);
  54. return 0;
  55. }
  56. static struct irq_host_ops fsl_msi_host_ops = {
  57. .map = fsl_msi_host_map,
  58. };
  59. static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
  60. {
  61. int rc;
  62. rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
  63. msi_data->irqhost->of_node);
  64. if (rc)
  65. return rc;
  66. rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
  67. if (rc < 0) {
  68. msi_bitmap_free(&msi_data->bitmap);
  69. return rc;
  70. }
  71. return 0;
  72. }
  73. static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
  74. {
  75. if (type == PCI_CAP_ID_MSIX)
  76. pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
  77. return 0;
  78. }
  79. static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
  80. {
  81. struct msi_desc *entry;
  82. struct fsl_msi *msi_data = fsl_msi;
  83. list_for_each_entry(entry, &pdev->msi_list, list) {
  84. if (entry->irq == NO_IRQ)
  85. continue;
  86. set_irq_msi(entry->irq, NULL);
  87. msi_bitmap_free_hwirqs(&msi_data->bitmap,
  88. virq_to_hw(entry->irq), 1);
  89. irq_dispose_mapping(entry->irq);
  90. }
  91. return;
  92. }
  93. static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
  94. struct msi_msg *msg)
  95. {
  96. struct fsl_msi *msi_data = fsl_msi;
  97. struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  98. u32 base = 0;
  99. pci_bus_read_config_dword(hose->bus,
  100. PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
  101. msg->address_lo = msi_data->msi_addr_lo + base;
  102. msg->address_hi = msi_data->msi_addr_hi;
  103. msg->data = hwirq;
  104. pr_debug("%s: allocated srs: %d, ibs: %d\n",
  105. __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
  106. }
  107. static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
  108. {
  109. int rc, hwirq;
  110. unsigned int virq;
  111. struct msi_desc *entry;
  112. struct msi_msg msg;
  113. struct fsl_msi *msi_data = fsl_msi;
  114. list_for_each_entry(entry, &pdev->msi_list, list) {
  115. hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
  116. if (hwirq < 0) {
  117. rc = hwirq;
  118. pr_debug("%s: fail allocating msi interrupt\n",
  119. __func__);
  120. goto out_free;
  121. }
  122. virq = irq_create_mapping(msi_data->irqhost, hwirq);
  123. if (virq == NO_IRQ) {
  124. pr_debug("%s: fail mapping hwirq 0x%x\n",
  125. __func__, hwirq);
  126. msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
  127. rc = -ENOSPC;
  128. goto out_free;
  129. }
  130. set_irq_msi(virq, entry);
  131. fsl_compose_msi_msg(pdev, hwirq, &msg);
  132. write_msi_msg(virq, &msg);
  133. }
  134. return 0;
  135. out_free:
  136. return rc;
  137. }
  138. static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
  139. {
  140. unsigned int cascade_irq;
  141. struct fsl_msi *msi_data = fsl_msi;
  142. int msir_index = -1;
  143. u32 msir_value = 0;
  144. u32 intr_index;
  145. u32 have_shift = 0;
  146. raw_spin_lock(&desc->lock);
  147. if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
  148. if (desc->chip->mask_ack)
  149. desc->chip->mask_ack(irq);
  150. else {
  151. desc->chip->mask(irq);
  152. desc->chip->ack(irq);
  153. }
  154. }
  155. if (unlikely(desc->status & IRQ_INPROGRESS))
  156. goto unlock;
  157. msir_index = (int)desc->handler_data;
  158. if (msir_index >= NR_MSI_REG)
  159. cascade_irq = NO_IRQ;
  160. desc->status |= IRQ_INPROGRESS;
  161. switch (fsl_msi->feature & FSL_PIC_IP_MASK) {
  162. case FSL_PIC_IP_MPIC:
  163. msir_value = fsl_msi_read(msi_data->msi_regs,
  164. msir_index * 0x10);
  165. break;
  166. case FSL_PIC_IP_IPIC:
  167. msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
  168. break;
  169. }
  170. while (msir_value) {
  171. intr_index = ffs(msir_value) - 1;
  172. cascade_irq = irq_linear_revmap(msi_data->irqhost,
  173. msir_index * IRQS_PER_MSI_REG +
  174. intr_index + have_shift);
  175. if (cascade_irq != NO_IRQ)
  176. generic_handle_irq(cascade_irq);
  177. have_shift += intr_index + 1;
  178. msir_value = msir_value >> (intr_index + 1);
  179. }
  180. desc->status &= ~IRQ_INPROGRESS;
  181. switch (msi_data->feature & FSL_PIC_IP_MASK) {
  182. case FSL_PIC_IP_MPIC:
  183. desc->chip->eoi(irq);
  184. break;
  185. case FSL_PIC_IP_IPIC:
  186. if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
  187. desc->chip->unmask(irq);
  188. break;
  189. }
  190. unlock:
  191. raw_spin_unlock(&desc->lock);
  192. }
  193. static int __devinit fsl_of_msi_probe(struct of_device *dev,
  194. const struct of_device_id *match)
  195. {
  196. struct fsl_msi *msi;
  197. struct resource res;
  198. int err, i, count;
  199. int rc;
  200. int virt_msir;
  201. const u32 *p;
  202. struct fsl_msi_feature *features = match->data;
  203. printk(KERN_DEBUG "Setting up Freescale MSI support\n");
  204. msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
  205. if (!msi) {
  206. dev_err(&dev->dev, "No memory for MSI structure\n");
  207. err = -ENOMEM;
  208. goto error_out;
  209. }
  210. msi->irqhost = irq_alloc_host(dev->node, IRQ_HOST_MAP_LINEAR,
  211. NR_MSI_IRQS, &fsl_msi_host_ops, 0);
  212. if (msi->irqhost == NULL) {
  213. dev_err(&dev->dev, "No memory for MSI irqhost\n");
  214. err = -ENOMEM;
  215. goto error_out;
  216. }
  217. /* Get the MSI reg base */
  218. err = of_address_to_resource(dev->node, 0, &res);
  219. if (err) {
  220. dev_err(&dev->dev, "%s resource error!\n",
  221. dev->node->full_name);
  222. goto error_out;
  223. }
  224. msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
  225. if (!msi->msi_regs) {
  226. dev_err(&dev->dev, "ioremap problem failed\n");
  227. goto error_out;
  228. }
  229. msi->feature = features->fsl_pic_ip;
  230. msi->irqhost->host_data = msi;
  231. msi->msi_addr_hi = 0x0;
  232. msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);
  233. rc = fsl_msi_init_allocator(msi);
  234. if (rc) {
  235. dev_err(&dev->dev, "Error allocating MSI bitmap\n");
  236. goto error_out;
  237. }
  238. p = of_get_property(dev->node, "interrupts", &count);
  239. if (!p) {
  240. dev_err(&dev->dev, "no interrupts property found on %s\n",
  241. dev->node->full_name);
  242. err = -ENODEV;
  243. goto error_out;
  244. }
  245. if (count % 8 != 0) {
  246. dev_err(&dev->dev, "Malformed interrupts property on %s\n",
  247. dev->node->full_name);
  248. err = -EINVAL;
  249. goto error_out;
  250. }
  251. count /= sizeof(u32);
  252. for (i = 0; i < count / 2; i++) {
  253. if (i > NR_MSI_REG)
  254. break;
  255. virt_msir = irq_of_parse_and_map(dev->node, i);
  256. if (virt_msir != NO_IRQ) {
  257. set_irq_data(virt_msir, (void *)i);
  258. set_irq_chained_handler(virt_msir, fsl_msi_cascade);
  259. }
  260. }
  261. fsl_msi = msi;
  262. WARN_ON(ppc_md.setup_msi_irqs);
  263. ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
  264. ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
  265. ppc_md.msi_check_device = fsl_msi_check_device;
  266. return 0;
  267. error_out:
  268. kfree(msi);
  269. return err;
  270. }
  271. static const struct fsl_msi_feature mpic_msi_feature = {
  272. .fsl_pic_ip = FSL_PIC_IP_MPIC,
  273. .msiir_offset = 0x140,
  274. };
  275. static const struct fsl_msi_feature ipic_msi_feature = {
  276. .fsl_pic_ip = FSL_PIC_IP_IPIC,
  277. .msiir_offset = 0x38,
  278. };
  279. static const struct of_device_id fsl_of_msi_ids[] = {
  280. {
  281. .compatible = "fsl,mpic-msi",
  282. .data = (void *)&mpic_msi_feature,
  283. },
  284. {
  285. .compatible = "fsl,ipic-msi",
  286. .data = (void *)&ipic_msi_feature,
  287. },
  288. {}
  289. };
  290. static struct of_platform_driver fsl_of_msi_driver = {
  291. .name = "fsl-msi",
  292. .match_table = fsl_of_msi_ids,
  293. .probe = fsl_of_msi_probe,
  294. };
  295. static __init int fsl_of_msi_init(void)
  296. {
  297. return of_register_platform_driver(&fsl_of_msi_driver);
  298. }
  299. subsys_initcall(fsl_of_msi_init);