cs5536_ehci.c 4.0 KB

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  1. /*
  2. * the EHCI Virtual Support Module of AMD CS5536
  3. *
  4. * Copyright (C) 2007 Lemote, Inc.
  5. * Author : jlliu, liujl@lemote.com
  6. *
  7. * Copyright (C) 2009 Lemote, Inc.
  8. * Author: Wu Zhangjin, wuzhangjin@gmail.com
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. */
  15. #include <cs5536/cs5536.h>
  16. #include <cs5536/cs5536_pci.h>
  17. void pci_ehci_write_reg(int reg, u32 value)
  18. {
  19. u32 hi = 0, lo = value;
  20. switch (reg) {
  21. case PCI_COMMAND:
  22. _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
  23. if (value & PCI_COMMAND_MASTER)
  24. hi |= PCI_COMMAND_MASTER;
  25. else
  26. hi &= ~PCI_COMMAND_MASTER;
  27. if (value & PCI_COMMAND_MEMORY)
  28. hi |= PCI_COMMAND_MEMORY;
  29. else
  30. hi &= ~PCI_COMMAND_MEMORY;
  31. _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
  32. break;
  33. case PCI_STATUS:
  34. if (value & PCI_STATUS_PARITY) {
  35. _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
  36. if (lo & SB_PARE_ERR_FLAG) {
  37. lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
  38. _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
  39. }
  40. }
  41. break;
  42. case PCI_BAR0_REG:
  43. if (value == PCI_BAR_RANGE_MASK) {
  44. _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
  45. lo |= SOFT_BAR_EHCI_FLAG;
  46. _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
  47. } else if ((value & 0x01) == 0x00) {
  48. _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
  49. value &= 0xfffffff0;
  50. hi = 0x40000000 | ((value & 0xff000000) >> 24);
  51. lo = 0x000fffff | ((value & 0x00fff000) << 8);
  52. _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo);
  53. }
  54. break;
  55. case PCI_EHCI_LEGSMIEN_REG:
  56. _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
  57. hi &= 0x003f0000;
  58. hi |= (value & 0x3f) << 16;
  59. _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
  60. break;
  61. case PCI_EHCI_FLADJ_REG:
  62. _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
  63. hi &= ~0x00003f00;
  64. hi |= value & 0x00003f00;
  65. _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
  66. break;
  67. default:
  68. break;
  69. }
  70. }
  71. u32 pci_ehci_read_reg(int reg)
  72. {
  73. u32 conf_data = 0;
  74. u32 hi, lo;
  75. switch (reg) {
  76. case PCI_VENDOR_ID:
  77. conf_data =
  78. CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID);
  79. break;
  80. case PCI_COMMAND:
  81. _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
  82. if (hi & PCI_COMMAND_MASTER)
  83. conf_data |= PCI_COMMAND_MASTER;
  84. if (hi & PCI_COMMAND_MEMORY)
  85. conf_data |= PCI_COMMAND_MEMORY;
  86. break;
  87. case PCI_STATUS:
  88. conf_data |= PCI_STATUS_66MHZ;
  89. conf_data |= PCI_STATUS_FAST_BACK;
  90. _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
  91. if (lo & SB_PARE_ERR_FLAG)
  92. conf_data |= PCI_STATUS_PARITY;
  93. conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
  94. break;
  95. case PCI_CLASS_REVISION:
  96. _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
  97. conf_data = lo & 0x000000ff;
  98. conf_data |= (CS5536_EHCI_CLASS_CODE << 8);
  99. break;
  100. case PCI_CACHE_LINE_SIZE:
  101. conf_data =
  102. CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
  103. PCI_NORMAL_LATENCY_TIMER);
  104. break;
  105. case PCI_BAR0_REG:
  106. _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
  107. if (lo & SOFT_BAR_EHCI_FLAG) {
  108. conf_data = CS5536_EHCI_RANGE |
  109. PCI_BASE_ADDRESS_SPACE_MEMORY;
  110. lo &= ~SOFT_BAR_EHCI_FLAG;
  111. _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
  112. } else {
  113. _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
  114. conf_data = lo & 0xfffff000;
  115. }
  116. break;
  117. case PCI_CARDBUS_CIS:
  118. conf_data = PCI_CARDBUS_CIS_POINTER;
  119. break;
  120. case PCI_SUBSYSTEM_VENDOR_ID:
  121. conf_data =
  122. CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
  123. break;
  124. case PCI_ROM_ADDRESS:
  125. conf_data = PCI_EXPANSION_ROM_BAR;
  126. break;
  127. case PCI_CAPABILITY_LIST:
  128. conf_data = PCI_CAPLIST_USB_POINTER;
  129. break;
  130. case PCI_INTERRUPT_LINE:
  131. conf_data =
  132. CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
  133. break;
  134. case PCI_EHCI_LEGSMIEN_REG:
  135. _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
  136. conf_data = (hi & 0x003f0000) >> 16;
  137. break;
  138. case PCI_EHCI_LEGSMISTS_REG:
  139. _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
  140. conf_data = (hi & 0x3f000000) >> 24;
  141. break;
  142. case PCI_EHCI_FLADJ_REG:
  143. _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
  144. conf_data = hi & 0x00003f00;
  145. break;
  146. default:
  147. break;
  148. }
  149. return conf_data;
  150. }