minotaur.c 13 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2008-2009 Cambridge Signal Processing
  4. * 2005 National ICT Australia (NICTA)
  5. * Aidan Williams <aidan@nicta.com.au>
  6. *
  7. * Licensed under the GPL-2 or later.
  8. */
  9. #include <linux/device.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/mtd/mtd.h>
  12. #include <linux/mtd/partitions.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/spi/flash.h>
  15. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  16. #include <linux/usb/isp1362.h>
  17. #endif
  18. #include <linux/ata_platform.h>
  19. #include <linux/irq.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/usb/sl811.h>
  22. #include <asm/dma.h>
  23. #include <asm/bfin5xx_spi.h>
  24. #include <asm/reboot.h>
  25. #include <linux/spi/ad7877.h>
  26. /*
  27. * Name the Board for the /proc/cpuinfo
  28. */
  29. char *bfin_board_name = "CamSig Minotaur BF537";
  30. #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
  31. static struct resource bfin_pcmcia_cf_resources[] = {
  32. {
  33. .start = 0x20310000, /* IO PORT */
  34. .end = 0x20312000,
  35. .flags = IORESOURCE_MEM,
  36. }, {
  37. .start = 0x20311000, /* Attribute Memory */
  38. .end = 0x20311FFF,
  39. .flags = IORESOURCE_MEM,
  40. }, {
  41. .start = IRQ_PF4,
  42. .end = IRQ_PF4,
  43. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
  44. }, {
  45. .start = IRQ_PF6, /* Card Detect PF6 */
  46. .end = IRQ_PF6,
  47. .flags = IORESOURCE_IRQ,
  48. },
  49. };
  50. static struct platform_device bfin_pcmcia_cf_device = {
  51. .name = "bfin_cf_pcmcia",
  52. .id = -1,
  53. .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
  54. .resource = bfin_pcmcia_cf_resources,
  55. };
  56. #endif
  57. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  58. static struct platform_device rtc_device = {
  59. .name = "rtc-bfin",
  60. .id = -1,
  61. };
  62. #endif
  63. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  64. static struct platform_device bfin_mii_bus = {
  65. .name = "bfin_mii_bus",
  66. };
  67. static struct platform_device bfin_mac_device = {
  68. .name = "bfin_mac",
  69. .dev.platform_data = &bfin_mii_bus,
  70. };
  71. #endif
  72. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  73. static struct resource net2272_bfin_resources[] = {
  74. {
  75. .start = 0x20300000,
  76. .end = 0x20300000 + 0x100,
  77. .flags = IORESOURCE_MEM,
  78. }, {
  79. .start = IRQ_PF7,
  80. .end = IRQ_PF7,
  81. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  82. },
  83. };
  84. static struct platform_device net2272_bfin_device = {
  85. .name = "net2272",
  86. .id = -1,
  87. .num_resources = ARRAY_SIZE(net2272_bfin_resources),
  88. .resource = net2272_bfin_resources,
  89. };
  90. #endif
  91. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  92. /* all SPI peripherals info goes here */
  93. #if defined(CONFIG_MTD_M25P80) \
  94. || defined(CONFIG_MTD_M25P80_MODULE)
  95. /* Partition sizes */
  96. #define FLASH_SIZE 0x00400000
  97. #define PSIZE_UBOOT 0x00030000
  98. #define PSIZE_INITRAMFS 0x00240000
  99. static struct mtd_partition bfin_spi_flash_partitions[] = {
  100. {
  101. .name = "bootloader(spi)",
  102. .size = PSIZE_UBOOT,
  103. .offset = 0x000000,
  104. .mask_flags = MTD_CAP_ROM
  105. }, {
  106. .name = "initramfs(spi)",
  107. .size = PSIZE_INITRAMFS,
  108. .offset = PSIZE_UBOOT
  109. }, {
  110. .name = "opt(spi)",
  111. .size = FLASH_SIZE - (PSIZE_UBOOT + PSIZE_INITRAMFS),
  112. .offset = PSIZE_UBOOT + PSIZE_INITRAMFS,
  113. }
  114. };
  115. static struct flash_platform_data bfin_spi_flash_data = {
  116. .name = "m25p80",
  117. .parts = bfin_spi_flash_partitions,
  118. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  119. .type = "m25p64",
  120. };
  121. /* SPI flash chip (m25p64) */
  122. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  123. .enable_dma = 0, /* use dma transfer with this chip*/
  124. .bits_per_word = 8,
  125. };
  126. #endif
  127. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  128. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  129. .enable_dma = 0,
  130. .bits_per_word = 8,
  131. };
  132. #endif
  133. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  134. #if defined(CONFIG_MTD_M25P80) \
  135. || defined(CONFIG_MTD_M25P80_MODULE)
  136. {
  137. /* the modalias must be the same as spi device driver name */
  138. .modalias = "m25p80", /* Name of spi_driver for this device */
  139. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  140. .bus_num = 0, /* Framework bus number */
  141. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  142. .platform_data = &bfin_spi_flash_data,
  143. .controller_data = &spi_flash_chip_info,
  144. .mode = SPI_MODE_3,
  145. },
  146. #endif
  147. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  148. {
  149. .modalias = "mmc_spi",
  150. .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
  151. .bus_num = 0,
  152. .chip_select = 5,
  153. .controller_data = &mmc_spi_chip_info,
  154. .mode = SPI_MODE_3,
  155. },
  156. #endif
  157. };
  158. /* SPI controller data */
  159. static struct bfin5xx_spi_master bfin_spi0_info = {
  160. .num_chipselect = 8,
  161. .enable_dma = 1, /* master has the ability to do dma transfer */
  162. };
  163. /* SPI (0) */
  164. static struct resource bfin_spi0_resource[] = {
  165. [0] = {
  166. .start = SPI0_REGBASE,
  167. .end = SPI0_REGBASE + 0xFF,
  168. .flags = IORESOURCE_MEM,
  169. },
  170. [1] = {
  171. .start = CH_SPI,
  172. .end = CH_SPI,
  173. .flags = IORESOURCE_DMA,
  174. },
  175. [2] = {
  176. .start = IRQ_SPI,
  177. .end = IRQ_SPI,
  178. .flags = IORESOURCE_IRQ,
  179. },
  180. };
  181. static struct platform_device bfin_spi0_device = {
  182. .name = "bfin-spi",
  183. .id = 0, /* Bus number */
  184. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  185. .resource = bfin_spi0_resource,
  186. .dev = {
  187. .platform_data = &bfin_spi0_info, /* Passed to driver */
  188. },
  189. };
  190. #endif /* spi master and devices */
  191. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  192. #ifdef CONFIG_SERIAL_BFIN_UART0
  193. static struct resource bfin_uart0_resources[] = {
  194. {
  195. .start = UART0_THR,
  196. .end = UART0_GCTL+2,
  197. .flags = IORESOURCE_MEM,
  198. },
  199. {
  200. .start = IRQ_UART0_RX,
  201. .end = IRQ_UART0_RX+1,
  202. .flags = IORESOURCE_IRQ,
  203. },
  204. {
  205. .start = IRQ_UART0_ERROR,
  206. .end = IRQ_UART0_ERROR,
  207. .flags = IORESOURCE_IRQ,
  208. },
  209. {
  210. .start = CH_UART0_TX,
  211. .end = CH_UART0_TX,
  212. .flags = IORESOURCE_DMA,
  213. },
  214. {
  215. .start = CH_UART0_RX,
  216. .end = CH_UART0_RX,
  217. .flags = IORESOURCE_DMA,
  218. },
  219. };
  220. unsigned short bfin_uart0_peripherals[] = {
  221. P_UART0_TX, P_UART0_RX, 0
  222. };
  223. static struct platform_device bfin_uart0_device = {
  224. .name = "bfin-uart",
  225. .id = 0,
  226. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  227. .resource = bfin_uart0_resources,
  228. .dev = {
  229. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  230. },
  231. };
  232. #endif
  233. #ifdef CONFIG_SERIAL_BFIN_UART1
  234. static struct resource bfin_uart1_resources[] = {
  235. {
  236. .start = UART1_THR,
  237. .end = UART1_GCTL+2,
  238. .flags = IORESOURCE_MEM,
  239. },
  240. {
  241. .start = IRQ_UART1_RX,
  242. .end = IRQ_UART1_RX+1,
  243. .flags = IORESOURCE_IRQ,
  244. },
  245. {
  246. .start = IRQ_UART1_ERROR,
  247. .end = IRQ_UART1_ERROR,
  248. .flags = IORESOURCE_IRQ,
  249. },
  250. {
  251. .start = CH_UART1_TX,
  252. .end = CH_UART1_TX,
  253. .flags = IORESOURCE_DMA,
  254. },
  255. {
  256. .start = CH_UART1_RX,
  257. .end = CH_UART1_RX,
  258. .flags = IORESOURCE_DMA,
  259. },
  260. };
  261. unsigned short bfin_uart1_peripherals[] = {
  262. P_UART1_TX, P_UART1_RX, 0
  263. };
  264. static struct platform_device bfin_uart1_device = {
  265. .name = "bfin-uart",
  266. .id = 1,
  267. .num_resources = ARRAY_SIZE(bfin_uart1_resources),
  268. .resource = bfin_uart1_resources,
  269. .dev = {
  270. .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
  271. },
  272. };
  273. #endif
  274. #endif
  275. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  276. #ifdef CONFIG_BFIN_SIR0
  277. static struct resource bfin_sir0_resources[] = {
  278. {
  279. .start = 0xFFC00400,
  280. .end = 0xFFC004FF,
  281. .flags = IORESOURCE_MEM,
  282. },
  283. {
  284. .start = IRQ_UART0_RX,
  285. .end = IRQ_UART0_RX+1,
  286. .flags = IORESOURCE_IRQ,
  287. },
  288. {
  289. .start = CH_UART0_RX,
  290. .end = CH_UART0_RX+1,
  291. .flags = IORESOURCE_DMA,
  292. },
  293. };
  294. static struct platform_device bfin_sir0_device = {
  295. .name = "bfin_sir",
  296. .id = 0,
  297. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  298. .resource = bfin_sir0_resources,
  299. };
  300. #endif
  301. #ifdef CONFIG_BFIN_SIR1
  302. static struct resource bfin_sir1_resources[] = {
  303. {
  304. .start = 0xFFC02000,
  305. .end = 0xFFC020FF,
  306. .flags = IORESOURCE_MEM,
  307. },
  308. {
  309. .start = IRQ_UART1_RX,
  310. .end = IRQ_UART1_RX+1,
  311. .flags = IORESOURCE_IRQ,
  312. },
  313. {
  314. .start = CH_UART1_RX,
  315. .end = CH_UART1_RX+1,
  316. .flags = IORESOURCE_DMA,
  317. },
  318. };
  319. static struct platform_device bfin_sir1_device = {
  320. .name = "bfin_sir",
  321. .id = 1,
  322. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  323. .resource = bfin_sir1_resources,
  324. };
  325. #endif
  326. #endif
  327. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  328. static struct resource bfin_twi0_resource[] = {
  329. [0] = {
  330. .start = TWI0_REGBASE,
  331. .end = TWI0_REGBASE + 0xFF,
  332. .flags = IORESOURCE_MEM,
  333. },
  334. [1] = {
  335. .start = IRQ_TWI,
  336. .end = IRQ_TWI,
  337. .flags = IORESOURCE_IRQ,
  338. },
  339. };
  340. static struct platform_device i2c_bfin_twi_device = {
  341. .name = "i2c-bfin-twi",
  342. .id = 0,
  343. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  344. .resource = bfin_twi0_resource,
  345. };
  346. #endif
  347. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  348. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  349. static struct resource bfin_sport0_uart_resources[] = {
  350. {
  351. .start = SPORT0_TCR1,
  352. .end = SPORT0_MRCS3+4,
  353. .flags = IORESOURCE_MEM,
  354. },
  355. {
  356. .start = IRQ_SPORT0_RX,
  357. .end = IRQ_SPORT0_RX+1,
  358. .flags = IORESOURCE_IRQ,
  359. },
  360. {
  361. .start = IRQ_SPORT0_ERROR,
  362. .end = IRQ_SPORT0_ERROR,
  363. .flags = IORESOURCE_IRQ,
  364. },
  365. };
  366. unsigned short bfin_sport0_peripherals[] = {
  367. P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
  368. P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
  369. };
  370. static struct platform_device bfin_sport0_uart_device = {
  371. .name = "bfin-sport-uart",
  372. .id = 0,
  373. .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
  374. .resource = bfin_sport0_uart_resources,
  375. .dev = {
  376. .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
  377. },
  378. };
  379. #endif
  380. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  381. static struct resource bfin_sport1_uart_resources[] = {
  382. {
  383. .start = SPORT1_TCR1,
  384. .end = SPORT1_MRCS3+4,
  385. .flags = IORESOURCE_MEM,
  386. },
  387. {
  388. .start = IRQ_SPORT1_RX,
  389. .end = IRQ_SPORT1_RX+1,
  390. .flags = IORESOURCE_IRQ,
  391. },
  392. {
  393. .start = IRQ_SPORT1_ERROR,
  394. .end = IRQ_SPORT1_ERROR,
  395. .flags = IORESOURCE_IRQ,
  396. },
  397. };
  398. unsigned short bfin_sport1_peripherals[] = {
  399. P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
  400. P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
  401. };
  402. static struct platform_device bfin_sport1_uart_device = {
  403. .name = "bfin-sport-uart",
  404. .id = 1,
  405. .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
  406. .resource = bfin_sport1_uart_resources,
  407. .dev = {
  408. .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
  409. },
  410. };
  411. #endif
  412. #endif
  413. static struct platform_device *minotaur_devices[] __initdata = {
  414. #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
  415. &bfin_pcmcia_cf_device,
  416. #endif
  417. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  418. &rtc_device,
  419. #endif
  420. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  421. &bfin_mii_bus,
  422. &bfin_mac_device,
  423. #endif
  424. #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
  425. &net2272_bfin_device,
  426. #endif
  427. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  428. &bfin_spi0_device,
  429. #endif
  430. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  431. #ifdef CONFIG_SERIAL_BFIN_UART0
  432. &bfin_uart0_device,
  433. #endif
  434. #ifdef CONFIG_SERIAL_BFIN_UART1
  435. &bfin_uart1_device,
  436. #endif
  437. #endif
  438. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  439. #ifdef CONFIG_BFIN_SIR0
  440. &bfin_sir0_device,
  441. #endif
  442. #ifdef CONFIG_BFIN_SIR1
  443. &bfin_sir1_device,
  444. #endif
  445. #endif
  446. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  447. &i2c_bfin_twi_device,
  448. #endif
  449. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  450. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  451. &bfin_sport0_uart_device,
  452. #endif
  453. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  454. &bfin_sport1_uart_device,
  455. #endif
  456. #endif
  457. };
  458. static int __init minotaur_init(void)
  459. {
  460. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  461. platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices));
  462. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  463. spi_register_board_info(bfin_spi_board_info,
  464. ARRAY_SIZE(bfin_spi_board_info));
  465. #endif
  466. return 0;
  467. }
  468. arch_initcall(minotaur_init);
  469. static struct platform_device *minotaur_early_devices[] __initdata = {
  470. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  471. #ifdef CONFIG_SERIAL_BFIN_UART0
  472. &bfin_uart0_device,
  473. #endif
  474. #ifdef CONFIG_SERIAL_BFIN_UART1
  475. &bfin_uart1_device,
  476. #endif
  477. #endif
  478. #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
  479. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  480. &bfin_sport0_uart_device,
  481. #endif
  482. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  483. &bfin_sport1_uart_device,
  484. #endif
  485. #endif
  486. };
  487. void __init native_machine_early_platform_add_devices(void)
  488. {
  489. printk(KERN_INFO "register early platform devices\n");
  490. early_platform_add_devices(minotaur_early_devices,
  491. ARRAY_SIZE(minotaur_early_devices));
  492. }
  493. void native_machine_restart(char *cmd)
  494. {
  495. /* workaround reboot hang when booting from SPI */
  496. if ((bfin_read_SYSCR() & 0x7) == 0x3)
  497. bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
  498. }