iommu.c 20 KB

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  1. /*
  2. * omap iommu: tlb and pagetable primitives
  3. *
  4. * Copyright (C) 2008-2010 Nokia Corporation
  5. *
  6. * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
  7. * Paul Mundt and Toshihiro Kobayashi
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/err.h>
  14. #include <linux/module.h>
  15. #include <linux/slab.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/ioport.h>
  18. #include <linux/clk.h>
  19. #include <linux/platform_device.h>
  20. #include <asm/cacheflush.h>
  21. #include <plat/iommu.h>
  22. #include "iopgtable.h"
  23. /* accommodate the difference between omap1 and omap2/3 */
  24. static const struct iommu_functions *arch_iommu;
  25. static struct platform_driver omap_iommu_driver;
  26. static struct kmem_cache *iopte_cachep;
  27. /**
  28. * install_iommu_arch - Install archtecure specific iommu functions
  29. * @ops: a pointer to architecture specific iommu functions
  30. *
  31. * There are several kind of iommu algorithm(tlb, pagetable) among
  32. * omap series. This interface installs such an iommu algorighm.
  33. **/
  34. int install_iommu_arch(const struct iommu_functions *ops)
  35. {
  36. if (arch_iommu)
  37. return -EBUSY;
  38. arch_iommu = ops;
  39. return 0;
  40. }
  41. EXPORT_SYMBOL_GPL(install_iommu_arch);
  42. /**
  43. * uninstall_iommu_arch - Uninstall archtecure specific iommu functions
  44. * @ops: a pointer to architecture specific iommu functions
  45. *
  46. * This interface uninstalls the iommu algorighm installed previously.
  47. **/
  48. void uninstall_iommu_arch(const struct iommu_functions *ops)
  49. {
  50. if (arch_iommu != ops)
  51. pr_err("%s: not your arch\n", __func__);
  52. arch_iommu = NULL;
  53. }
  54. EXPORT_SYMBOL_GPL(uninstall_iommu_arch);
  55. /**
  56. * iommu_save_ctx - Save registers for pm off-mode support
  57. * @obj: target iommu
  58. **/
  59. void iommu_save_ctx(struct iommu *obj)
  60. {
  61. arch_iommu->save_ctx(obj);
  62. }
  63. EXPORT_SYMBOL_GPL(iommu_save_ctx);
  64. /**
  65. * iommu_restore_ctx - Restore registers for pm off-mode support
  66. * @obj: target iommu
  67. **/
  68. void iommu_restore_ctx(struct iommu *obj)
  69. {
  70. arch_iommu->restore_ctx(obj);
  71. }
  72. EXPORT_SYMBOL_GPL(iommu_restore_ctx);
  73. /**
  74. * iommu_arch_version - Return running iommu arch version
  75. **/
  76. u32 iommu_arch_version(void)
  77. {
  78. return arch_iommu->version;
  79. }
  80. EXPORT_SYMBOL_GPL(iommu_arch_version);
  81. static int iommu_enable(struct iommu *obj)
  82. {
  83. int err;
  84. if (!obj)
  85. return -EINVAL;
  86. clk_enable(obj->clk);
  87. err = arch_iommu->enable(obj);
  88. clk_disable(obj->clk);
  89. return err;
  90. }
  91. static void iommu_disable(struct iommu *obj)
  92. {
  93. if (!obj)
  94. return;
  95. clk_enable(obj->clk);
  96. arch_iommu->disable(obj);
  97. clk_disable(obj->clk);
  98. }
  99. /*
  100. * TLB operations
  101. */
  102. void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
  103. {
  104. BUG_ON(!cr || !e);
  105. arch_iommu->cr_to_e(cr, e);
  106. }
  107. EXPORT_SYMBOL_GPL(iotlb_cr_to_e);
  108. static inline int iotlb_cr_valid(struct cr_regs *cr)
  109. {
  110. if (!cr)
  111. return -EINVAL;
  112. return arch_iommu->cr_valid(cr);
  113. }
  114. static inline struct cr_regs *iotlb_alloc_cr(struct iommu *obj,
  115. struct iotlb_entry *e)
  116. {
  117. if (!e)
  118. return NULL;
  119. return arch_iommu->alloc_cr(obj, e);
  120. }
  121. u32 iotlb_cr_to_virt(struct cr_regs *cr)
  122. {
  123. return arch_iommu->cr_to_virt(cr);
  124. }
  125. EXPORT_SYMBOL_GPL(iotlb_cr_to_virt);
  126. static u32 get_iopte_attr(struct iotlb_entry *e)
  127. {
  128. return arch_iommu->get_pte_attr(e);
  129. }
  130. static u32 iommu_report_fault(struct iommu *obj, u32 *da)
  131. {
  132. return arch_iommu->fault_isr(obj, da);
  133. }
  134. static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l)
  135. {
  136. u32 val;
  137. val = iommu_read_reg(obj, MMU_LOCK);
  138. l->base = MMU_LOCK_BASE(val);
  139. l->vict = MMU_LOCK_VICT(val);
  140. BUG_ON(l->base != 0); /* Currently no preservation is used */
  141. }
  142. static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l)
  143. {
  144. u32 val;
  145. BUG_ON(l->base != 0); /* Currently no preservation is used */
  146. val = (l->base << MMU_LOCK_BASE_SHIFT);
  147. val |= (l->vict << MMU_LOCK_VICT_SHIFT);
  148. iommu_write_reg(obj, val, MMU_LOCK);
  149. }
  150. static void iotlb_read_cr(struct iommu *obj, struct cr_regs *cr)
  151. {
  152. arch_iommu->tlb_read_cr(obj, cr);
  153. }
  154. static void iotlb_load_cr(struct iommu *obj, struct cr_regs *cr)
  155. {
  156. arch_iommu->tlb_load_cr(obj, cr);
  157. iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
  158. iommu_write_reg(obj, 1, MMU_LD_TLB);
  159. }
  160. /**
  161. * iotlb_dump_cr - Dump an iommu tlb entry into buf
  162. * @obj: target iommu
  163. * @cr: contents of cam and ram register
  164. * @buf: output buffer
  165. **/
  166. static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr,
  167. char *buf)
  168. {
  169. BUG_ON(!cr || !buf);
  170. return arch_iommu->dump_cr(obj, cr, buf);
  171. }
  172. /**
  173. * load_iotlb_entry - Set an iommu tlb entry
  174. * @obj: target iommu
  175. * @e: an iommu tlb entry info
  176. **/
  177. int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
  178. {
  179. int i;
  180. int err = 0;
  181. struct iotlb_lock l;
  182. struct cr_regs *cr;
  183. if (!obj || !obj->nr_tlb_entries || !e)
  184. return -EINVAL;
  185. clk_enable(obj->clk);
  186. for (i = 0; i < obj->nr_tlb_entries; i++) {
  187. struct cr_regs tmp;
  188. iotlb_lock_get(obj, &l);
  189. l.vict = i;
  190. iotlb_lock_set(obj, &l);
  191. iotlb_read_cr(obj, &tmp);
  192. if (!iotlb_cr_valid(&tmp))
  193. break;
  194. }
  195. if (i == obj->nr_tlb_entries) {
  196. dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
  197. err = -EBUSY;
  198. goto out;
  199. }
  200. cr = iotlb_alloc_cr(obj, e);
  201. if (IS_ERR(cr)) {
  202. clk_disable(obj->clk);
  203. return PTR_ERR(cr);
  204. }
  205. iotlb_load_cr(obj, cr);
  206. kfree(cr);
  207. /* increment victim for next tlb load */
  208. if (++l.vict == obj->nr_tlb_entries)
  209. l.vict = 0;
  210. iotlb_lock_set(obj, &l);
  211. out:
  212. clk_disable(obj->clk);
  213. return err;
  214. }
  215. EXPORT_SYMBOL_GPL(load_iotlb_entry);
  216. /**
  217. * flush_iotlb_page - Clear an iommu tlb entry
  218. * @obj: target iommu
  219. * @da: iommu device virtual address
  220. *
  221. * Clear an iommu tlb entry which includes 'da' address.
  222. **/
  223. void flush_iotlb_page(struct iommu *obj, u32 da)
  224. {
  225. struct iotlb_lock l;
  226. int i;
  227. clk_enable(obj->clk);
  228. for (i = 0; i < obj->nr_tlb_entries; i++) {
  229. struct cr_regs cr;
  230. u32 start;
  231. size_t bytes;
  232. iotlb_lock_get(obj, &l);
  233. l.vict = i;
  234. iotlb_lock_set(obj, &l);
  235. iotlb_read_cr(obj, &cr);
  236. if (!iotlb_cr_valid(&cr))
  237. continue;
  238. start = iotlb_cr_to_virt(&cr);
  239. bytes = iopgsz_to_bytes(cr.cam & 3);
  240. if ((start <= da) && (da < start + bytes)) {
  241. dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
  242. __func__, start, da, bytes);
  243. iotlb_load_cr(obj, &cr);
  244. iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
  245. }
  246. }
  247. clk_disable(obj->clk);
  248. if (i == obj->nr_tlb_entries)
  249. dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
  250. }
  251. EXPORT_SYMBOL_GPL(flush_iotlb_page);
  252. /**
  253. * flush_iotlb_range - Clear an iommu tlb entries
  254. * @obj: target iommu
  255. * @start: iommu device virtual address(start)
  256. * @end: iommu device virtual address(end)
  257. *
  258. * Clear an iommu tlb entry which includes 'da' address.
  259. **/
  260. void flush_iotlb_range(struct iommu *obj, u32 start, u32 end)
  261. {
  262. u32 da = start;
  263. while (da < end) {
  264. flush_iotlb_page(obj, da);
  265. /* FIXME: Optimize for multiple page size */
  266. da += IOPTE_SIZE;
  267. }
  268. }
  269. EXPORT_SYMBOL_GPL(flush_iotlb_range);
  270. /**
  271. * flush_iotlb_all - Clear all iommu tlb entries
  272. * @obj: target iommu
  273. **/
  274. void flush_iotlb_all(struct iommu *obj)
  275. {
  276. struct iotlb_lock l;
  277. clk_enable(obj->clk);
  278. l.base = 0;
  279. l.vict = 0;
  280. iotlb_lock_set(obj, &l);
  281. iommu_write_reg(obj, 1, MMU_GFLUSH);
  282. clk_disable(obj->clk);
  283. }
  284. EXPORT_SYMBOL_GPL(flush_iotlb_all);
  285. #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
  286. ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)
  287. {
  288. if (!obj || !buf)
  289. return -EINVAL;
  290. clk_enable(obj->clk);
  291. bytes = arch_iommu->dump_ctx(obj, buf, bytes);
  292. clk_disable(obj->clk);
  293. return bytes;
  294. }
  295. EXPORT_SYMBOL_GPL(iommu_dump_ctx);
  296. static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num)
  297. {
  298. int i;
  299. struct iotlb_lock saved, l;
  300. struct cr_regs *p = crs;
  301. clk_enable(obj->clk);
  302. iotlb_lock_get(obj, &saved);
  303. memcpy(&l, &saved, sizeof(saved));
  304. for (i = 0; i < num; i++) {
  305. struct cr_regs tmp;
  306. iotlb_lock_get(obj, &l);
  307. l.vict = i;
  308. iotlb_lock_set(obj, &l);
  309. iotlb_read_cr(obj, &tmp);
  310. if (!iotlb_cr_valid(&tmp))
  311. continue;
  312. *p++ = tmp;
  313. }
  314. iotlb_lock_set(obj, &saved);
  315. clk_disable(obj->clk);
  316. return p - crs;
  317. }
  318. /**
  319. * dump_tlb_entries - dump cr arrays to given buffer
  320. * @obj: target iommu
  321. * @buf: output buffer
  322. **/
  323. size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t bytes)
  324. {
  325. int i, num;
  326. struct cr_regs *cr;
  327. char *p = buf;
  328. num = bytes / sizeof(*cr);
  329. num = min(obj->nr_tlb_entries, num);
  330. cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
  331. if (!cr)
  332. return 0;
  333. num = __dump_tlb_entries(obj, cr, num);
  334. for (i = 0; i < num; i++)
  335. p += iotlb_dump_cr(obj, cr + i, p);
  336. kfree(cr);
  337. return p - buf;
  338. }
  339. EXPORT_SYMBOL_GPL(dump_tlb_entries);
  340. int foreach_iommu_device(void *data, int (*fn)(struct device *, void *))
  341. {
  342. return driver_for_each_device(&omap_iommu_driver.driver,
  343. NULL, data, fn);
  344. }
  345. EXPORT_SYMBOL_GPL(foreach_iommu_device);
  346. #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
  347. /*
  348. * H/W pagetable operations
  349. */
  350. static void flush_iopgd_range(u32 *first, u32 *last)
  351. {
  352. /* FIXME: L2 cache should be taken care of if it exists */
  353. do {
  354. asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
  355. : : "r" (first));
  356. first += L1_CACHE_BYTES / sizeof(*first);
  357. } while (first <= last);
  358. }
  359. static void flush_iopte_range(u32 *first, u32 *last)
  360. {
  361. /* FIXME: L2 cache should be taken care of if it exists */
  362. do {
  363. asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
  364. : : "r" (first));
  365. first += L1_CACHE_BYTES / sizeof(*first);
  366. } while (first <= last);
  367. }
  368. static void iopte_free(u32 *iopte)
  369. {
  370. /* Note: freed iopte's must be clean ready for re-use */
  371. kmem_cache_free(iopte_cachep, iopte);
  372. }
  373. static u32 *iopte_alloc(struct iommu *obj, u32 *iopgd, u32 da)
  374. {
  375. u32 *iopte;
  376. /* a table has already existed */
  377. if (*iopgd)
  378. goto pte_ready;
  379. /*
  380. * do the allocation outside the page table lock
  381. */
  382. spin_unlock(&obj->page_table_lock);
  383. iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
  384. spin_lock(&obj->page_table_lock);
  385. if (!*iopgd) {
  386. if (!iopte)
  387. return ERR_PTR(-ENOMEM);
  388. *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
  389. flush_iopgd_range(iopgd, iopgd);
  390. dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
  391. } else {
  392. /* We raced, free the reduniovant table */
  393. iopte_free(iopte);
  394. }
  395. pte_ready:
  396. iopte = iopte_offset(iopgd, da);
  397. dev_vdbg(obj->dev,
  398. "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
  399. __func__, da, iopgd, *iopgd, iopte, *iopte);
  400. return iopte;
  401. }
  402. static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot)
  403. {
  404. u32 *iopgd = iopgd_offset(obj, da);
  405. *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
  406. flush_iopgd_range(iopgd, iopgd);
  407. return 0;
  408. }
  409. static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot)
  410. {
  411. u32 *iopgd = iopgd_offset(obj, da);
  412. int i;
  413. for (i = 0; i < 16; i++)
  414. *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
  415. flush_iopgd_range(iopgd, iopgd + 15);
  416. return 0;
  417. }
  418. static int iopte_alloc_page(struct iommu *obj, u32 da, u32 pa, u32 prot)
  419. {
  420. u32 *iopgd = iopgd_offset(obj, da);
  421. u32 *iopte = iopte_alloc(obj, iopgd, da);
  422. if (IS_ERR(iopte))
  423. return PTR_ERR(iopte);
  424. *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
  425. flush_iopte_range(iopte, iopte);
  426. dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
  427. __func__, da, pa, iopte, *iopte);
  428. return 0;
  429. }
  430. static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot)
  431. {
  432. u32 *iopgd = iopgd_offset(obj, da);
  433. u32 *iopte = iopte_alloc(obj, iopgd, da);
  434. int i;
  435. if (IS_ERR(iopte))
  436. return PTR_ERR(iopte);
  437. for (i = 0; i < 16; i++)
  438. *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
  439. flush_iopte_range(iopte, iopte + 15);
  440. return 0;
  441. }
  442. static int iopgtable_store_entry_core(struct iommu *obj, struct iotlb_entry *e)
  443. {
  444. int (*fn)(struct iommu *, u32, u32, u32);
  445. u32 prot;
  446. int err;
  447. if (!obj || !e)
  448. return -EINVAL;
  449. switch (e->pgsz) {
  450. case MMU_CAM_PGSZ_16M:
  451. fn = iopgd_alloc_super;
  452. break;
  453. case MMU_CAM_PGSZ_1M:
  454. fn = iopgd_alloc_section;
  455. break;
  456. case MMU_CAM_PGSZ_64K:
  457. fn = iopte_alloc_large;
  458. break;
  459. case MMU_CAM_PGSZ_4K:
  460. fn = iopte_alloc_page;
  461. break;
  462. default:
  463. fn = NULL;
  464. BUG();
  465. break;
  466. }
  467. prot = get_iopte_attr(e);
  468. spin_lock(&obj->page_table_lock);
  469. err = fn(obj, e->da, e->pa, prot);
  470. spin_unlock(&obj->page_table_lock);
  471. return err;
  472. }
  473. /**
  474. * iopgtable_store_entry - Make an iommu pte entry
  475. * @obj: target iommu
  476. * @e: an iommu tlb entry info
  477. **/
  478. int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e)
  479. {
  480. int err;
  481. flush_iotlb_page(obj, e->da);
  482. err = iopgtable_store_entry_core(obj, e);
  483. #ifdef PREFETCH_IOTLB
  484. if (!err)
  485. load_iotlb_entry(obj, e);
  486. #endif
  487. return err;
  488. }
  489. EXPORT_SYMBOL_GPL(iopgtable_store_entry);
  490. /**
  491. * iopgtable_lookup_entry - Lookup an iommu pte entry
  492. * @obj: target iommu
  493. * @da: iommu device virtual address
  494. * @ppgd: iommu pgd entry pointer to be returned
  495. * @ppte: iommu pte entry pointer to be returned
  496. **/
  497. void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
  498. {
  499. u32 *iopgd, *iopte = NULL;
  500. iopgd = iopgd_offset(obj, da);
  501. if (!*iopgd)
  502. goto out;
  503. if (*iopgd & IOPGD_TABLE)
  504. iopte = iopte_offset(iopgd, da);
  505. out:
  506. *ppgd = iopgd;
  507. *ppte = iopte;
  508. }
  509. EXPORT_SYMBOL_GPL(iopgtable_lookup_entry);
  510. static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da)
  511. {
  512. size_t bytes;
  513. u32 *iopgd = iopgd_offset(obj, da);
  514. int nent = 1;
  515. if (!*iopgd)
  516. return 0;
  517. if (*iopgd & IOPGD_TABLE) {
  518. int i;
  519. u32 *iopte = iopte_offset(iopgd, da);
  520. bytes = IOPTE_SIZE;
  521. if (*iopte & IOPTE_LARGE) {
  522. nent *= 16;
  523. /* rewind to the 1st entry */
  524. iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
  525. }
  526. bytes *= nent;
  527. memset(iopte, 0, nent * sizeof(*iopte));
  528. flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
  529. /*
  530. * do table walk to check if this table is necessary or not
  531. */
  532. iopte = iopte_offset(iopgd, 0);
  533. for (i = 0; i < PTRS_PER_IOPTE; i++)
  534. if (iopte[i])
  535. goto out;
  536. iopte_free(iopte);
  537. nent = 1; /* for the next L1 entry */
  538. } else {
  539. bytes = IOPGD_SIZE;
  540. if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
  541. nent *= 16;
  542. /* rewind to the 1st entry */
  543. iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
  544. }
  545. bytes *= nent;
  546. }
  547. memset(iopgd, 0, nent * sizeof(*iopgd));
  548. flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
  549. out:
  550. return bytes;
  551. }
  552. /**
  553. * iopgtable_clear_entry - Remove an iommu pte entry
  554. * @obj: target iommu
  555. * @da: iommu device virtual address
  556. **/
  557. size_t iopgtable_clear_entry(struct iommu *obj, u32 da)
  558. {
  559. size_t bytes;
  560. spin_lock(&obj->page_table_lock);
  561. bytes = iopgtable_clear_entry_core(obj, da);
  562. flush_iotlb_page(obj, da);
  563. spin_unlock(&obj->page_table_lock);
  564. return bytes;
  565. }
  566. EXPORT_SYMBOL_GPL(iopgtable_clear_entry);
  567. static void iopgtable_clear_entry_all(struct iommu *obj)
  568. {
  569. int i;
  570. spin_lock(&obj->page_table_lock);
  571. for (i = 0; i < PTRS_PER_IOPGD; i++) {
  572. u32 da;
  573. u32 *iopgd;
  574. da = i << IOPGD_SHIFT;
  575. iopgd = iopgd_offset(obj, da);
  576. if (!*iopgd)
  577. continue;
  578. if (*iopgd & IOPGD_TABLE)
  579. iopte_free(iopte_offset(iopgd, 0));
  580. *iopgd = 0;
  581. flush_iopgd_range(iopgd, iopgd);
  582. }
  583. flush_iotlb_all(obj);
  584. spin_unlock(&obj->page_table_lock);
  585. }
  586. /*
  587. * Device IOMMU generic operations
  588. */
  589. static irqreturn_t iommu_fault_handler(int irq, void *data)
  590. {
  591. u32 stat, da;
  592. u32 *iopgd, *iopte;
  593. int err = -EIO;
  594. struct iommu *obj = data;
  595. if (!obj->refcount)
  596. return IRQ_NONE;
  597. /* Dynamic loading TLB or PTE */
  598. if (obj->isr)
  599. err = obj->isr(obj);
  600. if (!err)
  601. return IRQ_HANDLED;
  602. clk_enable(obj->clk);
  603. stat = iommu_report_fault(obj, &da);
  604. clk_disable(obj->clk);
  605. if (!stat)
  606. return IRQ_HANDLED;
  607. iopgd = iopgd_offset(obj, da);
  608. if (!(*iopgd & IOPGD_TABLE)) {
  609. dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__,
  610. da, iopgd, *iopgd);
  611. return IRQ_NONE;
  612. }
  613. iopte = iopte_offset(iopgd, da);
  614. dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
  615. __func__, da, iopgd, *iopgd, iopte, *iopte);
  616. return IRQ_NONE;
  617. }
  618. static int device_match_by_alias(struct device *dev, void *data)
  619. {
  620. struct iommu *obj = to_iommu(dev);
  621. const char *name = data;
  622. pr_debug("%s: %s %s\n", __func__, obj->name, name);
  623. return strcmp(obj->name, name) == 0;
  624. }
  625. /**
  626. * iommu_get - Get iommu handler
  627. * @name: target iommu name
  628. **/
  629. struct iommu *iommu_get(const char *name)
  630. {
  631. int err = -ENOMEM;
  632. struct device *dev;
  633. struct iommu *obj;
  634. dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name,
  635. device_match_by_alias);
  636. if (!dev)
  637. return ERR_PTR(-ENODEV);
  638. obj = to_iommu(dev);
  639. mutex_lock(&obj->iommu_lock);
  640. if (obj->refcount++ == 0) {
  641. err = iommu_enable(obj);
  642. if (err)
  643. goto err_enable;
  644. flush_iotlb_all(obj);
  645. }
  646. if (!try_module_get(obj->owner))
  647. goto err_module;
  648. mutex_unlock(&obj->iommu_lock);
  649. dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
  650. return obj;
  651. err_module:
  652. if (obj->refcount == 1)
  653. iommu_disable(obj);
  654. err_enable:
  655. obj->refcount--;
  656. mutex_unlock(&obj->iommu_lock);
  657. return ERR_PTR(err);
  658. }
  659. EXPORT_SYMBOL_GPL(iommu_get);
  660. /**
  661. * iommu_put - Put back iommu handler
  662. * @obj: target iommu
  663. **/
  664. void iommu_put(struct iommu *obj)
  665. {
  666. if (!obj || IS_ERR(obj))
  667. return;
  668. mutex_lock(&obj->iommu_lock);
  669. if (--obj->refcount == 0)
  670. iommu_disable(obj);
  671. module_put(obj->owner);
  672. mutex_unlock(&obj->iommu_lock);
  673. dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
  674. }
  675. EXPORT_SYMBOL_GPL(iommu_put);
  676. /*
  677. * OMAP Device MMU(IOMMU) detection
  678. */
  679. static int __devinit omap_iommu_probe(struct platform_device *pdev)
  680. {
  681. int err = -ENODEV;
  682. void *p;
  683. int irq;
  684. struct iommu *obj;
  685. struct resource *res;
  686. struct iommu_platform_data *pdata = pdev->dev.platform_data;
  687. if (pdev->num_resources != 2)
  688. return -EINVAL;
  689. obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
  690. if (!obj)
  691. return -ENOMEM;
  692. obj->clk = clk_get(&pdev->dev, pdata->clk_name);
  693. if (IS_ERR(obj->clk))
  694. goto err_clk;
  695. obj->nr_tlb_entries = pdata->nr_tlb_entries;
  696. obj->name = pdata->name;
  697. obj->dev = &pdev->dev;
  698. obj->ctx = (void *)obj + sizeof(*obj);
  699. mutex_init(&obj->iommu_lock);
  700. mutex_init(&obj->mmap_lock);
  701. spin_lock_init(&obj->page_table_lock);
  702. INIT_LIST_HEAD(&obj->mmap);
  703. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  704. if (!res) {
  705. err = -ENODEV;
  706. goto err_mem;
  707. }
  708. obj->regbase = ioremap(res->start, resource_size(res));
  709. if (!obj->regbase) {
  710. err = -ENOMEM;
  711. goto err_mem;
  712. }
  713. res = request_mem_region(res->start, resource_size(res),
  714. dev_name(&pdev->dev));
  715. if (!res) {
  716. err = -EIO;
  717. goto err_mem;
  718. }
  719. irq = platform_get_irq(pdev, 0);
  720. if (irq < 0) {
  721. err = -ENODEV;
  722. goto err_irq;
  723. }
  724. err = request_irq(irq, iommu_fault_handler, IRQF_SHARED,
  725. dev_name(&pdev->dev), obj);
  726. if (err < 0)
  727. goto err_irq;
  728. platform_set_drvdata(pdev, obj);
  729. p = (void *)__get_free_pages(GFP_KERNEL, get_order(IOPGD_TABLE_SIZE));
  730. if (!p) {
  731. err = -ENOMEM;
  732. goto err_pgd;
  733. }
  734. memset(p, 0, IOPGD_TABLE_SIZE);
  735. clean_dcache_area(p, IOPGD_TABLE_SIZE);
  736. obj->iopgd = p;
  737. BUG_ON(!IS_ALIGNED((unsigned long)obj->iopgd, IOPGD_TABLE_SIZE));
  738. dev_info(&pdev->dev, "%s registered\n", obj->name);
  739. return 0;
  740. err_pgd:
  741. free_irq(irq, obj);
  742. err_irq:
  743. release_mem_region(res->start, resource_size(res));
  744. iounmap(obj->regbase);
  745. err_mem:
  746. clk_put(obj->clk);
  747. err_clk:
  748. kfree(obj);
  749. return err;
  750. }
  751. static int __devexit omap_iommu_remove(struct platform_device *pdev)
  752. {
  753. int irq;
  754. struct resource *res;
  755. struct iommu *obj = platform_get_drvdata(pdev);
  756. platform_set_drvdata(pdev, NULL);
  757. iopgtable_clear_entry_all(obj);
  758. free_pages((unsigned long)obj->iopgd, get_order(IOPGD_TABLE_SIZE));
  759. irq = platform_get_irq(pdev, 0);
  760. free_irq(irq, obj);
  761. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  762. release_mem_region(res->start, resource_size(res));
  763. iounmap(obj->regbase);
  764. clk_put(obj->clk);
  765. dev_info(&pdev->dev, "%s removed\n", obj->name);
  766. kfree(obj);
  767. return 0;
  768. }
  769. static struct platform_driver omap_iommu_driver = {
  770. .probe = omap_iommu_probe,
  771. .remove = __devexit_p(omap_iommu_remove),
  772. .driver = {
  773. .name = "omap-iommu",
  774. },
  775. };
  776. static void iopte_cachep_ctor(void *iopte)
  777. {
  778. clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
  779. }
  780. static int __init omap_iommu_init(void)
  781. {
  782. struct kmem_cache *p;
  783. const unsigned long flags = SLAB_HWCACHE_ALIGN;
  784. size_t align = 1 << 10; /* L2 pagetable alignement */
  785. p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
  786. iopte_cachep_ctor);
  787. if (!p)
  788. return -ENOMEM;
  789. iopte_cachep = p;
  790. return platform_driver_register(&omap_iommu_driver);
  791. }
  792. module_init(omap_iommu_init);
  793. static void __exit omap_iommu_exit(void)
  794. {
  795. kmem_cache_destroy(iopte_cachep);
  796. platform_driver_unregister(&omap_iommu_driver);
  797. }
  798. module_exit(omap_iommu_exit);
  799. MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
  800. MODULE_ALIAS("platform:omap-iommu");
  801. MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
  802. MODULE_LICENSE("GPL v2");