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mach-s5pv210
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regs-clock.h

regs-clock.h 5.5 KB
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  1. /* linux/arch/arm/mach-s5pv210/include/mach/regs-clock.h
    2. 

  2.  *
    3. 

  3.  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
    4. 

  4.  *		http://www.samsung.com/
    5. 

  5.  *
    6. 

  6.  * S5PV210 - Clock register definitions
    7. 

  7.  *
    8. 

  8.  * This program is free software; you can redistribute it and/or modify
    9. 

  9.  * it under the terms of the GNU General Public License version 2 as
    10. 

  10.  * published by the Free Software Foundation.
    11. 

  11. */
    12. 

  12. 

  13. #ifndef __ASM_ARCH_REGS_CLOCK_H
    14. 

  14. #define __ASM_ARCH_REGS_CLOCK_H __FILE__
    15. 

  15. 

  16. #include <mach/map.h>
    17. 

  17. 

  18. #define S5P_CLKREG(x)		(S3C_VA_SYS + (x))
    19. 

  19. 

  20. #define S5P_APLL_LOCK		S5P_CLKREG(0x00)
    21. 

  21. #define S5P_MPLL_LOCK		S5P_CLKREG(0x08)
    22. 

  22. #define S5P_EPLL_LOCK		S5P_CLKREG(0x10)
    23. 

  23. #define S5P_VPLL_LOCK		S5P_CLKREG(0x20)
    24. 

  24. 

  25. #define S5P_APLL_CON		S5P_CLKREG(0x100)
    26. 

  26. #define S5P_MPLL_CON		S5P_CLKREG(0x108)
    27. 

  27. #define S5P_EPLL_CON		S5P_CLKREG(0x110)
    28. 

  28. #define S5P_VPLL_CON		S5P_CLKREG(0x120)
    29. 

  29. 

  30. #define S5P_CLK_SRC0		S5P_CLKREG(0x200)
    31. 

  31. #define S5P_CLK_SRC1		S5P_CLKREG(0x204)
    32. 

  32. #define S5P_CLK_SRC2		S5P_CLKREG(0x208)
    33. 

  33. #define S5P_CLK_SRC3		S5P_CLKREG(0x20C)
    34. 

  34. #define S5P_CLK_SRC4		S5P_CLKREG(0x210)
    35. 

  35. #define S5P_CLK_SRC5		S5P_CLKREG(0x214)
    36. 

  36. #define S5P_CLK_SRC6		S5P_CLKREG(0x218)
    37. 

  37. 

  38. #define S5P_CLK_SRC_MASK0	S5P_CLKREG(0x280)
    39. 

  39. #define S5P_CLK_SRC_MASK1	S5P_CLKREG(0x284)
    40. 

  40. 

  41. #define S5P_CLK_DIV0		S5P_CLKREG(0x300)
    42. 

  42. #define S5P_CLK_DIV1		S5P_CLKREG(0x304)
    43. 

  43. #define S5P_CLK_DIV2		S5P_CLKREG(0x308)
    44. 

  44. #define S5P_CLK_DIV3		S5P_CLKREG(0x30C)
    45. 

  45. #define S5P_CLK_DIV4		S5P_CLKREG(0x310)
    46. 

  46. #define S5P_CLK_DIV5		S5P_CLKREG(0x314)
    47. 

  47. #define S5P_CLK_DIV6		S5P_CLKREG(0x318)
    48. 

  48. #define S5P_CLK_DIV7		S5P_CLKREG(0x31C)
    49. 

  49. 

  50. #define S5P_CLKGATE_MAIN0	S5P_CLKREG(0x400)
    51. 

  51. #define S5P_CLKGATE_MAIN1	S5P_CLKREG(0x404)
    52. 

  52. #define S5P_CLKGATE_MAIN2	S5P_CLKREG(0x408)
    53. 

  53. 

  54. #define S5P_CLKGATE_PERI0	S5P_CLKREG(0x420)
    55. 

  55. #define S5P_CLKGATE_PERI1	S5P_CLKREG(0x424)
    56. 

  56. 

  57. #define S5P_CLKGATE_SCLK0	S5P_CLKREG(0x440)
    58. 

  58. #define S5P_CLKGATE_SCLK1	S5P_CLKREG(0x444)
    59. 

  59. #define S5P_CLKGATE_IP0		S5P_CLKREG(0x460)
    60. 

  60. #define S5P_CLKGATE_IP1		S5P_CLKREG(0x464)
    61. 

  61. #define S5P_CLKGATE_IP2		S5P_CLKREG(0x468)
    62. 

  62. #define S5P_CLKGATE_IP3		S5P_CLKREG(0x46C)
    63. 

  63. #define S5P_CLKGATE_IP4		S5P_CLKREG(0x470)
    64. 

  64. 

  65. #define S5P_CLKGATE_BLOCK	S5P_CLKREG(0x480)
    66. 

  66. #define S5P_CLKGATE_BUS0	S5P_CLKREG(0x484)
    67. 

  67. #define S5P_CLKGATE_BUS1	S5P_CLKREG(0x488)
    68. 

  68. #define S5P_CLK_OUT		S5P_CLKREG(0x500)
    69. 

  69. 

  70. /* CLKSRC0 */
    71. 

  71. #define S5P_CLKSRC0_MUX200_MASK		(0x1<<16)
    72. 

  72. #define S5P_CLKSRC0_MUX166_MASK		(0x1<<20)
    73. 

  73. #define S5P_CLKSRC0_MUX133_MASK		(0x1<<24)
    74. 

  74. 

  75. /* CLKDIV0 */
    76. 

  76. #define S5P_CLKDIV0_APLL_SHIFT		(0)
    77. 

  77. #define S5P_CLKDIV0_APLL_MASK		(0x7 << S5P_CLKDIV0_APLL_SHIFT)
    78. 

  78. #define S5P_CLKDIV0_A2M_SHIFT		(4)
    79. 

  79. #define S5P_CLKDIV0_A2M_MASK		(0x7 << S5P_CLKDIV0_A2M_SHIFT)
    80. 

  80. #define S5P_CLKDIV0_HCLK200_SHIFT	(8)
    81. 

  81. #define S5P_CLKDIV0_HCLK200_MASK	(0x7 << S5P_CLKDIV0_HCLK200_SHIFT)
    82. 

  82. #define S5P_CLKDIV0_PCLK100_SHIFT	(12)
    83. 

  83. #define S5P_CLKDIV0_PCLK100_MASK	(0x7 << S5P_CLKDIV0_PCLK100_SHIFT)
    84. 

  84. #define S5P_CLKDIV0_HCLK166_SHIFT	(16)
    85. 

  85. #define S5P_CLKDIV0_HCLK166_MASK	(0xF << S5P_CLKDIV0_HCLK166_SHIFT)
    86. 

  86. #define S5P_CLKDIV0_PCLK83_SHIFT	(20)
    87. 

  87. #define S5P_CLKDIV0_PCLK83_MASK		(0x7 << S5P_CLKDIV0_PCLK83_SHIFT)
    88. 

  88. #define S5P_CLKDIV0_HCLK133_SHIFT	(24)
    89. 

  89. #define S5P_CLKDIV0_HCLK133_MASK	(0xF << S5P_CLKDIV0_HCLK133_SHIFT)
    90. 

  90. #define S5P_CLKDIV0_PCLK66_SHIFT	(28)
    91. 

  91. #define S5P_CLKDIV0_PCLK66_MASK		(0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
    92. 

  92. 

  93. /* Registers related to power management */
    94. 

  94. #define S5P_PWR_CFG		S5P_CLKREG(0xC000)
    95. 

  95. #define S5P_EINT_WAKEUP_MASK	S5P_CLKREG(0xC004)
    96. 

  96. #define S5P_WAKEUP_MASK 	S5P_CLKREG(0xC008)
    97. 

  97. #define S5P_PWR_MODE		S5P_CLKREG(0xC00C)
    98. 

  98. #define S5P_NORMAL_CFG		S5P_CLKREG(0xC010)
    99. 

  99. #define S5P_IDLE_CFG		S5P_CLKREG(0xC020)
    100. 

  100. #define S5P_STOP_CFG		S5P_CLKREG(0xC030)
    101. 

  101. #define S5P_STOP_MEM_CFG	S5P_CLKREG(0xC034)
    102. 

  102. #define S5P_SLEEP_CFG		S5P_CLKREG(0xC040)
    103. 

  103. 

  104. #define S5P_OSC_FREQ		S5P_CLKREG(0xC100)
    105. 

  105. #define S5P_OSC_STABLE		S5P_CLKREG(0xC104)
    106. 

  106. #define S5P_PWR_STABLE		S5P_CLKREG(0xC108)
    107. 

  107. #define S5P_MTC_STABLE		S5P_CLKREG(0xC110)
    108. 

  108. #define S5P_CLAMP_STABLE	S5P_CLKREG(0xC114)
    109. 

  109. 

  110. #define S5P_WAKEUP_STAT		S5P_CLKREG(0xC200)
    111. 

  111. #define S5P_BLK_PWR_STAT	S5P_CLKREG(0xC204)
    112. 

  112. 

  113. #define S5P_OTHERS		S5P_CLKREG(0xE000)
    114. 

  114. #define S5P_OM_STAT		S5P_CLKREG(0xE100)
    115. 

  115. #define S5P_USB_PHY_CONTROL	S5P_CLKREG(0xE80C)
    116. 

  116. #define S5P_DAC_CONTROL		S5P_CLKREG(0xE810)
    117. 

  117. 

  118. #define S5P_INFORM0		S5P_CLKREG(0xF000)
    119. 

  119. #define S5P_INFORM1		S5P_CLKREG(0xF004)
    120. 

  120. #define S5P_INFORM2		S5P_CLKREG(0xF008)
    121. 

  121. #define S5P_INFORM3		S5P_CLKREG(0xF00C)
    122. 

  122. #define S5P_INFORM4		S5P_CLKREG(0xF010)
    123. 

  123. #define S5P_INFORM5		S5P_CLKREG(0xF014)
    124. 

  124. #define S5P_INFORM6		S5P_CLKREG(0xF018)
    125. 

  125. #define S5P_INFORM7		S5P_CLKREG(0xF01C)
    126. 

  126. 

  127. #define S5P_RST_STAT		S5P_CLKREG(0xA000)
    128. 

  128. #define S5P_OSC_CON		S5P_CLKREG(0x8000)
    129. 

  129. #define S5P_MIPI_PHY_CON0	S5P_CLKREG(0x7200)
    130. 

  130. #define S5P_MIPI_PHY_CON1	S5P_CLKREG(0x7204)
    131. 

  131. #define S5P_MIPI_CONTROL	S5P_CLKREG(0xE814)
    132. 

  132. 

  133. #define S5P_IDLE_CFG_TL_MASK	(3 << 30)
    134. 

  134. #define S5P_IDLE_CFG_TM_MASK	(3 << 28)
    135. 

  135. #define S5P_IDLE_CFG_TL_ON	(2 << 30)
    136. 

  136. #define S5P_IDLE_CFG_TM_ON	(2 << 28)
    137. 

  137. #define S5P_IDLE_CFG_DIDLE	(1 << 0)
    138. 

  138. 

  139. #define S5P_CFG_WFI_CLEAN		(~(3 << 8))
    140. 

  140. #define S5P_CFG_WFI_IDLE		(1 << 8)
    141. 

  141. #define S5P_CFG_WFI_STOP		(2 << 8)
    142. 

  142. #define S5P_CFG_WFI_SLEEP		(3 << 8)
    143. 

  143. 

  144. #define S5P_OTHER_SYS_INT		24
    145. 

  145. #define S5P_OTHER_STA_TYPE		23
    146. 

  146. #define S5P_OTHER_SYSC_INTOFF		(1 << 0)
    147. 

  147. #define STA_TYPE_EXPON			0
    148. 

  148. #define STA_TYPE_SFR			1
    149. 

  149. 

  150. #define S5P_PWR_STA_EXP_SCALE		0
    151. 

  151. #define S5P_PWR_STA_CNT			4
    152. 

  152. 

  153. #define S5P_PWR_STABLE_COUNT		85500
    154. 

  154. 

  155. #define S5P_SLEEP_CFG_OSC_EN		(1 << 0)
    156. 

  156. #define S5P_SLEEP_CFG_USBOSC_EN		(1 << 1)
    157. 

  157. 

  158. /* OTHERS Resgister */
    159. 

  159. #define S5P_OTHERS_USB_SIG_MASK		(1 << 16)
    160. 

  160. #define S5P_OTHERS_MIPI_DPHY_EN		(1 << 28)
    161. 

  161. 

  162. /* MIPI */
    163. 

  163. #define S5P_MIPI_DPHY_EN		(3)
    164. 

  164. 

  165. /* S5P_DAC_CONTROL */
    166. 

  166. #define S5P_DAC_ENABLE			(1)
    167. 

  167. #define S5P_DAC_DISABLE			(0)
    168. 

  168. 

  169. #endif /* __ASM_ARCH_REGS_CLOCK_H */
    170.