powerdomains34xx.h 6.2 KB

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  1. /*
  2. * OMAP3 powerdomain definitions
  3. *
  4. * Copyright (C) 2007-2008 Texas Instruments, Inc.
  5. * Copyright (C) 2007-2010 Nokia Corporation
  6. *
  7. * Written by Paul Walmsley
  8. * Debugging and integration fixes by Jouni Högander
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
  15. #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
  16. /*
  17. * N.B. If powerdomains are added or removed from this file, update
  18. * the array in mach-omap2/powerdomains.h.
  19. */
  20. #include <plat/powerdomain.h>
  21. #include "prcm-common.h"
  22. #include "prm.h"
  23. #include "prm-regbits-34xx.h"
  24. #include "cm.h"
  25. #include "cm-regbits-34xx.h"
  26. /*
  27. * 34XX-specific powerdomains, dependencies
  28. */
  29. #ifdef CONFIG_ARCH_OMAP3
  30. /*
  31. * Powerdomains
  32. */
  33. static struct powerdomain iva2_pwrdm = {
  34. .name = "iva2_pwrdm",
  35. .prcm_offs = OMAP3430_IVA2_MOD,
  36. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  37. .pwrsts = PWRSTS_OFF_RET_ON,
  38. .pwrsts_logic_ret = PWRSTS_OFF_RET,
  39. .banks = 4,
  40. .pwrsts_mem_ret = {
  41. [0] = PWRSTS_OFF_RET,
  42. [1] = PWRSTS_OFF_RET,
  43. [2] = PWRSTS_OFF_RET,
  44. [3] = PWRSTS_OFF_RET,
  45. },
  46. .pwrsts_mem_on = {
  47. [0] = PWRDM_POWER_ON,
  48. [1] = PWRDM_POWER_ON,
  49. [2] = PWRSTS_OFF_ON,
  50. [3] = PWRDM_POWER_ON,
  51. },
  52. };
  53. static struct powerdomain mpu_3xxx_pwrdm = {
  54. .name = "mpu_pwrdm",
  55. .prcm_offs = MPU_MOD,
  56. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  57. .pwrsts = PWRSTS_OFF_RET_ON,
  58. .pwrsts_logic_ret = PWRSTS_OFF_RET,
  59. .flags = PWRDM_HAS_MPU_QUIRK,
  60. .banks = 1,
  61. .pwrsts_mem_ret = {
  62. [0] = PWRSTS_OFF_RET,
  63. },
  64. .pwrsts_mem_on = {
  65. [0] = PWRSTS_OFF_ON,
  66. },
  67. };
  68. static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
  69. .name = "core_pwrdm",
  70. .prcm_offs = CORE_MOD,
  71. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
  72. CHIP_IS_OMAP3430ES2 |
  73. CHIP_IS_OMAP3430ES3_0),
  74. .pwrsts = PWRSTS_OFF_RET_ON,
  75. .pwrsts_logic_ret = PWRSTS_OFF_RET,
  76. .banks = 2,
  77. .pwrsts_mem_ret = {
  78. [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
  79. [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
  80. },
  81. .pwrsts_mem_on = {
  82. [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
  83. [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
  84. },
  85. };
  86. static struct powerdomain core_3xxx_es3_1_pwrdm = {
  87. .name = "core_pwrdm",
  88. .prcm_offs = CORE_MOD,
  89. .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
  90. .pwrsts = PWRSTS_OFF_RET_ON,
  91. .pwrsts_logic_ret = PWRSTS_OFF_RET,
  92. .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
  93. .banks = 2,
  94. .pwrsts_mem_ret = {
  95. [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
  96. [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
  97. },
  98. .pwrsts_mem_on = {
  99. [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
  100. [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
  101. },
  102. };
  103. static struct powerdomain dss_pwrdm = {
  104. .name = "dss_pwrdm",
  105. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  106. .prcm_offs = OMAP3430_DSS_MOD,
  107. .pwrsts = PWRSTS_OFF_RET_ON,
  108. .pwrsts_logic_ret = PWRDM_POWER_RET,
  109. .banks = 1,
  110. .pwrsts_mem_ret = {
  111. [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
  112. },
  113. .pwrsts_mem_on = {
  114. [0] = PWRDM_POWER_ON, /* MEMONSTATE */
  115. },
  116. };
  117. /*
  118. * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
  119. * possible SGX powerstate, the SGX device itself does not support
  120. * retention.
  121. */
  122. static struct powerdomain sgx_pwrdm = {
  123. .name = "sgx_pwrdm",
  124. .prcm_offs = OMAP3430ES2_SGX_MOD,
  125. .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
  126. /* XXX This is accurate for 3430 SGX, but what about GFX? */
  127. .pwrsts = PWRSTS_OFF_ON,
  128. .pwrsts_logic_ret = PWRDM_POWER_RET,
  129. .banks = 1,
  130. .pwrsts_mem_ret = {
  131. [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
  132. },
  133. .pwrsts_mem_on = {
  134. [0] = PWRDM_POWER_ON, /* MEMONSTATE */
  135. },
  136. };
  137. static struct powerdomain cam_pwrdm = {
  138. .name = "cam_pwrdm",
  139. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  140. .prcm_offs = OMAP3430_CAM_MOD,
  141. .pwrsts = PWRSTS_OFF_RET_ON,
  142. .pwrsts_logic_ret = PWRDM_POWER_RET,
  143. .banks = 1,
  144. .pwrsts_mem_ret = {
  145. [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
  146. },
  147. .pwrsts_mem_on = {
  148. [0] = PWRDM_POWER_ON, /* MEMONSTATE */
  149. },
  150. };
  151. static struct powerdomain per_pwrdm = {
  152. .name = "per_pwrdm",
  153. .prcm_offs = OMAP3430_PER_MOD,
  154. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  155. .pwrsts = PWRSTS_OFF_RET_ON,
  156. .pwrsts_logic_ret = PWRSTS_OFF_RET,
  157. .banks = 1,
  158. .pwrsts_mem_ret = {
  159. [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
  160. },
  161. .pwrsts_mem_on = {
  162. [0] = PWRDM_POWER_ON, /* MEMONSTATE */
  163. },
  164. };
  165. static struct powerdomain emu_pwrdm = {
  166. .name = "emu_pwrdm",
  167. .prcm_offs = OMAP3430_EMU_MOD,
  168. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  169. };
  170. static struct powerdomain neon_pwrdm = {
  171. .name = "neon_pwrdm",
  172. .prcm_offs = OMAP3430_NEON_MOD,
  173. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  174. .pwrsts = PWRSTS_OFF_RET_ON,
  175. .pwrsts_logic_ret = PWRDM_POWER_RET,
  176. };
  177. static struct powerdomain usbhost_pwrdm = {
  178. .name = "usbhost_pwrdm",
  179. .prcm_offs = OMAP3430ES2_USBHOST_MOD,
  180. .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
  181. .pwrsts = PWRSTS_OFF_RET_ON,
  182. .pwrsts_logic_ret = PWRDM_POWER_RET,
  183. /*
  184. * REVISIT: Enabling usb host save and restore mechanism seems to
  185. * leave the usb host domain permanently in ACTIVE mode after
  186. * changing the usb host power domain state from OFF to active once.
  187. * Disabling for now.
  188. */
  189. /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
  190. .banks = 1,
  191. .pwrsts_mem_ret = {
  192. [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
  193. },
  194. .pwrsts_mem_on = {
  195. [0] = PWRDM_POWER_ON, /* MEMONSTATE */
  196. },
  197. };
  198. static struct powerdomain dpll1_pwrdm = {
  199. .name = "dpll1_pwrdm",
  200. .prcm_offs = MPU_MOD,
  201. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  202. };
  203. static struct powerdomain dpll2_pwrdm = {
  204. .name = "dpll2_pwrdm",
  205. .prcm_offs = OMAP3430_IVA2_MOD,
  206. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  207. };
  208. static struct powerdomain dpll3_pwrdm = {
  209. .name = "dpll3_pwrdm",
  210. .prcm_offs = PLL_MOD,
  211. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  212. };
  213. static struct powerdomain dpll4_pwrdm = {
  214. .name = "dpll4_pwrdm",
  215. .prcm_offs = PLL_MOD,
  216. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  217. };
  218. static struct powerdomain dpll5_pwrdm = {
  219. .name = "dpll5_pwrdm",
  220. .prcm_offs = PLL_MOD,
  221. .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
  222. };
  223. #endif /* CONFIG_ARCH_OMAP3 */
  224. #endif