iwl3945-base.c 243 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/version.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/ieee80211_radiotap.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-3945.h"
  46. #include "iwl-helpers.h"
  47. #ifdef CONFIG_IWL3945_DEBUG
  48. u32 iwl3945_debug_level;
  49. #endif
  50. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  51. struct iwl3945_tx_queue *txq);
  52. /******************************************************************************
  53. *
  54. * module boiler plate
  55. *
  56. ******************************************************************************/
  57. /* module parameters */
  58. static int iwl3945_param_disable_hw_scan;
  59. static int iwl3945_param_debug;
  60. static int iwl3945_param_disable; /* def: enable radio */
  61. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  62. int iwl3945_param_hwcrypto; /* def: using software encryption */
  63. static int iwl3945_param_qos_enable = 1;
  64. int iwl3945_param_queues_num = IWL_MAX_NUM_QUEUES;
  65. /*
  66. * module name, copyright, version, etc.
  67. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  68. */
  69. #define DRV_DESCRIPTION \
  70. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  71. #ifdef CONFIG_IWL3945_DEBUG
  72. #define VD "d"
  73. #else
  74. #define VD
  75. #endif
  76. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  77. #define VS "s"
  78. #else
  79. #define VS
  80. #endif
  81. #define IWLWIFI_VERSION "1.1.19k" VD VS
  82. #define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation"
  83. #define DRV_VERSION IWLWIFI_VERSION
  84. /* Change firmware file name, using "-" and incrementing number,
  85. * *only* when uCode interface or architecture changes so that it
  86. * is not compatible with earlier drivers.
  87. * This number will also appear in << 8 position of 1st dword of uCode file */
  88. #define IWL3945_UCODE_API "-1"
  89. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  90. MODULE_VERSION(DRV_VERSION);
  91. MODULE_AUTHOR(DRV_COPYRIGHT);
  92. MODULE_LICENSE("GPL");
  93. static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
  94. {
  95. u16 fc = le16_to_cpu(hdr->frame_control);
  96. int hdr_len = ieee80211_get_hdrlen(fc);
  97. if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
  98. return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
  99. return NULL;
  100. }
  101. static const struct ieee80211_hw_mode *iwl3945_get_hw_mode(
  102. struct iwl3945_priv *priv, int mode)
  103. {
  104. int i;
  105. for (i = 0; i < 3; i++)
  106. if (priv->modes[i].mode == mode)
  107. return &priv->modes[i];
  108. return NULL;
  109. }
  110. static int iwl3945_is_empty_essid(const char *essid, int essid_len)
  111. {
  112. /* Single white space is for Linksys APs */
  113. if (essid_len == 1 && essid[0] == ' ')
  114. return 1;
  115. /* Otherwise, if the entire essid is 0, we assume it is hidden */
  116. while (essid_len) {
  117. essid_len--;
  118. if (essid[essid_len] != '\0')
  119. return 0;
  120. }
  121. return 1;
  122. }
  123. static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
  124. {
  125. static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
  126. const char *s = essid;
  127. char *d = escaped;
  128. if (iwl3945_is_empty_essid(essid, essid_len)) {
  129. memcpy(escaped, "<hidden>", sizeof("<hidden>"));
  130. return escaped;
  131. }
  132. essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
  133. while (essid_len--) {
  134. if (*s == '\0') {
  135. *d++ = '\\';
  136. *d++ = '0';
  137. s++;
  138. } else
  139. *d++ = *s++;
  140. }
  141. *d = '\0';
  142. return escaped;
  143. }
  144. static void iwl3945_print_hex_dump(int level, void *p, u32 len)
  145. {
  146. #ifdef CONFIG_IWL3945_DEBUG
  147. if (!(iwl3945_debug_level & level))
  148. return;
  149. print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
  150. p, len, 1);
  151. #endif
  152. }
  153. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  154. * DMA services
  155. *
  156. * Theory of operation
  157. *
  158. * A queue is a circular buffers with 'Read' and 'Write' pointers.
  159. * 2 empty entries always kept in the buffer to protect from overflow.
  160. *
  161. * For Tx queue, there are low mark and high mark limits. If, after queuing
  162. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  163. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  164. * Tx queue resumed.
  165. *
  166. * The IWL operates with six queues, one receive queue in the device's
  167. * sram, one transmit queue for sending commands to the device firmware,
  168. * and four transmit queues for data.
  169. ***************************************************/
  170. static int iwl3945_queue_space(const struct iwl3945_queue *q)
  171. {
  172. int s = q->read_ptr - q->write_ptr;
  173. if (q->read_ptr > q->write_ptr)
  174. s -= q->n_bd;
  175. if (s <= 0)
  176. s += q->n_window;
  177. /* keep some reserve to not confuse empty and full situations */
  178. s -= 2;
  179. if (s < 0)
  180. s = 0;
  181. return s;
  182. }
  183. /* XXX: n_bd must be power-of-two size */
  184. static inline int iwl3945_queue_inc_wrap(int index, int n_bd)
  185. {
  186. return ++index & (n_bd - 1);
  187. }
  188. /* XXX: n_bd must be power-of-two size */
  189. static inline int iwl3945_queue_dec_wrap(int index, int n_bd)
  190. {
  191. return --index & (n_bd - 1);
  192. }
  193. static inline int x2_queue_used(const struct iwl3945_queue *q, int i)
  194. {
  195. return q->write_ptr > q->read_ptr ?
  196. (i >= q->read_ptr && i < q->write_ptr) :
  197. !(i < q->read_ptr && i >= q->write_ptr);
  198. }
  199. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  200. {
  201. if (is_huge)
  202. return q->n_window;
  203. return index & (q->n_window - 1);
  204. }
  205. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  206. int count, int slots_num, u32 id)
  207. {
  208. q->n_bd = count;
  209. q->n_window = slots_num;
  210. q->id = id;
  211. /* count must be power-of-two size, otherwise iwl3945_queue_inc_wrap
  212. * and iwl3945_queue_dec_wrap are broken. */
  213. BUG_ON(!is_power_of_2(count));
  214. /* slots_num must be power-of-two size, otherwise
  215. * get_cmd_index is broken. */
  216. BUG_ON(!is_power_of_2(slots_num));
  217. q->low_mark = q->n_window / 4;
  218. if (q->low_mark < 4)
  219. q->low_mark = 4;
  220. q->high_mark = q->n_window / 8;
  221. if (q->high_mark < 2)
  222. q->high_mark = 2;
  223. q->write_ptr = q->read_ptr = 0;
  224. return 0;
  225. }
  226. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  227. struct iwl3945_tx_queue *txq, u32 id)
  228. {
  229. struct pci_dev *dev = priv->pci_dev;
  230. if (id != IWL_CMD_QUEUE_NUM) {
  231. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  232. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  233. if (!txq->txb) {
  234. IWL_ERROR("kmalloc for auxiliary BD "
  235. "structures failed\n");
  236. goto error;
  237. }
  238. } else
  239. txq->txb = NULL;
  240. txq->bd = pci_alloc_consistent(dev,
  241. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  242. &txq->q.dma_addr);
  243. if (!txq->bd) {
  244. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  245. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  246. goto error;
  247. }
  248. txq->q.id = id;
  249. return 0;
  250. error:
  251. if (txq->txb) {
  252. kfree(txq->txb);
  253. txq->txb = NULL;
  254. }
  255. return -ENOMEM;
  256. }
  257. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  258. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  259. {
  260. struct pci_dev *dev = priv->pci_dev;
  261. int len;
  262. int rc = 0;
  263. /* allocate command space + one big command for scan since scan
  264. * command is very huge the system will not have two scan at the
  265. * same time */
  266. len = sizeof(struct iwl3945_cmd) * slots_num;
  267. if (txq_id == IWL_CMD_QUEUE_NUM)
  268. len += IWL_MAX_SCAN_SIZE;
  269. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  270. if (!txq->cmd)
  271. return -ENOMEM;
  272. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  273. if (rc) {
  274. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  275. return -ENOMEM;
  276. }
  277. txq->need_update = 0;
  278. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  279. * iwl3945_queue_inc_wrap and iwl3945_queue_dec_wrap are broken. */
  280. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  281. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  282. iwl3945_hw_tx_queue_init(priv, txq);
  283. return 0;
  284. }
  285. /**
  286. * iwl3945_tx_queue_free - Deallocate DMA queue.
  287. * @txq: Transmit queue to deallocate.
  288. *
  289. * Empty queue by removing and destroying all BD's.
  290. * Free all buffers. txq itself is not freed.
  291. *
  292. */
  293. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  294. {
  295. struct iwl3945_queue *q = &txq->q;
  296. struct pci_dev *dev = priv->pci_dev;
  297. int len;
  298. if (q->n_bd == 0)
  299. return;
  300. /* first, empty all BD's */
  301. for (; q->write_ptr != q->read_ptr;
  302. q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd))
  303. iwl3945_hw_txq_free_tfd(priv, txq);
  304. len = sizeof(struct iwl3945_cmd) * q->n_window;
  305. if (q->id == IWL_CMD_QUEUE_NUM)
  306. len += IWL_MAX_SCAN_SIZE;
  307. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  308. /* free buffers belonging to queue itself */
  309. if (txq->q.n_bd)
  310. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  311. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  312. if (txq->txb) {
  313. kfree(txq->txb);
  314. txq->txb = NULL;
  315. }
  316. /* 0 fill whole structure */
  317. memset(txq, 0, sizeof(*txq));
  318. }
  319. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  320. /*************** STATION TABLE MANAGEMENT ****
  321. * mac80211 should be examined to determine if sta_info is duplicating
  322. * the functionality provided here
  323. */
  324. /**************************************************************/
  325. #if 0 /* temporary disable till we add real remove station */
  326. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  327. {
  328. int index = IWL_INVALID_STATION;
  329. int i;
  330. unsigned long flags;
  331. spin_lock_irqsave(&priv->sta_lock, flags);
  332. if (is_ap)
  333. index = IWL_AP_ID;
  334. else if (is_broadcast_ether_addr(addr))
  335. index = priv->hw_setting.bcast_sta_id;
  336. else
  337. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  338. if (priv->stations[i].used &&
  339. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  340. addr)) {
  341. index = i;
  342. break;
  343. }
  344. if (unlikely(index == IWL_INVALID_STATION))
  345. goto out;
  346. if (priv->stations[index].used) {
  347. priv->stations[index].used = 0;
  348. priv->num_stations--;
  349. }
  350. BUG_ON(priv->num_stations < 0);
  351. out:
  352. spin_unlock_irqrestore(&priv->sta_lock, flags);
  353. return 0;
  354. }
  355. #endif
  356. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  357. {
  358. unsigned long flags;
  359. spin_lock_irqsave(&priv->sta_lock, flags);
  360. priv->num_stations = 0;
  361. memset(priv->stations, 0, sizeof(priv->stations));
  362. spin_unlock_irqrestore(&priv->sta_lock, flags);
  363. }
  364. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  365. {
  366. int i;
  367. int index = IWL_INVALID_STATION;
  368. struct iwl3945_station_entry *station;
  369. unsigned long flags_spin;
  370. DECLARE_MAC_BUF(mac);
  371. u8 rate;
  372. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  373. if (is_ap)
  374. index = IWL_AP_ID;
  375. else if (is_broadcast_ether_addr(addr))
  376. index = priv->hw_setting.bcast_sta_id;
  377. else
  378. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  379. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  380. addr)) {
  381. index = i;
  382. break;
  383. }
  384. if (!priv->stations[i].used &&
  385. index == IWL_INVALID_STATION)
  386. index = i;
  387. }
  388. /* These two conditions has the same outcome but keep them separate
  389. since they have different meaning */
  390. if (unlikely(index == IWL_INVALID_STATION)) {
  391. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  392. return index;
  393. }
  394. if (priv->stations[index].used &&
  395. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  396. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  397. return index;
  398. }
  399. IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
  400. station = &priv->stations[index];
  401. station->used = 1;
  402. priv->num_stations++;
  403. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  404. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  405. station->sta.mode = 0;
  406. station->sta.sta.sta_id = index;
  407. station->sta.station_flags = 0;
  408. if (priv->phymode == MODE_IEEE80211A)
  409. rate = IWL_RATE_6M_PLCP;
  410. else
  411. rate = IWL_RATE_1M_PLCP;
  412. /* Turn on both antennas for the station... */
  413. station->sta.rate_n_flags =
  414. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  415. station->current_rate.rate_n_flags =
  416. le16_to_cpu(station->sta.rate_n_flags);
  417. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  418. iwl3945_send_add_station(priv, &station->sta, flags);
  419. return index;
  420. }
  421. /*************** DRIVER STATUS FUNCTIONS *****/
  422. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  423. {
  424. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  425. * set but EXIT_PENDING is not */
  426. return test_bit(STATUS_READY, &priv->status) &&
  427. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  428. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  429. }
  430. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  431. {
  432. return test_bit(STATUS_ALIVE, &priv->status);
  433. }
  434. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  435. {
  436. return test_bit(STATUS_INIT, &priv->status);
  437. }
  438. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  439. {
  440. return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
  441. test_bit(STATUS_RF_KILL_SW, &priv->status);
  442. }
  443. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  444. {
  445. if (iwl3945_is_rfkill(priv))
  446. return 0;
  447. return iwl3945_is_ready(priv);
  448. }
  449. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  450. #define IWL_CMD(x) case x : return #x
  451. static const char *get_cmd_string(u8 cmd)
  452. {
  453. switch (cmd) {
  454. IWL_CMD(REPLY_ALIVE);
  455. IWL_CMD(REPLY_ERROR);
  456. IWL_CMD(REPLY_RXON);
  457. IWL_CMD(REPLY_RXON_ASSOC);
  458. IWL_CMD(REPLY_QOS_PARAM);
  459. IWL_CMD(REPLY_RXON_TIMING);
  460. IWL_CMD(REPLY_ADD_STA);
  461. IWL_CMD(REPLY_REMOVE_STA);
  462. IWL_CMD(REPLY_REMOVE_ALL_STA);
  463. IWL_CMD(REPLY_3945_RX);
  464. IWL_CMD(REPLY_TX);
  465. IWL_CMD(REPLY_RATE_SCALE);
  466. IWL_CMD(REPLY_LEDS_CMD);
  467. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  468. IWL_CMD(RADAR_NOTIFICATION);
  469. IWL_CMD(REPLY_QUIET_CMD);
  470. IWL_CMD(REPLY_CHANNEL_SWITCH);
  471. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  472. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  473. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  474. IWL_CMD(POWER_TABLE_CMD);
  475. IWL_CMD(PM_SLEEP_NOTIFICATION);
  476. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  477. IWL_CMD(REPLY_SCAN_CMD);
  478. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  479. IWL_CMD(SCAN_START_NOTIFICATION);
  480. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  481. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  482. IWL_CMD(BEACON_NOTIFICATION);
  483. IWL_CMD(REPLY_TX_BEACON);
  484. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  485. IWL_CMD(QUIET_NOTIFICATION);
  486. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  487. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  488. IWL_CMD(REPLY_BT_CONFIG);
  489. IWL_CMD(REPLY_STATISTICS_CMD);
  490. IWL_CMD(STATISTICS_NOTIFICATION);
  491. IWL_CMD(REPLY_CARD_STATE_CMD);
  492. IWL_CMD(CARD_STATE_NOTIFICATION);
  493. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  494. default:
  495. return "UNKNOWN";
  496. }
  497. }
  498. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  499. /**
  500. * iwl3945_enqueue_hcmd - enqueue a uCode command
  501. * @priv: device private data point
  502. * @cmd: a point to the ucode command structure
  503. *
  504. * The function returns < 0 values to indicate the operation is
  505. * failed. On success, it turns the index (> 0) of command in the
  506. * command queue.
  507. */
  508. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  509. {
  510. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  511. struct iwl3945_queue *q = &txq->q;
  512. struct iwl3945_tfd_frame *tfd;
  513. u32 *control_flags;
  514. struct iwl3945_cmd *out_cmd;
  515. u32 idx;
  516. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  517. dma_addr_t phys_addr;
  518. int pad;
  519. u16 count;
  520. int ret;
  521. unsigned long flags;
  522. /* If any of the command structures end up being larger than
  523. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  524. * we will need to increase the size of the TFD entries */
  525. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  526. !(cmd->meta.flags & CMD_SIZE_HUGE));
  527. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  528. IWL_ERROR("No space for Tx\n");
  529. return -ENOSPC;
  530. }
  531. spin_lock_irqsave(&priv->hcmd_lock, flags);
  532. tfd = &txq->bd[q->write_ptr];
  533. memset(tfd, 0, sizeof(*tfd));
  534. control_flags = (u32 *) tfd;
  535. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  536. out_cmd = &txq->cmd[idx];
  537. out_cmd->hdr.cmd = cmd->id;
  538. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  539. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  540. /* At this point, the out_cmd now has all of the incoming cmd
  541. * information */
  542. out_cmd->hdr.flags = 0;
  543. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  544. INDEX_TO_SEQ(q->write_ptr));
  545. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  546. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  547. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  548. offsetof(struct iwl3945_cmd, hdr);
  549. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  550. pad = U32_PAD(cmd->len);
  551. count = TFD_CTL_COUNT_GET(*control_flags);
  552. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  553. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  554. "%d bytes at %d[%d]:%d\n",
  555. get_cmd_string(out_cmd->hdr.cmd),
  556. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  557. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  558. txq->need_update = 1;
  559. q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
  560. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  561. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  562. return ret ? ret : idx;
  563. }
  564. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  565. {
  566. int ret;
  567. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  568. /* An asynchronous command can not expect an SKB to be set. */
  569. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  570. /* An asynchronous command MUST have a callback. */
  571. BUG_ON(!cmd->meta.u.callback);
  572. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  573. return -EBUSY;
  574. ret = iwl3945_enqueue_hcmd(priv, cmd);
  575. if (ret < 0) {
  576. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  577. get_cmd_string(cmd->id), ret);
  578. return ret;
  579. }
  580. return 0;
  581. }
  582. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  583. {
  584. int cmd_idx;
  585. int ret;
  586. static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */
  587. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  588. /* A synchronous command can not have a callback set. */
  589. BUG_ON(cmd->meta.u.callback != NULL);
  590. if (atomic_xchg(&entry, 1)) {
  591. IWL_ERROR("Error sending %s: Already sending a host command\n",
  592. get_cmd_string(cmd->id));
  593. return -EBUSY;
  594. }
  595. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  596. if (cmd->meta.flags & CMD_WANT_SKB)
  597. cmd->meta.source = &cmd->meta;
  598. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  599. if (cmd_idx < 0) {
  600. ret = cmd_idx;
  601. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  602. get_cmd_string(cmd->id), ret);
  603. goto out;
  604. }
  605. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  606. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  607. HOST_COMPLETE_TIMEOUT);
  608. if (!ret) {
  609. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  610. IWL_ERROR("Error sending %s: time out after %dms.\n",
  611. get_cmd_string(cmd->id),
  612. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  613. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  614. ret = -ETIMEDOUT;
  615. goto cancel;
  616. }
  617. }
  618. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  619. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  620. get_cmd_string(cmd->id));
  621. ret = -ECANCELED;
  622. goto fail;
  623. }
  624. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  625. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  626. get_cmd_string(cmd->id));
  627. ret = -EIO;
  628. goto fail;
  629. }
  630. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  631. IWL_ERROR("Error: Response NULL in '%s'\n",
  632. get_cmd_string(cmd->id));
  633. ret = -EIO;
  634. goto out;
  635. }
  636. ret = 0;
  637. goto out;
  638. cancel:
  639. if (cmd->meta.flags & CMD_WANT_SKB) {
  640. struct iwl3945_cmd *qcmd;
  641. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  642. * TX cmd queue. Otherwise in case the cmd comes
  643. * in later, it will possibly set an invalid
  644. * address (cmd->meta.source). */
  645. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  646. qcmd->meta.flags &= ~CMD_WANT_SKB;
  647. }
  648. fail:
  649. if (cmd->meta.u.skb) {
  650. dev_kfree_skb_any(cmd->meta.u.skb);
  651. cmd->meta.u.skb = NULL;
  652. }
  653. out:
  654. atomic_set(&entry, 0);
  655. return ret;
  656. }
  657. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  658. {
  659. if (cmd->meta.flags & CMD_ASYNC)
  660. return iwl3945_send_cmd_async(priv, cmd);
  661. return iwl3945_send_cmd_sync(priv, cmd);
  662. }
  663. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  664. {
  665. struct iwl3945_host_cmd cmd = {
  666. .id = id,
  667. .len = len,
  668. .data = data,
  669. };
  670. return iwl3945_send_cmd_sync(priv, &cmd);
  671. }
  672. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  673. {
  674. struct iwl3945_host_cmd cmd = {
  675. .id = id,
  676. .len = sizeof(val),
  677. .data = &val,
  678. };
  679. return iwl3945_send_cmd_sync(priv, &cmd);
  680. }
  681. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  682. {
  683. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  684. }
  685. /**
  686. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  687. * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
  688. * @channel: Any channel valid for the requested phymode
  689. * In addition to setting the staging RXON, priv->phymode is also set.
  690. *
  691. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  692. * in the staging RXON flag structure based on the phymode
  693. */
  694. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv, u8 phymode, u16 channel)
  695. {
  696. if (!iwl3945_get_channel_info(priv, phymode, channel)) {
  697. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  698. channel, phymode);
  699. return -EINVAL;
  700. }
  701. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  702. (priv->phymode == phymode))
  703. return 0;
  704. priv->staging_rxon.channel = cpu_to_le16(channel);
  705. if (phymode == MODE_IEEE80211A)
  706. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  707. else
  708. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  709. priv->phymode = phymode;
  710. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, phymode);
  711. return 0;
  712. }
  713. /**
  714. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  715. *
  716. * NOTE: This is really only useful during development and can eventually
  717. * be #ifdef'd out once the driver is stable and folks aren't actively
  718. * making changes
  719. */
  720. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  721. {
  722. int error = 0;
  723. int counter = 1;
  724. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  725. error |= le32_to_cpu(rxon->flags &
  726. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  727. RXON_FLG_RADAR_DETECT_MSK));
  728. if (error)
  729. IWL_WARNING("check 24G fields %d | %d\n",
  730. counter++, error);
  731. } else {
  732. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  733. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  734. if (error)
  735. IWL_WARNING("check 52 fields %d | %d\n",
  736. counter++, error);
  737. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  738. if (error)
  739. IWL_WARNING("check 52 CCK %d | %d\n",
  740. counter++, error);
  741. }
  742. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  743. if (error)
  744. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  745. /* make sure basic rates 6Mbps and 1Mbps are supported */
  746. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  747. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  748. if (error)
  749. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  750. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  751. if (error)
  752. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  753. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  754. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  755. if (error)
  756. IWL_WARNING("check CCK and short slot %d | %d\n",
  757. counter++, error);
  758. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  759. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  760. if (error)
  761. IWL_WARNING("check CCK & auto detect %d | %d\n",
  762. counter++, error);
  763. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  764. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  765. if (error)
  766. IWL_WARNING("check TGG and auto detect %d | %d\n",
  767. counter++, error);
  768. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  769. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  770. RXON_FLG_ANT_A_MSK)) == 0);
  771. if (error)
  772. IWL_WARNING("check antenna %d %d\n", counter++, error);
  773. if (error)
  774. IWL_WARNING("Tuning to channel %d\n",
  775. le16_to_cpu(rxon->channel));
  776. if (error) {
  777. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  778. return -1;
  779. }
  780. return 0;
  781. }
  782. /**
  783. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  784. * @priv: staging_rxon is compared to active_rxon
  785. *
  786. * If the RXON structure is changing enough to require a new tune,
  787. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  788. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  789. */
  790. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  791. {
  792. /* These items are only settable from the full RXON command */
  793. if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
  794. compare_ether_addr(priv->staging_rxon.bssid_addr,
  795. priv->active_rxon.bssid_addr) ||
  796. compare_ether_addr(priv->staging_rxon.node_addr,
  797. priv->active_rxon.node_addr) ||
  798. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  799. priv->active_rxon.wlap_bssid_addr) ||
  800. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  801. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  802. (priv->staging_rxon.air_propagation !=
  803. priv->active_rxon.air_propagation) ||
  804. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  805. return 1;
  806. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  807. * be updated with the RXON_ASSOC command -- however only some
  808. * flag transitions are allowed using RXON_ASSOC */
  809. /* Check if we are not switching bands */
  810. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  811. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  812. return 1;
  813. /* Check if we are switching association toggle */
  814. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  815. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  816. return 1;
  817. return 0;
  818. }
  819. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  820. {
  821. int rc = 0;
  822. struct iwl3945_rx_packet *res = NULL;
  823. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  824. struct iwl3945_host_cmd cmd = {
  825. .id = REPLY_RXON_ASSOC,
  826. .len = sizeof(rxon_assoc),
  827. .meta.flags = CMD_WANT_SKB,
  828. .data = &rxon_assoc,
  829. };
  830. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  831. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  832. if ((rxon1->flags == rxon2->flags) &&
  833. (rxon1->filter_flags == rxon2->filter_flags) &&
  834. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  835. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  836. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  837. return 0;
  838. }
  839. rxon_assoc.flags = priv->staging_rxon.flags;
  840. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  841. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  842. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  843. rxon_assoc.reserved = 0;
  844. rc = iwl3945_send_cmd_sync(priv, &cmd);
  845. if (rc)
  846. return rc;
  847. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  848. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  849. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  850. rc = -EIO;
  851. }
  852. priv->alloc_rxb_skb--;
  853. dev_kfree_skb_any(cmd.meta.u.skb);
  854. return rc;
  855. }
  856. /**
  857. * iwl3945_commit_rxon - commit staging_rxon to hardware
  858. *
  859. * The RXON command in staging_rxon is committed to the hardware and
  860. * the active_rxon structure is updated with the new data. This
  861. * function correctly transitions out of the RXON_ASSOC_MSK state if
  862. * a HW tune is required based on the RXON structure changes.
  863. */
  864. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  865. {
  866. /* cast away the const for active_rxon in this function */
  867. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  868. int rc = 0;
  869. DECLARE_MAC_BUF(mac);
  870. if (!iwl3945_is_alive(priv))
  871. return -1;
  872. /* always get timestamp with Rx frame */
  873. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  874. /* select antenna */
  875. priv->staging_rxon.flags &=
  876. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  877. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  878. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  879. if (rc) {
  880. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  881. return -EINVAL;
  882. }
  883. /* If we don't need to send a full RXON, we can use
  884. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  885. * and other flags for the current radio configuration. */
  886. if (!iwl3945_full_rxon_required(priv)) {
  887. rc = iwl3945_send_rxon_assoc(priv);
  888. if (rc) {
  889. IWL_ERROR("Error setting RXON_ASSOC "
  890. "configuration (%d).\n", rc);
  891. return rc;
  892. }
  893. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  894. return 0;
  895. }
  896. /* If we are currently associated and the new config requires
  897. * an RXON_ASSOC and the new config wants the associated mask enabled,
  898. * we must clear the associated from the active configuration
  899. * before we apply the new config */
  900. if (iwl3945_is_associated(priv) &&
  901. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  902. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  903. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  904. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  905. sizeof(struct iwl3945_rxon_cmd),
  906. &priv->active_rxon);
  907. /* If the mask clearing failed then we set
  908. * active_rxon back to what it was previously */
  909. if (rc) {
  910. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  911. IWL_ERROR("Error clearing ASSOC_MSK on current "
  912. "configuration (%d).\n", rc);
  913. return rc;
  914. }
  915. }
  916. IWL_DEBUG_INFO("Sending RXON\n"
  917. "* with%s RXON_FILTER_ASSOC_MSK\n"
  918. "* channel = %d\n"
  919. "* bssid = %s\n",
  920. ((priv->staging_rxon.filter_flags &
  921. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  922. le16_to_cpu(priv->staging_rxon.channel),
  923. print_mac(mac, priv->staging_rxon.bssid_addr));
  924. /* Apply the new configuration */
  925. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  926. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  927. if (rc) {
  928. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  929. return rc;
  930. }
  931. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  932. iwl3945_clear_stations_table(priv);
  933. /* If we issue a new RXON command which required a tune then we must
  934. * send a new TXPOWER command or we won't be able to Tx any frames */
  935. rc = iwl3945_hw_reg_send_txpower(priv);
  936. if (rc) {
  937. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  938. return rc;
  939. }
  940. /* Add the broadcast address so we can send broadcast frames */
  941. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  942. IWL_INVALID_STATION) {
  943. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  944. return -EIO;
  945. }
  946. /* If we have set the ASSOC_MSK and we are in BSS mode then
  947. * add the IWL_AP_ID to the station rate table */
  948. if (iwl3945_is_associated(priv) &&
  949. (priv->iw_mode == IEEE80211_IF_TYPE_STA))
  950. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  951. == IWL_INVALID_STATION) {
  952. IWL_ERROR("Error adding AP address for transmit.\n");
  953. return -EIO;
  954. }
  955. /* Init the hardware's rate fallback order based on the
  956. * phymode */
  957. rc = iwl3945_init_hw_rate_table(priv);
  958. if (rc) {
  959. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  960. return -EIO;
  961. }
  962. return 0;
  963. }
  964. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  965. {
  966. struct iwl3945_bt_cmd bt_cmd = {
  967. .flags = 3,
  968. .lead_time = 0xAA,
  969. .max_kill = 1,
  970. .kill_ack_mask = 0,
  971. .kill_cts_mask = 0,
  972. };
  973. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  974. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  975. }
  976. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  977. {
  978. int rc = 0;
  979. struct iwl3945_rx_packet *res;
  980. struct iwl3945_host_cmd cmd = {
  981. .id = REPLY_SCAN_ABORT_CMD,
  982. .meta.flags = CMD_WANT_SKB,
  983. };
  984. /* If there isn't a scan actively going on in the hardware
  985. * then we are in between scan bands and not actually
  986. * actively scanning, so don't send the abort command */
  987. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  988. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  989. return 0;
  990. }
  991. rc = iwl3945_send_cmd_sync(priv, &cmd);
  992. if (rc) {
  993. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  994. return rc;
  995. }
  996. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  997. if (res->u.status != CAN_ABORT_STATUS) {
  998. /* The scan abort will return 1 for success or
  999. * 2 for "failure". A failure condition can be
  1000. * due to simply not being in an active scan which
  1001. * can occur if we send the scan abort before we
  1002. * the microcode has notified us that a scan is
  1003. * completed. */
  1004. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  1005. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1006. clear_bit(STATUS_SCAN_HW, &priv->status);
  1007. }
  1008. dev_kfree_skb_any(cmd.meta.u.skb);
  1009. return rc;
  1010. }
  1011. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  1012. struct iwl3945_cmd *cmd,
  1013. struct sk_buff *skb)
  1014. {
  1015. return 1;
  1016. }
  1017. /*
  1018. * CARD_STATE_CMD
  1019. *
  1020. * Use: Sets the device's internal card state to enable, disable, or halt
  1021. *
  1022. * When in the 'enable' state the card operates as normal.
  1023. * When in the 'disable' state, the card enters into a low power mode.
  1024. * When in the 'halt' state, the card is shut down and must be fully
  1025. * restarted to come back on.
  1026. */
  1027. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1028. {
  1029. struct iwl3945_host_cmd cmd = {
  1030. .id = REPLY_CARD_STATE_CMD,
  1031. .len = sizeof(u32),
  1032. .data = &flags,
  1033. .meta.flags = meta_flag,
  1034. };
  1035. if (meta_flag & CMD_ASYNC)
  1036. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1037. return iwl3945_send_cmd(priv, &cmd);
  1038. }
  1039. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1040. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1041. {
  1042. struct iwl3945_rx_packet *res = NULL;
  1043. if (!skb) {
  1044. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1045. return 1;
  1046. }
  1047. res = (struct iwl3945_rx_packet *)skb->data;
  1048. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1049. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1050. res->hdr.flags);
  1051. return 1;
  1052. }
  1053. switch (res->u.add_sta.status) {
  1054. case ADD_STA_SUCCESS_MSK:
  1055. break;
  1056. default:
  1057. break;
  1058. }
  1059. /* We didn't cache the SKB; let the caller free it */
  1060. return 1;
  1061. }
  1062. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1063. struct iwl3945_addsta_cmd *sta, u8 flags)
  1064. {
  1065. struct iwl3945_rx_packet *res = NULL;
  1066. int rc = 0;
  1067. struct iwl3945_host_cmd cmd = {
  1068. .id = REPLY_ADD_STA,
  1069. .len = sizeof(struct iwl3945_addsta_cmd),
  1070. .meta.flags = flags,
  1071. .data = sta,
  1072. };
  1073. if (flags & CMD_ASYNC)
  1074. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1075. else
  1076. cmd.meta.flags |= CMD_WANT_SKB;
  1077. rc = iwl3945_send_cmd(priv, &cmd);
  1078. if (rc || (flags & CMD_ASYNC))
  1079. return rc;
  1080. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1081. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1082. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1083. res->hdr.flags);
  1084. rc = -EIO;
  1085. }
  1086. if (rc == 0) {
  1087. switch (res->u.add_sta.status) {
  1088. case ADD_STA_SUCCESS_MSK:
  1089. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1090. break;
  1091. default:
  1092. rc = -EIO;
  1093. IWL_WARNING("REPLY_ADD_STA failed\n");
  1094. break;
  1095. }
  1096. }
  1097. priv->alloc_rxb_skb--;
  1098. dev_kfree_skb_any(cmd.meta.u.skb);
  1099. return rc;
  1100. }
  1101. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1102. struct ieee80211_key_conf *keyconf,
  1103. u8 sta_id)
  1104. {
  1105. unsigned long flags;
  1106. __le16 key_flags = 0;
  1107. switch (keyconf->alg) {
  1108. case ALG_CCMP:
  1109. key_flags |= STA_KEY_FLG_CCMP;
  1110. key_flags |= cpu_to_le16(
  1111. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1112. key_flags &= ~STA_KEY_FLG_INVALID;
  1113. break;
  1114. case ALG_TKIP:
  1115. case ALG_WEP:
  1116. default:
  1117. return -EINVAL;
  1118. }
  1119. spin_lock_irqsave(&priv->sta_lock, flags);
  1120. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1121. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1122. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1123. keyconf->keylen);
  1124. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1125. keyconf->keylen);
  1126. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1127. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1128. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1129. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1130. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1131. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1132. return 0;
  1133. }
  1134. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1135. {
  1136. unsigned long flags;
  1137. spin_lock_irqsave(&priv->sta_lock, flags);
  1138. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1139. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1140. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1141. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1142. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1143. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1144. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1145. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1146. return 0;
  1147. }
  1148. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1149. {
  1150. struct list_head *element;
  1151. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1152. priv->frames_count);
  1153. while (!list_empty(&priv->free_frames)) {
  1154. element = priv->free_frames.next;
  1155. list_del(element);
  1156. kfree(list_entry(element, struct iwl3945_frame, list));
  1157. priv->frames_count--;
  1158. }
  1159. if (priv->frames_count) {
  1160. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1161. priv->frames_count);
  1162. priv->frames_count = 0;
  1163. }
  1164. }
  1165. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1166. {
  1167. struct iwl3945_frame *frame;
  1168. struct list_head *element;
  1169. if (list_empty(&priv->free_frames)) {
  1170. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1171. if (!frame) {
  1172. IWL_ERROR("Could not allocate frame!\n");
  1173. return NULL;
  1174. }
  1175. priv->frames_count++;
  1176. return frame;
  1177. }
  1178. element = priv->free_frames.next;
  1179. list_del(element);
  1180. return list_entry(element, struct iwl3945_frame, list);
  1181. }
  1182. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1183. {
  1184. memset(frame, 0, sizeof(*frame));
  1185. list_add(&frame->list, &priv->free_frames);
  1186. }
  1187. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1188. struct ieee80211_hdr *hdr,
  1189. const u8 *dest, int left)
  1190. {
  1191. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1192. ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
  1193. (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
  1194. return 0;
  1195. if (priv->ibss_beacon->len > left)
  1196. return 0;
  1197. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1198. return priv->ibss_beacon->len;
  1199. }
  1200. static int iwl3945_rate_index_from_plcp(int plcp)
  1201. {
  1202. int i = 0;
  1203. for (i = 0; i < IWL_RATE_COUNT; i++)
  1204. if (iwl3945_rates[i].plcp == plcp)
  1205. return i;
  1206. return -1;
  1207. }
  1208. static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
  1209. {
  1210. u8 i;
  1211. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1212. i = iwl3945_rates[i].next_ieee) {
  1213. if (rate_mask & (1 << i))
  1214. return iwl3945_rates[i].plcp;
  1215. }
  1216. return IWL_RATE_INVALID;
  1217. }
  1218. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1219. {
  1220. struct iwl3945_frame *frame;
  1221. unsigned int frame_size;
  1222. int rc;
  1223. u8 rate;
  1224. frame = iwl3945_get_free_frame(priv);
  1225. if (!frame) {
  1226. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1227. "command.\n");
  1228. return -ENOMEM;
  1229. }
  1230. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1231. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
  1232. 0xFF0);
  1233. if (rate == IWL_INVALID_RATE)
  1234. rate = IWL_RATE_6M_PLCP;
  1235. } else {
  1236. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1237. if (rate == IWL_INVALID_RATE)
  1238. rate = IWL_RATE_1M_PLCP;
  1239. }
  1240. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1241. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1242. &frame->u.cmd[0]);
  1243. iwl3945_free_frame(priv, frame);
  1244. return rc;
  1245. }
  1246. /******************************************************************************
  1247. *
  1248. * EEPROM related functions
  1249. *
  1250. ******************************************************************************/
  1251. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1252. {
  1253. memcpy(mac, priv->eeprom.mac_address, 6);
  1254. }
  1255. /**
  1256. * iwl3945_eeprom_init - read EEPROM contents
  1257. *
  1258. * Load the EEPROM from adapter into priv->eeprom
  1259. *
  1260. * NOTE: This routine uses the non-debug IO access functions.
  1261. */
  1262. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1263. {
  1264. u16 *e = (u16 *)&priv->eeprom;
  1265. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1266. u32 r;
  1267. int sz = sizeof(priv->eeprom);
  1268. int rc;
  1269. int i;
  1270. u16 addr;
  1271. /* The EEPROM structure has several padding buffers within it
  1272. * and when adding new EEPROM maps is subject to programmer errors
  1273. * which may be very difficult to identify without explicitly
  1274. * checking the resulting size of the eeprom map. */
  1275. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1276. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1277. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
  1278. return -ENOENT;
  1279. }
  1280. rc = iwl3945_eeprom_acquire_semaphore(priv);
  1281. if (rc < 0) {
  1282. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1283. return -ENOENT;
  1284. }
  1285. /* eeprom is an array of 16bit values */
  1286. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1287. _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
  1288. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1289. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1290. i += IWL_EEPROM_ACCESS_DELAY) {
  1291. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1292. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1293. break;
  1294. udelay(IWL_EEPROM_ACCESS_DELAY);
  1295. }
  1296. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1297. IWL_ERROR("Time out reading EEPROM[%d]", addr);
  1298. return -ETIMEDOUT;
  1299. }
  1300. e[addr / 2] = le16_to_cpu(r >> 16);
  1301. }
  1302. return 0;
  1303. }
  1304. /******************************************************************************
  1305. *
  1306. * Misc. internal state and helper functions
  1307. *
  1308. ******************************************************************************/
  1309. #ifdef CONFIG_IWL3945_DEBUG
  1310. /**
  1311. * iwl3945_report_frame - dump frame to syslog during debug sessions
  1312. *
  1313. * You may hack this function to show different aspects of received frames,
  1314. * including selective frame dumps.
  1315. * group100 parameter selects whether to show 1 out of 100 good frames.
  1316. */
  1317. void iwl3945_report_frame(struct iwl3945_priv *priv,
  1318. struct iwl3945_rx_packet *pkt,
  1319. struct ieee80211_hdr *header, int group100)
  1320. {
  1321. u32 to_us;
  1322. u32 print_summary = 0;
  1323. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  1324. u32 hundred = 0;
  1325. u32 dataframe = 0;
  1326. u16 fc;
  1327. u16 seq_ctl;
  1328. u16 channel;
  1329. u16 phy_flags;
  1330. int rate_sym;
  1331. u16 length;
  1332. u16 status;
  1333. u16 bcn_tmr;
  1334. u32 tsf_low;
  1335. u64 tsf;
  1336. u8 rssi;
  1337. u8 agc;
  1338. u16 sig_avg;
  1339. u16 noise_diff;
  1340. struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  1341. struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  1342. struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
  1343. u8 *data = IWL_RX_DATA(pkt);
  1344. /* MAC header */
  1345. fc = le16_to_cpu(header->frame_control);
  1346. seq_ctl = le16_to_cpu(header->seq_ctrl);
  1347. /* metadata */
  1348. channel = le16_to_cpu(rx_hdr->channel);
  1349. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  1350. rate_sym = rx_hdr->rate;
  1351. length = le16_to_cpu(rx_hdr->len);
  1352. /* end-of-frame status and timestamp */
  1353. status = le32_to_cpu(rx_end->status);
  1354. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  1355. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  1356. tsf = le64_to_cpu(rx_end->timestamp);
  1357. /* signal statistics */
  1358. rssi = rx_stats->rssi;
  1359. agc = rx_stats->agc;
  1360. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  1361. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  1362. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  1363. /* if data frame is to us and all is good,
  1364. * (optionally) print summary for only 1 out of every 100 */
  1365. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  1366. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  1367. dataframe = 1;
  1368. if (!group100)
  1369. print_summary = 1; /* print each frame */
  1370. else if (priv->framecnt_to_us < 100) {
  1371. priv->framecnt_to_us++;
  1372. print_summary = 0;
  1373. } else {
  1374. priv->framecnt_to_us = 0;
  1375. print_summary = 1;
  1376. hundred = 1;
  1377. }
  1378. } else {
  1379. /* print summary for all other frames */
  1380. print_summary = 1;
  1381. }
  1382. if (print_summary) {
  1383. char *title;
  1384. u32 rate;
  1385. if (hundred)
  1386. title = "100Frames";
  1387. else if (fc & IEEE80211_FCTL_RETRY)
  1388. title = "Retry";
  1389. else if (ieee80211_is_assoc_response(fc))
  1390. title = "AscRsp";
  1391. else if (ieee80211_is_reassoc_response(fc))
  1392. title = "RasRsp";
  1393. else if (ieee80211_is_probe_response(fc)) {
  1394. title = "PrbRsp";
  1395. print_dump = 1; /* dump frame contents */
  1396. } else if (ieee80211_is_beacon(fc)) {
  1397. title = "Beacon";
  1398. print_dump = 1; /* dump frame contents */
  1399. } else if (ieee80211_is_atim(fc))
  1400. title = "ATIM";
  1401. else if (ieee80211_is_auth(fc))
  1402. title = "Auth";
  1403. else if (ieee80211_is_deauth(fc))
  1404. title = "DeAuth";
  1405. else if (ieee80211_is_disassoc(fc))
  1406. title = "DisAssoc";
  1407. else
  1408. title = "Frame";
  1409. rate = iwl3945_rate_index_from_plcp(rate_sym);
  1410. if (rate == -1)
  1411. rate = 0;
  1412. else
  1413. rate = iwl3945_rates[rate].ieee / 2;
  1414. /* print frame summary.
  1415. * MAC addresses show just the last byte (for brevity),
  1416. * but you can hack it to show more, if you'd like to. */
  1417. if (dataframe)
  1418. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  1419. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  1420. title, fc, header->addr1[5],
  1421. length, rssi, channel, rate);
  1422. else {
  1423. /* src/dst addresses assume managed mode */
  1424. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  1425. "src=0x%02x, rssi=%u, tim=%lu usec, "
  1426. "phy=0x%02x, chnl=%d\n",
  1427. title, fc, header->addr1[5],
  1428. header->addr3[5], rssi,
  1429. tsf_low - priv->scan_start_tsf,
  1430. phy_flags, channel);
  1431. }
  1432. }
  1433. if (print_dump)
  1434. iwl3945_print_hex_dump(IWL_DL_RX, data, length);
  1435. }
  1436. #endif
  1437. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1438. {
  1439. if (priv->hw_setting.shared_virt)
  1440. pci_free_consistent(priv->pci_dev,
  1441. sizeof(struct iwl3945_shared),
  1442. priv->hw_setting.shared_virt,
  1443. priv->hw_setting.shared_phys);
  1444. }
  1445. /**
  1446. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1447. *
  1448. * return : set the bit for each supported rate insert in ie
  1449. */
  1450. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1451. u16 basic_rate, int *left)
  1452. {
  1453. u16 ret_rates = 0, bit;
  1454. int i;
  1455. u8 *cnt = ie;
  1456. u8 *rates = ie + 1;
  1457. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1458. if (bit & supported_rate) {
  1459. ret_rates |= bit;
  1460. rates[*cnt] = iwl3945_rates[i].ieee |
  1461. ((bit & basic_rate) ? 0x80 : 0x00);
  1462. (*cnt)++;
  1463. (*left)--;
  1464. if ((*left <= 0) ||
  1465. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1466. break;
  1467. }
  1468. }
  1469. return ret_rates;
  1470. }
  1471. /**
  1472. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1473. */
  1474. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1475. struct ieee80211_mgmt *frame,
  1476. int left, int is_direct)
  1477. {
  1478. int len = 0;
  1479. u8 *pos = NULL;
  1480. u16 active_rates, ret_rates, cck_rates;
  1481. /* Make sure there is enough space for the probe request,
  1482. * two mandatory IEs and the data */
  1483. left -= 24;
  1484. if (left < 0)
  1485. return 0;
  1486. len += 24;
  1487. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1488. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1489. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1490. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1491. frame->seq_ctrl = 0;
  1492. /* fill in our indirect SSID IE */
  1493. /* ...next IE... */
  1494. left -= 2;
  1495. if (left < 0)
  1496. return 0;
  1497. len += 2;
  1498. pos = &(frame->u.probe_req.variable[0]);
  1499. *pos++ = WLAN_EID_SSID;
  1500. *pos++ = 0;
  1501. /* fill in our direct SSID IE... */
  1502. if (is_direct) {
  1503. /* ...next IE... */
  1504. left -= 2 + priv->essid_len;
  1505. if (left < 0)
  1506. return 0;
  1507. /* ... fill it in... */
  1508. *pos++ = WLAN_EID_SSID;
  1509. *pos++ = priv->essid_len;
  1510. memcpy(pos, priv->essid, priv->essid_len);
  1511. pos += priv->essid_len;
  1512. len += 2 + priv->essid_len;
  1513. }
  1514. /* fill in supported rate */
  1515. /* ...next IE... */
  1516. left -= 2;
  1517. if (left < 0)
  1518. return 0;
  1519. /* ... fill it in... */
  1520. *pos++ = WLAN_EID_SUPP_RATES;
  1521. *pos = 0;
  1522. priv->active_rate = priv->rates_mask;
  1523. active_rates = priv->active_rate;
  1524. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1525. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1526. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1527. priv->active_rate_basic, &left);
  1528. active_rates &= ~ret_rates;
  1529. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1530. priv->active_rate_basic, &left);
  1531. active_rates &= ~ret_rates;
  1532. len += 2 + *pos;
  1533. pos += (*pos) + 1;
  1534. if (active_rates == 0)
  1535. goto fill_end;
  1536. /* fill in supported extended rate */
  1537. /* ...next IE... */
  1538. left -= 2;
  1539. if (left < 0)
  1540. return 0;
  1541. /* ... fill it in... */
  1542. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1543. *pos = 0;
  1544. iwl3945_supported_rate_to_ie(pos, active_rates,
  1545. priv->active_rate_basic, &left);
  1546. if (*pos > 0)
  1547. len += 2 + *pos;
  1548. fill_end:
  1549. return (u16)len;
  1550. }
  1551. /*
  1552. * QoS support
  1553. */
  1554. #ifdef CONFIG_IWL3945_QOS
  1555. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1556. struct iwl3945_qosparam_cmd *qos)
  1557. {
  1558. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1559. sizeof(struct iwl3945_qosparam_cmd), qos);
  1560. }
  1561. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1562. {
  1563. u16 cw_min = 15;
  1564. u16 cw_max = 1023;
  1565. u8 aifs = 2;
  1566. u8 is_legacy = 0;
  1567. unsigned long flags;
  1568. int i;
  1569. spin_lock_irqsave(&priv->lock, flags);
  1570. priv->qos_data.qos_active = 0;
  1571. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
  1572. if (priv->qos_data.qos_enable)
  1573. priv->qos_data.qos_active = 1;
  1574. if (!(priv->active_rate & 0xfff0)) {
  1575. cw_min = 31;
  1576. is_legacy = 1;
  1577. }
  1578. } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1579. if (priv->qos_data.qos_enable)
  1580. priv->qos_data.qos_active = 1;
  1581. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1582. cw_min = 31;
  1583. is_legacy = 1;
  1584. }
  1585. if (priv->qos_data.qos_active)
  1586. aifs = 3;
  1587. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1588. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1589. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1590. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1591. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1592. if (priv->qos_data.qos_active) {
  1593. i = 1;
  1594. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1595. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1596. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1597. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1598. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1599. i = 2;
  1600. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1601. cpu_to_le16((cw_min + 1) / 2 - 1);
  1602. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1603. cpu_to_le16(cw_max);
  1604. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1605. if (is_legacy)
  1606. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1607. cpu_to_le16(6016);
  1608. else
  1609. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1610. cpu_to_le16(3008);
  1611. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1612. i = 3;
  1613. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1614. cpu_to_le16((cw_min + 1) / 4 - 1);
  1615. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1616. cpu_to_le16((cw_max + 1) / 2 - 1);
  1617. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1618. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1619. if (is_legacy)
  1620. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1621. cpu_to_le16(3264);
  1622. else
  1623. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1624. cpu_to_le16(1504);
  1625. } else {
  1626. for (i = 1; i < 4; i++) {
  1627. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1628. cpu_to_le16(cw_min);
  1629. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1630. cpu_to_le16(cw_max);
  1631. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1632. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1633. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1634. }
  1635. }
  1636. IWL_DEBUG_QOS("set QoS to default \n");
  1637. spin_unlock_irqrestore(&priv->lock, flags);
  1638. }
  1639. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1640. {
  1641. unsigned long flags;
  1642. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1643. return;
  1644. if (!priv->qos_data.qos_enable)
  1645. return;
  1646. spin_lock_irqsave(&priv->lock, flags);
  1647. priv->qos_data.def_qos_parm.qos_flags = 0;
  1648. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1649. !priv->qos_data.qos_cap.q_AP.txop_request)
  1650. priv->qos_data.def_qos_parm.qos_flags |=
  1651. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1652. if (priv->qos_data.qos_active)
  1653. priv->qos_data.def_qos_parm.qos_flags |=
  1654. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1655. spin_unlock_irqrestore(&priv->lock, flags);
  1656. if (force || iwl3945_is_associated(priv)) {
  1657. IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
  1658. priv->qos_data.qos_active);
  1659. iwl3945_send_qos_params_command(priv,
  1660. &(priv->qos_data.def_qos_parm));
  1661. }
  1662. }
  1663. #endif /* CONFIG_IWL3945_QOS */
  1664. /*
  1665. * Power management (not Tx power!) functions
  1666. */
  1667. #define MSEC_TO_USEC 1024
  1668. #define NOSLP __constant_cpu_to_le32(0)
  1669. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1670. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1671. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1672. __constant_cpu_to_le32(X1), \
  1673. __constant_cpu_to_le32(X2), \
  1674. __constant_cpu_to_le32(X3), \
  1675. __constant_cpu_to_le32(X4)}
  1676. /* default power management (not Tx power) table values */
  1677. /* for tim 0-10 */
  1678. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1679. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1680. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1681. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1682. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1683. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1684. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1685. };
  1686. /* for tim > 10 */
  1687. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1688. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1689. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1690. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1691. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1692. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1693. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1694. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1695. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1696. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1697. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1698. };
  1699. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1700. {
  1701. int rc = 0, i;
  1702. struct iwl3945_power_mgr *pow_data;
  1703. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1704. u16 pci_pm;
  1705. IWL_DEBUG_POWER("Initialize power \n");
  1706. pow_data = &(priv->power_data);
  1707. memset(pow_data, 0, sizeof(*pow_data));
  1708. pow_data->active_index = IWL_POWER_RANGE_0;
  1709. pow_data->dtim_val = 0xffff;
  1710. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1711. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1712. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1713. if (rc != 0)
  1714. return 0;
  1715. else {
  1716. struct iwl3945_powertable_cmd *cmd;
  1717. IWL_DEBUG_POWER("adjust power command flags\n");
  1718. for (i = 0; i < IWL_POWER_AC; i++) {
  1719. cmd = &pow_data->pwr_range_0[i].cmd;
  1720. if (pci_pm & 0x1)
  1721. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1722. else
  1723. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1724. }
  1725. }
  1726. return rc;
  1727. }
  1728. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1729. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1730. {
  1731. int rc = 0, i;
  1732. u8 skip;
  1733. u32 max_sleep = 0;
  1734. struct iwl3945_power_vec_entry *range;
  1735. u8 period = 0;
  1736. struct iwl3945_power_mgr *pow_data;
  1737. if (mode > IWL_POWER_INDEX_5) {
  1738. IWL_DEBUG_POWER("Error invalid power mode \n");
  1739. return -1;
  1740. }
  1741. pow_data = &(priv->power_data);
  1742. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1743. range = &pow_data->pwr_range_0[0];
  1744. else
  1745. range = &pow_data->pwr_range_1[1];
  1746. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1747. #ifdef IWL_MAC80211_DISABLE
  1748. if (priv->assoc_network != NULL) {
  1749. unsigned long flags;
  1750. period = priv->assoc_network->tim.tim_period;
  1751. }
  1752. #endif /*IWL_MAC80211_DISABLE */
  1753. skip = range[mode].no_dtim;
  1754. if (period == 0) {
  1755. period = 1;
  1756. skip = 0;
  1757. }
  1758. if (skip == 0) {
  1759. max_sleep = period;
  1760. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1761. } else {
  1762. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1763. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1764. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1765. }
  1766. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1767. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1768. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1769. }
  1770. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1771. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1772. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1773. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1774. le32_to_cpu(cmd->sleep_interval[0]),
  1775. le32_to_cpu(cmd->sleep_interval[1]),
  1776. le32_to_cpu(cmd->sleep_interval[2]),
  1777. le32_to_cpu(cmd->sleep_interval[3]),
  1778. le32_to_cpu(cmd->sleep_interval[4]));
  1779. return rc;
  1780. }
  1781. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1782. {
  1783. u32 uninitialized_var(final_mode);
  1784. int rc;
  1785. struct iwl3945_powertable_cmd cmd;
  1786. /* If on battery, set to 3,
  1787. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1788. * else user level */
  1789. switch (mode) {
  1790. case IWL_POWER_BATTERY:
  1791. final_mode = IWL_POWER_INDEX_3;
  1792. break;
  1793. case IWL_POWER_AC:
  1794. final_mode = IWL_POWER_MODE_CAM;
  1795. break;
  1796. default:
  1797. final_mode = mode;
  1798. break;
  1799. }
  1800. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1801. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1802. if (final_mode == IWL_POWER_MODE_CAM)
  1803. clear_bit(STATUS_POWER_PMI, &priv->status);
  1804. else
  1805. set_bit(STATUS_POWER_PMI, &priv->status);
  1806. return rc;
  1807. }
  1808. int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  1809. {
  1810. /* Filter incoming packets to determine if they are targeted toward
  1811. * this network, discarding packets coming from ourselves */
  1812. switch (priv->iw_mode) {
  1813. case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
  1814. /* packets from our adapter are dropped (echo) */
  1815. if (!compare_ether_addr(header->addr2, priv->mac_addr))
  1816. return 0;
  1817. /* {broad,multi}cast packets to our IBSS go through */
  1818. if (is_multicast_ether_addr(header->addr1))
  1819. return !compare_ether_addr(header->addr3, priv->bssid);
  1820. /* packets to our adapter go through */
  1821. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1822. case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
  1823. /* packets from our adapter are dropped (echo) */
  1824. if (!compare_ether_addr(header->addr3, priv->mac_addr))
  1825. return 0;
  1826. /* {broad,multi}cast packets to our BSS go through */
  1827. if (is_multicast_ether_addr(header->addr1))
  1828. return !compare_ether_addr(header->addr2, priv->bssid);
  1829. /* packets to our adapter go through */
  1830. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1831. }
  1832. return 1;
  1833. }
  1834. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  1835. static const char *iwl3945_get_tx_fail_reason(u32 status)
  1836. {
  1837. switch (status & TX_STATUS_MSK) {
  1838. case TX_STATUS_SUCCESS:
  1839. return "SUCCESS";
  1840. TX_STATUS_ENTRY(SHORT_LIMIT);
  1841. TX_STATUS_ENTRY(LONG_LIMIT);
  1842. TX_STATUS_ENTRY(FIFO_UNDERRUN);
  1843. TX_STATUS_ENTRY(MGMNT_ABORT);
  1844. TX_STATUS_ENTRY(NEXT_FRAG);
  1845. TX_STATUS_ENTRY(LIFE_EXPIRE);
  1846. TX_STATUS_ENTRY(DEST_PS);
  1847. TX_STATUS_ENTRY(ABORTED);
  1848. TX_STATUS_ENTRY(BT_RETRY);
  1849. TX_STATUS_ENTRY(STA_INVALID);
  1850. TX_STATUS_ENTRY(FRAG_DROPPED);
  1851. TX_STATUS_ENTRY(TID_DISABLE);
  1852. TX_STATUS_ENTRY(FRAME_FLUSHED);
  1853. TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
  1854. TX_STATUS_ENTRY(TX_LOCKED);
  1855. TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
  1856. }
  1857. return "UNKNOWN";
  1858. }
  1859. /**
  1860. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1861. *
  1862. * NOTE: priv->mutex is not required before calling this function
  1863. */
  1864. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1865. {
  1866. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1867. clear_bit(STATUS_SCANNING, &priv->status);
  1868. return 0;
  1869. }
  1870. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1871. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1872. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1873. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1874. queue_work(priv->workqueue, &priv->abort_scan);
  1875. } else
  1876. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1877. return test_bit(STATUS_SCANNING, &priv->status);
  1878. }
  1879. return 0;
  1880. }
  1881. /**
  1882. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1883. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1884. *
  1885. * NOTE: priv->mutex must be held before calling this function
  1886. */
  1887. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1888. {
  1889. unsigned long now = jiffies;
  1890. int ret;
  1891. ret = iwl3945_scan_cancel(priv);
  1892. if (ret && ms) {
  1893. mutex_unlock(&priv->mutex);
  1894. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1895. test_bit(STATUS_SCANNING, &priv->status))
  1896. msleep(1);
  1897. mutex_lock(&priv->mutex);
  1898. return test_bit(STATUS_SCANNING, &priv->status);
  1899. }
  1900. return ret;
  1901. }
  1902. static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
  1903. {
  1904. /* Reset ieee stats */
  1905. /* We don't reset the net_device_stats (ieee->stats) on
  1906. * re-association */
  1907. priv->last_seq_num = -1;
  1908. priv->last_frag_num = -1;
  1909. priv->last_packet_time = 0;
  1910. iwl3945_scan_cancel(priv);
  1911. }
  1912. #define MAX_UCODE_BEACON_INTERVAL 1024
  1913. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1914. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1915. {
  1916. u16 new_val = 0;
  1917. u16 beacon_factor = 0;
  1918. beacon_factor =
  1919. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1920. / MAX_UCODE_BEACON_INTERVAL;
  1921. new_val = beacon_val / beacon_factor;
  1922. return cpu_to_le16(new_val);
  1923. }
  1924. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1925. {
  1926. u64 interval_tm_unit;
  1927. u64 tsf, result;
  1928. unsigned long flags;
  1929. struct ieee80211_conf *conf = NULL;
  1930. u16 beacon_int = 0;
  1931. conf = ieee80211_get_hw_conf(priv->hw);
  1932. spin_lock_irqsave(&priv->lock, flags);
  1933. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1934. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1935. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1936. tsf = priv->timestamp1;
  1937. tsf = ((tsf << 32) | priv->timestamp0);
  1938. beacon_int = priv->beacon_int;
  1939. spin_unlock_irqrestore(&priv->lock, flags);
  1940. if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
  1941. if (beacon_int == 0) {
  1942. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1943. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1944. } else {
  1945. priv->rxon_timing.beacon_interval =
  1946. cpu_to_le16(beacon_int);
  1947. priv->rxon_timing.beacon_interval =
  1948. iwl3945_adjust_beacon_interval(
  1949. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1950. }
  1951. priv->rxon_timing.atim_window = 0;
  1952. } else {
  1953. priv->rxon_timing.beacon_interval =
  1954. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1955. /* TODO: we need to get atim_window from upper stack
  1956. * for now we set to 0 */
  1957. priv->rxon_timing.atim_window = 0;
  1958. }
  1959. interval_tm_unit =
  1960. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1961. result = do_div(tsf, interval_tm_unit);
  1962. priv->rxon_timing.beacon_init_val =
  1963. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1964. IWL_DEBUG_ASSOC
  1965. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1966. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1967. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1968. le16_to_cpu(priv->rxon_timing.atim_window));
  1969. }
  1970. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1971. {
  1972. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1973. IWL_ERROR("APs don't scan.\n");
  1974. return 0;
  1975. }
  1976. if (!iwl3945_is_ready_rf(priv)) {
  1977. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1978. return -EIO;
  1979. }
  1980. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1981. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1982. return -EAGAIN;
  1983. }
  1984. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1985. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1986. "Queuing.\n");
  1987. return -EAGAIN;
  1988. }
  1989. IWL_DEBUG_INFO("Starting scan...\n");
  1990. priv->scan_bands = 2;
  1991. set_bit(STATUS_SCANNING, &priv->status);
  1992. priv->scan_start = jiffies;
  1993. priv->scan_pass_start = priv->scan_start;
  1994. queue_work(priv->workqueue, &priv->request_scan);
  1995. return 0;
  1996. }
  1997. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  1998. {
  1999. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  2000. if (hw_decrypt)
  2001. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  2002. else
  2003. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  2004. return 0;
  2005. }
  2006. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv, u8 phymode)
  2007. {
  2008. if (phymode == MODE_IEEE80211A) {
  2009. priv->staging_rxon.flags &=
  2010. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  2011. | RXON_FLG_CCK_MSK);
  2012. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2013. } else {
  2014. /* Copied from iwl3945_bg_post_associate() */
  2015. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2016. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2017. else
  2018. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2019. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  2020. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2021. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  2022. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  2023. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  2024. }
  2025. }
  2026. /*
  2027. * initialize rxon structure with default values from eeprom
  2028. */
  2029. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
  2030. {
  2031. const struct iwl3945_channel_info *ch_info;
  2032. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  2033. switch (priv->iw_mode) {
  2034. case IEEE80211_IF_TYPE_AP:
  2035. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  2036. break;
  2037. case IEEE80211_IF_TYPE_STA:
  2038. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  2039. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  2040. break;
  2041. case IEEE80211_IF_TYPE_IBSS:
  2042. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  2043. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  2044. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  2045. RXON_FILTER_ACCEPT_GRP_MSK;
  2046. break;
  2047. case IEEE80211_IF_TYPE_MNTR:
  2048. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  2049. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  2050. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  2051. break;
  2052. }
  2053. #if 0
  2054. /* TODO: Figure out when short_preamble would be set and cache from
  2055. * that */
  2056. if (!hw_to_local(priv->hw)->short_preamble)
  2057. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2058. else
  2059. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2060. #endif
  2061. ch_info = iwl3945_get_channel_info(priv, priv->phymode,
  2062. le16_to_cpu(priv->staging_rxon.channel));
  2063. if (!ch_info)
  2064. ch_info = &priv->channel_info[0];
  2065. /*
  2066. * in some case A channels are all non IBSS
  2067. * in this case force B/G channel
  2068. */
  2069. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  2070. !(is_channel_ibss(ch_info)))
  2071. ch_info = &priv->channel_info[0];
  2072. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  2073. if (is_channel_a_band(ch_info))
  2074. priv->phymode = MODE_IEEE80211A;
  2075. else
  2076. priv->phymode = MODE_IEEE80211G;
  2077. iwl3945_set_flags_for_phymode(priv, priv->phymode);
  2078. priv->staging_rxon.ofdm_basic_rates =
  2079. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2080. priv->staging_rxon.cck_basic_rates =
  2081. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2082. }
  2083. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  2084. {
  2085. if (!iwl3945_is_ready_rf(priv))
  2086. return -EAGAIN;
  2087. if (mode == IEEE80211_IF_TYPE_IBSS) {
  2088. const struct iwl3945_channel_info *ch_info;
  2089. ch_info = iwl3945_get_channel_info(priv,
  2090. priv->phymode,
  2091. le16_to_cpu(priv->staging_rxon.channel));
  2092. if (!ch_info || !is_channel_ibss(ch_info)) {
  2093. IWL_ERROR("channel %d not IBSS channel\n",
  2094. le16_to_cpu(priv->staging_rxon.channel));
  2095. return -EINVAL;
  2096. }
  2097. }
  2098. cancel_delayed_work(&priv->scan_check);
  2099. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  2100. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  2101. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  2102. return -EAGAIN;
  2103. }
  2104. priv->iw_mode = mode;
  2105. iwl3945_connection_init_rx_config(priv);
  2106. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2107. iwl3945_clear_stations_table(priv);
  2108. iwl3945_commit_rxon(priv);
  2109. return 0;
  2110. }
  2111. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  2112. struct ieee80211_tx_control *ctl,
  2113. struct iwl3945_cmd *cmd,
  2114. struct sk_buff *skb_frag,
  2115. int last_frag)
  2116. {
  2117. struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
  2118. switch (keyinfo->alg) {
  2119. case ALG_CCMP:
  2120. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  2121. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  2122. IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
  2123. break;
  2124. case ALG_TKIP:
  2125. #if 0
  2126. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  2127. if (last_frag)
  2128. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  2129. 8);
  2130. else
  2131. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  2132. #endif
  2133. break;
  2134. case ALG_WEP:
  2135. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  2136. (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  2137. if (keyinfo->keylen == 13)
  2138. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  2139. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  2140. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  2141. "with key %d\n", ctl->key_idx);
  2142. break;
  2143. default:
  2144. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  2145. break;
  2146. }
  2147. }
  2148. /*
  2149. * handle build REPLY_TX command notification.
  2150. */
  2151. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  2152. struct iwl3945_cmd *cmd,
  2153. struct ieee80211_tx_control *ctrl,
  2154. struct ieee80211_hdr *hdr,
  2155. int is_unicast, u8 std_id)
  2156. {
  2157. __le16 *qc;
  2158. u16 fc = le16_to_cpu(hdr->frame_control);
  2159. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  2160. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2161. if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
  2162. tx_flags |= TX_CMD_FLG_ACK_MSK;
  2163. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
  2164. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2165. if (ieee80211_is_probe_response(fc) &&
  2166. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  2167. tx_flags |= TX_CMD_FLG_TSF_MSK;
  2168. } else {
  2169. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  2170. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2171. }
  2172. cmd->cmd.tx.sta_id = std_id;
  2173. if (ieee80211_get_morefrag(hdr))
  2174. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  2175. qc = ieee80211_get_qos_ctrl(hdr);
  2176. if (qc) {
  2177. cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
  2178. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  2179. } else
  2180. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2181. if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
  2182. tx_flags |= TX_CMD_FLG_RTS_MSK;
  2183. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  2184. } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
  2185. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2186. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2187. }
  2188. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  2189. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  2190. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  2191. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
  2192. if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
  2193. (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
  2194. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  2195. else
  2196. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  2197. } else
  2198. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  2199. cmd->cmd.tx.driver_txop = 0;
  2200. cmd->cmd.tx.tx_flags = tx_flags;
  2201. cmd->cmd.tx.next_frame_len = 0;
  2202. }
  2203. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2204. {
  2205. int sta_id;
  2206. u16 fc = le16_to_cpu(hdr->frame_control);
  2207. /* If this frame is broadcast or not data then use the broadcast
  2208. * station id */
  2209. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2210. is_multicast_ether_addr(hdr->addr1))
  2211. return priv->hw_setting.bcast_sta_id;
  2212. switch (priv->iw_mode) {
  2213. /* If this frame is part of a BSS network (we're a station), then
  2214. * we use the AP's station id */
  2215. case IEEE80211_IF_TYPE_STA:
  2216. return IWL_AP_ID;
  2217. /* If we are an AP, then find the station, or use BCAST */
  2218. case IEEE80211_IF_TYPE_AP:
  2219. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2220. if (sta_id != IWL_INVALID_STATION)
  2221. return sta_id;
  2222. return priv->hw_setting.bcast_sta_id;
  2223. /* If this frame is part of a IBSS network, then we use the
  2224. * target specific station id */
  2225. case IEEE80211_IF_TYPE_IBSS: {
  2226. DECLARE_MAC_BUF(mac);
  2227. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2228. if (sta_id != IWL_INVALID_STATION)
  2229. return sta_id;
  2230. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2231. if (sta_id != IWL_INVALID_STATION)
  2232. return sta_id;
  2233. IWL_DEBUG_DROP("Station %s not in station map. "
  2234. "Defaulting to broadcast...\n",
  2235. print_mac(mac, hdr->addr1));
  2236. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2237. return priv->hw_setting.bcast_sta_id;
  2238. }
  2239. default:
  2240. IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
  2241. return priv->hw_setting.bcast_sta_id;
  2242. }
  2243. }
  2244. /*
  2245. * start REPLY_TX command process
  2246. */
  2247. static int iwl3945_tx_skb(struct iwl3945_priv *priv,
  2248. struct sk_buff *skb, struct ieee80211_tx_control *ctl)
  2249. {
  2250. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2251. struct iwl3945_tfd_frame *tfd;
  2252. u32 *control_flags;
  2253. int txq_id = ctl->queue;
  2254. struct iwl3945_tx_queue *txq = NULL;
  2255. struct iwl3945_queue *q = NULL;
  2256. dma_addr_t phys_addr;
  2257. dma_addr_t txcmd_phys;
  2258. struct iwl3945_cmd *out_cmd = NULL;
  2259. u16 len, idx, len_org;
  2260. u8 id, hdr_len, unicast;
  2261. u8 sta_id;
  2262. u16 seq_number = 0;
  2263. u16 fc;
  2264. __le16 *qc;
  2265. u8 wait_write_ptr = 0;
  2266. unsigned long flags;
  2267. int rc;
  2268. spin_lock_irqsave(&priv->lock, flags);
  2269. if (iwl3945_is_rfkill(priv)) {
  2270. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2271. goto drop_unlock;
  2272. }
  2273. if (!priv->interface_id) {
  2274. IWL_DEBUG_DROP("Dropping - !priv->interface_id\n");
  2275. goto drop_unlock;
  2276. }
  2277. if ((ctl->tx_rate & 0xFF) == IWL_INVALID_RATE) {
  2278. IWL_ERROR("ERROR: No TX rate available.\n");
  2279. goto drop_unlock;
  2280. }
  2281. unicast = !is_multicast_ether_addr(hdr->addr1);
  2282. id = 0;
  2283. fc = le16_to_cpu(hdr->frame_control);
  2284. #ifdef CONFIG_IWL3945_DEBUG
  2285. if (ieee80211_is_auth(fc))
  2286. IWL_DEBUG_TX("Sending AUTH frame\n");
  2287. else if (ieee80211_is_assoc_request(fc))
  2288. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2289. else if (ieee80211_is_reassoc_request(fc))
  2290. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2291. #endif
  2292. if (!iwl3945_is_associated(priv) &&
  2293. ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
  2294. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2295. goto drop_unlock;
  2296. }
  2297. spin_unlock_irqrestore(&priv->lock, flags);
  2298. hdr_len = ieee80211_get_hdrlen(fc);
  2299. sta_id = iwl3945_get_sta_id(priv, hdr);
  2300. if (sta_id == IWL_INVALID_STATION) {
  2301. DECLARE_MAC_BUF(mac);
  2302. IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
  2303. print_mac(mac, hdr->addr1));
  2304. goto drop;
  2305. }
  2306. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2307. qc = ieee80211_get_qos_ctrl(hdr);
  2308. if (qc) {
  2309. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2310. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2311. IEEE80211_SCTL_SEQ;
  2312. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2313. (hdr->seq_ctrl &
  2314. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2315. seq_number += 0x10;
  2316. }
  2317. txq = &priv->txq[txq_id];
  2318. q = &txq->q;
  2319. spin_lock_irqsave(&priv->lock, flags);
  2320. tfd = &txq->bd[q->write_ptr];
  2321. memset(tfd, 0, sizeof(*tfd));
  2322. control_flags = (u32 *) tfd;
  2323. idx = get_cmd_index(q, q->write_ptr, 0);
  2324. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2325. txq->txb[q->write_ptr].skb[0] = skb;
  2326. memcpy(&(txq->txb[q->write_ptr].status.control),
  2327. ctl, sizeof(struct ieee80211_tx_control));
  2328. out_cmd = &txq->cmd[idx];
  2329. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2330. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2331. out_cmd->hdr.cmd = REPLY_TX;
  2332. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2333. INDEX_TO_SEQ(q->write_ptr)));
  2334. /* copy frags header */
  2335. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2336. /* hdr = (struct ieee80211_hdr *)out_cmd->cmd.tx.hdr; */
  2337. len = priv->hw_setting.tx_cmd_len +
  2338. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2339. len_org = len;
  2340. len = (len + 3) & ~3;
  2341. if (len_org != len)
  2342. len_org = 1;
  2343. else
  2344. len_org = 0;
  2345. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2346. offsetof(struct iwl3945_cmd, hdr);
  2347. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2348. if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
  2349. iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
  2350. /* 802.11 null functions have no payload... */
  2351. len = skb->len - hdr_len;
  2352. if (len) {
  2353. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2354. len, PCI_DMA_TODEVICE);
  2355. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2356. }
  2357. /* If there is no payload, then only one TFD is used */
  2358. if (!len)
  2359. *control_flags = TFD_CTL_COUNT_SET(1);
  2360. else
  2361. *control_flags = TFD_CTL_COUNT_SET(2) |
  2362. TFD_CTL_PAD_SET(U32_PAD(len));
  2363. len = (u16)skb->len;
  2364. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2365. /* TODO need this for burst mode later on */
  2366. iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
  2367. /* set is_hcca to 0; it probably will never be implemented */
  2368. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
  2369. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2370. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2371. if (!ieee80211_get_morefrag(hdr)) {
  2372. txq->need_update = 1;
  2373. if (qc) {
  2374. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2375. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2376. }
  2377. } else {
  2378. wait_write_ptr = 1;
  2379. txq->need_update = 0;
  2380. }
  2381. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2382. sizeof(out_cmd->cmd.tx));
  2383. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2384. ieee80211_get_hdrlen(fc));
  2385. q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
  2386. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2387. spin_unlock_irqrestore(&priv->lock, flags);
  2388. if (rc)
  2389. return rc;
  2390. if ((iwl3945_queue_space(q) < q->high_mark)
  2391. && priv->mac80211_registered) {
  2392. if (wait_write_ptr) {
  2393. spin_lock_irqsave(&priv->lock, flags);
  2394. txq->need_update = 1;
  2395. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2396. spin_unlock_irqrestore(&priv->lock, flags);
  2397. }
  2398. ieee80211_stop_queue(priv->hw, ctl->queue);
  2399. }
  2400. return 0;
  2401. drop_unlock:
  2402. spin_unlock_irqrestore(&priv->lock, flags);
  2403. drop:
  2404. return -1;
  2405. }
  2406. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2407. {
  2408. const struct ieee80211_hw_mode *hw = NULL;
  2409. struct ieee80211_rate *rate;
  2410. int i;
  2411. hw = iwl3945_get_hw_mode(priv, priv->phymode);
  2412. if (!hw) {
  2413. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2414. return;
  2415. }
  2416. priv->active_rate = 0;
  2417. priv->active_rate_basic = 0;
  2418. IWL_DEBUG_RATE("Setting rates for 802.11%c\n",
  2419. hw->mode == MODE_IEEE80211A ?
  2420. 'a' : ((hw->mode == MODE_IEEE80211B) ? 'b' : 'g'));
  2421. for (i = 0; i < hw->num_rates; i++) {
  2422. rate = &(hw->rates[i]);
  2423. if ((rate->val < IWL_RATE_COUNT) &&
  2424. (rate->flags & IEEE80211_RATE_SUPPORTED)) {
  2425. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)%s\n",
  2426. rate->val, iwl3945_rates[rate->val].plcp,
  2427. (rate->flags & IEEE80211_RATE_BASIC) ?
  2428. "*" : "");
  2429. priv->active_rate |= (1 << rate->val);
  2430. if (rate->flags & IEEE80211_RATE_BASIC)
  2431. priv->active_rate_basic |= (1 << rate->val);
  2432. } else
  2433. IWL_DEBUG_RATE("Not adding rate %d (plcp %d)\n",
  2434. rate->val, iwl3945_rates[rate->val].plcp);
  2435. }
  2436. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2437. priv->active_rate, priv->active_rate_basic);
  2438. /*
  2439. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2440. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2441. * OFDM
  2442. */
  2443. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2444. priv->staging_rxon.cck_basic_rates =
  2445. ((priv->active_rate_basic &
  2446. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2447. else
  2448. priv->staging_rxon.cck_basic_rates =
  2449. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2450. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2451. priv->staging_rxon.ofdm_basic_rates =
  2452. ((priv->active_rate_basic &
  2453. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2454. IWL_FIRST_OFDM_RATE) & 0xFF;
  2455. else
  2456. priv->staging_rxon.ofdm_basic_rates =
  2457. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2458. }
  2459. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2460. {
  2461. unsigned long flags;
  2462. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2463. return;
  2464. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2465. disable_radio ? "OFF" : "ON");
  2466. if (disable_radio) {
  2467. iwl3945_scan_cancel(priv);
  2468. /* FIXME: This is a workaround for AP */
  2469. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  2470. spin_lock_irqsave(&priv->lock, flags);
  2471. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2472. CSR_UCODE_SW_BIT_RFKILL);
  2473. spin_unlock_irqrestore(&priv->lock, flags);
  2474. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2475. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2476. }
  2477. return;
  2478. }
  2479. spin_lock_irqsave(&priv->lock, flags);
  2480. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2481. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2482. spin_unlock_irqrestore(&priv->lock, flags);
  2483. /* wake up ucode */
  2484. msleep(10);
  2485. spin_lock_irqsave(&priv->lock, flags);
  2486. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2487. if (!iwl3945_grab_nic_access(priv))
  2488. iwl3945_release_nic_access(priv);
  2489. spin_unlock_irqrestore(&priv->lock, flags);
  2490. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2491. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2492. "disabled by HW switch\n");
  2493. return;
  2494. }
  2495. queue_work(priv->workqueue, &priv->restart);
  2496. return;
  2497. }
  2498. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2499. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2500. {
  2501. u16 fc =
  2502. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2503. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2504. return;
  2505. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2506. return;
  2507. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2508. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2509. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2510. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2511. RX_RES_STATUS_BAD_ICV_MIC)
  2512. stats->flag |= RX_FLAG_MMIC_ERROR;
  2513. case RX_RES_STATUS_SEC_TYPE_WEP:
  2514. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2515. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2516. RX_RES_STATUS_DECRYPT_OK) {
  2517. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2518. stats->flag |= RX_FLAG_DECRYPTED;
  2519. }
  2520. break;
  2521. default:
  2522. break;
  2523. }
  2524. }
  2525. void iwl3945_handle_data_packet_monitor(struct iwl3945_priv *priv,
  2526. struct iwl3945_rx_mem_buffer *rxb,
  2527. void *data, short len,
  2528. struct ieee80211_rx_status *stats,
  2529. u16 phy_flags)
  2530. {
  2531. struct iwl3945_rt_rx_hdr *iwl3945_rt;
  2532. /* First cache any information we need before we overwrite
  2533. * the information provided in the skb from the hardware */
  2534. s8 signal = stats->ssi;
  2535. s8 noise = 0;
  2536. int rate = stats->rate;
  2537. u64 tsf = stats->mactime;
  2538. __le16 phy_flags_hw = cpu_to_le16(phy_flags);
  2539. /* We received data from the HW, so stop the watchdog */
  2540. if (len > IWL_RX_BUF_SIZE - sizeof(*iwl3945_rt)) {
  2541. IWL_DEBUG_DROP("Dropping too large packet in monitor\n");
  2542. return;
  2543. }
  2544. /* copy the frame data to write after where the radiotap header goes */
  2545. iwl3945_rt = (void *)rxb->skb->data;
  2546. memmove(iwl3945_rt->payload, data, len);
  2547. iwl3945_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
  2548. iwl3945_rt->rt_hdr.it_pad = 0; /* always good to zero */
  2549. /* total header + data */
  2550. iwl3945_rt->rt_hdr.it_len = cpu_to_le16(sizeof(*iwl3945_rt));
  2551. /* Set the size of the skb to the size of the frame */
  2552. skb_put(rxb->skb, sizeof(*iwl3945_rt) + len);
  2553. /* Big bitfield of all the fields we provide in radiotap */
  2554. iwl3945_rt->rt_hdr.it_present =
  2555. cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
  2556. (1 << IEEE80211_RADIOTAP_FLAGS) |
  2557. (1 << IEEE80211_RADIOTAP_RATE) |
  2558. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  2559. (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
  2560. (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
  2561. (1 << IEEE80211_RADIOTAP_ANTENNA));
  2562. /* Zero the flags, we'll add to them as we go */
  2563. iwl3945_rt->rt_flags = 0;
  2564. iwl3945_rt->rt_tsf = cpu_to_le64(tsf);
  2565. /* Convert to dBm */
  2566. iwl3945_rt->rt_dbmsignal = signal;
  2567. iwl3945_rt->rt_dbmnoise = noise;
  2568. /* Convert the channel frequency and set the flags */
  2569. iwl3945_rt->rt_channelMHz = cpu_to_le16(stats->freq);
  2570. if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
  2571. iwl3945_rt->rt_chbitmask =
  2572. cpu_to_le16((IEEE80211_CHAN_OFDM | IEEE80211_CHAN_5GHZ));
  2573. else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
  2574. iwl3945_rt->rt_chbitmask =
  2575. cpu_to_le16((IEEE80211_CHAN_CCK | IEEE80211_CHAN_2GHZ));
  2576. else /* 802.11g */
  2577. iwl3945_rt->rt_chbitmask =
  2578. cpu_to_le16((IEEE80211_CHAN_OFDM | IEEE80211_CHAN_2GHZ));
  2579. rate = iwl3945_rate_index_from_plcp(rate);
  2580. if (rate == -1)
  2581. iwl3945_rt->rt_rate = 0;
  2582. else
  2583. iwl3945_rt->rt_rate = iwl3945_rates[rate].ieee;
  2584. /* antenna number */
  2585. iwl3945_rt->rt_antenna =
  2586. le16_to_cpu(phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
  2587. /* set the preamble flag if we have it */
  2588. if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  2589. iwl3945_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
  2590. IWL_DEBUG_RX("Rx packet of %d bytes.\n", rxb->skb->len);
  2591. stats->flag |= RX_FLAG_RADIOTAP;
  2592. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  2593. rxb->skb = NULL;
  2594. }
  2595. #define IWL_PACKET_RETRY_TIME HZ
  2596. int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  2597. {
  2598. u16 sc = le16_to_cpu(header->seq_ctrl);
  2599. u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
  2600. u16 frag = sc & IEEE80211_SCTL_FRAG;
  2601. u16 *last_seq, *last_frag;
  2602. unsigned long *last_time;
  2603. switch (priv->iw_mode) {
  2604. case IEEE80211_IF_TYPE_IBSS:{
  2605. struct list_head *p;
  2606. struct iwl3945_ibss_seq *entry = NULL;
  2607. u8 *mac = header->addr2;
  2608. int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
  2609. __list_for_each(p, &priv->ibss_mac_hash[index]) {
  2610. entry = list_entry(p, struct iwl3945_ibss_seq, list);
  2611. if (!compare_ether_addr(entry->mac, mac))
  2612. break;
  2613. }
  2614. if (p == &priv->ibss_mac_hash[index]) {
  2615. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  2616. if (!entry) {
  2617. IWL_ERROR("Cannot malloc new mac entry\n");
  2618. return 0;
  2619. }
  2620. memcpy(entry->mac, mac, ETH_ALEN);
  2621. entry->seq_num = seq;
  2622. entry->frag_num = frag;
  2623. entry->packet_time = jiffies;
  2624. list_add(&entry->list, &priv->ibss_mac_hash[index]);
  2625. return 0;
  2626. }
  2627. last_seq = &entry->seq_num;
  2628. last_frag = &entry->frag_num;
  2629. last_time = &entry->packet_time;
  2630. break;
  2631. }
  2632. case IEEE80211_IF_TYPE_STA:
  2633. last_seq = &priv->last_seq_num;
  2634. last_frag = &priv->last_frag_num;
  2635. last_time = &priv->last_packet_time;
  2636. break;
  2637. default:
  2638. return 0;
  2639. }
  2640. if ((*last_seq == seq) &&
  2641. time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
  2642. if (*last_frag == frag)
  2643. goto drop;
  2644. if (*last_frag + 1 != frag)
  2645. /* out-of-order fragment */
  2646. goto drop;
  2647. } else
  2648. *last_seq = seq;
  2649. *last_frag = frag;
  2650. *last_time = jiffies;
  2651. return 0;
  2652. drop:
  2653. return 1;
  2654. }
  2655. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2656. #include "iwl-spectrum.h"
  2657. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2658. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2659. #define TIME_UNIT 1024
  2660. /*
  2661. * extended beacon time format
  2662. * time in usec will be changed into a 32-bit value in 8:24 format
  2663. * the high 1 byte is the beacon counts
  2664. * the lower 3 bytes is the time in usec within one beacon interval
  2665. */
  2666. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2667. {
  2668. u32 quot;
  2669. u32 rem;
  2670. u32 interval = beacon_interval * 1024;
  2671. if (!interval || !usec)
  2672. return 0;
  2673. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2674. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2675. return (quot << 24) + rem;
  2676. }
  2677. /* base is usually what we get from ucode with each received frame,
  2678. * the same as HW timer counter counting down
  2679. */
  2680. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2681. {
  2682. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2683. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2684. u32 interval = beacon_interval * TIME_UNIT;
  2685. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2686. (addon & BEACON_TIME_MASK_HIGH);
  2687. if (base_low > addon_low)
  2688. res += base_low - addon_low;
  2689. else if (base_low < addon_low) {
  2690. res += interval + base_low - addon_low;
  2691. res += (1 << 24);
  2692. } else
  2693. res += (1 << 24);
  2694. return cpu_to_le32(res);
  2695. }
  2696. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2697. struct ieee80211_measurement_params *params,
  2698. u8 type)
  2699. {
  2700. struct iwl3945_spectrum_cmd spectrum;
  2701. struct iwl3945_rx_packet *res;
  2702. struct iwl3945_host_cmd cmd = {
  2703. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2704. .data = (void *)&spectrum,
  2705. .meta.flags = CMD_WANT_SKB,
  2706. };
  2707. u32 add_time = le64_to_cpu(params->start_time);
  2708. int rc;
  2709. int spectrum_resp_status;
  2710. int duration = le16_to_cpu(params->duration);
  2711. if (iwl3945_is_associated(priv))
  2712. add_time =
  2713. iwl3945_usecs_to_beacons(
  2714. le64_to_cpu(params->start_time) - priv->last_tsf,
  2715. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2716. memset(&spectrum, 0, sizeof(spectrum));
  2717. spectrum.channel_count = cpu_to_le16(1);
  2718. spectrum.flags =
  2719. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2720. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2721. cmd.len = sizeof(spectrum);
  2722. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2723. if (iwl3945_is_associated(priv))
  2724. spectrum.start_time =
  2725. iwl3945_add_beacon_time(priv->last_beacon_time,
  2726. add_time,
  2727. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2728. else
  2729. spectrum.start_time = 0;
  2730. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2731. spectrum.channels[0].channel = params->channel;
  2732. spectrum.channels[0].type = type;
  2733. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2734. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2735. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2736. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2737. if (rc)
  2738. return rc;
  2739. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2740. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2741. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2742. rc = -EIO;
  2743. }
  2744. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2745. switch (spectrum_resp_status) {
  2746. case 0: /* Command will be handled */
  2747. if (res->u.spectrum.id != 0xff) {
  2748. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2749. res->u.spectrum.id);
  2750. priv->measurement_status &= ~MEASUREMENT_READY;
  2751. }
  2752. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2753. rc = 0;
  2754. break;
  2755. case 1: /* Command will not be handled */
  2756. rc = -EAGAIN;
  2757. break;
  2758. }
  2759. dev_kfree_skb_any(cmd.meta.u.skb);
  2760. return rc;
  2761. }
  2762. #endif
  2763. static void iwl3945_txstatus_to_ieee(struct iwl3945_priv *priv,
  2764. struct iwl3945_tx_info *tx_sta)
  2765. {
  2766. tx_sta->status.ack_signal = 0;
  2767. tx_sta->status.excessive_retries = 0;
  2768. tx_sta->status.queue_length = 0;
  2769. tx_sta->status.queue_number = 0;
  2770. if (in_interrupt())
  2771. ieee80211_tx_status_irqsafe(priv->hw,
  2772. tx_sta->skb[0], &(tx_sta->status));
  2773. else
  2774. ieee80211_tx_status(priv->hw,
  2775. tx_sta->skb[0], &(tx_sta->status));
  2776. tx_sta->skb[0] = NULL;
  2777. }
  2778. /**
  2779. * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries no more used by NIC.
  2780. *
  2781. * When FW advances 'R' index, all entries between old and
  2782. * new 'R' index need to be reclaimed. As result, some free space
  2783. * forms. If there is enough free space (> low mark), wake Tx queue.
  2784. */
  2785. static int iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv, int txq_id, int index)
  2786. {
  2787. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2788. struct iwl3945_queue *q = &txq->q;
  2789. int nfreed = 0;
  2790. if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
  2791. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2792. "is out of range [0-%d] %d %d.\n", txq_id,
  2793. index, q->n_bd, q->write_ptr, q->read_ptr);
  2794. return 0;
  2795. }
  2796. for (index = iwl3945_queue_inc_wrap(index, q->n_bd);
  2797. q->read_ptr != index;
  2798. q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2799. if (txq_id != IWL_CMD_QUEUE_NUM) {
  2800. iwl3945_txstatus_to_ieee(priv,
  2801. &(txq->txb[txq->q.read_ptr]));
  2802. iwl3945_hw_txq_free_tfd(priv, txq);
  2803. } else if (nfreed > 1) {
  2804. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2805. q->write_ptr, q->read_ptr);
  2806. queue_work(priv->workqueue, &priv->restart);
  2807. }
  2808. nfreed++;
  2809. }
  2810. if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
  2811. (txq_id != IWL_CMD_QUEUE_NUM) &&
  2812. priv->mac80211_registered)
  2813. ieee80211_wake_queue(priv->hw, txq_id);
  2814. return nfreed;
  2815. }
  2816. static int iwl3945_is_tx_success(u32 status)
  2817. {
  2818. return (status & 0xFF) == 0x1;
  2819. }
  2820. /******************************************************************************
  2821. *
  2822. * Generic RX handler implementations
  2823. *
  2824. ******************************************************************************/
  2825. static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
  2826. struct iwl3945_rx_mem_buffer *rxb)
  2827. {
  2828. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2829. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2830. int txq_id = SEQ_TO_QUEUE(sequence);
  2831. int index = SEQ_TO_INDEX(sequence);
  2832. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2833. struct ieee80211_tx_status *tx_status;
  2834. struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  2835. u32 status = le32_to_cpu(tx_resp->status);
  2836. if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
  2837. IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
  2838. "is out of range [0-%d] %d %d\n", txq_id,
  2839. index, txq->q.n_bd, txq->q.write_ptr,
  2840. txq->q.read_ptr);
  2841. return;
  2842. }
  2843. tx_status = &(txq->txb[txq->q.read_ptr].status);
  2844. tx_status->retry_count = tx_resp->failure_frame;
  2845. tx_status->queue_number = status;
  2846. tx_status->queue_length = tx_resp->bt_kill_count;
  2847. tx_status->queue_length |= tx_resp->failure_rts;
  2848. tx_status->flags =
  2849. iwl3945_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
  2850. tx_status->control.tx_rate = iwl3945_rate_index_from_plcp(tx_resp->rate);
  2851. IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
  2852. txq_id, iwl3945_get_tx_fail_reason(status), status,
  2853. tx_resp->rate, tx_resp->failure_frame);
  2854. IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
  2855. if (index != -1)
  2856. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  2857. if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
  2858. IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
  2859. }
  2860. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2861. struct iwl3945_rx_mem_buffer *rxb)
  2862. {
  2863. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2864. struct iwl3945_alive_resp *palive;
  2865. struct delayed_work *pwork;
  2866. palive = &pkt->u.alive_frame;
  2867. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2868. "0x%01X 0x%01X\n",
  2869. palive->is_valid, palive->ver_type,
  2870. palive->ver_subtype);
  2871. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2872. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2873. memcpy(&priv->card_alive_init,
  2874. &pkt->u.alive_frame,
  2875. sizeof(struct iwl3945_init_alive_resp));
  2876. pwork = &priv->init_alive_start;
  2877. } else {
  2878. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2879. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2880. sizeof(struct iwl3945_alive_resp));
  2881. pwork = &priv->alive_start;
  2882. iwl3945_disable_events(priv);
  2883. }
  2884. /* We delay the ALIVE response by 5ms to
  2885. * give the HW RF Kill time to activate... */
  2886. if (palive->is_valid == UCODE_VALID_OK)
  2887. queue_delayed_work(priv->workqueue, pwork,
  2888. msecs_to_jiffies(5));
  2889. else
  2890. IWL_WARNING("uCode did not respond OK.\n");
  2891. }
  2892. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2893. struct iwl3945_rx_mem_buffer *rxb)
  2894. {
  2895. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2896. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2897. return;
  2898. }
  2899. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2900. struct iwl3945_rx_mem_buffer *rxb)
  2901. {
  2902. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2903. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2904. "seq 0x%04X ser 0x%08X\n",
  2905. le32_to_cpu(pkt->u.err_resp.error_type),
  2906. get_cmd_string(pkt->u.err_resp.cmd_id),
  2907. pkt->u.err_resp.cmd_id,
  2908. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2909. le32_to_cpu(pkt->u.err_resp.error_info));
  2910. }
  2911. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2912. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2913. {
  2914. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2915. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2916. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  2917. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2918. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2919. rxon->channel = csa->channel;
  2920. priv->staging_rxon.channel = csa->channel;
  2921. }
  2922. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2923. struct iwl3945_rx_mem_buffer *rxb)
  2924. {
  2925. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2926. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2927. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2928. if (!report->state) {
  2929. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2930. "Spectrum Measure Notification: Start\n");
  2931. return;
  2932. }
  2933. memcpy(&priv->measure_report, report, sizeof(*report));
  2934. priv->measurement_status |= MEASUREMENT_READY;
  2935. #endif
  2936. }
  2937. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2938. struct iwl3945_rx_mem_buffer *rxb)
  2939. {
  2940. #ifdef CONFIG_IWL3945_DEBUG
  2941. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2942. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2943. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2944. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2945. #endif
  2946. }
  2947. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2948. struct iwl3945_rx_mem_buffer *rxb)
  2949. {
  2950. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2951. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2952. "notification for %s:\n",
  2953. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2954. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2955. }
  2956. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2957. {
  2958. struct iwl3945_priv *priv =
  2959. container_of(work, struct iwl3945_priv, beacon_update);
  2960. struct sk_buff *beacon;
  2961. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2962. beacon = ieee80211_beacon_get(priv->hw, priv->interface_id, NULL);
  2963. if (!beacon) {
  2964. IWL_ERROR("update beacon failed\n");
  2965. return;
  2966. }
  2967. mutex_lock(&priv->mutex);
  2968. /* new beacon skb is allocated every time; dispose previous.*/
  2969. if (priv->ibss_beacon)
  2970. dev_kfree_skb(priv->ibss_beacon);
  2971. priv->ibss_beacon = beacon;
  2972. mutex_unlock(&priv->mutex);
  2973. iwl3945_send_beacon_cmd(priv);
  2974. }
  2975. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2976. struct iwl3945_rx_mem_buffer *rxb)
  2977. {
  2978. #ifdef CONFIG_IWL3945_DEBUG
  2979. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2980. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2981. u8 rate = beacon->beacon_notify_hdr.rate;
  2982. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2983. "tsf %d %d rate %d\n",
  2984. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2985. beacon->beacon_notify_hdr.failure_frame,
  2986. le32_to_cpu(beacon->ibss_mgr_status),
  2987. le32_to_cpu(beacon->high_tsf),
  2988. le32_to_cpu(beacon->low_tsf), rate);
  2989. #endif
  2990. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  2991. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2992. queue_work(priv->workqueue, &priv->beacon_update);
  2993. }
  2994. /* Service response to REPLY_SCAN_CMD (0x80) */
  2995. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  2996. struct iwl3945_rx_mem_buffer *rxb)
  2997. {
  2998. #ifdef CONFIG_IWL3945_DEBUG
  2999. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3000. struct iwl3945_scanreq_notification *notif =
  3001. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  3002. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  3003. #endif
  3004. }
  3005. /* Service SCAN_START_NOTIFICATION (0x82) */
  3006. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  3007. struct iwl3945_rx_mem_buffer *rxb)
  3008. {
  3009. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3010. struct iwl3945_scanstart_notification *notif =
  3011. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  3012. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  3013. IWL_DEBUG_SCAN("Scan start: "
  3014. "%d [802.11%s] "
  3015. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  3016. notif->channel,
  3017. notif->band ? "bg" : "a",
  3018. notif->tsf_high,
  3019. notif->tsf_low, notif->status, notif->beacon_timer);
  3020. }
  3021. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  3022. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  3023. struct iwl3945_rx_mem_buffer *rxb)
  3024. {
  3025. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3026. struct iwl3945_scanresults_notification *notif =
  3027. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  3028. IWL_DEBUG_SCAN("Scan ch.res: "
  3029. "%d [802.11%s] "
  3030. "(TSF: 0x%08X:%08X) - %d "
  3031. "elapsed=%lu usec (%dms since last)\n",
  3032. notif->channel,
  3033. notif->band ? "bg" : "a",
  3034. le32_to_cpu(notif->tsf_high),
  3035. le32_to_cpu(notif->tsf_low),
  3036. le32_to_cpu(notif->statistics[0]),
  3037. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  3038. jiffies_to_msecs(elapsed_jiffies
  3039. (priv->last_scan_jiffies, jiffies)));
  3040. priv->last_scan_jiffies = jiffies;
  3041. }
  3042. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  3043. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  3044. struct iwl3945_rx_mem_buffer *rxb)
  3045. {
  3046. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3047. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  3048. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  3049. scan_notif->scanned_channels,
  3050. scan_notif->tsf_low,
  3051. scan_notif->tsf_high, scan_notif->status);
  3052. /* The HW is no longer scanning */
  3053. clear_bit(STATUS_SCAN_HW, &priv->status);
  3054. /* The scan completion notification came in, so kill that timer... */
  3055. cancel_delayed_work(&priv->scan_check);
  3056. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  3057. (priv->scan_bands == 2) ? "2.4" : "5.2",
  3058. jiffies_to_msecs(elapsed_jiffies
  3059. (priv->scan_pass_start, jiffies)));
  3060. /* Remove this scanned band from the list
  3061. * of pending bands to scan */
  3062. priv->scan_bands--;
  3063. /* If a request to abort was given, or the scan did not succeed
  3064. * then we reset the scan state machine and terminate,
  3065. * re-queuing another scan if one has been requested */
  3066. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  3067. IWL_DEBUG_INFO("Aborted scan completed.\n");
  3068. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  3069. } else {
  3070. /* If there are more bands on this scan pass reschedule */
  3071. if (priv->scan_bands > 0)
  3072. goto reschedule;
  3073. }
  3074. priv->last_scan_jiffies = jiffies;
  3075. IWL_DEBUG_INFO("Setting scan to off\n");
  3076. clear_bit(STATUS_SCANNING, &priv->status);
  3077. IWL_DEBUG_INFO("Scan took %dms\n",
  3078. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  3079. queue_work(priv->workqueue, &priv->scan_completed);
  3080. return;
  3081. reschedule:
  3082. priv->scan_pass_start = jiffies;
  3083. queue_work(priv->workqueue, &priv->request_scan);
  3084. }
  3085. /* Handle notification from uCode that card's power state is changing
  3086. * due to software, hardware, or critical temperature RFKILL */
  3087. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  3088. struct iwl3945_rx_mem_buffer *rxb)
  3089. {
  3090. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3091. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  3092. unsigned long status = priv->status;
  3093. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  3094. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  3095. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  3096. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  3097. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  3098. if (flags & HW_CARD_DISABLED)
  3099. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3100. else
  3101. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3102. if (flags & SW_CARD_DISABLED)
  3103. set_bit(STATUS_RF_KILL_SW, &priv->status);
  3104. else
  3105. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  3106. iwl3945_scan_cancel(priv);
  3107. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  3108. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  3109. (test_bit(STATUS_RF_KILL_SW, &status) !=
  3110. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  3111. queue_work(priv->workqueue, &priv->rf_kill);
  3112. else
  3113. wake_up_interruptible(&priv->wait_command_queue);
  3114. }
  3115. /**
  3116. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  3117. *
  3118. * Setup the RX handlers for each of the reply types sent from the uCode
  3119. * to the host.
  3120. *
  3121. * This function chains into the hardware specific files for them to setup
  3122. * any hardware specific handlers as well.
  3123. */
  3124. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  3125. {
  3126. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  3127. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  3128. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  3129. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  3130. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  3131. iwl3945_rx_spectrum_measure_notif;
  3132. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  3133. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  3134. iwl3945_rx_pm_debug_statistics_notif;
  3135. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  3136. /*
  3137. * The same handler is used for both the REPLY to a discrete
  3138. * statistics request from the host as well as for the periodic
  3139. * statistics notifications (after received beacons) from the uCode.
  3140. */
  3141. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  3142. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  3143. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  3144. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  3145. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  3146. iwl3945_rx_scan_results_notif;
  3147. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  3148. iwl3945_rx_scan_complete_notif;
  3149. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  3150. priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
  3151. /* Set up hardware specific Rx handlers */
  3152. iwl3945_hw_rx_handler_setup(priv);
  3153. }
  3154. /**
  3155. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  3156. * @rxb: Rx buffer to reclaim
  3157. *
  3158. * If an Rx buffer has an async callback associated with it the callback
  3159. * will be executed. The attached skb (if present) will only be freed
  3160. * if the callback returns 1
  3161. */
  3162. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  3163. struct iwl3945_rx_mem_buffer *rxb)
  3164. {
  3165. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3166. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  3167. int txq_id = SEQ_TO_QUEUE(sequence);
  3168. int index = SEQ_TO_INDEX(sequence);
  3169. int huge = sequence & SEQ_HUGE_FRAME;
  3170. int cmd_index;
  3171. struct iwl3945_cmd *cmd;
  3172. /* If a Tx command is being handled and it isn't in the actual
  3173. * command queue then there a command routing bug has been introduced
  3174. * in the queue management code. */
  3175. if (txq_id != IWL_CMD_QUEUE_NUM)
  3176. IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
  3177. txq_id, pkt->hdr.cmd);
  3178. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  3179. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  3180. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  3181. /* Input error checking is done when commands are added to queue. */
  3182. if (cmd->meta.flags & CMD_WANT_SKB) {
  3183. cmd->meta.source->u.skb = rxb->skb;
  3184. rxb->skb = NULL;
  3185. } else if (cmd->meta.u.callback &&
  3186. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  3187. rxb->skb = NULL;
  3188. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  3189. if (!(cmd->meta.flags & CMD_ASYNC)) {
  3190. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3191. wake_up_interruptible(&priv->wait_command_queue);
  3192. }
  3193. }
  3194. /************************** RX-FUNCTIONS ****************************/
  3195. /*
  3196. * Rx theory of operation
  3197. *
  3198. * The host allocates 32 DMA target addresses and passes the host address
  3199. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  3200. * 0 to 31
  3201. *
  3202. * Rx Queue Indexes
  3203. * The host/firmware share two index registers for managing the Rx buffers.
  3204. *
  3205. * The READ index maps to the first position that the firmware may be writing
  3206. * to -- the driver can read up to (but not including) this position and get
  3207. * good data.
  3208. * The READ index is managed by the firmware once the card is enabled.
  3209. *
  3210. * The WRITE index maps to the last position the driver has read from -- the
  3211. * position preceding WRITE is the last slot the firmware can place a packet.
  3212. *
  3213. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  3214. * WRITE = READ.
  3215. *
  3216. * During initialization, the host sets up the READ queue position to the first
  3217. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  3218. *
  3219. * When the firmware places a packet in a buffer, it will advance the READ index
  3220. * and fire the RX interrupt. The driver can then query the READ index and
  3221. * process as many packets as possible, moving the WRITE index forward as it
  3222. * resets the Rx queue buffers with new memory.
  3223. *
  3224. * The management in the driver is as follows:
  3225. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  3226. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  3227. * to replenish the iwl->rxq->rx_free.
  3228. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  3229. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  3230. * 'processed' and 'read' driver indexes as well)
  3231. * + A received packet is processed and handed to the kernel network stack,
  3232. * detached from the iwl->rxq. The driver 'processed' index is updated.
  3233. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  3234. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  3235. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  3236. * were enough free buffers and RX_STALLED is set it is cleared.
  3237. *
  3238. *
  3239. * Driver sequence:
  3240. *
  3241. * iwl3945_rx_queue_alloc() Allocates rx_free
  3242. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  3243. * iwl3945_rx_queue_restock
  3244. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  3245. * queue, updates firmware pointers, and updates
  3246. * the WRITE index. If insufficient rx_free buffers
  3247. * are available, schedules iwl3945_rx_replenish
  3248. *
  3249. * -- enable interrupts --
  3250. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  3251. * READ INDEX, detaching the SKB from the pool.
  3252. * Moves the packet buffer from queue to rx_used.
  3253. * Calls iwl3945_rx_queue_restock to refill any empty
  3254. * slots.
  3255. * ...
  3256. *
  3257. */
  3258. /**
  3259. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  3260. */
  3261. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  3262. {
  3263. int s = q->read - q->write;
  3264. if (s <= 0)
  3265. s += RX_QUEUE_SIZE;
  3266. /* keep some buffer to not confuse full and empty queue */
  3267. s -= 2;
  3268. if (s < 0)
  3269. s = 0;
  3270. return s;
  3271. }
  3272. /**
  3273. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  3274. */
  3275. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  3276. {
  3277. u32 reg = 0;
  3278. int rc = 0;
  3279. unsigned long flags;
  3280. spin_lock_irqsave(&q->lock, flags);
  3281. if (q->need_update == 0)
  3282. goto exit_unlock;
  3283. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3284. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3285. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3286. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3287. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3288. goto exit_unlock;
  3289. }
  3290. rc = iwl3945_grab_nic_access(priv);
  3291. if (rc)
  3292. goto exit_unlock;
  3293. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  3294. q->write & ~0x7);
  3295. iwl3945_release_nic_access(priv);
  3296. } else
  3297. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  3298. q->need_update = 0;
  3299. exit_unlock:
  3300. spin_unlock_irqrestore(&q->lock, flags);
  3301. return rc;
  3302. }
  3303. /**
  3304. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  3305. */
  3306. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  3307. dma_addr_t dma_addr)
  3308. {
  3309. return cpu_to_le32((u32)dma_addr);
  3310. }
  3311. /**
  3312. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  3313. *
  3314. * If there are slots in the RX queue that need to be restocked,
  3315. * and we have free pre-allocated buffers, fill the ranks as much
  3316. * as we can, pulling from rx_free.
  3317. *
  3318. * This moves the 'write' index forward to catch up with 'processed', and
  3319. * also updates the memory address in the firmware to reference the new
  3320. * target buffer.
  3321. */
  3322. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  3323. {
  3324. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3325. struct list_head *element;
  3326. struct iwl3945_rx_mem_buffer *rxb;
  3327. unsigned long flags;
  3328. int write, rc;
  3329. spin_lock_irqsave(&rxq->lock, flags);
  3330. write = rxq->write & ~0x7;
  3331. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  3332. element = rxq->rx_free.next;
  3333. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3334. list_del(element);
  3335. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  3336. rxq->queue[rxq->write] = rxb;
  3337. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  3338. rxq->free_count--;
  3339. }
  3340. spin_unlock_irqrestore(&rxq->lock, flags);
  3341. /* If the pre-allocated buffer pool is dropping low, schedule to
  3342. * refill it */
  3343. if (rxq->free_count <= RX_LOW_WATERMARK)
  3344. queue_work(priv->workqueue, &priv->rx_replenish);
  3345. /* If we've added more space for the firmware to place data, tell it */
  3346. if ((write != (rxq->write & ~0x7))
  3347. || (abs(rxq->write - rxq->read) > 7)) {
  3348. spin_lock_irqsave(&rxq->lock, flags);
  3349. rxq->need_update = 1;
  3350. spin_unlock_irqrestore(&rxq->lock, flags);
  3351. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  3352. if (rc)
  3353. return rc;
  3354. }
  3355. return 0;
  3356. }
  3357. /**
  3358. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  3359. *
  3360. * When moving to rx_free an SKB is allocated for the slot.
  3361. *
  3362. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  3363. * This is called as a scheduled work item (except for during initialization)
  3364. */
  3365. void iwl3945_rx_replenish(void *data)
  3366. {
  3367. struct iwl3945_priv *priv = data;
  3368. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3369. struct list_head *element;
  3370. struct iwl3945_rx_mem_buffer *rxb;
  3371. unsigned long flags;
  3372. spin_lock_irqsave(&rxq->lock, flags);
  3373. while (!list_empty(&rxq->rx_used)) {
  3374. element = rxq->rx_used.next;
  3375. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3376. rxb->skb =
  3377. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3378. if (!rxb->skb) {
  3379. if (net_ratelimit())
  3380. printk(KERN_CRIT DRV_NAME
  3381. ": Can not allocate SKB buffers\n");
  3382. /* We don't reschedule replenish work here -- we will
  3383. * call the restock method and if it still needs
  3384. * more buffers it will schedule replenish */
  3385. break;
  3386. }
  3387. priv->alloc_rxb_skb++;
  3388. list_del(element);
  3389. rxb->dma_addr =
  3390. pci_map_single(priv->pci_dev, rxb->skb->data,
  3391. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3392. list_add_tail(&rxb->list, &rxq->rx_free);
  3393. rxq->free_count++;
  3394. }
  3395. spin_unlock_irqrestore(&rxq->lock, flags);
  3396. spin_lock_irqsave(&priv->lock, flags);
  3397. iwl3945_rx_queue_restock(priv);
  3398. spin_unlock_irqrestore(&priv->lock, flags);
  3399. }
  3400. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3401. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3402. * This free routine walks the list of POOL entries and if SKB is set to
  3403. * non NULL it is unmapped and freed
  3404. */
  3405. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3406. {
  3407. int i;
  3408. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3409. if (rxq->pool[i].skb != NULL) {
  3410. pci_unmap_single(priv->pci_dev,
  3411. rxq->pool[i].dma_addr,
  3412. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3413. dev_kfree_skb(rxq->pool[i].skb);
  3414. }
  3415. }
  3416. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3417. rxq->dma_addr);
  3418. rxq->bd = NULL;
  3419. }
  3420. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3421. {
  3422. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3423. struct pci_dev *dev = priv->pci_dev;
  3424. int i;
  3425. spin_lock_init(&rxq->lock);
  3426. INIT_LIST_HEAD(&rxq->rx_free);
  3427. INIT_LIST_HEAD(&rxq->rx_used);
  3428. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3429. if (!rxq->bd)
  3430. return -ENOMEM;
  3431. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3432. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3433. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3434. /* Set us so that we have processed and used all buffers, but have
  3435. * not restocked the Rx queue with fresh buffers */
  3436. rxq->read = rxq->write = 0;
  3437. rxq->free_count = 0;
  3438. rxq->need_update = 0;
  3439. return 0;
  3440. }
  3441. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3442. {
  3443. unsigned long flags;
  3444. int i;
  3445. spin_lock_irqsave(&rxq->lock, flags);
  3446. INIT_LIST_HEAD(&rxq->rx_free);
  3447. INIT_LIST_HEAD(&rxq->rx_used);
  3448. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3449. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3450. /* In the reset function, these buffers may have been allocated
  3451. * to an SKB, so we need to unmap and free potential storage */
  3452. if (rxq->pool[i].skb != NULL) {
  3453. pci_unmap_single(priv->pci_dev,
  3454. rxq->pool[i].dma_addr,
  3455. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3456. priv->alloc_rxb_skb--;
  3457. dev_kfree_skb(rxq->pool[i].skb);
  3458. rxq->pool[i].skb = NULL;
  3459. }
  3460. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3461. }
  3462. /* Set us so that we have processed and used all buffers, but have
  3463. * not restocked the Rx queue with fresh buffers */
  3464. rxq->read = rxq->write = 0;
  3465. rxq->free_count = 0;
  3466. spin_unlock_irqrestore(&rxq->lock, flags);
  3467. }
  3468. /* Convert linear signal-to-noise ratio into dB */
  3469. static u8 ratio2dB[100] = {
  3470. /* 0 1 2 3 4 5 6 7 8 9 */
  3471. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3472. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3473. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3474. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3475. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3476. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3477. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3478. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3479. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3480. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3481. };
  3482. /* Calculates a relative dB value from a ratio of linear
  3483. * (i.e. not dB) signal levels.
  3484. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3485. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3486. {
  3487. /* Anything above 1000:1 just report as 60 dB */
  3488. if (sig_ratio > 1000)
  3489. return 60;
  3490. /* Above 100:1, divide by 10 and use table,
  3491. * add 20 dB to make up for divide by 10 */
  3492. if (sig_ratio > 100)
  3493. return (20 + (int)ratio2dB[sig_ratio/10]);
  3494. /* We shouldn't see this */
  3495. if (sig_ratio < 1)
  3496. return 0;
  3497. /* Use table for ratios 1:1 - 99:1 */
  3498. return (int)ratio2dB[sig_ratio];
  3499. }
  3500. #define PERFECT_RSSI (-20) /* dBm */
  3501. #define WORST_RSSI (-95) /* dBm */
  3502. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3503. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3504. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3505. * about formulas used below. */
  3506. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3507. {
  3508. int sig_qual;
  3509. int degradation = PERFECT_RSSI - rssi_dbm;
  3510. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3511. * as indicator; formula is (signal dbm - noise dbm).
  3512. * SNR at or above 40 is a great signal (100%).
  3513. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3514. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3515. if (noise_dbm) {
  3516. if (rssi_dbm - noise_dbm >= 40)
  3517. return 100;
  3518. else if (rssi_dbm < noise_dbm)
  3519. return 0;
  3520. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3521. /* Else use just the signal level.
  3522. * This formula is a least squares fit of data points collected and
  3523. * compared with a reference system that had a percentage (%) display
  3524. * for signal quality. */
  3525. } else
  3526. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3527. (15 * RSSI_RANGE + 62 * degradation)) /
  3528. (RSSI_RANGE * RSSI_RANGE);
  3529. if (sig_qual > 100)
  3530. sig_qual = 100;
  3531. else if (sig_qual < 1)
  3532. sig_qual = 0;
  3533. return sig_qual;
  3534. }
  3535. /**
  3536. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3537. *
  3538. * Uses the priv->rx_handlers callback function array to invoke
  3539. * the appropriate handlers, including command responses,
  3540. * frame-received notifications, and other notifications.
  3541. */
  3542. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3543. {
  3544. struct iwl3945_rx_mem_buffer *rxb;
  3545. struct iwl3945_rx_packet *pkt;
  3546. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3547. u32 r, i;
  3548. int reclaim;
  3549. unsigned long flags;
  3550. r = iwl3945_hw_get_rx_read(priv);
  3551. i = rxq->read;
  3552. /* Rx interrupt, but nothing sent from uCode */
  3553. if (i == r)
  3554. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3555. while (i != r) {
  3556. rxb = rxq->queue[i];
  3557. /* If an RXB doesn't have a Rx queue slot associated with it,
  3558. * then a bug has been introduced in the queue refilling
  3559. * routines -- catch it here */
  3560. BUG_ON(rxb == NULL);
  3561. rxq->queue[i] = NULL;
  3562. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3563. IWL_RX_BUF_SIZE,
  3564. PCI_DMA_FROMDEVICE);
  3565. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3566. /* Reclaim a command buffer only if this packet is a response
  3567. * to a (driver-originated) command.
  3568. * If the packet (e.g. Rx frame) originated from uCode,
  3569. * there is no command buffer to reclaim.
  3570. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3571. * but apparently a few don't get set; catch them here. */
  3572. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3573. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3574. (pkt->hdr.cmd != REPLY_TX);
  3575. /* Based on type of command response or notification,
  3576. * handle those that need handling via function in
  3577. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3578. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3579. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3580. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3581. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3582. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3583. } else {
  3584. /* No handling needed */
  3585. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3586. "r %d i %d No handler needed for %s, 0x%02x\n",
  3587. r, i, get_cmd_string(pkt->hdr.cmd),
  3588. pkt->hdr.cmd);
  3589. }
  3590. if (reclaim) {
  3591. /* Invoke any callbacks, transfer the skb to caller, and
  3592. * fire off the (possibly) blocking iwl3945_send_cmd()
  3593. * as we reclaim the driver command queue */
  3594. if (rxb && rxb->skb)
  3595. iwl3945_tx_cmd_complete(priv, rxb);
  3596. else
  3597. IWL_WARNING("Claim null rxb?\n");
  3598. }
  3599. /* For now we just don't re-use anything. We can tweak this
  3600. * later to try and re-use notification packets and SKBs that
  3601. * fail to Rx correctly */
  3602. if (rxb->skb != NULL) {
  3603. priv->alloc_rxb_skb--;
  3604. dev_kfree_skb_any(rxb->skb);
  3605. rxb->skb = NULL;
  3606. }
  3607. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3608. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3609. spin_lock_irqsave(&rxq->lock, flags);
  3610. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3611. spin_unlock_irqrestore(&rxq->lock, flags);
  3612. i = (i + 1) & RX_QUEUE_MASK;
  3613. }
  3614. /* Backtrack one entry */
  3615. priv->rxq.read = i;
  3616. iwl3945_rx_queue_restock(priv);
  3617. }
  3618. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3619. struct iwl3945_tx_queue *txq)
  3620. {
  3621. u32 reg = 0;
  3622. int rc = 0;
  3623. int txq_id = txq->q.id;
  3624. if (txq->need_update == 0)
  3625. return rc;
  3626. /* if we're trying to save power */
  3627. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3628. /* wake up nic if it's powered down ...
  3629. * uCode will wake up, and interrupt us again, so next
  3630. * time we'll skip this part. */
  3631. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3632. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3633. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3634. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3635. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3636. return rc;
  3637. }
  3638. /* restore this queue's parameters in nic hardware. */
  3639. rc = iwl3945_grab_nic_access(priv);
  3640. if (rc)
  3641. return rc;
  3642. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3643. txq->q.write_ptr | (txq_id << 8));
  3644. iwl3945_release_nic_access(priv);
  3645. /* else not in power-save mode, uCode will never sleep when we're
  3646. * trying to tx (during RFKILL, we're not trying to tx). */
  3647. } else
  3648. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3649. txq->q.write_ptr | (txq_id << 8));
  3650. txq->need_update = 0;
  3651. return rc;
  3652. }
  3653. #ifdef CONFIG_IWL3945_DEBUG
  3654. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3655. {
  3656. DECLARE_MAC_BUF(mac);
  3657. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3658. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3659. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3660. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3661. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3662. le32_to_cpu(rxon->filter_flags));
  3663. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3664. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3665. rxon->ofdm_basic_rates);
  3666. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3667. IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
  3668. print_mac(mac, rxon->node_addr));
  3669. IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
  3670. print_mac(mac, rxon->bssid_addr));
  3671. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3672. }
  3673. #endif
  3674. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3675. {
  3676. IWL_DEBUG_ISR("Enabling interrupts\n");
  3677. set_bit(STATUS_INT_ENABLED, &priv->status);
  3678. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3679. }
  3680. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3681. {
  3682. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3683. /* disable interrupts from uCode/NIC to host */
  3684. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3685. /* acknowledge/clear/reset any interrupts still pending
  3686. * from uCode or flow handler (Rx/Tx DMA) */
  3687. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3688. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3689. IWL_DEBUG_ISR("Disabled interrupts\n");
  3690. }
  3691. static const char *desc_lookup(int i)
  3692. {
  3693. switch (i) {
  3694. case 1:
  3695. return "FAIL";
  3696. case 2:
  3697. return "BAD_PARAM";
  3698. case 3:
  3699. return "BAD_CHECKSUM";
  3700. case 4:
  3701. return "NMI_INTERRUPT";
  3702. case 5:
  3703. return "SYSASSERT";
  3704. case 6:
  3705. return "FATAL_ERROR";
  3706. }
  3707. return "UNKNOWN";
  3708. }
  3709. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3710. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3711. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3712. {
  3713. u32 i;
  3714. u32 desc, time, count, base, data1;
  3715. u32 blink1, blink2, ilink1, ilink2;
  3716. int rc;
  3717. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3718. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3719. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3720. return;
  3721. }
  3722. rc = iwl3945_grab_nic_access(priv);
  3723. if (rc) {
  3724. IWL_WARNING("Can not read from adapter at this time.\n");
  3725. return;
  3726. }
  3727. count = iwl3945_read_targ_mem(priv, base);
  3728. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3729. IWL_ERROR("Start IWL Error Log Dump:\n");
  3730. IWL_ERROR("Status: 0x%08lX, Config: %08X count: %d\n",
  3731. priv->status, priv->config, count);
  3732. }
  3733. IWL_ERROR("Desc Time asrtPC blink2 "
  3734. "ilink1 nmiPC Line\n");
  3735. for (i = ERROR_START_OFFSET;
  3736. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3737. i += ERROR_ELEM_SIZE) {
  3738. desc = iwl3945_read_targ_mem(priv, base + i);
  3739. time =
  3740. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3741. blink1 =
  3742. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3743. blink2 =
  3744. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3745. ilink1 =
  3746. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3747. ilink2 =
  3748. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3749. data1 =
  3750. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3751. IWL_ERROR
  3752. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3753. desc_lookup(desc), desc, time, blink1, blink2,
  3754. ilink1, ilink2, data1);
  3755. }
  3756. iwl3945_release_nic_access(priv);
  3757. }
  3758. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3759. /**
  3760. * iwl3945_print_event_log - Dump error event log to syslog
  3761. *
  3762. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3763. */
  3764. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3765. u32 num_events, u32 mode)
  3766. {
  3767. u32 i;
  3768. u32 base; /* SRAM byte address of event log header */
  3769. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3770. u32 ptr; /* SRAM byte address of log data */
  3771. u32 ev, time, data; /* event log data */
  3772. if (num_events == 0)
  3773. return;
  3774. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3775. if (mode == 0)
  3776. event_size = 2 * sizeof(u32);
  3777. else
  3778. event_size = 3 * sizeof(u32);
  3779. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3780. /* "time" is actually "data" for mode 0 (no timestamp).
  3781. * place event id # at far right for easier visual parsing. */
  3782. for (i = 0; i < num_events; i++) {
  3783. ev = iwl3945_read_targ_mem(priv, ptr);
  3784. ptr += sizeof(u32);
  3785. time = iwl3945_read_targ_mem(priv, ptr);
  3786. ptr += sizeof(u32);
  3787. if (mode == 0)
  3788. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3789. else {
  3790. data = iwl3945_read_targ_mem(priv, ptr);
  3791. ptr += sizeof(u32);
  3792. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3793. }
  3794. }
  3795. }
  3796. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3797. {
  3798. int rc;
  3799. u32 base; /* SRAM byte address of event log header */
  3800. u32 capacity; /* event log capacity in # entries */
  3801. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3802. u32 num_wraps; /* # times uCode wrapped to top of log */
  3803. u32 next_entry; /* index of next entry to be written by uCode */
  3804. u32 size; /* # entries that we'll print */
  3805. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3806. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3807. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3808. return;
  3809. }
  3810. rc = iwl3945_grab_nic_access(priv);
  3811. if (rc) {
  3812. IWL_WARNING("Can not read from adapter at this time.\n");
  3813. return;
  3814. }
  3815. /* event log header */
  3816. capacity = iwl3945_read_targ_mem(priv, base);
  3817. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3818. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3819. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3820. size = num_wraps ? capacity : next_entry;
  3821. /* bail out if nothing in log */
  3822. if (size == 0) {
  3823. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3824. iwl3945_release_nic_access(priv);
  3825. return;
  3826. }
  3827. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3828. size, num_wraps);
  3829. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3830. * i.e the next one that uCode would fill. */
  3831. if (num_wraps)
  3832. iwl3945_print_event_log(priv, next_entry,
  3833. capacity - next_entry, mode);
  3834. /* (then/else) start at top of log */
  3835. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3836. iwl3945_release_nic_access(priv);
  3837. }
  3838. /**
  3839. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3840. */
  3841. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3842. {
  3843. /* Set the FW error flag -- cleared on iwl3945_down */
  3844. set_bit(STATUS_FW_ERROR, &priv->status);
  3845. /* Cancel currently queued command. */
  3846. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3847. #ifdef CONFIG_IWL3945_DEBUG
  3848. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3849. iwl3945_dump_nic_error_log(priv);
  3850. iwl3945_dump_nic_event_log(priv);
  3851. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3852. }
  3853. #endif
  3854. wake_up_interruptible(&priv->wait_command_queue);
  3855. /* Keep the restart process from trying to send host
  3856. * commands by clearing the INIT status bit */
  3857. clear_bit(STATUS_READY, &priv->status);
  3858. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3859. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3860. "Restarting adapter due to uCode error.\n");
  3861. if (iwl3945_is_associated(priv)) {
  3862. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3863. sizeof(priv->recovery_rxon));
  3864. priv->error_recovering = 1;
  3865. }
  3866. queue_work(priv->workqueue, &priv->restart);
  3867. }
  3868. }
  3869. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3870. {
  3871. unsigned long flags;
  3872. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3873. sizeof(priv->staging_rxon));
  3874. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3875. iwl3945_commit_rxon(priv);
  3876. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3877. spin_lock_irqsave(&priv->lock, flags);
  3878. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3879. priv->error_recovering = 0;
  3880. spin_unlock_irqrestore(&priv->lock, flags);
  3881. }
  3882. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3883. {
  3884. u32 inta, handled = 0;
  3885. u32 inta_fh;
  3886. unsigned long flags;
  3887. #ifdef CONFIG_IWL3945_DEBUG
  3888. u32 inta_mask;
  3889. #endif
  3890. spin_lock_irqsave(&priv->lock, flags);
  3891. /* Ack/clear/reset pending uCode interrupts.
  3892. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3893. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3894. inta = iwl3945_read32(priv, CSR_INT);
  3895. iwl3945_write32(priv, CSR_INT, inta);
  3896. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3897. * Any new interrupts that happen after this, either while we're
  3898. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3899. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3900. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3901. #ifdef CONFIG_IWL3945_DEBUG
  3902. if (iwl3945_debug_level & IWL_DL_ISR) {
  3903. /* just for debug */
  3904. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3905. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3906. inta, inta_mask, inta_fh);
  3907. }
  3908. #endif
  3909. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3910. * atomic, make sure that inta covers all the interrupts that
  3911. * we've discovered, even if FH interrupt came in just after
  3912. * reading CSR_INT. */
  3913. if (inta_fh & CSR_FH_INT_RX_MASK)
  3914. inta |= CSR_INT_BIT_FH_RX;
  3915. if (inta_fh & CSR_FH_INT_TX_MASK)
  3916. inta |= CSR_INT_BIT_FH_TX;
  3917. /* Now service all interrupt bits discovered above. */
  3918. if (inta & CSR_INT_BIT_HW_ERR) {
  3919. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3920. /* Tell the device to stop sending interrupts */
  3921. iwl3945_disable_interrupts(priv);
  3922. iwl3945_irq_handle_error(priv);
  3923. handled |= CSR_INT_BIT_HW_ERR;
  3924. spin_unlock_irqrestore(&priv->lock, flags);
  3925. return;
  3926. }
  3927. #ifdef CONFIG_IWL3945_DEBUG
  3928. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3929. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3930. if (inta & CSR_INT_BIT_MAC_CLK_ACTV)
  3931. IWL_DEBUG_ISR("Microcode started or stopped.\n");
  3932. /* Alive notification via Rx interrupt will do the real work */
  3933. if (inta & CSR_INT_BIT_ALIVE)
  3934. IWL_DEBUG_ISR("Alive interrupt\n");
  3935. }
  3936. #endif
  3937. /* Safely ignore these bits for debug checks below */
  3938. inta &= ~(CSR_INT_BIT_MAC_CLK_ACTV | CSR_INT_BIT_ALIVE);
  3939. /* HW RF KILL switch toggled (4965 only) */
  3940. if (inta & CSR_INT_BIT_RF_KILL) {
  3941. int hw_rf_kill = 0;
  3942. if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
  3943. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  3944. hw_rf_kill = 1;
  3945. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  3946. "RF_KILL bit toggled to %s.\n",
  3947. hw_rf_kill ? "disable radio":"enable radio");
  3948. /* Queue restart only if RF_KILL switch was set to "kill"
  3949. * when we loaded driver, and is now set to "enable".
  3950. * After we're Alive, RF_KILL gets handled by
  3951. * iwl_rx_card_state_notif() */
  3952. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  3953. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3954. queue_work(priv->workqueue, &priv->restart);
  3955. }
  3956. handled |= CSR_INT_BIT_RF_KILL;
  3957. }
  3958. /* Chip got too hot and stopped itself (4965 only) */
  3959. if (inta & CSR_INT_BIT_CT_KILL) {
  3960. IWL_ERROR("Microcode CT kill error detected.\n");
  3961. handled |= CSR_INT_BIT_CT_KILL;
  3962. }
  3963. /* Error detected by uCode */
  3964. if (inta & CSR_INT_BIT_SW_ERR) {
  3965. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3966. inta);
  3967. iwl3945_irq_handle_error(priv);
  3968. handled |= CSR_INT_BIT_SW_ERR;
  3969. }
  3970. /* uCode wakes up after power-down sleep */
  3971. if (inta & CSR_INT_BIT_WAKEUP) {
  3972. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3973. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3974. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3975. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3976. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3977. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3978. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3979. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3980. handled |= CSR_INT_BIT_WAKEUP;
  3981. }
  3982. /* All uCode command responses, including Tx command responses,
  3983. * Rx "responses" (frame-received notification), and other
  3984. * notifications from uCode come through here*/
  3985. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3986. iwl3945_rx_handle(priv);
  3987. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3988. }
  3989. if (inta & CSR_INT_BIT_FH_TX) {
  3990. IWL_DEBUG_ISR("Tx interrupt\n");
  3991. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3992. if (!iwl3945_grab_nic_access(priv)) {
  3993. iwl3945_write_direct32(priv,
  3994. FH_TCSR_CREDIT
  3995. (ALM_FH_SRVC_CHNL), 0x0);
  3996. iwl3945_release_nic_access(priv);
  3997. }
  3998. handled |= CSR_INT_BIT_FH_TX;
  3999. }
  4000. if (inta & ~handled)
  4001. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  4002. if (inta & ~CSR_INI_SET_MASK) {
  4003. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  4004. inta & ~CSR_INI_SET_MASK);
  4005. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  4006. }
  4007. /* Re-enable all interrupts */
  4008. iwl3945_enable_interrupts(priv);
  4009. #ifdef CONFIG_IWL3945_DEBUG
  4010. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  4011. inta = iwl3945_read32(priv, CSR_INT);
  4012. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  4013. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  4014. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  4015. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  4016. }
  4017. #endif
  4018. spin_unlock_irqrestore(&priv->lock, flags);
  4019. }
  4020. static irqreturn_t iwl3945_isr(int irq, void *data)
  4021. {
  4022. struct iwl3945_priv *priv = data;
  4023. u32 inta, inta_mask;
  4024. u32 inta_fh;
  4025. if (!priv)
  4026. return IRQ_NONE;
  4027. spin_lock(&priv->lock);
  4028. /* Disable (but don't clear!) interrupts here to avoid
  4029. * back-to-back ISRs and sporadic interrupts from our NIC.
  4030. * If we have something to service, the tasklet will re-enable ints.
  4031. * If we *don't* have something, we'll re-enable before leaving here. */
  4032. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  4033. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  4034. /* Discover which interrupts are active/pending */
  4035. inta = iwl3945_read32(priv, CSR_INT);
  4036. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  4037. /* Ignore interrupt if there's nothing in NIC to service.
  4038. * This may be due to IRQ shared with another device,
  4039. * or due to sporadic interrupts thrown from our NIC. */
  4040. if (!inta && !inta_fh) {
  4041. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  4042. goto none;
  4043. }
  4044. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  4045. /* Hardware disappeared */
  4046. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  4047. goto unplugged;
  4048. }
  4049. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  4050. inta, inta_mask, inta_fh);
  4051. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  4052. tasklet_schedule(&priv->irq_tasklet);
  4053. unplugged:
  4054. spin_unlock(&priv->lock);
  4055. return IRQ_HANDLED;
  4056. none:
  4057. /* re-enable interrupts here since we don't have anything to service. */
  4058. iwl3945_enable_interrupts(priv);
  4059. spin_unlock(&priv->lock);
  4060. return IRQ_NONE;
  4061. }
  4062. /************************** EEPROM BANDS ****************************
  4063. *
  4064. * The iwl3945_eeprom_band definitions below provide the mapping from the
  4065. * EEPROM contents to the specific channel number supported for each
  4066. * band.
  4067. *
  4068. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  4069. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  4070. * The specific geography and calibration information for that channel
  4071. * is contained in the eeprom map itself.
  4072. *
  4073. * During init, we copy the eeprom information and channel map
  4074. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  4075. *
  4076. * channel_map_24/52 provides the index in the channel_info array for a
  4077. * given channel. We have to have two separate maps as there is channel
  4078. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  4079. * band_2
  4080. *
  4081. * A value of 0xff stored in the channel_map indicates that the channel
  4082. * is not supported by the hardware at all.
  4083. *
  4084. * A value of 0xfe in the channel_map indicates that the channel is not
  4085. * valid for Tx with the current hardware. This means that
  4086. * while the system can tune and receive on a given channel, it may not
  4087. * be able to associate or transmit any frames on that
  4088. * channel. There is no corresponding channel information for that
  4089. * entry.
  4090. *
  4091. *********************************************************************/
  4092. /* 2.4 GHz */
  4093. static const u8 iwl3945_eeprom_band_1[14] = {
  4094. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  4095. };
  4096. /* 5.2 GHz bands */
  4097. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  4098. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  4099. };
  4100. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  4101. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  4102. };
  4103. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  4104. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  4105. };
  4106. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  4107. 145, 149, 153, 157, 161, 165
  4108. };
  4109. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  4110. int *eeprom_ch_count,
  4111. const struct iwl3945_eeprom_channel
  4112. **eeprom_ch_info,
  4113. const u8 **eeprom_ch_index)
  4114. {
  4115. switch (band) {
  4116. case 1: /* 2.4GHz band */
  4117. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  4118. *eeprom_ch_info = priv->eeprom.band_1_channels;
  4119. *eeprom_ch_index = iwl3945_eeprom_band_1;
  4120. break;
  4121. case 2: /* 4.9GHz band */
  4122. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  4123. *eeprom_ch_info = priv->eeprom.band_2_channels;
  4124. *eeprom_ch_index = iwl3945_eeprom_band_2;
  4125. break;
  4126. case 3: /* 5.2GHz band */
  4127. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  4128. *eeprom_ch_info = priv->eeprom.band_3_channels;
  4129. *eeprom_ch_index = iwl3945_eeprom_band_3;
  4130. break;
  4131. case 4: /* 5.5GHz band */
  4132. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  4133. *eeprom_ch_info = priv->eeprom.band_4_channels;
  4134. *eeprom_ch_index = iwl3945_eeprom_band_4;
  4135. break;
  4136. case 5: /* 5.7GHz band */
  4137. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  4138. *eeprom_ch_info = priv->eeprom.band_5_channels;
  4139. *eeprom_ch_index = iwl3945_eeprom_band_5;
  4140. break;
  4141. default:
  4142. BUG();
  4143. return;
  4144. }
  4145. }
  4146. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  4147. int phymode, u16 channel)
  4148. {
  4149. int i;
  4150. switch (phymode) {
  4151. case MODE_IEEE80211A:
  4152. for (i = 14; i < priv->channel_count; i++) {
  4153. if (priv->channel_info[i].channel == channel)
  4154. return &priv->channel_info[i];
  4155. }
  4156. break;
  4157. case MODE_IEEE80211B:
  4158. case MODE_IEEE80211G:
  4159. if (channel >= 1 && channel <= 14)
  4160. return &priv->channel_info[channel - 1];
  4161. break;
  4162. }
  4163. return NULL;
  4164. }
  4165. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  4166. ? # x " " : "")
  4167. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  4168. {
  4169. int eeprom_ch_count = 0;
  4170. const u8 *eeprom_ch_index = NULL;
  4171. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  4172. int band, ch;
  4173. struct iwl3945_channel_info *ch_info;
  4174. if (priv->channel_count) {
  4175. IWL_DEBUG_INFO("Channel map already initialized.\n");
  4176. return 0;
  4177. }
  4178. if (priv->eeprom.version < 0x2f) {
  4179. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  4180. priv->eeprom.version);
  4181. return -EINVAL;
  4182. }
  4183. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  4184. priv->channel_count =
  4185. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  4186. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  4187. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  4188. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  4189. ARRAY_SIZE(iwl3945_eeprom_band_5);
  4190. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  4191. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  4192. priv->channel_count, GFP_KERNEL);
  4193. if (!priv->channel_info) {
  4194. IWL_ERROR("Could not allocate channel_info\n");
  4195. priv->channel_count = 0;
  4196. return -ENOMEM;
  4197. }
  4198. ch_info = priv->channel_info;
  4199. /* Loop through the 5 EEPROM bands adding them in order to the
  4200. * channel map we maintain (that contains additional information than
  4201. * what just in the EEPROM) */
  4202. for (band = 1; band <= 5; band++) {
  4203. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  4204. &eeprom_ch_info, &eeprom_ch_index);
  4205. /* Loop through each band adding each of the channels */
  4206. for (ch = 0; ch < eeprom_ch_count; ch++) {
  4207. ch_info->channel = eeprom_ch_index[ch];
  4208. ch_info->phymode = (band == 1) ? MODE_IEEE80211B :
  4209. MODE_IEEE80211A;
  4210. /* permanently store EEPROM's channel regulatory flags
  4211. * and max power in channel info database. */
  4212. ch_info->eeprom = eeprom_ch_info[ch];
  4213. /* Copy the run-time flags so they are there even on
  4214. * invalid channels */
  4215. ch_info->flags = eeprom_ch_info[ch].flags;
  4216. if (!(is_channel_valid(ch_info))) {
  4217. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  4218. "No traffic\n",
  4219. ch_info->channel,
  4220. ch_info->flags,
  4221. is_channel_a_band(ch_info) ?
  4222. "5.2" : "2.4");
  4223. ch_info++;
  4224. continue;
  4225. }
  4226. /* Initialize regulatory-based run-time data */
  4227. ch_info->max_power_avg = ch_info->curr_txpow =
  4228. eeprom_ch_info[ch].max_power_avg;
  4229. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  4230. ch_info->min_power = 0;
  4231. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  4232. " %ddBm): Ad-Hoc %ssupported\n",
  4233. ch_info->channel,
  4234. is_channel_a_band(ch_info) ?
  4235. "5.2" : "2.4",
  4236. CHECK_AND_PRINT(IBSS),
  4237. CHECK_AND_PRINT(ACTIVE),
  4238. CHECK_AND_PRINT(RADAR),
  4239. CHECK_AND_PRINT(WIDE),
  4240. CHECK_AND_PRINT(NARROW),
  4241. CHECK_AND_PRINT(DFS),
  4242. eeprom_ch_info[ch].flags,
  4243. eeprom_ch_info[ch].max_power_avg,
  4244. ((eeprom_ch_info[ch].
  4245. flags & EEPROM_CHANNEL_IBSS)
  4246. && !(eeprom_ch_info[ch].
  4247. flags & EEPROM_CHANNEL_RADAR))
  4248. ? "" : "not ");
  4249. /* Set the user_txpower_limit to the highest power
  4250. * supported by any channel */
  4251. if (eeprom_ch_info[ch].max_power_avg >
  4252. priv->user_txpower_limit)
  4253. priv->user_txpower_limit =
  4254. eeprom_ch_info[ch].max_power_avg;
  4255. ch_info++;
  4256. }
  4257. }
  4258. if (iwl3945_txpower_set_from_eeprom(priv))
  4259. return -EIO;
  4260. return 0;
  4261. }
  4262. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  4263. * sending probe req. This should be set long enough to hear probe responses
  4264. * from more than one AP. */
  4265. #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
  4266. #define IWL_ACTIVE_DWELL_TIME_52 (10)
  4267. /* For faster active scanning, scan will move to the next channel if fewer than
  4268. * PLCP_QUIET_THRESH packets are heard on this channel within
  4269. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  4270. * time if it's a quiet channel (nothing responded to our probe, and there's
  4271. * no other traffic).
  4272. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  4273. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  4274. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
  4275. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  4276. * Must be set longer than active dwell time.
  4277. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  4278. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  4279. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  4280. #define IWL_PASSIVE_DWELL_BASE (100)
  4281. #define IWL_CHANNEL_TUNE_TIME 5
  4282. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv, int phymode)
  4283. {
  4284. if (phymode == MODE_IEEE80211A)
  4285. return IWL_ACTIVE_DWELL_TIME_52;
  4286. else
  4287. return IWL_ACTIVE_DWELL_TIME_24;
  4288. }
  4289. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv, int phymode)
  4290. {
  4291. u16 active = iwl3945_get_active_dwell_time(priv, phymode);
  4292. u16 passive = (phymode != MODE_IEEE80211A) ?
  4293. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4294. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4295. if (iwl3945_is_associated(priv)) {
  4296. /* If we're associated, we clamp the maximum passive
  4297. * dwell time to be 98% of the beacon interval (minus
  4298. * 2 * channel tune time) */
  4299. passive = priv->beacon_int;
  4300. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4301. passive = IWL_PASSIVE_DWELL_BASE;
  4302. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4303. }
  4304. if (passive <= active)
  4305. passive = active + 1;
  4306. return passive;
  4307. }
  4308. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv, int phymode,
  4309. u8 is_active, u8 direct_mask,
  4310. struct iwl3945_scan_channel *scan_ch)
  4311. {
  4312. const struct ieee80211_channel *channels = NULL;
  4313. const struct ieee80211_hw_mode *hw_mode;
  4314. const struct iwl3945_channel_info *ch_info;
  4315. u16 passive_dwell = 0;
  4316. u16 active_dwell = 0;
  4317. int added, i;
  4318. hw_mode = iwl3945_get_hw_mode(priv, phymode);
  4319. if (!hw_mode)
  4320. return 0;
  4321. channels = hw_mode->channels;
  4322. active_dwell = iwl3945_get_active_dwell_time(priv, phymode);
  4323. passive_dwell = iwl3945_get_passive_dwell_time(priv, phymode);
  4324. for (i = 0, added = 0; i < hw_mode->num_channels; i++) {
  4325. if (channels[i].chan ==
  4326. le16_to_cpu(priv->active_rxon.channel)) {
  4327. if (iwl3945_is_associated(priv)) {
  4328. IWL_DEBUG_SCAN
  4329. ("Skipping current channel %d\n",
  4330. le16_to_cpu(priv->active_rxon.channel));
  4331. continue;
  4332. }
  4333. } else if (priv->only_active_channel)
  4334. continue;
  4335. scan_ch->channel = channels[i].chan;
  4336. ch_info = iwl3945_get_channel_info(priv, phymode, scan_ch->channel);
  4337. if (!is_channel_valid(ch_info)) {
  4338. IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
  4339. scan_ch->channel);
  4340. continue;
  4341. }
  4342. if (!is_active || is_channel_passive(ch_info) ||
  4343. !(channels[i].flag & IEEE80211_CHAN_W_ACTIVE_SCAN))
  4344. scan_ch->type = 0; /* passive */
  4345. else
  4346. scan_ch->type = 1; /* active */
  4347. if (scan_ch->type & 1)
  4348. scan_ch->type |= (direct_mask << 1);
  4349. if (is_channel_narrow(ch_info))
  4350. scan_ch->type |= (1 << 7);
  4351. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4352. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4353. /* Set txpower levels to defaults */
  4354. scan_ch->tpc.dsp_atten = 110;
  4355. /* scan_pwr_info->tpc.dsp_atten; */
  4356. /*scan_pwr_info->tpc.tx_gain; */
  4357. if (phymode == MODE_IEEE80211A)
  4358. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4359. else {
  4360. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4361. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4362. * power level:
  4363. * scan_ch->tpc.tx_gain = ((1<<5) | (2 << 3)) | 3;
  4364. */
  4365. }
  4366. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4367. scan_ch->channel,
  4368. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4369. (scan_ch->type & 1) ?
  4370. active_dwell : passive_dwell);
  4371. scan_ch++;
  4372. added++;
  4373. }
  4374. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4375. return added;
  4376. }
  4377. static void iwl3945_reset_channel_flag(struct iwl3945_priv *priv)
  4378. {
  4379. int i, j;
  4380. for (i = 0; i < 3; i++) {
  4381. struct ieee80211_hw_mode *hw_mode = (void *)&priv->modes[i];
  4382. for (j = 0; j < hw_mode->num_channels; j++)
  4383. hw_mode->channels[j].flag = hw_mode->channels[j].val;
  4384. }
  4385. }
  4386. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4387. struct ieee80211_rate *rates)
  4388. {
  4389. int i;
  4390. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4391. rates[i].rate = iwl3945_rates[i].ieee * 5;
  4392. rates[i].val = i; /* Rate scaling will work on indexes */
  4393. rates[i].val2 = i;
  4394. rates[i].flags = IEEE80211_RATE_SUPPORTED;
  4395. /* Only OFDM have the bits-per-symbol set */
  4396. if ((i <= IWL_LAST_OFDM_RATE) && (i >= IWL_FIRST_OFDM_RATE))
  4397. rates[i].flags |= IEEE80211_RATE_OFDM;
  4398. else {
  4399. /*
  4400. * If CCK 1M then set rate flag to CCK else CCK_2
  4401. * which is CCK | PREAMBLE2
  4402. */
  4403. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4404. IEEE80211_RATE_CCK : IEEE80211_RATE_CCK_2;
  4405. }
  4406. /* Set up which ones are basic rates... */
  4407. if (IWL_BASIC_RATES_MASK & (1 << i))
  4408. rates[i].flags |= IEEE80211_RATE_BASIC;
  4409. }
  4410. }
  4411. /**
  4412. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4413. */
  4414. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4415. {
  4416. struct iwl3945_channel_info *ch;
  4417. struct ieee80211_hw_mode *modes;
  4418. struct ieee80211_channel *channels;
  4419. struct ieee80211_channel *geo_ch;
  4420. struct ieee80211_rate *rates;
  4421. int i = 0;
  4422. enum {
  4423. A = 0,
  4424. B = 1,
  4425. G = 2,
  4426. };
  4427. int mode_count = 3;
  4428. if (priv->modes) {
  4429. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4430. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4431. return 0;
  4432. }
  4433. modes = kzalloc(sizeof(struct ieee80211_hw_mode) * mode_count,
  4434. GFP_KERNEL);
  4435. if (!modes)
  4436. return -ENOMEM;
  4437. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4438. priv->channel_count, GFP_KERNEL);
  4439. if (!channels) {
  4440. kfree(modes);
  4441. return -ENOMEM;
  4442. }
  4443. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_MAX_RATES + 1)),
  4444. GFP_KERNEL);
  4445. if (!rates) {
  4446. kfree(modes);
  4447. kfree(channels);
  4448. return -ENOMEM;
  4449. }
  4450. /* 0 = 802.11a
  4451. * 1 = 802.11b
  4452. * 2 = 802.11g
  4453. */
  4454. /* 5.2GHz channels start after the 2.4GHz channels */
  4455. modes[A].mode = MODE_IEEE80211A;
  4456. modes[A].channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4457. modes[A].rates = &rates[4];
  4458. modes[A].num_rates = 8; /* just OFDM */
  4459. modes[A].num_channels = 0;
  4460. modes[B].mode = MODE_IEEE80211B;
  4461. modes[B].channels = channels;
  4462. modes[B].rates = rates;
  4463. modes[B].num_rates = 4; /* just CCK */
  4464. modes[B].num_channels = 0;
  4465. modes[G].mode = MODE_IEEE80211G;
  4466. modes[G].channels = channels;
  4467. modes[G].rates = rates;
  4468. modes[G].num_rates = 12; /* OFDM & CCK */
  4469. modes[G].num_channels = 0;
  4470. priv->ieee_channels = channels;
  4471. priv->ieee_rates = rates;
  4472. iwl3945_init_hw_rates(priv, rates);
  4473. for (i = 0, geo_ch = channels; i < priv->channel_count; i++) {
  4474. ch = &priv->channel_info[i];
  4475. if (!is_channel_valid(ch)) {
  4476. IWL_DEBUG_INFO("Channel %d [%sGHz] is restricted -- "
  4477. "skipping.\n",
  4478. ch->channel, is_channel_a_band(ch) ?
  4479. "5.2" : "2.4");
  4480. continue;
  4481. }
  4482. if (is_channel_a_band(ch))
  4483. geo_ch = &modes[A].channels[modes[A].num_channels++];
  4484. else {
  4485. geo_ch = &modes[B].channels[modes[B].num_channels++];
  4486. modes[G].num_channels++;
  4487. }
  4488. geo_ch->freq = ieee80211chan2mhz(ch->channel);
  4489. geo_ch->chan = ch->channel;
  4490. geo_ch->power_level = ch->max_power_avg;
  4491. geo_ch->antenna_max = 0xff;
  4492. if (is_channel_valid(ch)) {
  4493. geo_ch->flag = IEEE80211_CHAN_W_SCAN;
  4494. if (ch->flags & EEPROM_CHANNEL_IBSS)
  4495. geo_ch->flag |= IEEE80211_CHAN_W_IBSS;
  4496. if (ch->flags & EEPROM_CHANNEL_ACTIVE)
  4497. geo_ch->flag |= IEEE80211_CHAN_W_ACTIVE_SCAN;
  4498. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4499. geo_ch->flag |= IEEE80211_CHAN_W_RADAR_DETECT;
  4500. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4501. priv->max_channel_txpower_limit =
  4502. ch->max_power_avg;
  4503. }
  4504. geo_ch->val = geo_ch->flag;
  4505. }
  4506. if ((modes[A].num_channels == 0) && priv->is_abg) {
  4507. printk(KERN_INFO DRV_NAME
  4508. ": Incorrectly detected BG card as ABG. Please send "
  4509. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4510. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4511. priv->is_abg = 0;
  4512. }
  4513. printk(KERN_INFO DRV_NAME
  4514. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4515. modes[G].num_channels, modes[A].num_channels);
  4516. /*
  4517. * NOTE: We register these in preference of order -- the
  4518. * stack doesn't currently (as of 7.0.6 / Apr 24 '07) pick
  4519. * a phymode based on rates or AP capabilities but seems to
  4520. * configure it purely on if the channel being configured
  4521. * is supported by a mode -- and the first match is taken
  4522. */
  4523. if (modes[G].num_channels)
  4524. ieee80211_register_hwmode(priv->hw, &modes[G]);
  4525. if (modes[B].num_channels)
  4526. ieee80211_register_hwmode(priv->hw, &modes[B]);
  4527. if (modes[A].num_channels)
  4528. ieee80211_register_hwmode(priv->hw, &modes[A]);
  4529. priv->modes = modes;
  4530. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4531. return 0;
  4532. }
  4533. /******************************************************************************
  4534. *
  4535. * uCode download functions
  4536. *
  4537. ******************************************************************************/
  4538. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4539. {
  4540. if (priv->ucode_code.v_addr != NULL) {
  4541. pci_free_consistent(priv->pci_dev,
  4542. priv->ucode_code.len,
  4543. priv->ucode_code.v_addr,
  4544. priv->ucode_code.p_addr);
  4545. priv->ucode_code.v_addr = NULL;
  4546. }
  4547. if (priv->ucode_data.v_addr != NULL) {
  4548. pci_free_consistent(priv->pci_dev,
  4549. priv->ucode_data.len,
  4550. priv->ucode_data.v_addr,
  4551. priv->ucode_data.p_addr);
  4552. priv->ucode_data.v_addr = NULL;
  4553. }
  4554. if (priv->ucode_data_backup.v_addr != NULL) {
  4555. pci_free_consistent(priv->pci_dev,
  4556. priv->ucode_data_backup.len,
  4557. priv->ucode_data_backup.v_addr,
  4558. priv->ucode_data_backup.p_addr);
  4559. priv->ucode_data_backup.v_addr = NULL;
  4560. }
  4561. if (priv->ucode_init.v_addr != NULL) {
  4562. pci_free_consistent(priv->pci_dev,
  4563. priv->ucode_init.len,
  4564. priv->ucode_init.v_addr,
  4565. priv->ucode_init.p_addr);
  4566. priv->ucode_init.v_addr = NULL;
  4567. }
  4568. if (priv->ucode_init_data.v_addr != NULL) {
  4569. pci_free_consistent(priv->pci_dev,
  4570. priv->ucode_init_data.len,
  4571. priv->ucode_init_data.v_addr,
  4572. priv->ucode_init_data.p_addr);
  4573. priv->ucode_init_data.v_addr = NULL;
  4574. }
  4575. if (priv->ucode_boot.v_addr != NULL) {
  4576. pci_free_consistent(priv->pci_dev,
  4577. priv->ucode_boot.len,
  4578. priv->ucode_boot.v_addr,
  4579. priv->ucode_boot.p_addr);
  4580. priv->ucode_boot.v_addr = NULL;
  4581. }
  4582. }
  4583. /**
  4584. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4585. * looking at all data.
  4586. */
  4587. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
  4588. {
  4589. u32 val;
  4590. u32 save_len = len;
  4591. int rc = 0;
  4592. u32 errcnt;
  4593. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4594. rc = iwl3945_grab_nic_access(priv);
  4595. if (rc)
  4596. return rc;
  4597. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4598. errcnt = 0;
  4599. for (; len > 0; len -= sizeof(u32), image++) {
  4600. /* read data comes through single port, auto-incr addr */
  4601. /* NOTE: Use the debugless read so we don't flood kernel log
  4602. * if IWL_DL_IO is set */
  4603. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4604. if (val != le32_to_cpu(*image)) {
  4605. IWL_ERROR("uCode INST section is invalid at "
  4606. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4607. save_len - len, val, le32_to_cpu(*image));
  4608. rc = -EIO;
  4609. errcnt++;
  4610. if (errcnt >= 20)
  4611. break;
  4612. }
  4613. }
  4614. iwl3945_release_nic_access(priv);
  4615. if (!errcnt)
  4616. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4617. return rc;
  4618. }
  4619. /**
  4620. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4621. * using sample data 100 bytes apart. If these sample points are good,
  4622. * it's a pretty good bet that everything between them is good, too.
  4623. */
  4624. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4625. {
  4626. u32 val;
  4627. int rc = 0;
  4628. u32 errcnt = 0;
  4629. u32 i;
  4630. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4631. rc = iwl3945_grab_nic_access(priv);
  4632. if (rc)
  4633. return rc;
  4634. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4635. /* read data comes through single port, auto-incr addr */
  4636. /* NOTE: Use the debugless read so we don't flood kernel log
  4637. * if IWL_DL_IO is set */
  4638. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4639. i + RTC_INST_LOWER_BOUND);
  4640. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4641. if (val != le32_to_cpu(*image)) {
  4642. #if 0 /* Enable this if you want to see details */
  4643. IWL_ERROR("uCode INST section is invalid at "
  4644. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4645. i, val, *image);
  4646. #endif
  4647. rc = -EIO;
  4648. errcnt++;
  4649. if (errcnt >= 3)
  4650. break;
  4651. }
  4652. }
  4653. iwl3945_release_nic_access(priv);
  4654. return rc;
  4655. }
  4656. /**
  4657. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4658. * and verify its contents
  4659. */
  4660. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4661. {
  4662. __le32 *image;
  4663. u32 len;
  4664. int rc = 0;
  4665. /* Try bootstrap */
  4666. image = (__le32 *)priv->ucode_boot.v_addr;
  4667. len = priv->ucode_boot.len;
  4668. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4669. if (rc == 0) {
  4670. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4671. return 0;
  4672. }
  4673. /* Try initialize */
  4674. image = (__le32 *)priv->ucode_init.v_addr;
  4675. len = priv->ucode_init.len;
  4676. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4677. if (rc == 0) {
  4678. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4679. return 0;
  4680. }
  4681. /* Try runtime/protocol */
  4682. image = (__le32 *)priv->ucode_code.v_addr;
  4683. len = priv->ucode_code.len;
  4684. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4685. if (rc == 0) {
  4686. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4687. return 0;
  4688. }
  4689. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4690. /* Since nothing seems to match, show first several data entries in
  4691. * instruction SRAM, so maybe visual inspection will give a clue.
  4692. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4693. image = (__le32 *)priv->ucode_boot.v_addr;
  4694. len = priv->ucode_boot.len;
  4695. rc = iwl3945_verify_inst_full(priv, image, len);
  4696. return rc;
  4697. }
  4698. /* check contents of special bootstrap uCode SRAM */
  4699. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4700. {
  4701. __le32 *image = priv->ucode_boot.v_addr;
  4702. u32 len = priv->ucode_boot.len;
  4703. u32 reg;
  4704. u32 val;
  4705. IWL_DEBUG_INFO("Begin verify bsm\n");
  4706. /* verify BSM SRAM contents */
  4707. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4708. for (reg = BSM_SRAM_LOWER_BOUND;
  4709. reg < BSM_SRAM_LOWER_BOUND + len;
  4710. reg += sizeof(u32), image ++) {
  4711. val = iwl3945_read_prph(priv, reg);
  4712. if (val != le32_to_cpu(*image)) {
  4713. IWL_ERROR("BSM uCode verification failed at "
  4714. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4715. BSM_SRAM_LOWER_BOUND,
  4716. reg - BSM_SRAM_LOWER_BOUND, len,
  4717. val, le32_to_cpu(*image));
  4718. return -EIO;
  4719. }
  4720. }
  4721. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4722. return 0;
  4723. }
  4724. /**
  4725. * iwl3945_load_bsm - Load bootstrap instructions
  4726. *
  4727. * BSM operation:
  4728. *
  4729. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4730. * in special SRAM that does not power down during RFKILL. When powering back
  4731. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4732. * the bootstrap program into the on-board processor, and starts it.
  4733. *
  4734. * The bootstrap program loads (via DMA) instructions and data for a new
  4735. * program from host DRAM locations indicated by the host driver in the
  4736. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4737. * automatically.
  4738. *
  4739. * When initializing the NIC, the host driver points the BSM to the
  4740. * "initialize" uCode image. This uCode sets up some internal data, then
  4741. * notifies host via "initialize alive" that it is complete.
  4742. *
  4743. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4744. * normal runtime uCode instructions and a backup uCode data cache buffer
  4745. * (filled initially with starting data values for the on-board processor),
  4746. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4747. * which begins normal operation.
  4748. *
  4749. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4750. * the backup data cache in DRAM before SRAM is powered down.
  4751. *
  4752. * When powering back up, the BSM loads the bootstrap program. This reloads
  4753. * the runtime uCode instructions and the backup data cache into SRAM,
  4754. * and re-launches the runtime uCode from where it left off.
  4755. */
  4756. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4757. {
  4758. __le32 *image = priv->ucode_boot.v_addr;
  4759. u32 len = priv->ucode_boot.len;
  4760. dma_addr_t pinst;
  4761. dma_addr_t pdata;
  4762. u32 inst_len;
  4763. u32 data_len;
  4764. int rc;
  4765. int i;
  4766. u32 done;
  4767. u32 reg_offset;
  4768. IWL_DEBUG_INFO("Begin load bsm\n");
  4769. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4770. if (len > IWL_MAX_BSM_SIZE)
  4771. return -EINVAL;
  4772. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4773. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4774. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4775. * after the "initialize" uCode has run, to point to
  4776. * runtime/protocol instructions and backup data cache. */
  4777. pinst = priv->ucode_init.p_addr;
  4778. pdata = priv->ucode_init_data.p_addr;
  4779. inst_len = priv->ucode_init.len;
  4780. data_len = priv->ucode_init_data.len;
  4781. rc = iwl3945_grab_nic_access(priv);
  4782. if (rc)
  4783. return rc;
  4784. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4785. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4786. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4787. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4788. /* Fill BSM memory with bootstrap instructions */
  4789. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4790. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4791. reg_offset += sizeof(u32), image++)
  4792. _iwl3945_write_prph(priv, reg_offset,
  4793. le32_to_cpu(*image));
  4794. rc = iwl3945_verify_bsm(priv);
  4795. if (rc) {
  4796. iwl3945_release_nic_access(priv);
  4797. return rc;
  4798. }
  4799. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4800. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4801. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4802. RTC_INST_LOWER_BOUND);
  4803. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4804. /* Load bootstrap code into instruction SRAM now,
  4805. * to prepare to load "initialize" uCode */
  4806. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4807. BSM_WR_CTRL_REG_BIT_START);
  4808. /* Wait for load of bootstrap uCode to finish */
  4809. for (i = 0; i < 100; i++) {
  4810. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4811. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4812. break;
  4813. udelay(10);
  4814. }
  4815. if (i < 100)
  4816. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4817. else {
  4818. IWL_ERROR("BSM write did not complete!\n");
  4819. return -EIO;
  4820. }
  4821. /* Enable future boot loads whenever power management unit triggers it
  4822. * (e.g. when powering back up after power-save shutdown) */
  4823. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4824. BSM_WR_CTRL_REG_BIT_START_EN);
  4825. iwl3945_release_nic_access(priv);
  4826. return 0;
  4827. }
  4828. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4829. {
  4830. /* Remove all resets to allow NIC to operate */
  4831. iwl3945_write32(priv, CSR_RESET, 0);
  4832. }
  4833. static int iwl3945_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
  4834. {
  4835. desc->v_addr = pci_alloc_consistent(pci_dev, desc->len, &desc->p_addr);
  4836. return (desc->v_addr != NULL) ? 0 : -ENOMEM;
  4837. }
  4838. /**
  4839. * iwl3945_read_ucode - Read uCode images from disk file.
  4840. *
  4841. * Copy into buffers for card to fetch via bus-mastering
  4842. */
  4843. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4844. {
  4845. struct iwl3945_ucode *ucode;
  4846. int ret = 0;
  4847. const struct firmware *ucode_raw;
  4848. /* firmware file name contains uCode/driver compatibility version */
  4849. const char *name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode";
  4850. u8 *src;
  4851. size_t len;
  4852. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4853. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4854. * request_firmware() is synchronous, file is in memory on return. */
  4855. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  4856. if (ret < 0) {
  4857. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4858. name, ret);
  4859. goto error;
  4860. }
  4861. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4862. name, ucode_raw->size);
  4863. /* Make sure that we got at least our header! */
  4864. if (ucode_raw->size < sizeof(*ucode)) {
  4865. IWL_ERROR("File size way too small!\n");
  4866. ret = -EINVAL;
  4867. goto err_release;
  4868. }
  4869. /* Data from ucode file: header followed by uCode images */
  4870. ucode = (void *)ucode_raw->data;
  4871. ver = le32_to_cpu(ucode->ver);
  4872. inst_size = le32_to_cpu(ucode->inst_size);
  4873. data_size = le32_to_cpu(ucode->data_size);
  4874. init_size = le32_to_cpu(ucode->init_size);
  4875. init_data_size = le32_to_cpu(ucode->init_data_size);
  4876. boot_size = le32_to_cpu(ucode->boot_size);
  4877. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  4878. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4879. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4880. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4881. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4882. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4883. /* Verify size of file vs. image size info in file's header */
  4884. if (ucode_raw->size < sizeof(*ucode) +
  4885. inst_size + data_size + init_size +
  4886. init_data_size + boot_size) {
  4887. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4888. (int)ucode_raw->size);
  4889. ret = -EINVAL;
  4890. goto err_release;
  4891. }
  4892. /* Verify that uCode images will fit in card's SRAM */
  4893. if (inst_size > IWL_MAX_INST_SIZE) {
  4894. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4895. inst_size);
  4896. ret = -EINVAL;
  4897. goto err_release;
  4898. }
  4899. if (data_size > IWL_MAX_DATA_SIZE) {
  4900. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4901. data_size);
  4902. ret = -EINVAL;
  4903. goto err_release;
  4904. }
  4905. if (init_size > IWL_MAX_INST_SIZE) {
  4906. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4907. init_size);
  4908. ret = -EINVAL;
  4909. goto err_release;
  4910. }
  4911. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4912. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4913. init_data_size);
  4914. ret = -EINVAL;
  4915. goto err_release;
  4916. }
  4917. if (boot_size > IWL_MAX_BSM_SIZE) {
  4918. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4919. boot_size);
  4920. ret = -EINVAL;
  4921. goto err_release;
  4922. }
  4923. /* Allocate ucode buffers for card's bus-master loading ... */
  4924. /* Runtime instructions and 2 copies of data:
  4925. * 1) unmodified from disk
  4926. * 2) backup cache for save/restore during power-downs */
  4927. priv->ucode_code.len = inst_size;
  4928. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4929. priv->ucode_data.len = data_size;
  4930. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4931. priv->ucode_data_backup.len = data_size;
  4932. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4933. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4934. !priv->ucode_data_backup.v_addr)
  4935. goto err_pci_alloc;
  4936. /* Initialization instructions and data */
  4937. if (init_size && init_data_size) {
  4938. priv->ucode_init.len = init_size;
  4939. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4940. priv->ucode_init_data.len = init_data_size;
  4941. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4942. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4943. goto err_pci_alloc;
  4944. }
  4945. /* Bootstrap (instructions only, no data) */
  4946. if (boot_size) {
  4947. priv->ucode_boot.len = boot_size;
  4948. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4949. if (!priv->ucode_boot.v_addr)
  4950. goto err_pci_alloc;
  4951. }
  4952. /* Copy images into buffers for card's bus-master reads ... */
  4953. /* Runtime instructions (first block of data in file) */
  4954. src = &ucode->data[0];
  4955. len = priv->ucode_code.len;
  4956. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4957. memcpy(priv->ucode_code.v_addr, src, len);
  4958. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4959. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4960. /* Runtime data (2nd block)
  4961. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4962. src = &ucode->data[inst_size];
  4963. len = priv->ucode_data.len;
  4964. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4965. memcpy(priv->ucode_data.v_addr, src, len);
  4966. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4967. /* Initialization instructions (3rd block) */
  4968. if (init_size) {
  4969. src = &ucode->data[inst_size + data_size];
  4970. len = priv->ucode_init.len;
  4971. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4972. len);
  4973. memcpy(priv->ucode_init.v_addr, src, len);
  4974. }
  4975. /* Initialization data (4th block) */
  4976. if (init_data_size) {
  4977. src = &ucode->data[inst_size + data_size + init_size];
  4978. len = priv->ucode_init_data.len;
  4979. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4980. (int)len);
  4981. memcpy(priv->ucode_init_data.v_addr, src, len);
  4982. }
  4983. /* Bootstrap instructions (5th block) */
  4984. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4985. len = priv->ucode_boot.len;
  4986. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4987. (int)len);
  4988. memcpy(priv->ucode_boot.v_addr, src, len);
  4989. /* We have our copies now, allow OS release its copies */
  4990. release_firmware(ucode_raw);
  4991. return 0;
  4992. err_pci_alloc:
  4993. IWL_ERROR("failed to allocate pci memory\n");
  4994. ret = -ENOMEM;
  4995. iwl3945_dealloc_ucode_pci(priv);
  4996. err_release:
  4997. release_firmware(ucode_raw);
  4998. error:
  4999. return ret;
  5000. }
  5001. /**
  5002. * iwl3945_set_ucode_ptrs - Set uCode address location
  5003. *
  5004. * Tell initialization uCode where to find runtime uCode.
  5005. *
  5006. * BSM registers initially contain pointers to initialization uCode.
  5007. * We need to replace them to load runtime uCode inst and data,
  5008. * and to save runtime data when powering down.
  5009. */
  5010. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  5011. {
  5012. dma_addr_t pinst;
  5013. dma_addr_t pdata;
  5014. int rc = 0;
  5015. unsigned long flags;
  5016. /* bits 31:0 for 3945 */
  5017. pinst = priv->ucode_code.p_addr;
  5018. pdata = priv->ucode_data_backup.p_addr;
  5019. spin_lock_irqsave(&priv->lock, flags);
  5020. rc = iwl3945_grab_nic_access(priv);
  5021. if (rc) {
  5022. spin_unlock_irqrestore(&priv->lock, flags);
  5023. return rc;
  5024. }
  5025. /* Tell bootstrap uCode where to find image to load */
  5026. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  5027. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  5028. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  5029. priv->ucode_data.len);
  5030. /* Inst bytecount must be last to set up, bit 31 signals uCode
  5031. * that all new ptr/size info is in place */
  5032. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  5033. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  5034. iwl3945_release_nic_access(priv);
  5035. spin_unlock_irqrestore(&priv->lock, flags);
  5036. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  5037. return rc;
  5038. }
  5039. /**
  5040. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  5041. *
  5042. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  5043. *
  5044. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  5045. */
  5046. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  5047. {
  5048. /* Check alive response for "valid" sign from uCode */
  5049. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  5050. /* We had an error bringing up the hardware, so take it
  5051. * all the way back down so we can try again */
  5052. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  5053. goto restart;
  5054. }
  5055. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  5056. * This is a paranoid check, because we would not have gotten the
  5057. * "initialize" alive if code weren't properly loaded. */
  5058. if (iwl3945_verify_ucode(priv)) {
  5059. /* Runtime instruction load was bad;
  5060. * take it all the way back down so we can try again */
  5061. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  5062. goto restart;
  5063. }
  5064. /* Send pointers to protocol/runtime uCode image ... init code will
  5065. * load and launch runtime uCode, which will send us another "Alive"
  5066. * notification. */
  5067. IWL_DEBUG_INFO("Initialization Alive received.\n");
  5068. if (iwl3945_set_ucode_ptrs(priv)) {
  5069. /* Runtime instruction load won't happen;
  5070. * take it all the way back down so we can try again */
  5071. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  5072. goto restart;
  5073. }
  5074. return;
  5075. restart:
  5076. queue_work(priv->workqueue, &priv->restart);
  5077. }
  5078. /**
  5079. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  5080. * from protocol/runtime uCode (initialization uCode's
  5081. * Alive gets handled by iwl3945_init_alive_start()).
  5082. */
  5083. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  5084. {
  5085. int rc = 0;
  5086. int thermal_spin = 0;
  5087. u32 rfkill;
  5088. IWL_DEBUG_INFO("Runtime Alive received.\n");
  5089. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  5090. /* We had an error bringing up the hardware, so take it
  5091. * all the way back down so we can try again */
  5092. IWL_DEBUG_INFO("Alive failed.\n");
  5093. goto restart;
  5094. }
  5095. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  5096. * This is a paranoid check, because we would not have gotten the
  5097. * "runtime" alive if code weren't properly loaded. */
  5098. if (iwl3945_verify_ucode(priv)) {
  5099. /* Runtime instruction load was bad;
  5100. * take it all the way back down so we can try again */
  5101. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  5102. goto restart;
  5103. }
  5104. iwl3945_clear_stations_table(priv);
  5105. rc = iwl3945_grab_nic_access(priv);
  5106. if (rc) {
  5107. IWL_WARNING("Can not read rfkill status from adapter\n");
  5108. return;
  5109. }
  5110. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  5111. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  5112. iwl3945_release_nic_access(priv);
  5113. if (rfkill & 0x1) {
  5114. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  5115. /* if rfkill is not on, then wait for thermal
  5116. * sensor in adapter to kick in */
  5117. while (iwl3945_hw_get_temperature(priv) == 0) {
  5118. thermal_spin++;
  5119. udelay(10);
  5120. }
  5121. if (thermal_spin)
  5122. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  5123. thermal_spin * 10);
  5124. } else
  5125. set_bit(STATUS_RF_KILL_HW, &priv->status);
  5126. /* After the ALIVE response, we can send commands to 3945 uCode */
  5127. set_bit(STATUS_ALIVE, &priv->status);
  5128. /* Clear out the uCode error bit if it is set */
  5129. clear_bit(STATUS_FW_ERROR, &priv->status);
  5130. rc = iwl3945_init_channel_map(priv);
  5131. if (rc) {
  5132. IWL_ERROR("initializing regulatory failed: %d\n", rc);
  5133. return;
  5134. }
  5135. iwl3945_init_geos(priv);
  5136. if (iwl3945_is_rfkill(priv))
  5137. return;
  5138. if (!priv->mac80211_registered) {
  5139. /* Unlock so any user space entry points can call back into
  5140. * the driver without a deadlock... */
  5141. mutex_unlock(&priv->mutex);
  5142. iwl3945_rate_control_register(priv->hw);
  5143. rc = ieee80211_register_hw(priv->hw);
  5144. priv->hw->conf.beacon_int = 100;
  5145. mutex_lock(&priv->mutex);
  5146. if (rc) {
  5147. iwl3945_rate_control_unregister(priv->hw);
  5148. IWL_ERROR("Failed to register network "
  5149. "device (error %d)\n", rc);
  5150. return;
  5151. }
  5152. priv->mac80211_registered = 1;
  5153. iwl3945_reset_channel_flag(priv);
  5154. } else
  5155. ieee80211_start_queues(priv->hw);
  5156. priv->active_rate = priv->rates_mask;
  5157. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  5158. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  5159. if (iwl3945_is_associated(priv)) {
  5160. struct iwl3945_rxon_cmd *active_rxon =
  5161. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  5162. memcpy(&priv->staging_rxon, &priv->active_rxon,
  5163. sizeof(priv->staging_rxon));
  5164. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5165. } else {
  5166. /* Initialize our rx_config data */
  5167. iwl3945_connection_init_rx_config(priv);
  5168. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  5169. }
  5170. /* Configure Bluetooth device coexistence support */
  5171. iwl3945_send_bt_config(priv);
  5172. /* Configure the adapter for unassociated operation */
  5173. iwl3945_commit_rxon(priv);
  5174. /* At this point, the NIC is initialized and operational */
  5175. priv->notif_missed_beacons = 0;
  5176. set_bit(STATUS_READY, &priv->status);
  5177. iwl3945_reg_txpower_periodic(priv);
  5178. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  5179. if (priv->error_recovering)
  5180. iwl3945_error_recovery(priv);
  5181. return;
  5182. restart:
  5183. queue_work(priv->workqueue, &priv->restart);
  5184. }
  5185. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  5186. static void __iwl3945_down(struct iwl3945_priv *priv)
  5187. {
  5188. unsigned long flags;
  5189. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  5190. struct ieee80211_conf *conf = NULL;
  5191. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  5192. conf = ieee80211_get_hw_conf(priv->hw);
  5193. if (!exit_pending)
  5194. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5195. iwl3945_clear_stations_table(priv);
  5196. /* Unblock any waiting calls */
  5197. wake_up_interruptible_all(&priv->wait_command_queue);
  5198. /* Wipe out the EXIT_PENDING status bit if we are not actually
  5199. * exiting the module */
  5200. if (!exit_pending)
  5201. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  5202. /* stop and reset the on-board processor */
  5203. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  5204. /* tell the device to stop sending interrupts */
  5205. iwl3945_disable_interrupts(priv);
  5206. if (priv->mac80211_registered)
  5207. ieee80211_stop_queues(priv->hw);
  5208. /* If we have not previously called iwl3945_init() then
  5209. * clear all bits but the RF Kill and SUSPEND bits and return */
  5210. if (!iwl3945_is_init(priv)) {
  5211. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5212. STATUS_RF_KILL_HW |
  5213. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5214. STATUS_RF_KILL_SW |
  5215. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5216. STATUS_IN_SUSPEND;
  5217. goto exit;
  5218. }
  5219. /* ...otherwise clear out all the status bits but the RF Kill and
  5220. * SUSPEND bits and continue taking the NIC down. */
  5221. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5222. STATUS_RF_KILL_HW |
  5223. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5224. STATUS_RF_KILL_SW |
  5225. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5226. STATUS_IN_SUSPEND |
  5227. test_bit(STATUS_FW_ERROR, &priv->status) <<
  5228. STATUS_FW_ERROR;
  5229. spin_lock_irqsave(&priv->lock, flags);
  5230. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  5231. spin_unlock_irqrestore(&priv->lock, flags);
  5232. iwl3945_hw_txq_ctx_stop(priv);
  5233. iwl3945_hw_rxq_stop(priv);
  5234. spin_lock_irqsave(&priv->lock, flags);
  5235. if (!iwl3945_grab_nic_access(priv)) {
  5236. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  5237. APMG_CLK_VAL_DMA_CLK_RQT);
  5238. iwl3945_release_nic_access(priv);
  5239. }
  5240. spin_unlock_irqrestore(&priv->lock, flags);
  5241. udelay(5);
  5242. iwl3945_hw_nic_stop_master(priv);
  5243. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  5244. iwl3945_hw_nic_reset(priv);
  5245. exit:
  5246. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  5247. if (priv->ibss_beacon)
  5248. dev_kfree_skb(priv->ibss_beacon);
  5249. priv->ibss_beacon = NULL;
  5250. /* clear out any free frames */
  5251. iwl3945_clear_free_frames(priv);
  5252. }
  5253. static void iwl3945_down(struct iwl3945_priv *priv)
  5254. {
  5255. mutex_lock(&priv->mutex);
  5256. __iwl3945_down(priv);
  5257. mutex_unlock(&priv->mutex);
  5258. iwl3945_cancel_deferred_work(priv);
  5259. }
  5260. #define MAX_HW_RESTARTS 5
  5261. static int __iwl3945_up(struct iwl3945_priv *priv)
  5262. {
  5263. DECLARE_MAC_BUF(mac);
  5264. int rc, i;
  5265. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5266. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  5267. return -EIO;
  5268. }
  5269. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  5270. IWL_WARNING("Radio disabled by SW RF kill (module "
  5271. "parameter)\n");
  5272. return 0;
  5273. }
  5274. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  5275. IWL_ERROR("ucode not available for device bringup\n");
  5276. return -EIO;
  5277. }
  5278. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5279. rc = iwl3945_hw_nic_init(priv);
  5280. if (rc) {
  5281. IWL_ERROR("Unable to int nic\n");
  5282. return rc;
  5283. }
  5284. /* make sure rfkill handshake bits are cleared */
  5285. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5286. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  5287. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  5288. /* clear (again), then enable host interrupts */
  5289. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5290. iwl3945_enable_interrupts(priv);
  5291. /* really make sure rfkill handshake bits are cleared */
  5292. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5293. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5294. /* Copy original ucode data image from disk into backup cache.
  5295. * This will be used to initialize the on-board processor's
  5296. * data SRAM for a clean start when the runtime program first loads. */
  5297. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  5298. priv->ucode_data.len);
  5299. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  5300. iwl3945_clear_stations_table(priv);
  5301. /* load bootstrap state machine,
  5302. * load bootstrap program into processor's memory,
  5303. * prepare to load the "initialize" uCode */
  5304. rc = iwl3945_load_bsm(priv);
  5305. if (rc) {
  5306. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  5307. continue;
  5308. }
  5309. /* start card; "initialize" will load runtime ucode */
  5310. iwl3945_nic_start(priv);
  5311. /* MAC Address location in EEPROM is same for 3945/4965 */
  5312. get_eeprom_mac(priv, priv->mac_addr);
  5313. IWL_DEBUG_INFO("MAC address: %s\n",
  5314. print_mac(mac, priv->mac_addr));
  5315. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  5316. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  5317. return 0;
  5318. }
  5319. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5320. __iwl3945_down(priv);
  5321. /* tried to restart and config the device for as long as our
  5322. * patience could withstand */
  5323. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  5324. return -EIO;
  5325. }
  5326. /*****************************************************************************
  5327. *
  5328. * Workqueue callbacks
  5329. *
  5330. *****************************************************************************/
  5331. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  5332. {
  5333. struct iwl3945_priv *priv =
  5334. container_of(data, struct iwl3945_priv, init_alive_start.work);
  5335. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5336. return;
  5337. mutex_lock(&priv->mutex);
  5338. iwl3945_init_alive_start(priv);
  5339. mutex_unlock(&priv->mutex);
  5340. }
  5341. static void iwl3945_bg_alive_start(struct work_struct *data)
  5342. {
  5343. struct iwl3945_priv *priv =
  5344. container_of(data, struct iwl3945_priv, alive_start.work);
  5345. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5346. return;
  5347. mutex_lock(&priv->mutex);
  5348. iwl3945_alive_start(priv);
  5349. mutex_unlock(&priv->mutex);
  5350. }
  5351. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5352. {
  5353. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5354. wake_up_interruptible(&priv->wait_command_queue);
  5355. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5356. return;
  5357. mutex_lock(&priv->mutex);
  5358. if (!iwl3945_is_rfkill(priv)) {
  5359. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5360. "HW and/or SW RF Kill no longer active, restarting "
  5361. "device\n");
  5362. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5363. queue_work(priv->workqueue, &priv->restart);
  5364. } else {
  5365. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5366. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5367. "disabled by SW switch\n");
  5368. else
  5369. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5370. "Kill switch must be turned off for "
  5371. "wireless networking to work.\n");
  5372. }
  5373. mutex_unlock(&priv->mutex);
  5374. }
  5375. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5376. static void iwl3945_bg_scan_check(struct work_struct *data)
  5377. {
  5378. struct iwl3945_priv *priv =
  5379. container_of(data, struct iwl3945_priv, scan_check.work);
  5380. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5381. return;
  5382. mutex_lock(&priv->mutex);
  5383. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5384. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5385. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5386. "Scan completion watchdog resetting adapter (%dms)\n",
  5387. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5388. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5389. iwl3945_send_scan_abort(priv);
  5390. }
  5391. mutex_unlock(&priv->mutex);
  5392. }
  5393. static void iwl3945_bg_request_scan(struct work_struct *data)
  5394. {
  5395. struct iwl3945_priv *priv =
  5396. container_of(data, struct iwl3945_priv, request_scan);
  5397. struct iwl3945_host_cmd cmd = {
  5398. .id = REPLY_SCAN_CMD,
  5399. .len = sizeof(struct iwl3945_scan_cmd),
  5400. .meta.flags = CMD_SIZE_HUGE,
  5401. };
  5402. int rc = 0;
  5403. struct iwl3945_scan_cmd *scan;
  5404. struct ieee80211_conf *conf = NULL;
  5405. u8 direct_mask;
  5406. int phymode;
  5407. conf = ieee80211_get_hw_conf(priv->hw);
  5408. mutex_lock(&priv->mutex);
  5409. if (!iwl3945_is_ready(priv)) {
  5410. IWL_WARNING("request scan called when driver not ready.\n");
  5411. goto done;
  5412. }
  5413. /* Make sure the scan wasn't cancelled before this queued work
  5414. * was given the chance to run... */
  5415. if (!test_bit(STATUS_SCANNING, &priv->status))
  5416. goto done;
  5417. /* This should never be called or scheduled if there is currently
  5418. * a scan active in the hardware. */
  5419. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5420. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5421. "Ignoring second request.\n");
  5422. rc = -EIO;
  5423. goto done;
  5424. }
  5425. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5426. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5427. goto done;
  5428. }
  5429. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5430. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5431. goto done;
  5432. }
  5433. if (iwl3945_is_rfkill(priv)) {
  5434. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5435. goto done;
  5436. }
  5437. if (!test_bit(STATUS_READY, &priv->status)) {
  5438. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5439. goto done;
  5440. }
  5441. if (!priv->scan_bands) {
  5442. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5443. goto done;
  5444. }
  5445. if (!priv->scan) {
  5446. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5447. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5448. if (!priv->scan) {
  5449. rc = -ENOMEM;
  5450. goto done;
  5451. }
  5452. }
  5453. scan = priv->scan;
  5454. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5455. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5456. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5457. if (iwl3945_is_associated(priv)) {
  5458. u16 interval = 0;
  5459. u32 extra;
  5460. u32 suspend_time = 100;
  5461. u32 scan_suspend_time = 100;
  5462. unsigned long flags;
  5463. IWL_DEBUG_INFO("Scanning while associated...\n");
  5464. spin_lock_irqsave(&priv->lock, flags);
  5465. interval = priv->beacon_int;
  5466. spin_unlock_irqrestore(&priv->lock, flags);
  5467. scan->suspend_time = 0;
  5468. scan->max_out_time = cpu_to_le32(200 * 1024);
  5469. if (!interval)
  5470. interval = suspend_time;
  5471. /*
  5472. * suspend time format:
  5473. * 0-19: beacon interval in usec (time before exec.)
  5474. * 20-23: 0
  5475. * 24-31: number of beacons (suspend between channels)
  5476. */
  5477. extra = (suspend_time / interval) << 24;
  5478. scan_suspend_time = 0xFF0FFFFF &
  5479. (extra | ((suspend_time % interval) * 1024));
  5480. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5481. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5482. scan_suspend_time, interval);
  5483. }
  5484. /* We should add the ability for user to lock to PASSIVE ONLY */
  5485. if (priv->one_direct_scan) {
  5486. IWL_DEBUG_SCAN
  5487. ("Kicking off one direct scan for '%s'\n",
  5488. iwl3945_escape_essid(priv->direct_ssid,
  5489. priv->direct_ssid_len));
  5490. scan->direct_scan[0].id = WLAN_EID_SSID;
  5491. scan->direct_scan[0].len = priv->direct_ssid_len;
  5492. memcpy(scan->direct_scan[0].ssid,
  5493. priv->direct_ssid, priv->direct_ssid_len);
  5494. direct_mask = 1;
  5495. } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
  5496. scan->direct_scan[0].id = WLAN_EID_SSID;
  5497. scan->direct_scan[0].len = priv->essid_len;
  5498. memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
  5499. direct_mask = 1;
  5500. } else
  5501. direct_mask = 0;
  5502. /* We don't build a direct scan probe request; the uCode will do
  5503. * that based on the direct_mask added to each channel entry */
  5504. scan->tx_cmd.len = cpu_to_le16(
  5505. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5506. IWL_MAX_SCAN_SIZE - sizeof(scan), 0));
  5507. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5508. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5509. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5510. /* flags + rate selection */
  5511. switch (priv->scan_bands) {
  5512. case 2:
  5513. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5514. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5515. scan->good_CRC_th = 0;
  5516. phymode = MODE_IEEE80211G;
  5517. break;
  5518. case 1:
  5519. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5520. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5521. phymode = MODE_IEEE80211A;
  5522. break;
  5523. default:
  5524. IWL_WARNING("Invalid scan band count\n");
  5525. goto done;
  5526. }
  5527. /* select Rx antennas */
  5528. scan->flags |= iwl3945_get_antenna_flags(priv);
  5529. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
  5530. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5531. if (direct_mask)
  5532. IWL_DEBUG_SCAN
  5533. ("Initiating direct scan for %s.\n",
  5534. iwl3945_escape_essid(priv->essid, priv->essid_len));
  5535. else
  5536. IWL_DEBUG_SCAN("Initiating indirect scan.\n");
  5537. scan->channel_count =
  5538. iwl3945_get_channels_for_scan(
  5539. priv, phymode, 1, /* active */
  5540. direct_mask,
  5541. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5542. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5543. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5544. cmd.data = scan;
  5545. scan->len = cpu_to_le16(cmd.len);
  5546. set_bit(STATUS_SCAN_HW, &priv->status);
  5547. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5548. if (rc)
  5549. goto done;
  5550. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5551. IWL_SCAN_CHECK_WATCHDOG);
  5552. mutex_unlock(&priv->mutex);
  5553. return;
  5554. done:
  5555. /* inform mac80211 scan aborted */
  5556. queue_work(priv->workqueue, &priv->scan_completed);
  5557. mutex_unlock(&priv->mutex);
  5558. }
  5559. static void iwl3945_bg_up(struct work_struct *data)
  5560. {
  5561. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5562. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5563. return;
  5564. mutex_lock(&priv->mutex);
  5565. __iwl3945_up(priv);
  5566. mutex_unlock(&priv->mutex);
  5567. }
  5568. static void iwl3945_bg_restart(struct work_struct *data)
  5569. {
  5570. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5571. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5572. return;
  5573. iwl3945_down(priv);
  5574. queue_work(priv->workqueue, &priv->up);
  5575. }
  5576. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5577. {
  5578. struct iwl3945_priv *priv =
  5579. container_of(data, struct iwl3945_priv, rx_replenish);
  5580. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5581. return;
  5582. mutex_lock(&priv->mutex);
  5583. iwl3945_rx_replenish(priv);
  5584. mutex_unlock(&priv->mutex);
  5585. }
  5586. static void iwl3945_bg_post_associate(struct work_struct *data)
  5587. {
  5588. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
  5589. post_associate.work);
  5590. int rc = 0;
  5591. struct ieee80211_conf *conf = NULL;
  5592. DECLARE_MAC_BUF(mac);
  5593. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5594. IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
  5595. return;
  5596. }
  5597. IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
  5598. priv->assoc_id,
  5599. print_mac(mac, priv->active_rxon.bssid_addr));
  5600. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5601. return;
  5602. mutex_lock(&priv->mutex);
  5603. if (!priv->interface_id || !priv->is_open) {
  5604. mutex_unlock(&priv->mutex);
  5605. return;
  5606. }
  5607. iwl3945_scan_cancel_timeout(priv, 200);
  5608. conf = ieee80211_get_hw_conf(priv->hw);
  5609. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5610. iwl3945_commit_rxon(priv);
  5611. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5612. iwl3945_setup_rxon_timing(priv);
  5613. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5614. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5615. if (rc)
  5616. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5617. "Attempting to continue.\n");
  5618. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5619. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5620. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5621. priv->assoc_id, priv->beacon_int);
  5622. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5623. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5624. else
  5625. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5626. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5627. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5628. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5629. else
  5630. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5631. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5632. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5633. }
  5634. iwl3945_commit_rxon(priv);
  5635. switch (priv->iw_mode) {
  5636. case IEEE80211_IF_TYPE_STA:
  5637. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5638. break;
  5639. case IEEE80211_IF_TYPE_IBSS:
  5640. /* clear out the station table */
  5641. iwl3945_clear_stations_table(priv);
  5642. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5643. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5644. iwl3945_sync_sta(priv, IWL_STA_ID,
  5645. (priv->phymode == MODE_IEEE80211A)?
  5646. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5647. CMD_ASYNC);
  5648. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5649. iwl3945_send_beacon_cmd(priv);
  5650. break;
  5651. default:
  5652. IWL_ERROR("%s Should not be called in %d mode\n",
  5653. __FUNCTION__, priv->iw_mode);
  5654. break;
  5655. }
  5656. iwl3945_sequence_reset(priv);
  5657. #ifdef CONFIG_IWL3945_QOS
  5658. iwl3945_activate_qos(priv, 0);
  5659. #endif /* CONFIG_IWL3945_QOS */
  5660. mutex_unlock(&priv->mutex);
  5661. }
  5662. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5663. {
  5664. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5665. if (!iwl3945_is_ready(priv))
  5666. return;
  5667. mutex_lock(&priv->mutex);
  5668. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5669. iwl3945_send_scan_abort(priv);
  5670. mutex_unlock(&priv->mutex);
  5671. }
  5672. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5673. {
  5674. struct iwl3945_priv *priv =
  5675. container_of(work, struct iwl3945_priv, scan_completed);
  5676. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5677. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5678. return;
  5679. ieee80211_scan_completed(priv->hw);
  5680. /* Since setting the TXPOWER may have been deferred while
  5681. * performing the scan, fire one off */
  5682. mutex_lock(&priv->mutex);
  5683. iwl3945_hw_reg_send_txpower(priv);
  5684. mutex_unlock(&priv->mutex);
  5685. }
  5686. /*****************************************************************************
  5687. *
  5688. * mac80211 entry point functions
  5689. *
  5690. *****************************************************************************/
  5691. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5692. {
  5693. struct iwl3945_priv *priv = hw->priv;
  5694. IWL_DEBUG_MAC80211("enter\n");
  5695. /* we should be verifying the device is ready to be opened */
  5696. mutex_lock(&priv->mutex);
  5697. priv->is_open = 1;
  5698. if (!iwl3945_is_rfkill(priv))
  5699. ieee80211_start_queues(priv->hw);
  5700. mutex_unlock(&priv->mutex);
  5701. IWL_DEBUG_MAC80211("leave\n");
  5702. return 0;
  5703. }
  5704. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5705. {
  5706. struct iwl3945_priv *priv = hw->priv;
  5707. IWL_DEBUG_MAC80211("enter\n");
  5708. mutex_lock(&priv->mutex);
  5709. /* stop mac, cancel any scan request and clear
  5710. * RXON_FILTER_ASSOC_MSK BIT
  5711. */
  5712. priv->is_open = 0;
  5713. iwl3945_scan_cancel_timeout(priv, 100);
  5714. cancel_delayed_work(&priv->post_associate);
  5715. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5716. iwl3945_commit_rxon(priv);
  5717. mutex_unlock(&priv->mutex);
  5718. IWL_DEBUG_MAC80211("leave\n");
  5719. }
  5720. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
  5721. struct ieee80211_tx_control *ctl)
  5722. {
  5723. struct iwl3945_priv *priv = hw->priv;
  5724. IWL_DEBUG_MAC80211("enter\n");
  5725. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  5726. IWL_DEBUG_MAC80211("leave - monitor\n");
  5727. return -1;
  5728. }
  5729. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5730. ctl->tx_rate);
  5731. if (iwl3945_tx_skb(priv, skb, ctl))
  5732. dev_kfree_skb_any(skb);
  5733. IWL_DEBUG_MAC80211("leave\n");
  5734. return 0;
  5735. }
  5736. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5737. struct ieee80211_if_init_conf *conf)
  5738. {
  5739. struct iwl3945_priv *priv = hw->priv;
  5740. unsigned long flags;
  5741. DECLARE_MAC_BUF(mac);
  5742. IWL_DEBUG_MAC80211("enter: id %d, type %d\n", conf->if_id, conf->type);
  5743. if (priv->interface_id) {
  5744. IWL_DEBUG_MAC80211("leave - interface_id != 0\n");
  5745. return -EOPNOTSUPP;
  5746. }
  5747. spin_lock_irqsave(&priv->lock, flags);
  5748. priv->interface_id = conf->if_id;
  5749. spin_unlock_irqrestore(&priv->lock, flags);
  5750. mutex_lock(&priv->mutex);
  5751. if (conf->mac_addr) {
  5752. IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
  5753. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5754. }
  5755. iwl3945_set_mode(priv, conf->type);
  5756. IWL_DEBUG_MAC80211("leave\n");
  5757. mutex_unlock(&priv->mutex);
  5758. return 0;
  5759. }
  5760. /**
  5761. * iwl3945_mac_config - mac80211 config callback
  5762. *
  5763. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5764. * be set inappropriately and the driver currently sets the hardware up to
  5765. * use it whenever needed.
  5766. */
  5767. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  5768. {
  5769. struct iwl3945_priv *priv = hw->priv;
  5770. const struct iwl3945_channel_info *ch_info;
  5771. unsigned long flags;
  5772. mutex_lock(&priv->mutex);
  5773. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel);
  5774. if (!iwl3945_is_ready(priv)) {
  5775. IWL_DEBUG_MAC80211("leave - not ready\n");
  5776. mutex_unlock(&priv->mutex);
  5777. return -EIO;
  5778. }
  5779. /* TODO: Figure out how to get ieee80211_local->sta_scanning w/ only
  5780. * what is exposed through include/ declarations */
  5781. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5782. test_bit(STATUS_SCANNING, &priv->status))) {
  5783. IWL_DEBUG_MAC80211("leave - scanning\n");
  5784. mutex_unlock(&priv->mutex);
  5785. return 0;
  5786. }
  5787. spin_lock_irqsave(&priv->lock, flags);
  5788. ch_info = iwl3945_get_channel_info(priv, conf->phymode, conf->channel);
  5789. if (!is_channel_valid(ch_info)) {
  5790. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
  5791. conf->channel, conf->phymode);
  5792. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5793. spin_unlock_irqrestore(&priv->lock, flags);
  5794. mutex_unlock(&priv->mutex);
  5795. return -EINVAL;
  5796. }
  5797. iwl3945_set_rxon_channel(priv, conf->phymode, conf->channel);
  5798. iwl3945_set_flags_for_phymode(priv, conf->phymode);
  5799. /* The list of supported rates and rate mask can be different
  5800. * for each phymode; since the phymode may have changed, reset
  5801. * the rate mask to what mac80211 lists */
  5802. iwl3945_set_rate(priv);
  5803. spin_unlock_irqrestore(&priv->lock, flags);
  5804. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5805. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5806. iwl3945_hw_channel_switch(priv, conf->channel);
  5807. mutex_unlock(&priv->mutex);
  5808. return 0;
  5809. }
  5810. #endif
  5811. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5812. if (!conf->radio_enabled) {
  5813. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5814. mutex_unlock(&priv->mutex);
  5815. return 0;
  5816. }
  5817. if (iwl3945_is_rfkill(priv)) {
  5818. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5819. mutex_unlock(&priv->mutex);
  5820. return -EIO;
  5821. }
  5822. iwl3945_set_rate(priv);
  5823. if (memcmp(&priv->active_rxon,
  5824. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5825. iwl3945_commit_rxon(priv);
  5826. else
  5827. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5828. IWL_DEBUG_MAC80211("leave\n");
  5829. mutex_unlock(&priv->mutex);
  5830. return 0;
  5831. }
  5832. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5833. {
  5834. int rc = 0;
  5835. if (priv->status & STATUS_EXIT_PENDING)
  5836. return;
  5837. /* The following should be done only at AP bring up */
  5838. if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
  5839. /* RXON - unassoc (to set timing command) */
  5840. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5841. iwl3945_commit_rxon(priv);
  5842. /* RXON Timing */
  5843. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5844. iwl3945_setup_rxon_timing(priv);
  5845. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5846. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5847. if (rc)
  5848. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5849. "Attempting to continue.\n");
  5850. /* FIXME: what should be the assoc_id for AP? */
  5851. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5852. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5853. priv->staging_rxon.flags |=
  5854. RXON_FLG_SHORT_PREAMBLE_MSK;
  5855. else
  5856. priv->staging_rxon.flags &=
  5857. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5858. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5859. if (priv->assoc_capability &
  5860. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5861. priv->staging_rxon.flags |=
  5862. RXON_FLG_SHORT_SLOT_MSK;
  5863. else
  5864. priv->staging_rxon.flags &=
  5865. ~RXON_FLG_SHORT_SLOT_MSK;
  5866. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5867. priv->staging_rxon.flags &=
  5868. ~RXON_FLG_SHORT_SLOT_MSK;
  5869. }
  5870. /* restore RXON assoc */
  5871. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5872. iwl3945_commit_rxon(priv);
  5873. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5874. }
  5875. iwl3945_send_beacon_cmd(priv);
  5876. /* FIXME - we need to add code here to detect a totally new
  5877. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5878. * clear sta table, add BCAST sta... */
  5879. }
  5880. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw, int if_id,
  5881. struct ieee80211_if_conf *conf)
  5882. {
  5883. struct iwl3945_priv *priv = hw->priv;
  5884. DECLARE_MAC_BUF(mac);
  5885. unsigned long flags;
  5886. int rc;
  5887. if (conf == NULL)
  5888. return -EIO;
  5889. /* XXX: this MUST use conf->mac_addr */
  5890. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  5891. (!conf->beacon || !conf->ssid_len)) {
  5892. IWL_DEBUG_MAC80211
  5893. ("Leaving in AP mode because HostAPD is not ready.\n");
  5894. return 0;
  5895. }
  5896. mutex_lock(&priv->mutex);
  5897. IWL_DEBUG_MAC80211("enter: interface id %d\n", if_id);
  5898. if (conf->bssid)
  5899. IWL_DEBUG_MAC80211("bssid: %s\n",
  5900. print_mac(mac, conf->bssid));
  5901. /*
  5902. * very dubious code was here; the probe filtering flag is never set:
  5903. *
  5904. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5905. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5906. */
  5907. if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) {
  5908. IWL_DEBUG_MAC80211("leave - scanning\n");
  5909. mutex_unlock(&priv->mutex);
  5910. return 0;
  5911. }
  5912. if (priv->interface_id != if_id) {
  5913. IWL_DEBUG_MAC80211("leave - interface_id != if_id\n");
  5914. mutex_unlock(&priv->mutex);
  5915. return 0;
  5916. }
  5917. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5918. if (!conf->bssid) {
  5919. conf->bssid = priv->mac_addr;
  5920. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5921. IWL_DEBUG_MAC80211("bssid was set to: %s\n",
  5922. print_mac(mac, conf->bssid));
  5923. }
  5924. if (priv->ibss_beacon)
  5925. dev_kfree_skb(priv->ibss_beacon);
  5926. priv->ibss_beacon = conf->beacon;
  5927. }
  5928. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5929. !is_multicast_ether_addr(conf->bssid)) {
  5930. /* If there is currently a HW scan going on in the background
  5931. * then we need to cancel it else the RXON below will fail. */
  5932. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5933. IWL_WARNING("Aborted scan still in progress "
  5934. "after 100ms\n");
  5935. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5936. mutex_unlock(&priv->mutex);
  5937. return -EAGAIN;
  5938. }
  5939. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5940. /* TODO: Audit driver for usage of these members and see
  5941. * if mac80211 deprecates them (priv->bssid looks like it
  5942. * shouldn't be there, but I haven't scanned the IBSS code
  5943. * to verify) - jpk */
  5944. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5945. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  5946. iwl3945_config_ap(priv);
  5947. else {
  5948. rc = iwl3945_commit_rxon(priv);
  5949. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
  5950. iwl3945_add_station(priv,
  5951. priv->active_rxon.bssid_addr, 1, 0);
  5952. }
  5953. } else {
  5954. iwl3945_scan_cancel_timeout(priv, 100);
  5955. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5956. iwl3945_commit_rxon(priv);
  5957. }
  5958. spin_lock_irqsave(&priv->lock, flags);
  5959. if (!conf->ssid_len)
  5960. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5961. else
  5962. memcpy(priv->essid, conf->ssid, conf->ssid_len);
  5963. priv->essid_len = conf->ssid_len;
  5964. spin_unlock_irqrestore(&priv->lock, flags);
  5965. IWL_DEBUG_MAC80211("leave\n");
  5966. mutex_unlock(&priv->mutex);
  5967. return 0;
  5968. }
  5969. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5970. unsigned int changed_flags,
  5971. unsigned int *total_flags,
  5972. int mc_count, struct dev_addr_list *mc_list)
  5973. {
  5974. /*
  5975. * XXX: dummy
  5976. * see also iwl3945_connection_init_rx_config
  5977. */
  5978. *total_flags = 0;
  5979. }
  5980. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5981. struct ieee80211_if_init_conf *conf)
  5982. {
  5983. struct iwl3945_priv *priv = hw->priv;
  5984. IWL_DEBUG_MAC80211("enter\n");
  5985. mutex_lock(&priv->mutex);
  5986. iwl3945_scan_cancel_timeout(priv, 100);
  5987. cancel_delayed_work(&priv->post_associate);
  5988. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5989. iwl3945_commit_rxon(priv);
  5990. if (priv->interface_id == conf->if_id) {
  5991. priv->interface_id = 0;
  5992. memset(priv->bssid, 0, ETH_ALEN);
  5993. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5994. priv->essid_len = 0;
  5995. }
  5996. mutex_unlock(&priv->mutex);
  5997. IWL_DEBUG_MAC80211("leave\n");
  5998. }
  5999. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  6000. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  6001. {
  6002. int rc = 0;
  6003. unsigned long flags;
  6004. struct iwl3945_priv *priv = hw->priv;
  6005. IWL_DEBUG_MAC80211("enter\n");
  6006. mutex_lock(&priv->mutex);
  6007. spin_lock_irqsave(&priv->lock, flags);
  6008. if (!iwl3945_is_ready_rf(priv)) {
  6009. rc = -EIO;
  6010. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  6011. goto out_unlock;
  6012. }
  6013. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
  6014. rc = -EIO;
  6015. IWL_ERROR("ERROR: APs don't scan\n");
  6016. goto out_unlock;
  6017. }
  6018. /* if we just finished scan ask for delay */
  6019. if (priv->last_scan_jiffies &&
  6020. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  6021. jiffies)) {
  6022. rc = -EAGAIN;
  6023. goto out_unlock;
  6024. }
  6025. if (len) {
  6026. IWL_DEBUG_SCAN("direct scan for "
  6027. "%s [%d]\n ",
  6028. iwl3945_escape_essid(ssid, len), (int)len);
  6029. priv->one_direct_scan = 1;
  6030. priv->direct_ssid_len = (u8)
  6031. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  6032. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  6033. } else
  6034. priv->one_direct_scan = 0;
  6035. rc = iwl3945_scan_initiate(priv);
  6036. IWL_DEBUG_MAC80211("leave\n");
  6037. out_unlock:
  6038. spin_unlock_irqrestore(&priv->lock, flags);
  6039. mutex_unlock(&priv->mutex);
  6040. return rc;
  6041. }
  6042. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  6043. const u8 *local_addr, const u8 *addr,
  6044. struct ieee80211_key_conf *key)
  6045. {
  6046. struct iwl3945_priv *priv = hw->priv;
  6047. int rc = 0;
  6048. u8 sta_id;
  6049. IWL_DEBUG_MAC80211("enter\n");
  6050. if (!iwl3945_param_hwcrypto) {
  6051. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  6052. return -EOPNOTSUPP;
  6053. }
  6054. if (is_zero_ether_addr(addr))
  6055. /* only support pairwise keys */
  6056. return -EOPNOTSUPP;
  6057. sta_id = iwl3945_hw_find_station(priv, addr);
  6058. if (sta_id == IWL_INVALID_STATION) {
  6059. DECLARE_MAC_BUF(mac);
  6060. IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
  6061. print_mac(mac, addr));
  6062. return -EINVAL;
  6063. }
  6064. mutex_lock(&priv->mutex);
  6065. iwl3945_scan_cancel_timeout(priv, 100);
  6066. switch (cmd) {
  6067. case SET_KEY:
  6068. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  6069. if (!rc) {
  6070. iwl3945_set_rxon_hwcrypto(priv, 1);
  6071. iwl3945_commit_rxon(priv);
  6072. key->hw_key_idx = sta_id;
  6073. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  6074. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  6075. }
  6076. break;
  6077. case DISABLE_KEY:
  6078. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  6079. if (!rc) {
  6080. iwl3945_set_rxon_hwcrypto(priv, 0);
  6081. iwl3945_commit_rxon(priv);
  6082. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  6083. }
  6084. break;
  6085. default:
  6086. rc = -EINVAL;
  6087. }
  6088. IWL_DEBUG_MAC80211("leave\n");
  6089. mutex_unlock(&priv->mutex);
  6090. return rc;
  6091. }
  6092. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue,
  6093. const struct ieee80211_tx_queue_params *params)
  6094. {
  6095. struct iwl3945_priv *priv = hw->priv;
  6096. #ifdef CONFIG_IWL3945_QOS
  6097. unsigned long flags;
  6098. int q;
  6099. #endif /* CONFIG_IWL3945_QOS */
  6100. IWL_DEBUG_MAC80211("enter\n");
  6101. if (!iwl3945_is_ready_rf(priv)) {
  6102. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6103. return -EIO;
  6104. }
  6105. if (queue >= AC_NUM) {
  6106. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  6107. return 0;
  6108. }
  6109. #ifdef CONFIG_IWL3945_QOS
  6110. if (!priv->qos_data.qos_enable) {
  6111. priv->qos_data.qos_active = 0;
  6112. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  6113. return 0;
  6114. }
  6115. q = AC_NUM - 1 - queue;
  6116. spin_lock_irqsave(&priv->lock, flags);
  6117. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  6118. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  6119. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  6120. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  6121. cpu_to_le16((params->burst_time * 100));
  6122. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  6123. priv->qos_data.qos_active = 1;
  6124. spin_unlock_irqrestore(&priv->lock, flags);
  6125. mutex_lock(&priv->mutex);
  6126. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  6127. iwl3945_activate_qos(priv, 1);
  6128. else if (priv->assoc_id && iwl3945_is_associated(priv))
  6129. iwl3945_activate_qos(priv, 0);
  6130. mutex_unlock(&priv->mutex);
  6131. #endif /*CONFIG_IWL3945_QOS */
  6132. IWL_DEBUG_MAC80211("leave\n");
  6133. return 0;
  6134. }
  6135. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  6136. struct ieee80211_tx_queue_stats *stats)
  6137. {
  6138. struct iwl3945_priv *priv = hw->priv;
  6139. int i, avail;
  6140. struct iwl3945_tx_queue *txq;
  6141. struct iwl3945_queue *q;
  6142. unsigned long flags;
  6143. IWL_DEBUG_MAC80211("enter\n");
  6144. if (!iwl3945_is_ready_rf(priv)) {
  6145. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6146. return -EIO;
  6147. }
  6148. spin_lock_irqsave(&priv->lock, flags);
  6149. for (i = 0; i < AC_NUM; i++) {
  6150. txq = &priv->txq[i];
  6151. q = &txq->q;
  6152. avail = iwl3945_queue_space(q);
  6153. stats->data[i].len = q->n_window - avail;
  6154. stats->data[i].limit = q->n_window - q->high_mark;
  6155. stats->data[i].count = q->n_window;
  6156. }
  6157. spin_unlock_irqrestore(&priv->lock, flags);
  6158. IWL_DEBUG_MAC80211("leave\n");
  6159. return 0;
  6160. }
  6161. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  6162. struct ieee80211_low_level_stats *stats)
  6163. {
  6164. IWL_DEBUG_MAC80211("enter\n");
  6165. IWL_DEBUG_MAC80211("leave\n");
  6166. return 0;
  6167. }
  6168. static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
  6169. {
  6170. IWL_DEBUG_MAC80211("enter\n");
  6171. IWL_DEBUG_MAC80211("leave\n");
  6172. return 0;
  6173. }
  6174. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  6175. {
  6176. struct iwl3945_priv *priv = hw->priv;
  6177. unsigned long flags;
  6178. mutex_lock(&priv->mutex);
  6179. IWL_DEBUG_MAC80211("enter\n");
  6180. #ifdef CONFIG_IWL3945_QOS
  6181. iwl3945_reset_qos(priv);
  6182. #endif
  6183. cancel_delayed_work(&priv->post_associate);
  6184. spin_lock_irqsave(&priv->lock, flags);
  6185. priv->assoc_id = 0;
  6186. priv->assoc_capability = 0;
  6187. priv->call_post_assoc_from_beacon = 0;
  6188. /* new association get rid of ibss beacon skb */
  6189. if (priv->ibss_beacon)
  6190. dev_kfree_skb(priv->ibss_beacon);
  6191. priv->ibss_beacon = NULL;
  6192. priv->beacon_int = priv->hw->conf.beacon_int;
  6193. priv->timestamp1 = 0;
  6194. priv->timestamp0 = 0;
  6195. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
  6196. priv->beacon_int = 0;
  6197. spin_unlock_irqrestore(&priv->lock, flags);
  6198. /* we are restarting association process
  6199. * clear RXON_FILTER_ASSOC_MSK bit
  6200. */
  6201. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  6202. iwl3945_scan_cancel_timeout(priv, 100);
  6203. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6204. iwl3945_commit_rxon(priv);
  6205. }
  6206. /* Per mac80211.h: This is only used in IBSS mode... */
  6207. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6208. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  6209. mutex_unlock(&priv->mutex);
  6210. return;
  6211. }
  6212. if (!iwl3945_is_ready_rf(priv)) {
  6213. IWL_DEBUG_MAC80211("leave - not ready\n");
  6214. mutex_unlock(&priv->mutex);
  6215. return;
  6216. }
  6217. priv->only_active_channel = 0;
  6218. iwl3945_set_rate(priv);
  6219. mutex_unlock(&priv->mutex);
  6220. IWL_DEBUG_MAC80211("leave\n");
  6221. }
  6222. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
  6223. struct ieee80211_tx_control *control)
  6224. {
  6225. struct iwl3945_priv *priv = hw->priv;
  6226. unsigned long flags;
  6227. mutex_lock(&priv->mutex);
  6228. IWL_DEBUG_MAC80211("enter\n");
  6229. if (!iwl3945_is_ready_rf(priv)) {
  6230. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6231. mutex_unlock(&priv->mutex);
  6232. return -EIO;
  6233. }
  6234. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6235. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  6236. mutex_unlock(&priv->mutex);
  6237. return -EIO;
  6238. }
  6239. spin_lock_irqsave(&priv->lock, flags);
  6240. if (priv->ibss_beacon)
  6241. dev_kfree_skb(priv->ibss_beacon);
  6242. priv->ibss_beacon = skb;
  6243. priv->assoc_id = 0;
  6244. IWL_DEBUG_MAC80211("leave\n");
  6245. spin_unlock_irqrestore(&priv->lock, flags);
  6246. #ifdef CONFIG_IWL3945_QOS
  6247. iwl3945_reset_qos(priv);
  6248. #endif
  6249. queue_work(priv->workqueue, &priv->post_associate.work);
  6250. mutex_unlock(&priv->mutex);
  6251. return 0;
  6252. }
  6253. /*****************************************************************************
  6254. *
  6255. * sysfs attributes
  6256. *
  6257. *****************************************************************************/
  6258. #ifdef CONFIG_IWL3945_DEBUG
  6259. /*
  6260. * The following adds a new attribute to the sysfs representation
  6261. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6262. * used for controlling the debug level.
  6263. *
  6264. * See the level definitions in iwl for details.
  6265. */
  6266. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6267. {
  6268. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6269. }
  6270. static ssize_t store_debug_level(struct device_driver *d,
  6271. const char *buf, size_t count)
  6272. {
  6273. char *p = (char *)buf;
  6274. u32 val;
  6275. val = simple_strtoul(p, &p, 0);
  6276. if (p == buf)
  6277. printk(KERN_INFO DRV_NAME
  6278. ": %s is not in hex or decimal form.\n", buf);
  6279. else
  6280. iwl3945_debug_level = val;
  6281. return strnlen(buf, count);
  6282. }
  6283. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6284. show_debug_level, store_debug_level);
  6285. #endif /* CONFIG_IWL3945_DEBUG */
  6286. static ssize_t show_rf_kill(struct device *d,
  6287. struct device_attribute *attr, char *buf)
  6288. {
  6289. /*
  6290. * 0 - RF kill not enabled
  6291. * 1 - SW based RF kill active (sysfs)
  6292. * 2 - HW based RF kill active
  6293. * 3 - Both HW and SW based RF kill active
  6294. */
  6295. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6296. int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
  6297. (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
  6298. return sprintf(buf, "%i\n", val);
  6299. }
  6300. static ssize_t store_rf_kill(struct device *d,
  6301. struct device_attribute *attr,
  6302. const char *buf, size_t count)
  6303. {
  6304. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6305. mutex_lock(&priv->mutex);
  6306. iwl3945_radio_kill_sw(priv, buf[0] == '1');
  6307. mutex_unlock(&priv->mutex);
  6308. return count;
  6309. }
  6310. static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
  6311. static ssize_t show_temperature(struct device *d,
  6312. struct device_attribute *attr, char *buf)
  6313. {
  6314. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6315. if (!iwl3945_is_alive(priv))
  6316. return -EAGAIN;
  6317. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6318. }
  6319. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6320. static ssize_t show_rs_window(struct device *d,
  6321. struct device_attribute *attr,
  6322. char *buf)
  6323. {
  6324. struct iwl3945_priv *priv = d->driver_data;
  6325. return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
  6326. }
  6327. static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
  6328. static ssize_t show_tx_power(struct device *d,
  6329. struct device_attribute *attr, char *buf)
  6330. {
  6331. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6332. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6333. }
  6334. static ssize_t store_tx_power(struct device *d,
  6335. struct device_attribute *attr,
  6336. const char *buf, size_t count)
  6337. {
  6338. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6339. char *p = (char *)buf;
  6340. u32 val;
  6341. val = simple_strtoul(p, &p, 10);
  6342. if (p == buf)
  6343. printk(KERN_INFO DRV_NAME
  6344. ": %s is not in decimal form.\n", buf);
  6345. else
  6346. iwl3945_hw_reg_set_txpower(priv, val);
  6347. return count;
  6348. }
  6349. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6350. static ssize_t show_flags(struct device *d,
  6351. struct device_attribute *attr, char *buf)
  6352. {
  6353. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6354. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6355. }
  6356. static ssize_t store_flags(struct device *d,
  6357. struct device_attribute *attr,
  6358. const char *buf, size_t count)
  6359. {
  6360. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6361. u32 flags = simple_strtoul(buf, NULL, 0);
  6362. mutex_lock(&priv->mutex);
  6363. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6364. /* Cancel any currently running scans... */
  6365. if (iwl3945_scan_cancel_timeout(priv, 100))
  6366. IWL_WARNING("Could not cancel scan.\n");
  6367. else {
  6368. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6369. flags);
  6370. priv->staging_rxon.flags = cpu_to_le32(flags);
  6371. iwl3945_commit_rxon(priv);
  6372. }
  6373. }
  6374. mutex_unlock(&priv->mutex);
  6375. return count;
  6376. }
  6377. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6378. static ssize_t show_filter_flags(struct device *d,
  6379. struct device_attribute *attr, char *buf)
  6380. {
  6381. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6382. return sprintf(buf, "0x%04X\n",
  6383. le32_to_cpu(priv->active_rxon.filter_flags));
  6384. }
  6385. static ssize_t store_filter_flags(struct device *d,
  6386. struct device_attribute *attr,
  6387. const char *buf, size_t count)
  6388. {
  6389. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6390. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6391. mutex_lock(&priv->mutex);
  6392. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6393. /* Cancel any currently running scans... */
  6394. if (iwl3945_scan_cancel_timeout(priv, 100))
  6395. IWL_WARNING("Could not cancel scan.\n");
  6396. else {
  6397. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6398. "0x%04X\n", filter_flags);
  6399. priv->staging_rxon.filter_flags =
  6400. cpu_to_le32(filter_flags);
  6401. iwl3945_commit_rxon(priv);
  6402. }
  6403. }
  6404. mutex_unlock(&priv->mutex);
  6405. return count;
  6406. }
  6407. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6408. store_filter_flags);
  6409. static ssize_t show_tune(struct device *d,
  6410. struct device_attribute *attr, char *buf)
  6411. {
  6412. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6413. return sprintf(buf, "0x%04X\n",
  6414. (priv->phymode << 8) |
  6415. le16_to_cpu(priv->active_rxon.channel));
  6416. }
  6417. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv, u8 phymode);
  6418. static ssize_t store_tune(struct device *d,
  6419. struct device_attribute *attr,
  6420. const char *buf, size_t count)
  6421. {
  6422. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6423. char *p = (char *)buf;
  6424. u16 tune = simple_strtoul(p, &p, 0);
  6425. u8 phymode = (tune >> 8) & 0xff;
  6426. u16 channel = tune & 0xff;
  6427. IWL_DEBUG_INFO("Tune request to:%d channel:%d\n", phymode, channel);
  6428. mutex_lock(&priv->mutex);
  6429. if ((le16_to_cpu(priv->staging_rxon.channel) != channel) ||
  6430. (priv->phymode != phymode)) {
  6431. const struct iwl3945_channel_info *ch_info;
  6432. ch_info = iwl3945_get_channel_info(priv, phymode, channel);
  6433. if (!ch_info) {
  6434. IWL_WARNING("Requested invalid phymode/channel "
  6435. "combination: %d %d\n", phymode, channel);
  6436. mutex_unlock(&priv->mutex);
  6437. return -EINVAL;
  6438. }
  6439. /* Cancel any currently running scans... */
  6440. if (iwl3945_scan_cancel_timeout(priv, 100))
  6441. IWL_WARNING("Could not cancel scan.\n");
  6442. else {
  6443. IWL_DEBUG_INFO("Committing phymode and "
  6444. "rxon.channel = %d %d\n",
  6445. phymode, channel);
  6446. iwl3945_set_rxon_channel(priv, phymode, channel);
  6447. iwl3945_set_flags_for_phymode(priv, phymode);
  6448. iwl3945_set_rate(priv);
  6449. iwl3945_commit_rxon(priv);
  6450. }
  6451. }
  6452. mutex_unlock(&priv->mutex);
  6453. return count;
  6454. }
  6455. static DEVICE_ATTR(tune, S_IWUSR | S_IRUGO, show_tune, store_tune);
  6456. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6457. static ssize_t show_measurement(struct device *d,
  6458. struct device_attribute *attr, char *buf)
  6459. {
  6460. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6461. struct iwl3945_spectrum_notification measure_report;
  6462. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6463. u8 *data = (u8 *) & measure_report;
  6464. unsigned long flags;
  6465. spin_lock_irqsave(&priv->lock, flags);
  6466. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6467. spin_unlock_irqrestore(&priv->lock, flags);
  6468. return 0;
  6469. }
  6470. memcpy(&measure_report, &priv->measure_report, size);
  6471. priv->measurement_status = 0;
  6472. spin_unlock_irqrestore(&priv->lock, flags);
  6473. while (size && (PAGE_SIZE - len)) {
  6474. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6475. PAGE_SIZE - len, 1);
  6476. len = strlen(buf);
  6477. if (PAGE_SIZE - len)
  6478. buf[len++] = '\n';
  6479. ofs += 16;
  6480. size -= min(size, 16U);
  6481. }
  6482. return len;
  6483. }
  6484. static ssize_t store_measurement(struct device *d,
  6485. struct device_attribute *attr,
  6486. const char *buf, size_t count)
  6487. {
  6488. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6489. struct ieee80211_measurement_params params = {
  6490. .channel = le16_to_cpu(priv->active_rxon.channel),
  6491. .start_time = cpu_to_le64(priv->last_tsf),
  6492. .duration = cpu_to_le16(1),
  6493. };
  6494. u8 type = IWL_MEASURE_BASIC;
  6495. u8 buffer[32];
  6496. u8 channel;
  6497. if (count) {
  6498. char *p = buffer;
  6499. strncpy(buffer, buf, min(sizeof(buffer), count));
  6500. channel = simple_strtoul(p, NULL, 0);
  6501. if (channel)
  6502. params.channel = channel;
  6503. p = buffer;
  6504. while (*p && *p != ' ')
  6505. p++;
  6506. if (*p)
  6507. type = simple_strtoul(p + 1, NULL, 0);
  6508. }
  6509. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6510. "channel %d (for '%s')\n", type, params.channel, buf);
  6511. iwl3945_get_measurement(priv, &params, type);
  6512. return count;
  6513. }
  6514. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6515. show_measurement, store_measurement);
  6516. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6517. static ssize_t show_rate(struct device *d,
  6518. struct device_attribute *attr, char *buf)
  6519. {
  6520. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6521. unsigned long flags;
  6522. int i;
  6523. spin_lock_irqsave(&priv->sta_lock, flags);
  6524. if (priv->iw_mode == IEEE80211_IF_TYPE_STA)
  6525. i = priv->stations[IWL_AP_ID].current_rate.s.rate;
  6526. else
  6527. i = priv->stations[IWL_STA_ID].current_rate.s.rate;
  6528. spin_unlock_irqrestore(&priv->sta_lock, flags);
  6529. i = iwl3945_rate_index_from_plcp(i);
  6530. if (i == -1)
  6531. return sprintf(buf, "0\n");
  6532. return sprintf(buf, "%d%s\n",
  6533. (iwl3945_rates[i].ieee >> 1),
  6534. (iwl3945_rates[i].ieee & 0x1) ? ".5" : "");
  6535. }
  6536. static DEVICE_ATTR(rate, S_IRUSR, show_rate, NULL);
  6537. static ssize_t store_retry_rate(struct device *d,
  6538. struct device_attribute *attr,
  6539. const char *buf, size_t count)
  6540. {
  6541. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6542. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6543. if (priv->retry_rate <= 0)
  6544. priv->retry_rate = 1;
  6545. return count;
  6546. }
  6547. static ssize_t show_retry_rate(struct device *d,
  6548. struct device_attribute *attr, char *buf)
  6549. {
  6550. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6551. return sprintf(buf, "%d", priv->retry_rate);
  6552. }
  6553. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6554. store_retry_rate);
  6555. static ssize_t store_power_level(struct device *d,
  6556. struct device_attribute *attr,
  6557. const char *buf, size_t count)
  6558. {
  6559. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6560. int rc;
  6561. int mode;
  6562. mode = simple_strtoul(buf, NULL, 0);
  6563. mutex_lock(&priv->mutex);
  6564. if (!iwl3945_is_ready(priv)) {
  6565. rc = -EAGAIN;
  6566. goto out;
  6567. }
  6568. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6569. mode = IWL_POWER_AC;
  6570. else
  6571. mode |= IWL_POWER_ENABLED;
  6572. if (mode != priv->power_mode) {
  6573. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6574. if (rc) {
  6575. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6576. goto out;
  6577. }
  6578. priv->power_mode = mode;
  6579. }
  6580. rc = count;
  6581. out:
  6582. mutex_unlock(&priv->mutex);
  6583. return rc;
  6584. }
  6585. #define MAX_WX_STRING 80
  6586. /* Values are in microsecond */
  6587. static const s32 timeout_duration[] = {
  6588. 350000,
  6589. 250000,
  6590. 75000,
  6591. 37000,
  6592. 25000,
  6593. };
  6594. static const s32 period_duration[] = {
  6595. 400000,
  6596. 700000,
  6597. 1000000,
  6598. 1000000,
  6599. 1000000
  6600. };
  6601. static ssize_t show_power_level(struct device *d,
  6602. struct device_attribute *attr, char *buf)
  6603. {
  6604. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6605. int level = IWL_POWER_LEVEL(priv->power_mode);
  6606. char *p = buf;
  6607. p += sprintf(p, "%d ", level);
  6608. switch (level) {
  6609. case IWL_POWER_MODE_CAM:
  6610. case IWL_POWER_AC:
  6611. p += sprintf(p, "(AC)");
  6612. break;
  6613. case IWL_POWER_BATTERY:
  6614. p += sprintf(p, "(BATTERY)");
  6615. break;
  6616. default:
  6617. p += sprintf(p,
  6618. "(Timeout %dms, Period %dms)",
  6619. timeout_duration[level - 1] / 1000,
  6620. period_duration[level - 1] / 1000);
  6621. }
  6622. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6623. p += sprintf(p, " OFF\n");
  6624. else
  6625. p += sprintf(p, " \n");
  6626. return (p - buf + 1);
  6627. }
  6628. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6629. store_power_level);
  6630. static ssize_t show_channels(struct device *d,
  6631. struct device_attribute *attr, char *buf)
  6632. {
  6633. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6634. int len = 0, i;
  6635. struct ieee80211_channel *channels = NULL;
  6636. const struct ieee80211_hw_mode *hw_mode = NULL;
  6637. int count = 0;
  6638. if (!iwl3945_is_ready(priv))
  6639. return -EAGAIN;
  6640. hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211G);
  6641. if (!hw_mode)
  6642. hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211B);
  6643. if (hw_mode) {
  6644. channels = hw_mode->channels;
  6645. count = hw_mode->num_channels;
  6646. }
  6647. len +=
  6648. sprintf(&buf[len],
  6649. "Displaying %d channels in 2.4GHz band "
  6650. "(802.11bg):\n", count);
  6651. for (i = 0; i < count; i++)
  6652. len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
  6653. channels[i].chan,
  6654. channels[i].power_level,
  6655. channels[i].
  6656. flag & IEEE80211_CHAN_W_RADAR_DETECT ?
  6657. " (IEEE 802.11h required)" : "",
  6658. (!(channels[i].flag & IEEE80211_CHAN_W_IBSS)
  6659. || (channels[i].
  6660. flag &
  6661. IEEE80211_CHAN_W_RADAR_DETECT)) ? "" :
  6662. ", IBSS",
  6663. channels[i].
  6664. flag & IEEE80211_CHAN_W_ACTIVE_SCAN ?
  6665. "active/passive" : "passive only");
  6666. hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211A);
  6667. if (hw_mode) {
  6668. channels = hw_mode->channels;
  6669. count = hw_mode->num_channels;
  6670. } else {
  6671. channels = NULL;
  6672. count = 0;
  6673. }
  6674. len += sprintf(&buf[len], "Displaying %d channels in 5.2GHz band "
  6675. "(802.11a):\n", count);
  6676. for (i = 0; i < count; i++)
  6677. len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
  6678. channels[i].chan,
  6679. channels[i].power_level,
  6680. channels[i].
  6681. flag & IEEE80211_CHAN_W_RADAR_DETECT ?
  6682. " (IEEE 802.11h required)" : "",
  6683. (!(channels[i].flag & IEEE80211_CHAN_W_IBSS)
  6684. || (channels[i].
  6685. flag &
  6686. IEEE80211_CHAN_W_RADAR_DETECT)) ? "" :
  6687. ", IBSS",
  6688. channels[i].
  6689. flag & IEEE80211_CHAN_W_ACTIVE_SCAN ?
  6690. "active/passive" : "passive only");
  6691. return len;
  6692. }
  6693. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6694. static ssize_t show_statistics(struct device *d,
  6695. struct device_attribute *attr, char *buf)
  6696. {
  6697. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6698. u32 size = sizeof(struct iwl3945_notif_statistics);
  6699. u32 len = 0, ofs = 0;
  6700. u8 *data = (u8 *) & priv->statistics;
  6701. int rc = 0;
  6702. if (!iwl3945_is_alive(priv))
  6703. return -EAGAIN;
  6704. mutex_lock(&priv->mutex);
  6705. rc = iwl3945_send_statistics_request(priv);
  6706. mutex_unlock(&priv->mutex);
  6707. if (rc) {
  6708. len = sprintf(buf,
  6709. "Error sending statistics request: 0x%08X\n", rc);
  6710. return len;
  6711. }
  6712. while (size && (PAGE_SIZE - len)) {
  6713. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6714. PAGE_SIZE - len, 1);
  6715. len = strlen(buf);
  6716. if (PAGE_SIZE - len)
  6717. buf[len++] = '\n';
  6718. ofs += 16;
  6719. size -= min(size, 16U);
  6720. }
  6721. return len;
  6722. }
  6723. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6724. static ssize_t show_antenna(struct device *d,
  6725. struct device_attribute *attr, char *buf)
  6726. {
  6727. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6728. if (!iwl3945_is_alive(priv))
  6729. return -EAGAIN;
  6730. return sprintf(buf, "%d\n", priv->antenna);
  6731. }
  6732. static ssize_t store_antenna(struct device *d,
  6733. struct device_attribute *attr,
  6734. const char *buf, size_t count)
  6735. {
  6736. int ant;
  6737. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6738. if (count == 0)
  6739. return 0;
  6740. if (sscanf(buf, "%1i", &ant) != 1) {
  6741. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6742. return count;
  6743. }
  6744. if ((ant >= 0) && (ant <= 2)) {
  6745. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6746. priv->antenna = (enum iwl3945_antenna)ant;
  6747. } else
  6748. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6749. return count;
  6750. }
  6751. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6752. static ssize_t show_status(struct device *d,
  6753. struct device_attribute *attr, char *buf)
  6754. {
  6755. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6756. if (!iwl3945_is_alive(priv))
  6757. return -EAGAIN;
  6758. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6759. }
  6760. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6761. static ssize_t dump_error_log(struct device *d,
  6762. struct device_attribute *attr,
  6763. const char *buf, size_t count)
  6764. {
  6765. char *p = (char *)buf;
  6766. if (p[0] == '1')
  6767. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6768. return strnlen(buf, count);
  6769. }
  6770. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6771. static ssize_t dump_event_log(struct device *d,
  6772. struct device_attribute *attr,
  6773. const char *buf, size_t count)
  6774. {
  6775. char *p = (char *)buf;
  6776. if (p[0] == '1')
  6777. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6778. return strnlen(buf, count);
  6779. }
  6780. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6781. /*****************************************************************************
  6782. *
  6783. * driver setup and teardown
  6784. *
  6785. *****************************************************************************/
  6786. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6787. {
  6788. priv->workqueue = create_workqueue(DRV_NAME);
  6789. init_waitqueue_head(&priv->wait_command_queue);
  6790. INIT_WORK(&priv->up, iwl3945_bg_up);
  6791. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6792. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6793. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6794. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6795. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6796. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6797. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6798. INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
  6799. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6800. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6801. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6802. iwl3945_hw_setup_deferred_work(priv);
  6803. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6804. iwl3945_irq_tasklet, (unsigned long)priv);
  6805. }
  6806. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6807. {
  6808. iwl3945_hw_cancel_deferred_work(priv);
  6809. cancel_delayed_work_sync(&priv->init_alive_start);
  6810. cancel_delayed_work(&priv->scan_check);
  6811. cancel_delayed_work(&priv->alive_start);
  6812. cancel_delayed_work(&priv->post_associate);
  6813. cancel_work_sync(&priv->beacon_update);
  6814. }
  6815. static struct attribute *iwl3945_sysfs_entries[] = {
  6816. &dev_attr_antenna.attr,
  6817. &dev_attr_channels.attr,
  6818. &dev_attr_dump_errors.attr,
  6819. &dev_attr_dump_events.attr,
  6820. &dev_attr_flags.attr,
  6821. &dev_attr_filter_flags.attr,
  6822. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6823. &dev_attr_measurement.attr,
  6824. #endif
  6825. &dev_attr_power_level.attr,
  6826. &dev_attr_rate.attr,
  6827. &dev_attr_retry_rate.attr,
  6828. &dev_attr_rf_kill.attr,
  6829. &dev_attr_rs_window.attr,
  6830. &dev_attr_statistics.attr,
  6831. &dev_attr_status.attr,
  6832. &dev_attr_temperature.attr,
  6833. &dev_attr_tune.attr,
  6834. &dev_attr_tx_power.attr,
  6835. NULL
  6836. };
  6837. static struct attribute_group iwl3945_attribute_group = {
  6838. .name = NULL, /* put in device directory */
  6839. .attrs = iwl3945_sysfs_entries,
  6840. };
  6841. static struct ieee80211_ops iwl3945_hw_ops = {
  6842. .tx = iwl3945_mac_tx,
  6843. .start = iwl3945_mac_start,
  6844. .stop = iwl3945_mac_stop,
  6845. .add_interface = iwl3945_mac_add_interface,
  6846. .remove_interface = iwl3945_mac_remove_interface,
  6847. .config = iwl3945_mac_config,
  6848. .config_interface = iwl3945_mac_config_interface,
  6849. .configure_filter = iwl3945_configure_filter,
  6850. .set_key = iwl3945_mac_set_key,
  6851. .get_stats = iwl3945_mac_get_stats,
  6852. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6853. .conf_tx = iwl3945_mac_conf_tx,
  6854. .get_tsf = iwl3945_mac_get_tsf,
  6855. .reset_tsf = iwl3945_mac_reset_tsf,
  6856. .beacon_update = iwl3945_mac_beacon_update,
  6857. .hw_scan = iwl3945_mac_hw_scan
  6858. };
  6859. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6860. {
  6861. int err = 0;
  6862. u32 pci_id;
  6863. struct iwl3945_priv *priv;
  6864. struct ieee80211_hw *hw;
  6865. int i;
  6866. if (iwl3945_param_disable_hw_scan) {
  6867. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6868. iwl3945_hw_ops.hw_scan = NULL;
  6869. }
  6870. if ((iwl3945_param_queues_num > IWL_MAX_NUM_QUEUES) ||
  6871. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6872. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6873. IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
  6874. err = -EINVAL;
  6875. goto out;
  6876. }
  6877. /* mac80211 allocates memory for this device instance, including
  6878. * space for this driver's private structure */
  6879. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6880. if (hw == NULL) {
  6881. IWL_ERROR("Can not allocate network device\n");
  6882. err = -ENOMEM;
  6883. goto out;
  6884. }
  6885. SET_IEEE80211_DEV(hw, &pdev->dev);
  6886. hw->rate_control_algorithm = "iwl-3945-rs";
  6887. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6888. priv = hw->priv;
  6889. priv->hw = hw;
  6890. priv->pci_dev = pdev;
  6891. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6892. #ifdef CONFIG_IWL3945_DEBUG
  6893. iwl3945_debug_level = iwl3945_param_debug;
  6894. atomic_set(&priv->restrict_refcnt, 0);
  6895. #endif
  6896. priv->retry_rate = 1;
  6897. priv->ibss_beacon = NULL;
  6898. /* Tell mac80211 and its clients (e.g. Wireless Extensions)
  6899. * the range of signal quality values that we'll provide.
  6900. * Negative values for level/noise indicate that we'll provide dBm.
  6901. * For WE, at least, non-0 values here *enable* display of values
  6902. * in app (iwconfig). */
  6903. hw->max_rssi = -20; /* signal level, negative indicates dBm */
  6904. hw->max_noise = -20; /* noise level, negative indicates dBm */
  6905. hw->max_signal = 100; /* link quality indication (%) */
  6906. /* Tell mac80211 our Tx characteristics */
  6907. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
  6908. hw->queues = 4;
  6909. spin_lock_init(&priv->lock);
  6910. spin_lock_init(&priv->power_data.lock);
  6911. spin_lock_init(&priv->sta_lock);
  6912. spin_lock_init(&priv->hcmd_lock);
  6913. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
  6914. INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
  6915. INIT_LIST_HEAD(&priv->free_frames);
  6916. mutex_init(&priv->mutex);
  6917. if (pci_enable_device(pdev)) {
  6918. err = -ENODEV;
  6919. goto out_ieee80211_free_hw;
  6920. }
  6921. pci_set_master(pdev);
  6922. iwl3945_clear_stations_table(priv);
  6923. priv->data_retry_limit = -1;
  6924. priv->ieee_channels = NULL;
  6925. priv->ieee_rates = NULL;
  6926. priv->phymode = -1;
  6927. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6928. if (!err)
  6929. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6930. if (err) {
  6931. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6932. goto out_pci_disable_device;
  6933. }
  6934. pci_set_drvdata(pdev, priv);
  6935. err = pci_request_regions(pdev, DRV_NAME);
  6936. if (err)
  6937. goto out_pci_disable_device;
  6938. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6939. * PCI Tx retries from interfering with C3 CPU state */
  6940. pci_write_config_byte(pdev, 0x41, 0x00);
  6941. priv->hw_base = pci_iomap(pdev, 0, 0);
  6942. if (!priv->hw_base) {
  6943. err = -ENODEV;
  6944. goto out_pci_release_regions;
  6945. }
  6946. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6947. (unsigned long long) pci_resource_len(pdev, 0));
  6948. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6949. /* Initialize module parameter values here */
  6950. if (iwl3945_param_disable) {
  6951. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6952. IWL_DEBUG_INFO("Radio disabled.\n");
  6953. }
  6954. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  6955. pci_id =
  6956. (priv->pci_dev->device << 16) | priv->pci_dev->subsystem_device;
  6957. switch (pci_id) {
  6958. case 0x42221005: /* 0x4222 0x8086 0x1005 is BG SKU */
  6959. case 0x42221034: /* 0x4222 0x8086 0x1034 is BG SKU */
  6960. case 0x42271014: /* 0x4227 0x8086 0x1014 is BG SKU */
  6961. case 0x42221044: /* 0x4222 0x8086 0x1044 is BG SKU */
  6962. priv->is_abg = 0;
  6963. break;
  6964. /*
  6965. * Rest are assumed ABG SKU -- if this is not the
  6966. * case then the card will get the wrong 'Detected'
  6967. * line in the kernel log however the code that
  6968. * initializes the GEO table will detect no A-band
  6969. * channels and remove the is_abg mask.
  6970. */
  6971. default:
  6972. priv->is_abg = 1;
  6973. break;
  6974. }
  6975. printk(KERN_INFO DRV_NAME
  6976. ": Detected Intel PRO/Wireless 3945%sBG Network Connection\n",
  6977. priv->is_abg ? "A" : "");
  6978. /* Device-specific setup */
  6979. if (iwl3945_hw_set_hw_setting(priv)) {
  6980. IWL_ERROR("failed to set hw settings\n");
  6981. mutex_unlock(&priv->mutex);
  6982. goto out_iounmap;
  6983. }
  6984. #ifdef CONFIG_IWL3945_QOS
  6985. if (iwl3945_param_qos_enable)
  6986. priv->qos_data.qos_enable = 1;
  6987. iwl3945_reset_qos(priv);
  6988. priv->qos_data.qos_active = 0;
  6989. priv->qos_data.qos_cap.val = 0;
  6990. #endif /* CONFIG_IWL3945_QOS */
  6991. iwl3945_set_rxon_channel(priv, MODE_IEEE80211G, 6);
  6992. iwl3945_setup_deferred_work(priv);
  6993. iwl3945_setup_rx_handlers(priv);
  6994. priv->rates_mask = IWL_RATES_MASK;
  6995. /* If power management is turned on, default to AC mode */
  6996. priv->power_mode = IWL_POWER_AC;
  6997. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6998. iwl3945_disable_interrupts(priv);
  6999. pci_enable_msi(pdev);
  7000. err = request_irq(pdev->irq, iwl3945_isr, IRQF_SHARED, DRV_NAME, priv);
  7001. if (err) {
  7002. IWL_ERROR("Error allocating IRQ %d\n", pdev->irq);
  7003. goto out_disable_msi;
  7004. }
  7005. mutex_lock(&priv->mutex);
  7006. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  7007. if (err) {
  7008. IWL_ERROR("failed to create sysfs device attributes\n");
  7009. mutex_unlock(&priv->mutex);
  7010. goto out_release_irq;
  7011. }
  7012. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  7013. * ucode filename and max sizes are card-specific. */
  7014. err = iwl3945_read_ucode(priv);
  7015. if (err) {
  7016. IWL_ERROR("Could not read microcode: %d\n", err);
  7017. mutex_unlock(&priv->mutex);
  7018. goto out_pci_alloc;
  7019. }
  7020. mutex_unlock(&priv->mutex);
  7021. IWL_DEBUG_INFO("Queueing UP work.\n");
  7022. queue_work(priv->workqueue, &priv->up);
  7023. return 0;
  7024. out_pci_alloc:
  7025. iwl3945_dealloc_ucode_pci(priv);
  7026. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  7027. out_release_irq:
  7028. free_irq(pdev->irq, priv);
  7029. out_disable_msi:
  7030. pci_disable_msi(pdev);
  7031. destroy_workqueue(priv->workqueue);
  7032. priv->workqueue = NULL;
  7033. iwl3945_unset_hw_setting(priv);
  7034. out_iounmap:
  7035. pci_iounmap(pdev, priv->hw_base);
  7036. out_pci_release_regions:
  7037. pci_release_regions(pdev);
  7038. out_pci_disable_device:
  7039. pci_disable_device(pdev);
  7040. pci_set_drvdata(pdev, NULL);
  7041. out_ieee80211_free_hw:
  7042. ieee80211_free_hw(priv->hw);
  7043. out:
  7044. return err;
  7045. }
  7046. static void iwl3945_pci_remove(struct pci_dev *pdev)
  7047. {
  7048. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7049. struct list_head *p, *q;
  7050. int i;
  7051. if (!priv)
  7052. return;
  7053. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  7054. set_bit(STATUS_EXIT_PENDING, &priv->status);
  7055. iwl3945_down(priv);
  7056. /* Free MAC hash list for ADHOC */
  7057. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
  7058. list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
  7059. list_del(p);
  7060. kfree(list_entry(p, struct iwl3945_ibss_seq, list));
  7061. }
  7062. }
  7063. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  7064. iwl3945_dealloc_ucode_pci(priv);
  7065. if (priv->rxq.bd)
  7066. iwl3945_rx_queue_free(priv, &priv->rxq);
  7067. iwl3945_hw_txq_ctx_free(priv);
  7068. iwl3945_unset_hw_setting(priv);
  7069. iwl3945_clear_stations_table(priv);
  7070. if (priv->mac80211_registered) {
  7071. ieee80211_unregister_hw(priv->hw);
  7072. iwl3945_rate_control_unregister(priv->hw);
  7073. }
  7074. /*netif_stop_queue(dev); */
  7075. flush_workqueue(priv->workqueue);
  7076. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  7077. * priv->workqueue... so we can't take down the workqueue
  7078. * until now... */
  7079. destroy_workqueue(priv->workqueue);
  7080. priv->workqueue = NULL;
  7081. free_irq(pdev->irq, priv);
  7082. pci_disable_msi(pdev);
  7083. pci_iounmap(pdev, priv->hw_base);
  7084. pci_release_regions(pdev);
  7085. pci_disable_device(pdev);
  7086. pci_set_drvdata(pdev, NULL);
  7087. kfree(priv->channel_info);
  7088. kfree(priv->ieee_channels);
  7089. kfree(priv->ieee_rates);
  7090. if (priv->ibss_beacon)
  7091. dev_kfree_skb(priv->ibss_beacon);
  7092. ieee80211_free_hw(priv->hw);
  7093. }
  7094. #ifdef CONFIG_PM
  7095. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  7096. {
  7097. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7098. set_bit(STATUS_IN_SUSPEND, &priv->status);
  7099. /* Take down the device; powers it off, etc. */
  7100. iwl3945_down(priv);
  7101. if (priv->mac80211_registered)
  7102. ieee80211_stop_queues(priv->hw);
  7103. pci_save_state(pdev);
  7104. pci_disable_device(pdev);
  7105. pci_set_power_state(pdev, PCI_D3hot);
  7106. return 0;
  7107. }
  7108. static void iwl3945_resume(struct iwl3945_priv *priv)
  7109. {
  7110. unsigned long flags;
  7111. /* The following it a temporary work around due to the
  7112. * suspend / resume not fully initializing the NIC correctly.
  7113. * Without all of the following, resume will not attempt to take
  7114. * down the NIC (it shouldn't really need to) and will just try
  7115. * and bring the NIC back up. However that fails during the
  7116. * ucode verification process. This then causes iwl3945_down to be
  7117. * called *after* iwl3945_hw_nic_init() has succeeded -- which
  7118. * then lets the next init sequence succeed. So, we've
  7119. * replicated all of that NIC init code here... */
  7120. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  7121. iwl3945_hw_nic_init(priv);
  7122. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  7123. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  7124. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  7125. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  7126. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  7127. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  7128. /* tell the device to stop sending interrupts */
  7129. iwl3945_disable_interrupts(priv);
  7130. spin_lock_irqsave(&priv->lock, flags);
  7131. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  7132. if (!iwl3945_grab_nic_access(priv)) {
  7133. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  7134. APMG_CLK_VAL_DMA_CLK_RQT);
  7135. iwl3945_release_nic_access(priv);
  7136. }
  7137. spin_unlock_irqrestore(&priv->lock, flags);
  7138. udelay(5);
  7139. iwl3945_hw_nic_reset(priv);
  7140. /* Bring the device back up */
  7141. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  7142. queue_work(priv->workqueue, &priv->up);
  7143. }
  7144. static int iwl3945_pci_resume(struct pci_dev *pdev)
  7145. {
  7146. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7147. int err;
  7148. printk(KERN_INFO "Coming out of suspend...\n");
  7149. pci_set_power_state(pdev, PCI_D0);
  7150. err = pci_enable_device(pdev);
  7151. pci_restore_state(pdev);
  7152. /*
  7153. * Suspend/Resume resets the PCI configuration space, so we have to
  7154. * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
  7155. * from interfering with C3 CPU state. pci_restore_state won't help
  7156. * here since it only restores the first 64 bytes pci config header.
  7157. */
  7158. pci_write_config_byte(pdev, 0x41, 0x00);
  7159. iwl3945_resume(priv);
  7160. return 0;
  7161. }
  7162. #endif /* CONFIG_PM */
  7163. /*****************************************************************************
  7164. *
  7165. * driver and module entry point
  7166. *
  7167. *****************************************************************************/
  7168. static struct pci_driver iwl3945_driver = {
  7169. .name = DRV_NAME,
  7170. .id_table = iwl3945_hw_card_ids,
  7171. .probe = iwl3945_pci_probe,
  7172. .remove = __devexit_p(iwl3945_pci_remove),
  7173. #ifdef CONFIG_PM
  7174. .suspend = iwl3945_pci_suspend,
  7175. .resume = iwl3945_pci_resume,
  7176. #endif
  7177. };
  7178. static int __init iwl3945_init(void)
  7179. {
  7180. int ret;
  7181. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  7182. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  7183. ret = pci_register_driver(&iwl3945_driver);
  7184. if (ret) {
  7185. IWL_ERROR("Unable to initialize PCI module\n");
  7186. return ret;
  7187. }
  7188. #ifdef CONFIG_IWL3945_DEBUG
  7189. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  7190. if (ret) {
  7191. IWL_ERROR("Unable to create driver sysfs file\n");
  7192. pci_unregister_driver(&iwl3945_driver);
  7193. return ret;
  7194. }
  7195. #endif
  7196. return ret;
  7197. }
  7198. static void __exit iwl3945_exit(void)
  7199. {
  7200. #ifdef CONFIG_IWL3945_DEBUG
  7201. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  7202. #endif
  7203. pci_unregister_driver(&iwl3945_driver);
  7204. }
  7205. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  7206. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  7207. module_param_named(disable, iwl3945_param_disable, int, 0444);
  7208. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  7209. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  7210. MODULE_PARM_DESC(hwcrypto,
  7211. "using hardware crypto engine (default 0 [software])\n");
  7212. module_param_named(debug, iwl3945_param_debug, int, 0444);
  7213. MODULE_PARM_DESC(debug, "debug output mask");
  7214. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  7215. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  7216. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  7217. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  7218. /* QoS */
  7219. module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
  7220. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  7221. module_exit(iwl3945_exit);
  7222. module_init(iwl3945_init);